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Rev 1964 Rev 2161
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#define RADEON_INFO_WANT_CMASK		0x08 /* get access to CMASK on r300 */
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#define RADEON_INFO_WANT_CMASK		0x08 /* get access to CMASK on r300 */
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#define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
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#define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
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#define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
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#define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
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#define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
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#define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
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#define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
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#define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
- 
 
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#define RADEON_INFO_BACKEND_MAP		0x0d /* pipe to backend map, needed by mesa */
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struct drm_radeon_info {
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struct drm_radeon_info {
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	uint32_t		request;
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	uint32_t		request;
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	uint32_t		pad;
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	uint32_t		pad;