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21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
24 | * |
24 | * |
25 | */ |
25 | */ |
- | 26 | #ifndef _I915_DRM_H_ |
|
- | 27 | #define _I915_DRM_H_ |
|
Line 26... | Line -... | ||
26 | - | ||
27 | #ifndef _UAPI_I915_DRM_H_ |
- | |
28 | #define _UAPI_I915_DRM_H_ |
- | |
29 | 28 | ||
30 | #include |
- | |
31 | - | ||
32 | /* Please note that modifications to all structs defined here are |
- | |
33 | * subject to backwards-compatibility constraints. |
- | |
Line 34... | Line 29... | ||
34 | */ |
29 | #include |
35 | 30 | ||
36 | /* For use by IPS driver */ |
31 | /* For use by IPS driver */ |
37 | extern unsigned long i915_read_mch_val(void); |
32 | extern unsigned long i915_read_mch_val(void); |
38 | extern bool i915_gpu_raise(void); |
33 | extern bool i915_gpu_raise(void); |
39 | extern bool i915_gpu_lower(void); |
34 | extern bool i915_gpu_lower(void); |
40 | extern bool i915_gpu_busy(void); |
- | |
41 | extern bool i915_gpu_turbo_disable(void); |
- | |
42 | - | ||
43 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
- | |
44 | */ |
- | |
45 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
- | |
46 | * of chars for next/prev indices */ |
- | |
47 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 |
- | |
48 | - | ||
49 | typedef struct _drm_i915_init { |
- | |
50 | enum { |
- | |
51 | I915_INIT_DMA = 0x01, |
- | |
52 | I915_CLEANUP_DMA = 0x02, |
- | |
53 | I915_RESUME_DMA = 0x03 |
- | |
54 | } func; |
- | |
55 | unsigned int mmio_offset; |
- | |
56 | int sarea_priv_offset; |
- | |
57 | unsigned int ring_start; |
- | |
58 | unsigned int ring_end; |
- | |
59 | unsigned int ring_size; |
- | |
60 | unsigned int front_offset; |
- | |
61 | unsigned int back_offset; |
- | |
62 | unsigned int depth_offset; |
- | |
63 | unsigned int w; |
- | |
64 | unsigned int h; |
- | |
65 | unsigned int pitch; |
- | |
66 | unsigned int pitch_bits; |
- | |
67 | unsigned int back_pitch; |
- | |
68 | unsigned int depth_pitch; |
- | |
69 | unsigned int cpp; |
- | |
70 | unsigned int chipset; |
- | |
71 | } drm_i915_init_t; |
- | |
72 | - | ||
73 | typedef struct _drm_i915_sarea { |
- | |
74 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
- | |
75 | int last_upload; /* last time texture was uploaded */ |
- | |
76 | int last_enqueue; /* last time a buffer was enqueued */ |
- | |
77 | int last_dispatch; /* age of the most recently dispatched buffer */ |
- | |
78 | int ctxOwner; /* last context to upload state */ |
- | |
79 | int texAge; |
- | |
80 | int pf_enabled; /* is pageflipping allowed? */ |
- | |
81 | int pf_active; |
- | |
82 | int pf_current_page; /* which buffer is being displayed? */ |
- | |
83 | int perf_boxes; /* performance boxes to be displayed */ |
- | |
84 | int width, height; /* screen size in pixels */ |
- | |
85 | - | ||
86 | drm_handle_t front_handle; |
- | |
87 | int front_offset; |
- | |
88 | int front_size; |
- | |
89 | - | ||
90 | drm_handle_t back_handle; |
- | |
91 | int back_offset; |
- | |
92 | int back_size; |
- | |
93 | - | ||
94 | drm_handle_t depth_handle; |
- | |
95 | int depth_offset; |
- | |
96 | int depth_size; |
- | |
97 | - | ||
98 | drm_handle_t tex_handle; |
- | |
99 | int tex_offset; |
- | |
100 | int tex_size; |
- | |
101 | int log_tex_granularity; |
- | |
102 | int pitch; |
- | |
103 | int rotation; /* 0, 90, 180 or 270 */ |
- | |
104 | int rotated_offset; |
- | |
105 | int rotated_size; |
- | |
106 | int rotated_pitch; |
- | |
107 | int virtualX, virtualY; |
- | |
108 | - | ||
109 | unsigned int front_tiled; |
- | |
110 | unsigned int back_tiled; |
- | |
111 | unsigned int depth_tiled; |
- | |
112 | unsigned int rotated_tiled; |
- | |
113 | unsigned int rotated2_tiled; |
- | |
114 | - | ||
115 | int pipeA_x; |
- | |
116 | int pipeA_y; |
- | |
117 | int pipeA_w; |
- | |
118 | int pipeA_h; |
- | |
119 | int pipeB_x; |
- | |
120 | int pipeB_y; |
- | |
121 | int pipeB_w; |
- | |
122 | int pipeB_h; |
- | |
123 | - | ||
124 | /* fill out some space for old userspace triple buffer */ |
- | |
125 | drm_handle_t unused_handle; |
- | |
126 | __u32 unused1, unused2, unused3; |
- | |
127 | - | ||
128 | /* buffer object handles for static buffers. May change |
- | |
129 | * over the lifetime of the client. |
- | |
130 | */ |
- | |
131 | __u32 front_bo_handle; |
- | |
132 | __u32 back_bo_handle; |
- | |
133 | __u32 unused_bo_handle; |
- | |
134 | __u32 depth_bo_handle; |
- | |
135 | - | ||
136 | } drm_i915_sarea_t; |
- | |
137 | - | ||
138 | /* due to userspace building against these headers we need some compat here */ |
- | |
139 | #define planeA_x pipeA_x |
- | |
140 | #define planeA_y pipeA_y |
- | |
141 | #define planeA_w pipeA_w |
- | |
142 | #define planeA_h pipeA_h |
- | |
143 | #define planeB_x pipeB_x |
- | |
144 | #define planeB_y pipeB_y |
- | |
145 | #define planeB_w pipeB_w |
- | |
146 | #define planeB_h pipeB_h |
- | |
147 | - | ||
148 | /* Flags for perf_boxes |
- | |
149 | */ |
- | |
150 | #define I915_BOX_RING_EMPTY 0x1 |
- | |
151 | #define I915_BOX_FLIP 0x2 |
- | |
152 | #define I915_BOX_WAIT 0x4 |
- | |
153 | #define I915_BOX_TEXTURE_LOAD 0x8 |
- | |
154 | #define I915_BOX_LOST_CONTEXT 0x10 |
- | |
155 | - | ||
156 | /* I915 specific ioctls |
- | |
157 | * The device specific ioctl range is 0x40 to 0x79. |
- | |
158 | */ |
- | |
159 | #define DRM_I915_INIT 0x00 |
- | |
160 | #define DRM_I915_FLUSH 0x01 |
- | |
161 | #define DRM_I915_FLIP 0x02 |
- | |
162 | #define DRM_I915_BATCHBUFFER 0x03 |
- | |
163 | #define DRM_I915_IRQ_EMIT 0x04 |
- | |
164 | #define DRM_I915_IRQ_WAIT 0x05 |
- | |
165 | #define DRM_I915_GETPARAM 0x06 |
- | |
166 | #define DRM_I915_SETPARAM 0x07 |
- | |
167 | #define DRM_I915_ALLOC 0x08 |
- | |
168 | #define DRM_I915_FREE 0x09 |
- | |
169 | #define DRM_I915_INIT_HEAP 0x0a |
- | |
170 | #define DRM_I915_CMDBUFFER 0x0b |
- | |
171 | #define DRM_I915_DESTROY_HEAP 0x0c |
- | |
172 | #define DRM_I915_SET_VBLANK_PIPE 0x0d |
- | |
173 | #define DRM_I915_GET_VBLANK_PIPE 0x0e |
- | |
174 | #define DRM_I915_VBLANK_SWAP 0x0f |
- | |
175 | #define DRM_I915_HWS_ADDR 0x11 |
- | |
176 | #define DRM_I915_GEM_INIT 0x13 |
- | |
177 | #define DRM_I915_GEM_EXECBUFFER 0x14 |
- | |
178 | #define DRM_I915_GEM_PIN 0x15 |
- | |
179 | #define DRM_I915_GEM_UNPIN 0x16 |
- | |
180 | #define DRM_I915_GEM_BUSY 0x17 |
- | |
181 | #define DRM_I915_GEM_THROTTLE 0x18 |
- | |
182 | #define DRM_I915_GEM_ENTERVT 0x19 |
- | |
183 | #define DRM_I915_GEM_LEAVEVT 0x1a |
- | |
184 | #define DRM_I915_GEM_CREATE 0x1b |
- | |
185 | #define DRM_I915_GEM_PREAD 0x1c |
- | |
186 | #define DRM_I915_GEM_PWRITE 0x1d |
- | |
187 | #define DRM_I915_GEM_MMAP 0x1e |
- | |
188 | #define DRM_I915_GEM_SET_DOMAIN 0x1f |
- | |
189 | #define DRM_I915_GEM_SW_FINISH 0x20 |
- | |
190 | #define DRM_I915_GEM_SET_TILING 0x21 |
- | |
191 | #define DRM_I915_GEM_GET_TILING 0x22 |
- | |
192 | #define DRM_I915_GEM_GET_APERTURE 0x23 |
- | |
193 | #define DRM_I915_GEM_MMAP_GTT 0x24 |
- | |
194 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
- | |
195 | #define DRM_I915_GEM_MADVISE 0x26 |
- | |
196 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
- | |
197 | #define DRM_I915_OVERLAY_ATTRS 0x28 |
- | |
198 | #define DRM_I915_GEM_EXECBUFFER2 0x29 |
- | |
199 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
- | |
200 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
- | |
201 | #define DRM_I915_GEM_WAIT 0x2c |
- | |
202 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
- | |
203 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
- | |
204 | #define DRM_I915_GEM_SET_CACHING 0x2f |
- | |
205 | #define DRM_I915_GEM_GET_CACHING 0x30 |
- | |
206 | #define DRM_I915_REG_READ 0x31 |
- | |
207 | - | ||
208 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
- | |
209 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
- | |
210 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
- | |
211 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
- | |
212 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) |
- | |
213 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) |
- | |
214 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) |
- | |
215 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) |
- | |
216 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) |
- | |
217 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) |
- | |
218 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) |
- | |
219 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) |
- | |
220 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
- | |
221 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
- | |
222 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
- | |
223 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
- | |
224 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) |
- | |
225 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) |
- | |
226 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) |
- | |
227 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) |
- | |
228 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
- | |
229 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) |
- | |
230 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) |
- | |
231 | #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) |
- | |
232 | #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) |
- | |
233 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) |
- | |
234 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) |
- | |
235 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) |
- | |
236 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) |
- | |
237 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) |
- | |
238 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) |
- | |
239 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) |
- | |
240 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) |
- | |
241 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) |
- | |
242 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) |
- | |
243 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) |
- | |
244 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) |
- | |
245 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) |
- | |
246 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) |
- | |
247 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) |
- | |
248 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
- | |
249 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
- | |
250 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
- | |
251 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
- | |
252 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
- | |
253 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
- | |
254 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
- | |
255 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
- | |
256 | - | ||
257 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
- | |
258 | * on the security mechanisms provided by hardware. |
- | |
259 | */ |
- | |
260 | typedef struct drm_i915_batchbuffer { |
- | |
261 | int start; /* agp offset */ |
- | |
262 | int used; /* nr bytes in use */ |
- | |
263 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
- | |
264 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
- | |
265 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
- | |
266 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
- | |
267 | } drm_i915_batchbuffer_t; |
- | |
268 | - | ||
269 | /* As above, but pass a pointer to userspace buffer which can be |
- | |
270 | * validated by the kernel prior to sending to hardware. |
- | |
271 | */ |
- | |
272 | typedef struct _drm_i915_cmdbuffer { |
- | |
273 | char __user *buf; /* pointer to userspace command buffer */ |
- | |
274 | int sz; /* nr bytes in buf */ |
- | |
275 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
- | |
276 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
- | |
277 | int num_cliprects; /* mulitpass with multiple cliprects? */ |
- | |
278 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
- | |
279 | } drm_i915_cmdbuffer_t; |
- | |
280 | - | ||
281 | /* Userspace can request & wait on irq's: |
- | |
282 | */ |
- | |
283 | typedef struct drm_i915_irq_emit { |
- | |
284 | int __user *irq_seq; |
- | |
285 | } drm_i915_irq_emit_t; |
- | |
286 | - | ||
287 | typedef struct drm_i915_irq_wait { |
- | |
288 | int irq_seq; |
- | |
289 | } drm_i915_irq_wait_t; |
- | |
290 | - | ||
291 | /* Ioctl to query kernel params: |
- | |
292 | */ |
- | |
293 | #define I915_PARAM_IRQ_ACTIVE 1 |
- | |
294 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 |
- | |
295 | #define I915_PARAM_LAST_DISPATCH 3 |
- | |
296 | #define I915_PARAM_CHIPSET_ID 4 |
- | |
297 | #define I915_PARAM_HAS_GEM 5 |
- | |
298 | #define I915_PARAM_NUM_FENCES_AVAIL 6 |
- | |
299 | #define I915_PARAM_HAS_OVERLAY 7 |
- | |
300 | #define I915_PARAM_HAS_PAGEFLIPPING 8 |
- | |
301 | #define I915_PARAM_HAS_EXECBUF2 9 |
- | |
302 | #define I915_PARAM_HAS_BSD 10 |
- | |
303 | #define I915_PARAM_HAS_BLT 11 |
- | |
304 | #define I915_PARAM_HAS_RELAXED_FENCING 12 |
- | |
305 | #define I915_PARAM_HAS_COHERENT_RINGS 13 |
- | |
306 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
- | |
307 | #define I915_PARAM_HAS_RELAXED_DELTA 15 |
- | |
308 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
- | |
309 | #define I915_PARAM_HAS_LLC 17 |
- | |
310 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 |
- | |
311 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
- | |
312 | #define I915_PARAM_HAS_SEMAPHORES 20 |
- | |
313 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
- | |
314 | #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 |
- | |
315 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
- | |
316 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
- | |
317 | - | ||
318 | typedef struct drm_i915_getparam { |
- | |
319 | int param; |
- | |
320 | int __user *value; |
- | |
321 | } drm_i915_getparam_t; |
- | |
322 | - | ||
323 | /* Ioctl to set kernel params: |
- | |
324 | */ |
- | |
325 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
- | |
326 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
- | |
327 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
- | |
328 | #define I915_SETPARAM_NUM_USED_FENCES 4 |
- | |
329 | - | ||
330 | typedef struct drm_i915_setparam { |
- | |
331 | int param; |
- | |
332 | int value; |
- | |
333 | } drm_i915_setparam_t; |
- | |
334 | - | ||
335 | /* A memory manager for regions of shared memory: |
- | |
336 | */ |
- | |
337 | #define I915_MEM_REGION_AGP 1 |
- | |
338 | - | ||
339 | typedef struct drm_i915_mem_alloc { |
- | |
340 | int region; |
- | |
341 | int alignment; |
- | |
342 | int size; |
- | |
343 | int __user *region_offset; /* offset from start of fb or agp */ |
- | |
344 | } drm_i915_mem_alloc_t; |
- | |
345 | - | ||
346 | typedef struct drm_i915_mem_free { |
- | |
347 | int region; |
- | |
348 | int region_offset; |
- | |
349 | } drm_i915_mem_free_t; |
- | |
350 | - | ||
351 | typedef struct drm_i915_mem_init_heap { |
- | |
352 | int region; |
- | |
353 | int size; |
- | |
354 | int start; |
- | |
355 | } drm_i915_mem_init_heap_t; |
- | |
356 | - | ||
357 | /* Allow memory manager to be torn down and re-initialized (eg on |
- | |
358 | * rotate): |
- | |
359 | */ |
- | |
360 | typedef struct drm_i915_mem_destroy_heap { |
- | |
361 | int region; |
- | |
362 | } drm_i915_mem_destroy_heap_t; |
- | |
363 | - | ||
364 | /* Allow X server to configure which pipes to monitor for vblank signals |
- | |
365 | */ |
- | |
366 | #define DRM_I915_VBLANK_PIPE_A 1 |
- | |
367 | #define DRM_I915_VBLANK_PIPE_B 2 |
- | |
368 | - | ||
369 | typedef struct drm_i915_vblank_pipe { |
- | |
370 | int pipe; |
- | |
371 | } drm_i915_vblank_pipe_t; |
- | |
372 | - | ||
373 | /* Schedule buffer swap at given vertical blank: |
- | |
374 | */ |
- | |
375 | typedef struct drm_i915_vblank_swap { |
- | |
376 | drm_drawable_t drawable; |
- | |
377 | enum drm_vblank_seq_type seqtype; |
- | |
378 | unsigned int sequence; |
- | |
379 | } drm_i915_vblank_swap_t; |
- | |
380 | - | ||
381 | typedef struct drm_i915_hws_addr { |
- | |
382 | __u64 addr; |
- | |
383 | } drm_i915_hws_addr_t; |
- | |
384 | - | ||
385 | struct drm_i915_gem_init { |
- | |
386 | /** |
- | |
387 | * Beginning offset in the GTT to be managed by the DRM memory |
- | |
388 | * manager. |
- | |
389 | */ |
- | |
390 | __u64 gtt_start; |
- | |
391 | /** |
- | |
392 | * Ending offset in the GTT to be managed by the DRM memory |
- | |
393 | * manager. |
- | |
394 | */ |
- | |
395 | __u64 gtt_end; |
- | |
396 | }; |
- | |
397 | - | ||
398 | struct drm_i915_gem_create { |
- | |
399 | /** |
- | |
400 | * Requested size for the object. |
- | |
401 | * |
- | |
402 | * The (page-aligned) allocated size for the object will be returned. |
- | |
403 | */ |
- | |
404 | __u64 size; |
- | |
405 | /** |
- | |
406 | * Returned handle for the object. |
- | |
407 | * |
- | |
408 | * Object handles are nonzero. |
- | |
409 | */ |
- | |
410 | __u32 handle; |
- | |
411 | __u32 pad; |
- | |
412 | }; |
- | |
413 | - | ||
414 | struct drm_i915_gem_pread { |
- | |
415 | /** Handle for the object being read. */ |
- | |
416 | __u32 handle; |
- | |
417 | __u32 pad; |
- | |
418 | /** Offset into the object to read from */ |
- | |
419 | __u64 offset; |
- | |
420 | /** Length of data to read */ |
- | |
421 | __u64 size; |
- | |
422 | /** |
- | |
423 | * Pointer to write the data into. |
- | |
424 | * |
- | |
425 | * This is a fixed-size type for 32/64 compatibility. |
- | |
426 | */ |
- | |
427 | __u64 data_ptr; |
- | |
428 | }; |
- | |
429 | - | ||
430 | struct drm_i915_gem_pwrite { |
- | |
431 | /** Handle for the object being written to. */ |
- | |
432 | __u32 handle; |
- | |
433 | __u32 pad; |
- | |
434 | /** Offset into the object to write to */ |
- | |
435 | __u64 offset; |
- | |
436 | /** Length of data to write */ |
- | |
437 | __u64 size; |
- | |
438 | /** |
- | |
439 | * Pointer to read the data from. |
- | |
440 | * |
- | |
441 | * This is a fixed-size type for 32/64 compatibility. |
- | |
442 | */ |
- | |
443 | __u64 data_ptr; |
- | |
444 | }; |
- | |
445 | - | ||
446 | struct drm_i915_gem_mmap { |
- | |
447 | /** Handle for the object being mapped. */ |
- | |
448 | __u32 handle; |
- | |
449 | __u32 pad; |
- | |
450 | /** Offset in the object to map. */ |
- | |
451 | __u64 offset; |
- | |
452 | /** |
- | |
453 | * Length of data to map. |
- | |
454 | * |
- | |
455 | * The value will be page-aligned. |
- | |
456 | */ |
- | |
457 | __u64 size; |
- | |
458 | /** |
- | |
459 | * Returned pointer the data was mapped at. |
- | |
460 | * |
- | |
461 | * This is a fixed-size type for 32/64 compatibility. |
- | |
462 | */ |
- | |
463 | __u64 addr_ptr; |
- | |
464 | }; |
- | |
465 | - | ||
466 | struct drm_i915_gem_mmap_gtt { |
- | |
467 | /** Handle for the object being mapped. */ |
- | |
468 | __u32 handle; |
- | |
469 | __u32 pad; |
- | |
470 | /** |
- | |
471 | * Fake offset to use for subsequent mmap call |
- | |
472 | * |
- | |
473 | * This is a fixed-size type for 32/64 compatibility. |
- | |
474 | */ |
- | |
475 | __u64 offset; |
- | |
476 | }; |
- | |
477 | - | ||
478 | struct drm_i915_gem_set_domain { |
- | |
479 | /** Handle for the object */ |
- | |
480 | __u32 handle; |
- | |
481 | - | ||
482 | /** New read domains */ |
- | |
483 | __u32 read_domains; |
- | |
484 | - | ||
485 | /** New write domain */ |
- | |
486 | __u32 write_domain; |
- | |
487 | }; |
- | |
488 | - | ||
489 | struct drm_i915_gem_sw_finish { |
- | |
490 | /** Handle for the object */ |
- | |
491 | __u32 handle; |
- | |
492 | }; |
- | |
493 | - | ||
494 | struct drm_i915_gem_relocation_entry { |
- | |
495 | /** |
- | |
496 | * Handle of the buffer being pointed to by this relocation entry. |
- | |
497 | * |
- | |
498 | * It's appealing to make this be an index into the mm_validate_entry |
- | |
499 | * list to refer to the buffer, but this allows the driver to create |
- | |
500 | * a relocation list for state buffers and not re-write it per |
- | |
501 | * exec using the buffer. |
- | |
502 | */ |
- | |
503 | __u32 target_handle; |
- | |
504 | - | ||
505 | /** |
- | |
506 | * Value to be added to the offset of the target buffer to make up |
- | |
507 | * the relocation entry. |
- | |
508 | */ |
- | |
509 | __u32 delta; |
- | |
510 | - | ||
511 | /** Offset in the buffer the relocation entry will be written into */ |
- | |
512 | __u64 offset; |
- | |
513 | - | ||
514 | /** |
- | |
515 | * Offset value of the target buffer that the relocation entry was last |
- | |
516 | * written as. |
- | |
517 | * |
- | |
518 | * If the buffer has the same offset as last time, we can skip syncing |
- | |
519 | * and writing the relocation. This value is written back out by |
- | |
520 | * the execbuffer ioctl when the relocation is written. |
- | |
521 | */ |
- | |
522 | __u64 presumed_offset; |
- | |
523 | - | ||
524 | /** |
- | |
525 | * Target memory domains read by this operation. |
- | |
526 | */ |
- | |
527 | __u32 read_domains; |
- | |
528 | - | ||
529 | /** |
- | |
530 | * Target memory domains written by this operation. |
- | |
531 | * |
- | |
532 | * Note that only one domain may be written by the whole |
- | |
533 | * execbuffer operation, so that where there are conflicts, |
- | |
534 | * the application will get -EINVAL back. |
- | |
535 | */ |
- | |
536 | __u32 write_domain; |
- | |
537 | }; |
- | |
538 | - | ||
539 | /** @{ |
- | |
540 | * Intel memory domains |
- | |
541 | * |
- | |
542 | * Most of these just align with the various caches in |
- | |
543 | * the system and are used to flush and invalidate as |
- | |
544 | * objects end up cached in different domains. |
- | |
545 | */ |
- | |
546 | /** CPU cache */ |
- | |
547 | #define I915_GEM_DOMAIN_CPU 0x00000001 |
- | |
548 | /** Render cache, used by 2D and 3D drawing */ |
- | |
549 | #define I915_GEM_DOMAIN_RENDER 0x00000002 |
- | |
550 | /** Sampler cache, used by texture engine */ |
- | |
551 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
- | |
552 | /** Command queue, used to load batch buffers */ |
- | |
553 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 |
- | |
554 | /** Instruction cache, used by shader programs */ |
- | |
555 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
- | |
556 | /** Vertex address cache */ |
- | |
557 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 |
- | |
558 | /** GTT domain - aperture and scanout */ |
- | |
559 | #define I915_GEM_DOMAIN_GTT 0x00000040 |
- | |
560 | /** @} */ |
- | |
561 | - | ||
562 | struct drm_i915_gem_exec_object { |
- | |
563 | /** |
- | |
564 | * User's handle for a buffer to be bound into the GTT for this |
- | |
565 | * operation. |
- | |
566 | */ |
- | |
567 | __u32 handle; |
- | |
568 | - | ||
569 | /** Number of relocations to be performed on this buffer */ |
- | |
570 | __u32 relocation_count; |
- | |
571 | /** |
- | |
572 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
- | |
573 | * the relocations to be performed in this buffer. |
- | |
574 | */ |
- | |
575 | __u64 relocs_ptr; |
- | |
576 | - | ||
577 | /** Required alignment in graphics aperture */ |
- | |
578 | __u64 alignment; |
- | |
579 | - | ||
580 | /** |
- | |
581 | * Returned value of the updated offset of the object, for future |
- | |
582 | * presumed_offset writes. |
- | |
583 | */ |
- | |
584 | __u64 offset; |
- | |
585 | }; |
- | |
586 | - | ||
587 | struct drm_i915_gem_execbuffer { |
- | |
588 | /** |
- | |
589 | * List of buffers to be validated with their relocations to be |
- | |
590 | * performend on them. |
- | |
591 | * |
- | |
592 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. |
- | |
593 | * |
- | |
594 | * These buffers must be listed in an order such that all relocations |
- | |
595 | * a buffer is performing refer to buffers that have already appeared |
- | |
596 | * in the validate list. |
- | |
597 | */ |
- | |
598 | __u64 buffers_ptr; |
- | |
599 | __u32 buffer_count; |
- | |
600 | - | ||
601 | /** Offset in the batchbuffer to start execution from. */ |
- | |
602 | __u32 batch_start_offset; |
- | |
603 | /** Bytes used in batchbuffer from batch_start_offset */ |
- | |
604 | __u32 batch_len; |
- | |
605 | __u32 DR1; |
- | |
606 | __u32 DR4; |
- | |
607 | __u32 num_cliprects; |
- | |
608 | /** This is a struct drm_clip_rect *cliprects */ |
- | |
609 | __u64 cliprects_ptr; |
- | |
610 | }; |
- | |
611 | - | ||
612 | struct drm_i915_gem_exec_object2 { |
- | |
613 | /** |
- | |
614 | * User's handle for a buffer to be bound into the GTT for this |
- | |
615 | * operation. |
- | |
616 | */ |
- | |
617 | __u32 handle; |
- | |
618 | - | ||
619 | /** Number of relocations to be performed on this buffer */ |
- | |
620 | __u32 relocation_count; |
- | |
621 | /** |
- | |
622 | * Pointer to array of struct drm_i915_gem_relocation_entry containing |
- | |
623 | * the relocations to be performed in this buffer. |
- | |
624 | */ |
- | |
625 | __u64 relocs_ptr; |
- | |
626 | - | ||
627 | /** Required alignment in graphics aperture */ |
- | |
628 | __u64 alignment; |
- | |
629 | - | ||
630 | /** |
- | |
631 | * Returned value of the updated offset of the object, for future |
- | |
632 | * presumed_offset writes. |
- | |
633 | */ |
- | |
634 | __u64 offset; |
- | |
635 | - | ||
636 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
- | |
637 | __u64 flags; |
- | |
638 | __u64 rsvd1; |
- | |
639 | __u64 rsvd2; |
- | |
640 | }; |
- | |
641 | - | ||
642 | struct drm_i915_gem_execbuffer2 { |
- | |
643 | /** |
- | |
644 | * List of gem_exec_object2 structs |
- | |
645 | */ |
- | |
646 | __u64 buffers_ptr; |
- | |
647 | __u32 buffer_count; |
- | |
648 | - | ||
649 | /** Offset in the batchbuffer to start execution from. */ |
- | |
650 | __u32 batch_start_offset; |
- | |
651 | /** Bytes used in batchbuffer from batch_start_offset */ |
- | |
652 | __u32 batch_len; |
- | |
653 | __u32 DR1; |
- | |
654 | __u32 DR4; |
- | |
655 | __u32 num_cliprects; |
- | |
656 | /** This is a struct drm_clip_rect *cliprects */ |
- | |
657 | __u64 cliprects_ptr; |
- | |
658 | #define I915_EXEC_RING_MASK (7<<0) |
- | |
659 | #define I915_EXEC_DEFAULT (0<<0) |
- | |
660 | #define I915_EXEC_RENDER (1<<0) |
- | |
661 | #define I915_EXEC_BSD (2<<0) |
- | |
662 | #define I915_EXEC_BLT (3<<0) |
- | |
663 | - | ||
664 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. |
- | |
665 | * Gen6+ only supports relative addressing to dynamic state (default) and |
- | |
666 | * absolute addressing. |
- | |
667 | * |
- | |
668 | * These flags are ignored for the BSD and BLT rings. |
- | |
669 | */ |
- | |
670 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
- | |
671 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
- | |
672 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
- | |
673 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
- | |
674 | __u64 flags; |
- | |
675 | __u64 rsvd1; /* now used for context info */ |
- | |
676 | __u64 rsvd2; |
- | |
677 | }; |
- | |
678 | - | ||
679 | /** Resets the SO write offset registers for transform feedback on gen7. */ |
- | |
680 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) |
- | |
681 | - | ||
682 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
- | |
683 | #define i915_execbuffer2_set_context_id(eb2, context) \ |
- | |
684 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
- | |
685 | #define i915_execbuffer2_get_context_id(eb2) \ |
- | |
686 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
- | |
687 | - | ||
688 | struct drm_i915_gem_pin { |
- | |
689 | /** Handle of the buffer to be pinned. */ |
- | |
690 | __u32 handle; |
- | |
691 | __u32 pad; |
- | |
692 | - | ||
693 | /** alignment required within the aperture */ |
- | |
694 | __u64 alignment; |
- | |
695 | - | ||
696 | /** Returned GTT offset of the buffer. */ |
- | |
697 | __u64 offset; |
- | |
698 | }; |
- | |
699 | - | ||
700 | struct drm_i915_gem_unpin { |
- | |
701 | /** Handle of the buffer to be unpinned. */ |
- | |
702 | __u32 handle; |
- | |
703 | __u32 pad; |
- | |
704 | }; |
- | |
705 | - | ||
706 | struct drm_i915_gem_busy { |
- | |
707 | /** Handle of the buffer to check for busy */ |
- | |
708 | __u32 handle; |
- | |
709 | - | ||
710 | /** Return busy status (1 if busy, 0 if idle). |
- | |
711 | * The high word is used to indicate on which rings the object |
- | |
712 | * currently resides: |
- | |
713 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
- | |
714 | */ |
- | |
715 | __u32 busy; |
- | |
716 | }; |
- | |
717 | - | ||
718 | #define I915_CACHING_NONE 0 |
- | |
719 | #define I915_CACHING_CACHED 1 |
- | |
720 | - | ||
721 | struct drm_i915_gem_caching { |
- | |
722 | /** |
- | |
723 | * Handle of the buffer to set/get the caching level of. */ |
- | |
724 | __u32 handle; |
- | |
725 | - | ||
726 | /** |
- | |
727 | * Cacheing level to apply or return value |
- | |
728 | * |
- | |
729 | * bits0-15 are for generic caching control (i.e. the above defined |
- | |
730 | * values). bits16-31 are reserved for platform-specific variations |
- | |
731 | * (e.g. l3$ caching on gen7). */ |
- | |
732 | __u32 caching; |
- | |
733 | }; |
- | |
734 | - | ||
735 | #define I915_TILING_NONE 0 |
- | |
736 | #define I915_TILING_X 1 |
- | |
737 | #define I915_TILING_Y 2 |
- | |
738 | - | ||
739 | #define I915_BIT_6_SWIZZLE_NONE 0 |
- | |
740 | #define I915_BIT_6_SWIZZLE_9 1 |
- | |
741 | #define I915_BIT_6_SWIZZLE_9_10 2 |
- | |
742 | #define I915_BIT_6_SWIZZLE_9_11 3 |
- | |
743 | #define I915_BIT_6_SWIZZLE_9_10_11 4 |
- | |
744 | /* Not seen by userland */ |
- | |
745 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
- | |
746 | /* Seen by userland. */ |
- | |
747 | #define I915_BIT_6_SWIZZLE_9_17 6 |
- | |
748 | #define I915_BIT_6_SWIZZLE_9_10_17 7 |
- | |
749 | - | ||
750 | struct drm_i915_gem_set_tiling { |
- | |
751 | /** Handle of the buffer to have its tiling state updated */ |
- | |
752 | __u32 handle; |
- | |
753 | - | ||
754 | /** |
- | |
755 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
- | |
756 | * I915_TILING_Y). |
- | |
757 | * |
- | |
758 | * This value is to be set on request, and will be updated by the |
- | |
759 | * kernel on successful return with the actual chosen tiling layout. |
- | |
760 | * |
- | |
761 | * The tiling mode may be demoted to I915_TILING_NONE when the system |
- | |
762 | * has bit 6 swizzling that can't be managed correctly by GEM. |
- | |
763 | * |
- | |
764 | * Buffer contents become undefined when changing tiling_mode. |
- | |
765 | */ |
- | |
766 | __u32 tiling_mode; |
- | |
767 | - | ||
768 | /** |
- | |
769 | * Stride in bytes for the object when in I915_TILING_X or |
- | |
770 | * I915_TILING_Y. |
- | |
771 | */ |
- | |
772 | __u32 stride; |
- | |
773 | - | ||
774 | /** |
- | |
775 | * Returned address bit 6 swizzling required for CPU access through |
- | |
776 | * mmap mapping. |
- | |
777 | */ |
- | |
778 | __u32 swizzle_mode; |
- | |
779 | }; |
- | |
780 | - | ||
781 | struct drm_i915_gem_get_tiling { |
- | |
782 | /** Handle of the buffer to get tiling state for. */ |
- | |
783 | __u32 handle; |
- | |
784 | - | ||
785 | /** |
- | |
786 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
- | |
787 | * I915_TILING_Y). |
- | |
788 | */ |
- | |
789 | __u32 tiling_mode; |
- | |
790 | - | ||
791 | /** |
- | |
792 | * Returned address bit 6 swizzling required for CPU access through |
- | |
793 | * mmap mapping. |
- | |
794 | */ |
- | |
795 | __u32 swizzle_mode; |
- | |
796 | }; |
- | |
797 | - | ||
798 | struct drm_i915_gem_get_aperture { |
- | |
799 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
- | |
800 | __u64 aper_size; |
- | |
801 | - | ||
802 | /** |
- | |
803 | * Available space in the aperture used by i915_gem_execbuffer, in |
- | |
804 | * bytes |
- | |
805 | */ |
- | |
806 | __u64 aper_available_size; |
- | |
807 | }; |
- | |
808 | - | ||
809 | struct drm_i915_get_pipe_from_crtc_id { |
- | |
810 | /** ID of CRTC being requested **/ |
- | |
811 | __u32 crtc_id; |
- | |
812 | - | ||
813 | /** pipe of requested CRTC **/ |
- | |
814 | __u32 pipe; |
- | |
815 | }; |
- | |
816 | - | ||
817 | #define I915_MADV_WILLNEED 0 |
- | |
818 | #define I915_MADV_DONTNEED 1 |
- | |
819 | #define __I915_MADV_PURGED 2 /* internal state */ |
- | |
820 | - | ||
821 | struct drm_i915_gem_madvise { |
- | |
822 | /** Handle of the buffer to change the backing store advice */ |
- | |
823 | __u32 handle; |
- | |
824 | - | ||
825 | /* Advice: either the buffer will be needed again in the near future, |
- | |
826 | * or wont be and could be discarded under memory pressure. |
- | |
827 | */ |
- | |
828 | __u32 madv; |
- | |
829 | - | ||
830 | /** Whether the backing store still exists. */ |
- | |
831 | __u32 retained; |
- | |
832 | }; |
- | |
833 | - | ||
834 | /* flags */ |
- | |
835 | #define I915_OVERLAY_TYPE_MASK 0xff |
- | |
836 | #define I915_OVERLAY_YUV_PLANAR 0x01 |
- | |
837 | #define I915_OVERLAY_YUV_PACKED 0x02 |
- | |
838 | #define I915_OVERLAY_RGB 0x03 |
- | |
839 | - | ||
840 | #define I915_OVERLAY_DEPTH_MASK 0xff00 |
- | |
841 | #define I915_OVERLAY_RGB24 0x1000 |
- | |
842 | #define I915_OVERLAY_RGB16 0x2000 |
- | |
843 | #define I915_OVERLAY_RGB15 0x3000 |
- | |
844 | #define I915_OVERLAY_YUV422 0x0100 |
- | |
845 | #define I915_OVERLAY_YUV411 0x0200 |
- | |
846 | #define I915_OVERLAY_YUV420 0x0300 |
- | |
847 | #define I915_OVERLAY_YUV410 0x0400 |
- | |
848 | - | ||
849 | #define I915_OVERLAY_SWAP_MASK 0xff0000 |
- | |
850 | #define I915_OVERLAY_NO_SWAP 0x000000 |
- | |
851 | #define I915_OVERLAY_UV_SWAP 0x010000 |
- | |
852 | #define I915_OVERLAY_Y_SWAP 0x020000 |
- | |
853 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
- | |
854 | - | ||
855 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 |
- | |
856 | #define I915_OVERLAY_ENABLE 0x01000000 |
- | |
857 | - | ||
858 | struct drm_intel_overlay_put_image { |
- | |
859 | /* various flags and src format description */ |
- | |
860 | __u32 flags; |
- | |
861 | /* source picture description */ |
- | |
862 | __u32 bo_handle; |
- | |
863 | /* stride values and offsets are in bytes, buffer relative */ |
- | |
864 | __u16 stride_Y; /* stride for packed formats */ |
- | |
865 | __u16 stride_UV; |
- | |
866 | __u32 offset_Y; /* offset for packet formats */ |
- | |
867 | __u32 offset_U; |
- | |
868 | __u32 offset_V; |
- | |
869 | /* in pixels */ |
- | |
870 | __u16 src_width; |
- | |
871 | __u16 src_height; |
- | |
872 | /* to compensate the scaling factors for partially covered surfaces */ |
- | |
873 | __u16 src_scan_width; |
- | |
874 | __u16 src_scan_height; |
- | |
875 | /* output crtc description */ |
- | |
876 | __u32 crtc_id; |
- | |
877 | __u16 dst_x; |
- | |
878 | __u16 dst_y; |
- | |
879 | __u16 dst_width; |
- | |
880 | __u16 dst_height; |
- | |
881 | }; |
- | |
882 | - | ||
883 | /* flags */ |
- | |
884 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
- | |
885 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
- | |
886 | struct drm_intel_overlay_attrs { |
- | |
887 | __u32 flags; |
- | |
888 | __u32 color_key; |
- | |
889 | __s32 brightness; |
- | |
890 | __u32 contrast; |
- | |
891 | __u32 saturation; |
- | |
892 | __u32 gamma0; |
- | |
893 | __u32 gamma1; |
- | |
894 | __u32 gamma2; |
- | |
895 | __u32 gamma3; |
- | |
896 | __u32 gamma4; |
- | |
897 | __u32 gamma5; |
- | |
898 | }; |
- | |
899 | - | ||
900 | /* |
- | |
901 | * Intel sprite handling |
- | |
902 | * |
- | |
903 | * Color keying works with a min/mask/max tuple. Both source and destination |
- | |
904 | * color keying is allowed. |
- | |
905 | * |
- | |
906 | * Source keying: |
- | |
907 | * Sprite pixels within the min & max values, masked against the color channels |
- | |
908 | * specified in the mask field, will be transparent. All other pixels will |
- | |
909 | * be displayed on top of the primary plane. For RGB surfaces, only the min |
- | |
910 | * and mask fields will be used; ranged compares are not allowed. |
- | |
911 | * |
- | |
912 | * Destination keying: |
- | |
913 | * Primary plane pixels that match the min value, masked against the color |
- | |
914 | * channels specified in the mask field, will be replaced by corresponding |
- | |
915 | * pixels from the sprite plane. |
- | |
916 | * |
- | |
917 | * Note that source & destination keying are exclusive; only one can be |
- | |
918 | * active on a given plane. |
- | |
919 | */ |
- | |
920 | - | ||
921 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
- | |
922 | #define I915_SET_COLORKEY_DESTINATION (1<<1) |
- | |
923 | #define I915_SET_COLORKEY_SOURCE (1<<2) |
- | |
924 | struct drm_intel_sprite_colorkey { |
- | |
925 | __u32 plane_id; |
- | |
926 | __u32 min_value; |
- | |
927 | __u32 channel_mask; |
- | |
928 | __u32 max_value; |
- | |
929 | __u32 flags; |
- | |
930 | }; |
- | |
931 | - | ||
932 | struct drm_i915_gem_wait { |
- | |
933 | /** Handle of BO we shall wait on */ |
- | |
934 | __u32 bo_handle; |
- | |
935 | __u32 flags; |
- | |
936 | /** Number of nanoseconds to wait, Returns time remaining. */ |
- | |
937 | __s64 timeout_ns; |
- | |
938 | }; |
- | |
939 | - | ||
940 | struct drm_i915_gem_context_create { |
- | |
941 | /* output: id of new context*/ |
- | |
942 | __u32 ctx_id; |
- | |
943 | __u32 pad; |
- | |
944 | }; |
- | |
945 | - | ||
946 | struct drm_i915_gem_context_destroy { |
- | |
947 | __u32 ctx_id; |
- | |
948 | __u32 pad; |
- | |
949 | }; |
- | |
950 | - | ||
951 | struct drm_i915_reg_read { |
- | |
952 | __u64 offset; |
- | |
953 | __u64 val; /* Return value */ |
35 | extern bool i915_gpu_busy(void); |