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#define DP_TRAINING_LANE3_SET		    0x106
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#define DP_TRAINING_LANE3_SET		    0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
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# define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
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# define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
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# define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
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# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
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# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
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# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
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# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
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#define DP_TEST_CRC_G_Y			    0x242
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#define DP_TEST_CRC_G_Y			    0x242
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#define DP_TEST_CRC_B_CB		    0x244
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#define DP_TEST_CRC_B_CB		    0x244
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#define DP_TEST_SINK_MISC		    0x246
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#define DP_TEST_SINK_MISC		    0x246
-
 
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# define DP_TEST_CRC_SUPPORTED		    (1 << 5)
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#define DP_TEST_CRC_SUPPORTED		    (1 << 5)
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# define DP_TEST_COUNT_MASK		    0x7
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#define DP_TEST_RESPONSE		    0x260
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#define DP_TEST_RESPONSE		    0x260
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# define DP_TEST_ACK			    (1 << 0)
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# define DP_TEST_ACK			    (1 << 0)
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#define MODE_I2C_START	1
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#define MODE_I2C_START	1
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#define MODE_I2C_WRITE	2
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#define MODE_I2C_WRITE	2
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#define MODE_I2C_READ	4
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#define MODE_I2C_READ	4
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#define MODE_I2C_STOP	8
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#define MODE_I2C_STOP	8
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-
 
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/**
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 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
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 * 				 aux algorithm
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 * @running: set by the algo indicating whether an i2c is ongoing or whether
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 * 	     the i2c bus is quiescent
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 * @address: i2c target address for the currently ongoing transfer
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 * @aux_ch: driver callback to transfer a single byte of the i2c payload
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 */
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struct i2c_algo_dp_aux_data {
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	bool running;
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	u16 address;
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	int (*aux_ch) (struct i2c_adapter *adapter,
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		       int mode, uint8_t write_byte,
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		       uint8_t *read_byte);
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};
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int
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i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
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-
 
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#define DP_LINK_STATUS_SIZE	   6
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#define DP_LINK_STATUS_SIZE	   6
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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			  int lane_count);
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			  int lane_count);
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
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	struct i2c_adapter ddc;
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	struct i2c_adapter ddc;
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	struct device *dev;
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	struct device *dev;
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	struct mutex hw_mutex;
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	struct mutex hw_mutex;
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	ssize_t (*transfer)(struct drm_dp_aux *aux,
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	ssize_t (*transfer)(struct drm_dp_aux *aux,
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			    struct drm_dp_aux_msg *msg);
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			    struct drm_dp_aux_msg *msg);
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	unsigned i2c_nack_count, i2c_defer_count;
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};
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};
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ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
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ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
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			 void *buffer, size_t size);
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			 void *buffer, size_t size);