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| Rev 4103 | Rev 4559 | ||
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| Line 39... | Line 39... | ||
| 39 | * 1.2: DisplayPort 1.2 |
39 | * 1.2: DisplayPort 1.2 |
| 40 | * |
40 | * |
| 41 | * 1.2 formally includes both eDP and DPI definitions. |
41 | * 1.2 formally includes both eDP and DPI definitions. |
| 42 | */ |
42 | */ |
| Line 43... | Line 43... | ||
| 43 | 43 | ||
| 44 | #define AUX_NATIVE_WRITE 0x8 |
44 | #define DP_AUX_I2C_WRITE 0x0 |
| 45 | #define AUX_NATIVE_READ 0x9 |
45 | #define DP_AUX_I2C_READ 0x1 |
| 46 | #define AUX_I2C_WRITE 0x0 |
46 | #define DP_AUX_I2C_STATUS 0x2 |
| 47 | #define AUX_I2C_READ 0x1 |
47 | #define DP_AUX_I2C_MOT 0x4 |
| 48 | #define AUX_I2C_STATUS 0x2 |
48 | #define DP_AUX_NATIVE_WRITE 0x8 |
| 49 | #define AUX_I2C_MOT 0x4 |
49 | #define DP_AUX_NATIVE_READ 0x9 |
| 50 | 50 | ||
| 51 | #define AUX_NATIVE_REPLY_ACK (0x0 << 4) |
51 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
| 52 | #define AUX_NATIVE_REPLY_NACK (0x1 << 4) |
52 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
| 53 | #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) |
53 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
| 54 | #define AUX_NATIVE_REPLY_MASK (0x3 << 4) |
54 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
| 55 | 55 | ||
| 56 | #define AUX_I2C_REPLY_ACK (0x0 << 6) |
56 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
| 57 | #define AUX_I2C_REPLY_NACK (0x1 << 6) |
57 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
| 58 | #define AUX_I2C_REPLY_DEFER (0x2 << 6) |
58 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
| Line 59... | Line 59... | ||
| 59 | #define AUX_I2C_REPLY_MASK (0x3 << 6) |
59 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
| 60 | 60 | ||
| 61 | /* AUX CH addresses */ |
61 | /* AUX CH addresses */ |
| Line 75... | Line 75... | ||
| 75 | #define DP_NORP 0x004 |
75 | #define DP_NORP 0x004 |
| Line 76... | Line 76... | ||
| 76 | 76 | ||
| 77 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
77 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
| 78 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
78 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
| 79 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
79 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
| 80 | /* 00b = DisplayPort */ |
80 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
| 81 | /* 01b = Analog */ |
81 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
| 82 | /* 10b = TMDS or HDMI */ |
82 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
| 83 | /* 11b = Other */ |
83 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
| 84 | # define DP_FORMAT_CONVERSION (1 << 3) |
84 | # define DP_FORMAT_CONVERSION (1 << 3) |
| Line 85... | Line 85... | ||
| 85 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
85 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
| Line 264... | Line 264... | ||
| 264 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
264 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
| 265 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
265 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
| Line 266... | Line 266... | ||
| 266 | 266 | ||
| 267 | #define DP_TEST_REQUEST 0x218 |
267 | #define DP_TEST_REQUEST 0x218 |
| 268 | # define DP_TEST_LINK_TRAINING (1 << 0) |
268 | # define DP_TEST_LINK_TRAINING (1 << 0) |
| 269 | # define DP_TEST_LINK_PATTERN (1 << 1) |
269 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
| 270 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
270 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
| - | 271 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
|
| Line 271... | Line 272... | ||
| 271 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
272 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
| 272 | 273 | ||
| 273 | #define DP_TEST_LINK_RATE 0x219 |
274 | #define DP_TEST_LINK_RATE 0x219 |
| Line 331... | Line 332... | ||
| 331 | int |
332 | int |
| 332 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
333 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
| Line 333... | Line 334... | ||
| 333 | 334 | ||
| 334 | 335 | ||
| 335 | #define DP_LINK_STATUS_SIZE 6 |
336 | #define DP_LINK_STATUS_SIZE 6 |
| 336 | bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
337 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
| 337 | int lane_count); |
338 | int lane_count); |
| 338 | bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
339 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
| 339 | int lane_count); |
340 | int lane_count); |
| 340 | u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
341 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
| 341 | int lane); |
342 | int lane); |
| Line 342... | Line 343... | ||
| 342 | u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
343 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
| 343 | int lane); |
344 | int lane); |
| Line 344... | Line 345... | ||
| 344 | 345 | ||
| 345 | #define DP_RECEIVER_CAP_SIZE 0xf |
346 | #define DP_RECEIVER_CAP_SIZE 0xf |
| Line 346... | Line 347... | ||
| 346 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
347 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
| 347 | 348 | ||
| Line 348... | Line 349... | ||
| 348 | void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
349 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| Line 377... | Line 378... | ||
| 377 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
378 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
| 378 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
379 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
| 379 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
380 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
| Line 380... | Line 381... | ||
| 380 | 381 | ||
| 381 | static inline int |
382 | static inline int |
| 382 | drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
383 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| 383 | { |
384 | { |
| 384 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
385 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
| Line 385... | Line 386... | ||
| 385 | } |
386 | } |
| 386 | 387 | ||
| 387 | static inline u8 |
388 | static inline u8 |
| 388 | drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
389 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| 389 | { |
390 | { |
| Line -... | Line 391... | ||
| - | 391 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
|
| - | 392 | } |
|
| - | 393 | ||
| - | 394 | static inline bool |
|
| - | 395 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
|
| - | 396 | { |
|
| - | 397 | return dpcd[DP_DPCD_REV] >= 0x11 && |
|
| 390 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
398 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |