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Rev 3192 Rev 4103
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				     int lane);
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				     int lane);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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					  int lane);
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					  int lane);
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#define DP_RECEIVER_CAP_SIZE	0xf
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#define EDP_PSR_RECEIVER_CAP_SIZE	2
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#define DP_RECEIVER_CAP_SIZE	0xf
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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struct edp_sdp_header {
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	u8 HB0; /* Secondary Data Packet ID */
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	u8 HB1; /* Secondary Data Packet Type */
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	u8 HB2; /* 7:5 reserved, 4:0 revision number */
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	u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
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} __packed;
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#define EDP_SDP_HEADER_REVISION_MASK		0x1F
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#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES	0x1F
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struct edp_vsc_psr {
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	struct edp_sdp_header sdp_header;
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	u8 DB0; /* Stereo Interface */
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	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
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	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
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	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
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	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
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	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
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	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
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	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
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	u8 DB8_31[24]; /* Reserved */
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} __packed;
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#define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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#define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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#define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
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static inline int
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static inline int
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drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])