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| 23 | #ifndef _DRM_DP_HELPER_H_ |
23 | #ifndef _DRM_DP_HELPER_H_ |
| 24 | #define _DRM_DP_HELPER_H_ |
24 | #define _DRM_DP_HELPER_H_ |
| Line 25... | Line 25... | ||
| 25 | 25 | ||
| 26 | #include |
26 | #include |
| - | 27 | #include |
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| Line 27... | Line 28... | ||
| 27 | #include |
28 | #include |
| 28 | 29 | ||
| 29 | /* |
30 | /* |
| 30 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
| Line 309... | Line 310... | ||
| 309 | #define MODE_I2C_START 1 |
310 | #define MODE_I2C_START 1 |
| 310 | #define MODE_I2C_WRITE 2 |
311 | #define MODE_I2C_WRITE 2 |
| 311 | #define MODE_I2C_READ 4 |
312 | #define MODE_I2C_READ 4 |
| 312 | #define MODE_I2C_STOP 8 |
313 | #define MODE_I2C_STOP 8 |
| Line -... | Line 314... | ||
| - | 314 | ||
| - | 315 | /** |
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| - | 316 | * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp |
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| - | 317 | * aux algorithm |
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| - | 318 | * @running: set by the algo indicating whether an i2c is ongoing or whether |
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| - | 319 | * the i2c bus is quiescent |
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| - | 320 | * @address: i2c target address for the currently ongoing transfer |
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| - | 321 | * @aux_ch: driver callback to transfer a single byte of the i2c payload |
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| 313 | 322 | */ |
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| 314 | struct i2c_algo_dp_aux_data { |
323 | struct i2c_algo_dp_aux_data { |
| 315 | bool running; |
324 | bool running; |
| 316 | u16 address; |
325 | u16 address; |
| 317 | int (*aux_ch) (struct i2c_adapter *adapter, |
326 | int (*aux_ch) (struct i2c_adapter *adapter, |
| Line 320... | Line 329... | ||
| 320 | }; |
329 | }; |
| Line 321... | Line 330... | ||
| 321 | 330 | ||
| 322 | int |
331 | int |
| Line -... | Line 332... | ||
| - | 332 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
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| - | 333 | ||
| - | 334 | ||
| - | 335 | #define DP_LINK_STATUS_SIZE 6 |
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| - | 336 | bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
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| - | 337 | int lane_count); |
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| - | 338 | bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
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| - | 339 | int lane_count); |
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| - | 340 | u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
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| - | 341 | int lane); |
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| - | 342 | u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
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| - | 343 | int lane); |
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| - | 344 | ||
| - | 345 | #define DP_RECEIVER_CAP_SIZE 0xf |
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| - | 346 | void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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| - | 347 | void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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| - | 348 | ||
| - | 349 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
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| - | 350 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
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| - | 351 | ||
| - | 352 | static inline int |
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| - | 353 | drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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| - | 354 | { |
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| - | 355 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
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| - | 356 | } |
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| - | 357 | ||
| - | 358 | static inline u8 |
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| - | 359 | drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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| - | 360 | { |
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| - | 361 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
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| 323 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
362 | } |