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1 | #ifndef _ASM_X86_IO_H |
1 | #ifndef _ASM_X86_IO_H |
2 | #define _ASM_X86_IO_H |
2 | #define _ASM_X86_IO_H |
3 | 3 | ||
4 | /* |
4 | /* |
5 | * This file contains the definitions for the x86 IO instructions |
5 | * This file contains the definitions for the x86 IO instructions |
6 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same |
6 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same |
7 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" |
7 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" |
8 | * versions of the single-IO instructions (inb_p/inw_p/..). |
8 | * versions of the single-IO instructions (inb_p/inw_p/..). |
9 | * |
9 | * |
10 | * This file is not meant to be obfuscating: it's just complicated |
10 | * This file is not meant to be obfuscating: it's just complicated |
11 | * to (a) handle it all in a way that makes gcc able to optimize it |
11 | * to (a) handle it all in a way that makes gcc able to optimize it |
12 | * as well as possible and (b) trying to avoid writing the same thing |
12 | * as well as possible and (b) trying to avoid writing the same thing |
13 | * over and over again with slight variations and possibly making a |
13 | * over and over again with slight variations and possibly making a |
14 | * mistake somewhere. |
14 | * mistake somewhere. |
15 | */ |
15 | */ |
16 | 16 | ||
17 | /* |
17 | /* |
18 | * Thanks to James van Artsdalen for a better timing-fix than |
18 | * Thanks to James van Artsdalen for a better timing-fix than |
19 | * the two short jumps: using outb's to a nonexistent port seems |
19 | * the two short jumps: using outb's to a nonexistent port seems |
20 | * to guarantee better timings even on fast machines. |
20 | * to guarantee better timings even on fast machines. |
21 | * |
21 | * |
22 | * On the other hand, I'd like to be sure of a non-existent port: |
22 | * On the other hand, I'd like to be sure of a non-existent port: |
23 | * I feel a bit unsafe about using 0x80 (should be safe, though) |
23 | * I feel a bit unsafe about using 0x80 (should be safe, though) |
24 | * |
24 | * |
25 | * Linus |
25 | * Linus |
26 | */ |
26 | */ |
27 | 27 | ||
28 | /* |
28 | /* |
29 | * Bit simplified and optimized by Jan Hubicka |
29 | * Bit simplified and optimized by Jan Hubicka |
30 | * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. |
30 | * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. |
31 | * |
31 | * |
32 | * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, |
32 | * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, |
33 | * isa_read[wl] and isa_write[wl] fixed |
33 | * isa_read[wl] and isa_write[wl] fixed |
34 | * - Arnaldo Carvalho de Melo |
34 | * - Arnaldo Carvalho de Melo |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #define ARCH_HAS_IOREMAP_WC |
37 | #define ARCH_HAS_IOREMAP_WC |
38 | #define ARCH_HAS_IOREMAP_WT |
38 | #define ARCH_HAS_IOREMAP_WT |
39 | 39 | ||
40 | #include |
40 | #include |
41 | #include |
41 | #include |
42 | 42 | ||
43 | #define build_mmio_read(name, size, type, reg, barrier) \ |
43 | #define build_mmio_read(name, size, type, reg, barrier) \ |
44 | static inline type name(const volatile void __iomem *addr) \ |
44 | static inline type name(const volatile void __iomem *addr) \ |
45 | { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ |
45 | { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ |
46 | :"m" (*(volatile type __force *)addr) barrier); return ret; } |
46 | :"m" (*(volatile type __force *)addr) barrier); return ret; } |
47 | 47 | ||
48 | #define build_mmio_write(name, size, type, reg, barrier) \ |
48 | #define build_mmio_write(name, size, type, reg, barrier) \ |
49 | static inline void name(type val, volatile void __iomem *addr) \ |
49 | static inline void name(type val, volatile void __iomem *addr) \ |
50 | { asm volatile("mov" size " %0,%1": :reg (val), \ |
50 | { asm volatile("mov" size " %0,%1": :reg (val), \ |
51 | "m" (*(volatile type __force *)addr) barrier); } |
51 | "m" (*(volatile type __force *)addr) barrier); } |
52 | 52 | ||
53 | build_mmio_read(readb, "b", unsigned char, "=q", :"memory") |
53 | build_mmio_read(readb, "b", unsigned char, "=q", :"memory") |
54 | build_mmio_read(readw, "w", unsigned short, "=r", :"memory") |
54 | build_mmio_read(readw, "w", unsigned short, "=r", :"memory") |
55 | build_mmio_read(readl, "l", unsigned int, "=r", :"memory") |
55 | build_mmio_read(readl, "l", unsigned int, "=r", :"memory") |
56 | 56 | ||
57 | build_mmio_read(__readb, "b", unsigned char, "=q", ) |
57 | build_mmio_read(__readb, "b", unsigned char, "=q", ) |
58 | build_mmio_read(__readw, "w", unsigned short, "=r", ) |
58 | build_mmio_read(__readw, "w", unsigned short, "=r", ) |
59 | build_mmio_read(__readl, "l", unsigned int, "=r", ) |
59 | build_mmio_read(__readl, "l", unsigned int, "=r", ) |
60 | 60 | ||
61 | build_mmio_write(writeb, "b", unsigned char, "q", :"memory") |
61 | build_mmio_write(writeb, "b", unsigned char, "q", :"memory") |
62 | build_mmio_write(writew, "w", unsigned short, "r", :"memory") |
62 | build_mmio_write(writew, "w", unsigned short, "r", :"memory") |
63 | build_mmio_write(writel, "l", unsigned int, "r", :"memory") |
63 | build_mmio_write(writel, "l", unsigned int, "r", :"memory") |
64 | 64 | ||
65 | build_mmio_write(__writeb, "b", unsigned char, "q", ) |
65 | build_mmio_write(__writeb, "b", unsigned char, "q", ) |
66 | build_mmio_write(__writew, "w", unsigned short, "r", ) |
66 | build_mmio_write(__writew, "w", unsigned short, "r", ) |
67 | build_mmio_write(__writel, "l", unsigned int, "r", ) |
67 | build_mmio_write(__writel, "l", unsigned int, "r", ) |
68 | 68 | ||
69 | #define readb_relaxed(a) __readb(a) |
69 | #define readb_relaxed(a) __readb(a) |
70 | #define readw_relaxed(a) __readw(a) |
70 | #define readw_relaxed(a) __readw(a) |
71 | #define readl_relaxed(a) __readl(a) |
71 | #define readl_relaxed(a) __readl(a) |
72 | #define __raw_readb __readb |
72 | #define __raw_readb __readb |
73 | #define __raw_readw __readw |
73 | #define __raw_readw __readw |
74 | #define __raw_readl __readl |
74 | #define __raw_readl __readl |
75 | 75 | ||
76 | #define writeb_relaxed(v, a) __writeb(v, a) |
76 | #define writeb_relaxed(v, a) __writeb(v, a) |
77 | #define writew_relaxed(v, a) __writew(v, a) |
77 | #define writew_relaxed(v, a) __writew(v, a) |
78 | #define writel_relaxed(v, a) __writel(v, a) |
78 | #define writel_relaxed(v, a) __writel(v, a) |
79 | #define __raw_writeb __writeb |
79 | #define __raw_writeb __writeb |
80 | #define __raw_writew __writew |
80 | #define __raw_writew __writew |
81 | #define __raw_writel __writel |
81 | #define __raw_writel __writel |
82 | 82 | ||
83 | #define mmiowb() barrier() |
83 | #define mmiowb() barrier() |
84 | 84 | ||
85 | #ifdef CONFIG_X86_64 |
85 | #ifdef CONFIG_X86_64 |
86 | 86 | ||
87 | build_mmio_read(readq, "q", unsigned long, "=r", :"memory") |
87 | build_mmio_read(readq, "q", unsigned long, "=r", :"memory") |
88 | build_mmio_write(writeq, "q", unsigned long, "r", :"memory") |
88 | build_mmio_write(writeq, "q", unsigned long, "r", :"memory") |
89 | 89 | ||
90 | #define readq_relaxed(a) readq(a) |
90 | #define readq_relaxed(a) readq(a) |
91 | #define writeq_relaxed(v, a) writeq(v, a) |
91 | #define writeq_relaxed(v, a) writeq(v, a) |
92 | 92 | ||
93 | #define __raw_readq(a) readq(a) |
93 | #define __raw_readq(a) readq(a) |
94 | #define __raw_writeq(val, addr) writeq(val, addr) |
94 | #define __raw_writeq(val, addr) writeq(val, addr) |
95 | 95 | ||
96 | /* Let people know that we have them */ |
96 | /* Let people know that we have them */ |
97 | #define readq readq |
97 | #define readq readq |
98 | #define writeq writeq |
98 | #define writeq writeq |
99 | 99 | ||
100 | #endif |
100 | #endif |
101 | 101 | ||
102 | /** |
102 | /** |
103 | * virt_to_phys - map virtual addresses to physical |
103 | * virt_to_phys - map virtual addresses to physical |
104 | * @address: address to remap |
104 | * @address: address to remap |
105 | * |
105 | * |
106 | * The returned physical address is the physical (CPU) mapping for |
106 | * The returned physical address is the physical (CPU) mapping for |
107 | * the memory address given. It is only valid to use this function on |
107 | * the memory address given. It is only valid to use this function on |
108 | * addresses directly mapped or allocated via kmalloc. |
108 | * addresses directly mapped or allocated via kmalloc. |
109 | * |
109 | * |
110 | * This function does not give bus mappings for DMA transfers. In |
110 | * This function does not give bus mappings for DMA transfers. In |
111 | * almost all conceivable cases a device driver should not be using |
111 | * almost all conceivable cases a device driver should not be using |
112 | * this function |
112 | * this function |
113 | */ |
113 | */ |
114 | 114 | ||
115 | 115 | ||
116 | /** |
116 | /** |
117 | * phys_to_virt - map physical address to virtual |
117 | * phys_to_virt - map physical address to virtual |
118 | * @address: address to remap |
118 | * @address: address to remap |
119 | * |
119 | * |
120 | * The returned virtual address is a current CPU mapping for |
120 | * The returned virtual address is a current CPU mapping for |
121 | * the memory address given. It is only valid to use this function on |
121 | * the memory address given. It is only valid to use this function on |
122 | * addresses that have a kernel mapping |
122 | * addresses that have a kernel mapping |
123 | * |
123 | * |
124 | * This function does not handle bus mappings for DMA transfers. In |
124 | * This function does not handle bus mappings for DMA transfers. In |
125 | * almost all conceivable cases a device driver should not be using |
125 | * almost all conceivable cases a device driver should not be using |
126 | * this function |
126 | * this function |
127 | */ |
127 | */ |
128 | 128 | ||
129 | #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) |
129 | #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) |
130 | #define isa_bus_to_virt phys_to_virt |
130 | #define isa_bus_to_virt phys_to_virt |
131 | 131 | ||
132 | /* |
132 | /* |
133 | * However PCI ones are not necessarily 1:1 and therefore these interfaces |
133 | * However PCI ones are not necessarily 1:1 and therefore these interfaces |
134 | * are forbidden in portable PCI drivers. |
134 | * are forbidden in portable PCI drivers. |
135 | * |
135 | * |
136 | * Allow them on x86 for legacy drivers, though. |
136 | * Allow them on x86 for legacy drivers, though. |
137 | */ |
137 | */ |
138 | #define virt_to_bus virt_to_phys |
138 | #define virt_to_bus virt_to_phys |
139 | #define bus_to_virt phys_to_virt |
139 | #define bus_to_virt phys_to_virt |
140 | 140 | ||
141 | /** |
141 | /** |
142 | * ioremap - map bus memory into CPU space |
142 | * ioremap - map bus memory into CPU space |
143 | * @offset: bus address of the memory |
143 | * @offset: bus address of the memory |
144 | * @size: size of the resource to map |
144 | * @size: size of the resource to map |
145 | * |
145 | * |
146 | * ioremap performs a platform specific sequence of operations to |
146 | * ioremap performs a platform specific sequence of operations to |
147 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
147 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
148 | * writew/writel functions and the other mmio helpers. The returned |
148 | * writew/writel functions and the other mmio helpers. The returned |
149 | * address is not guaranteed to be usable directly as a virtual |
149 | * address is not guaranteed to be usable directly as a virtual |
150 | * address. |
150 | * address. |
151 | * |
151 | * |
152 | * If the area you are trying to map is a PCI BAR you should have a |
152 | * If the area you are trying to map is a PCI BAR you should have a |
153 | * look at pci_iomap(). |
153 | * look at pci_iomap(). |
154 | */ |
154 | */ |
155 | //extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); |
155 | extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); |
156 | extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); |
156 | extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); |
157 | #define ioremap_uc ioremap_uc |
157 | #define ioremap_uc ioremap_uc |
158 | 158 | ||
159 | extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); |
159 | extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); |
160 | extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, |
160 | extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, |
161 | unsigned long prot_val); |
161 | unsigned long prot_val); |
162 | 162 | ||
163 | /* |
163 | /* |
164 | * The default ioremap() behavior is non-cached: |
164 | * The default ioremap() behavior is non-cached: |
165 | */ |
165 | */ |
166 | //static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) |
166 | static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) |
167 | //{ |
167 | { |
168 | // return ioremap_nocache(offset, size); |
168 | return ioremap_nocache(offset, size); |
169 | //} |
169 | } |
170 | 170 | ||
171 | //extern void iounmap(volatile void __iomem *addr); |
171 | extern void iounmap(volatile void __iomem *addr); |
172 | 172 | ||
173 | extern void set_iounmap_nonlazy(void); |
173 | extern void set_iounmap_nonlazy(void); |
174 | 174 | ||
175 | #ifdef __KERNEL__ |
175 | #ifdef __KERNEL__ |
176 | 176 | ||
177 | #include |
177 | #include |
178 | 178 | ||
179 | /* |
179 | /* |
180 | * Convert a virtual cached pointer to an uncached pointer |
180 | * Convert a virtual cached pointer to an uncached pointer |
181 | */ |
181 | */ |
182 | #define xlate_dev_kmem_ptr(p) p |
182 | #define xlate_dev_kmem_ptr(p) p |
183 | 183 | ||
184 | static inline void |
184 | static inline void |
185 | memset_io(volatile void __iomem *addr, unsigned char val, size_t count) |
185 | memset_io(volatile void __iomem *addr, unsigned char val, size_t count) |
186 | { |
186 | { |
187 | memset((void __force *)addr, val, count); |
187 | memset((void __force *)addr, val, count); |
188 | } |
188 | } |
189 | 189 | ||
190 | static inline void |
190 | static inline void |
191 | memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) |
191 | memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) |
192 | { |
192 | { |
193 | memcpy(dst, (const void __force *)src, count); |
193 | memcpy(dst, (const void __force *)src, count); |
194 | } |
194 | } |
195 | 195 | ||
196 | static inline void |
196 | static inline void |
197 | memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) |
197 | memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) |
198 | { |
198 | { |
199 | memcpy((void __force *)dst, src, count); |
199 | memcpy((void __force *)dst, src, count); |
200 | } |
200 | } |
201 | 201 | ||
202 | /* |
202 | /* |
203 | * ISA space is 'always mapped' on a typical x86 system, no need to |
203 | * ISA space is 'always mapped' on a typical x86 system, no need to |
204 | * explicitly ioremap() it. The fact that the ISA IO space is mapped |
204 | * explicitly ioremap() it. The fact that the ISA IO space is mapped |
205 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
205 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
206 | * are physical addresses. The following constant pointer can be |
206 | * are physical addresses. The following constant pointer can be |
207 | * used as the IO-area pointer (it can be iounmapped as well, so the |
207 | * used as the IO-area pointer (it can be iounmapped as well, so the |
208 | * analogy with PCI is quite large): |
208 | * analogy with PCI is quite large): |
209 | */ |
209 | */ |
210 | #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) |
210 | #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) |
211 | 211 | ||
212 | /* |
212 | /* |
213 | * Cache management |
213 | * Cache management |
214 | * |
214 | * |
215 | * This needed for two cases |
215 | * This needed for two cases |
216 | * 1. Out of order aware processors |
216 | * 1. Out of order aware processors |
217 | * 2. Accidentally out of order processors (PPro errata #51) |
217 | * 2. Accidentally out of order processors (PPro errata #51) |
218 | */ |
218 | */ |
219 | 219 | ||
220 | static inline void flush_write_buffers(void) |
220 | static inline void flush_write_buffers(void) |
221 | { |
221 | { |
222 | #if defined(CONFIG_X86_PPRO_FENCE) |
222 | #if defined(CONFIG_X86_PPRO_FENCE) |
223 | asm volatile("lock; addl $0,0(%%esp)": : :"memory"); |
223 | asm volatile("lock; addl $0,0(%%esp)": : :"memory"); |
224 | #endif |
224 | #endif |
225 | } |
225 | } |
226 | 226 | ||
227 | #endif /* __KERNEL__ */ |
227 | #endif /* __KERNEL__ */ |
228 | 228 | ||
229 | extern void native_io_delay(void); |
229 | extern void native_io_delay(void); |
230 | 230 | ||
231 | extern int io_delay_type; |
231 | extern int io_delay_type; |
232 | extern void io_delay_init(void); |
232 | extern void io_delay_init(void); |
233 | 233 | ||
234 | #if defined(CONFIG_PARAVIRT) |
234 | #if defined(CONFIG_PARAVIRT) |
235 | #include |
235 | #include |
236 | #else |
236 | #else |
237 | 237 | ||
238 | static inline void slow_down_io(void) |
238 | static inline void slow_down_io(void) |
239 | { |
239 | { |
240 | native_io_delay(); |
240 | native_io_delay(); |
241 | #ifdef REALLY_SLOW_IO |
241 | #ifdef REALLY_SLOW_IO |
242 | native_io_delay(); |
242 | native_io_delay(); |
243 | native_io_delay(); |
243 | native_io_delay(); |
244 | native_io_delay(); |
244 | native_io_delay(); |
245 | #endif |
245 | #endif |
246 | } |
246 | } |
247 | 247 | ||
248 | #endif |
248 | #endif |
249 | 249 | ||
250 | #define BUILDIO(bwl, bw, type) \ |
250 | #define BUILDIO(bwl, bw, type) \ |
251 | static inline void out##bwl(unsigned type value, int port) \ |
251 | static inline void out##bwl(unsigned type value, int port) \ |
252 | { \ |
252 | { \ |
253 | asm volatile("out" #bwl " %" #bw "0, %w1" \ |
253 | asm volatile("out" #bwl " %" #bw "0, %w1" \ |
254 | : : "a"(value), "Nd"(port)); \ |
254 | : : "a"(value), "Nd"(port)); \ |
255 | } \ |
255 | } \ |
256 | \ |
256 | \ |
257 | static inline unsigned type in##bwl(int port) \ |
257 | static inline unsigned type in##bwl(int port) \ |
258 | { \ |
258 | { \ |
259 | unsigned type value; \ |
259 | unsigned type value; \ |
260 | asm volatile("in" #bwl " %w1, %" #bw "0" \ |
260 | asm volatile("in" #bwl " %w1, %" #bw "0" \ |
261 | : "=a"(value) : "Nd"(port)); \ |
261 | : "=a"(value) : "Nd"(port)); \ |
262 | return value; \ |
262 | return value; \ |
263 | } \ |
263 | } \ |
264 | \ |
264 | \ |
265 | static inline void out##bwl##_p(unsigned type value, int port) \ |
265 | static inline void out##bwl##_p(unsigned type value, int port) \ |
266 | { \ |
266 | { \ |
267 | out##bwl(value, port); \ |
267 | out##bwl(value, port); \ |
268 | slow_down_io(); \ |
268 | slow_down_io(); \ |
269 | } \ |
269 | } \ |
270 | \ |
270 | \ |
271 | static inline unsigned type in##bwl##_p(int port) \ |
271 | static inline unsigned type in##bwl##_p(int port) \ |
272 | { \ |
272 | { \ |
273 | unsigned type value = in##bwl(port); \ |
273 | unsigned type value = in##bwl(port); \ |
274 | slow_down_io(); \ |
274 | slow_down_io(); \ |
275 | return value; \ |
275 | return value; \ |
276 | } \ |
276 | } \ |
277 | \ |
277 | \ |
278 | static inline void outs##bwl(int port, const void *addr, unsigned long count) \ |
278 | static inline void outs##bwl(int port, const void *addr, unsigned long count) \ |
279 | { \ |
279 | { \ |
280 | asm volatile("rep; outs" #bwl \ |
280 | asm volatile("rep; outs" #bwl \ |
281 | : "+S"(addr), "+c"(count) : "d"(port)); \ |
281 | : "+S"(addr), "+c"(count) : "d"(port)); \ |
282 | } \ |
282 | } \ |
283 | \ |
283 | \ |
284 | static inline void ins##bwl(int port, void *addr, unsigned long count) \ |
284 | static inline void ins##bwl(int port, void *addr, unsigned long count) \ |
285 | { \ |
285 | { \ |
286 | asm volatile("rep; ins" #bwl \ |
286 | asm volatile("rep; ins" #bwl \ |
287 | : "+D"(addr), "+c"(count) : "d"(port)); \ |
287 | : "+D"(addr), "+c"(count) : "d"(port)); \ |
288 | } |
288 | } |
289 | 289 | ||
290 | BUILDIO(b, b, char) |
290 | BUILDIO(b, b, char) |
291 | BUILDIO(w, w, short) |
291 | BUILDIO(w, w, short) |
292 | BUILDIO(l, , int) |
292 | BUILDIO(l, , int) |
293 | 293 | ||
294 | extern void *xlate_dev_mem_ptr(phys_addr_t phys); |
294 | extern void *xlate_dev_mem_ptr(phys_addr_t phys); |
295 | extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); |
295 | extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); |
296 | 296 | ||
297 | extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, |
297 | extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, |
298 | enum page_cache_mode pcm); |
298 | enum page_cache_mode pcm); |
299 | //extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); |
299 | extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); |
300 | extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); |
300 | extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); |
301 | 301 | ||
302 | extern bool is_early_ioremap_ptep(pte_t *ptep); |
302 | extern bool is_early_ioremap_ptep(pte_t *ptep); |
303 | 303 | ||
304 | #ifdef CONFIG_XEN |
304 | #ifdef CONFIG_XEN |
305 | #include |
305 | #include |
306 | struct bio_vec; |
306 | struct bio_vec; |
307 | 307 | ||
308 | extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
308 | extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
309 | const struct bio_vec *vec2); |
309 | const struct bio_vec *vec2); |
310 | 310 | ||
311 | #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ |
311 | #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ |
312 | (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ |
312 | (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ |
313 | (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) |
313 | (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) |
314 | #endif /* CONFIG_XEN */ |
314 | #endif /* CONFIG_XEN */ |
315 | 315 | ||
316 | #define IO_SPACE_LIMIT 0xffff |
316 | #define IO_SPACE_LIMIT 0xffff |
317 | 317 | ||
318 | #ifdef CONFIG_MTRR |
318 | #ifdef CONFIG_MTRR |
319 | extern int __must_check arch_phys_wc_index(int handle); |
319 | extern int __must_check arch_phys_wc_index(int handle); |
320 | #define arch_phys_wc_index arch_phys_wc_index |
320 | #define arch_phys_wc_index arch_phys_wc_index |
321 | 321 | ||
322 | extern int __must_check arch_phys_wc_add(unsigned long base, |
322 | extern int __must_check arch_phys_wc_add(unsigned long base, |
323 | unsigned long size); |
323 | unsigned long size); |
324 | extern void arch_phys_wc_del(int handle); |
324 | extern void arch_phys_wc_del(int handle); |
325 | #define arch_phys_wc_add arch_phys_wc_add |
325 | #define arch_phys_wc_add arch_phys_wc_add |
326 | #endif |
326 | #endif |
327 | 327 | ||
328 | #endif /* _ASM_X86_IO_H */ |
328 | #endif /* _ASM_X86_IO_H */ |