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10 | 10 | ||
11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
12 | #include |
12 | #include |
Line 13... | Line 13... | ||
13 | #endif |
13 | #endif |
14 | 14 | ||
Line 15... | Line 15... | ||
15 | #define NCAPINTS 14 /* N 32-bit words worth of info */ |
15 | #define NCAPINTS 16 /* N 32-bit words worth of info */ |
16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
17 | 17 | ||
Line 179... | Line 179... | ||
179 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
179 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
180 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ |
180 | #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ |
Line 181... | Line 181... | ||
181 | 181 | ||
182 | /* |
182 | /* |
183 | * Auxiliary flags: Linux defined - For features scattered in various |
183 | * Auxiliary flags: Linux defined - For features scattered in various |
- | 184 | * CPUID levels like 0x6, 0xA etc, word 7. |
|
- | 185 | * |
|
184 | * CPUID levels like 0x6, 0xA etc, word 7 |
186 | * Reuse free bits when adding new feature flags! |
185 | */ |
- | |
186 | #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
- | |
- | 187 | */ |
|
187 | #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ |
188 | |
188 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
189 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
189 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
- | |
190 | #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
- | |
191 | #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ |
- | |
- | 190 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
|
192 | #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ |
191 | |
193 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
192 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
194 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
- | |
195 | #define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ |
- | |
196 | #define X86_FEATURE_HWP_NOTIFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ |
- | |
197 | #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ |
- | |
198 | #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ |
- | |
- | 193 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
|
199 | #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ |
194 | |
Line 200... | Line 195... | ||
200 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
195 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
201 | 196 | ||
202 | /* Virtualization flags: Linux defined, word 8 */ |
197 | /* Virtualization flags: Linux defined, word 8 */ |
203 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
198 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
204 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
199 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
205 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
200 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
206 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
- | |
207 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
- | |
208 | #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ |
- | |
209 | #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ |
- | |
210 | #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
- | |
211 | #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
- | |
212 | #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
- | |
213 | #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
- | |
214 | #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ |
- | |
215 | #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ |
- | |
- | 201 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
|
216 | #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ |
202 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
217 | #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ |
203 | |
Line 218... | Line 204... | ||
218 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
204 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
Line 257... | Line 243... | ||
257 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ |
243 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ |
Line 258... | Line 244... | ||
258 | 244 | ||
259 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ |
245 | /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ |
Line -... | Line 246... | ||
- | 246 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ |
|
- | 247 | ||
- | 248 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */ |
|
- | 249 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
|
- | 250 | #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */ |
|
- | 251 | #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */ |
|
- | 252 | #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */ |
|
- | 253 | #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */ |
|
- | 254 | #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */ |
|
- | 255 | #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */ |
|
- | 256 | #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ |
|
- | 257 | #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ |
|
- | 258 | #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ |
|
- | 259 | ||
- | 260 | /* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */ |
|
- | 261 | #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ |
|
- | 262 | #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */ |
|
- | 263 | #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */ |
|
- | 264 | #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */ |
|
- | 265 | #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */ |
|
- | 266 | #define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */ |
|
- | 267 | #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */ |
|
- | 268 | #define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */ |
|
- | 269 | #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */ |
|
260 | #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ |
270 | #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */ |
261 | 271 | ||
262 | /* |
272 | /* |
263 | * BUG word(s) |
273 | * BUG word(s) |
Line 277... | Line 287... | ||
277 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
287 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
Line 278... | Line 288... | ||
278 | 288 | ||
279 | #include |
289 | #include |
Line -... | Line 290... | ||
- | 290 | #include |
|
- | 291 | ||
- | 292 | enum cpuid_leafs |
|
- | 293 | { |
|
- | 294 | CPUID_1_EDX = 0, |
|
- | 295 | CPUID_8000_0001_EDX, |
|
- | 296 | CPUID_8086_0001_EDX, |
|
- | 297 | CPUID_LNX_1, |
|
- | 298 | CPUID_1_ECX, |
|
- | 299 | CPUID_C000_0001_EDX, |
|
- | 300 | CPUID_8000_0001_ECX, |
|
- | 301 | CPUID_LNX_2, |
|
- | 302 | CPUID_LNX_3, |
|
- | 303 | CPUID_7_0_EBX, |
|
- | 304 | CPUID_D_1_EAX, |
|
- | 305 | CPUID_F_0_EDX, |
|
- | 306 | CPUID_F_1_EDX, |
|
- | 307 | CPUID_8000_0008_EBX, |
|
- | 308 | CPUID_6_EAX, |
|
- | 309 | CPUID_8000_000A_EDX, |
|
280 | #include |
310 | }; |
281 | 311 | ||
282 | #ifdef CONFIG_X86_FEATURE_NAMES |
312 | #ifdef CONFIG_X86_FEATURE_NAMES |
283 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
313 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
284 | extern const char * const x86_power_flags[32]; |
314 | extern const char * const x86_power_flags[32]; |
Line 354... | Line 384... | ||
354 | set_cpu_cap(&boot_cpu_data, bit); \ |
384 | set_cpu_cap(&boot_cpu_data, bit); \ |
355 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
385 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
356 | } while (0) |
386 | } while (0) |
Line 357... | Line 387... | ||
357 | 387 | ||
358 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
- | |
359 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
388 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
360 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
389 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
361 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
390 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
362 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
391 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
363 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
- | |
364 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
- | |
365 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
- | |
366 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
392 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
367 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
393 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
368 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
394 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
369 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
- | |
370 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
- | |
371 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
395 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
372 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
396 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
373 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
397 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
374 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
- | |
375 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
- | |
376 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
- | |
377 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
- | |
378 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
- | |
379 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
- | |
380 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
- | |
381 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
- | |
382 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
- | |
383 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
- | |
384 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
- | |
385 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
- | |
386 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
- | |
387 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
- | |
388 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
398 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
389 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
- | |
390 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
399 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
391 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
400 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
392 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
401 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
393 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
- | |
394 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
- | |
395 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
402 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
396 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
403 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
397 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
- | |
398 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
404 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
399 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
405 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
400 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
406 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
- | 407 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
|
401 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
408 | /* |
402 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
- | |
403 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
- | |
404 | #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
- | |
405 | #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
409 | * Do not add any more of those clumsy macros - use static_cpu_has_safe() for |
406 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
- | |
407 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
- | |
408 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
- | |
409 | #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
- | |
- | 410 | * fast paths and boot_cpu_has() otherwise! |
|
Line 410... | Line 411... | ||
410 | #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) |
411 | */ |
411 | 412 | ||
412 | #if __GNUC__ >= 4 |
413 | #if __GNUC__ >= 4 && defined(CONFIG_X86_FAST_FEATURE_TESTS) |
Line 413... | Line 414... | ||
413 | extern void warn_pre_alternatives(void); |
414 | extern void warn_pre_alternatives(void); |
414 | extern bool __static_cpu_has_safe(u16 bit); |
415 | extern bool __static_cpu_has_safe(u16 bit); |