WebSVN – Kolibri OS – Diff – /drivers/ethernet/mtd80x.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  MTD80x driver for KolibriOS                                    ;;
;;                                                                 ;;
;;  Based on mtd80x.c from the etherboot project                   ;;
;;                                                                 ;;
;;  Written by hidnplayr@kolibrios.org                             ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format PE DLL native
entry START
 
        CURRENT_API             = 0x0200
        COMPATIBLE_API          = 0x0100
        API_VERSION             = (COMPATIBLE_API shl 16) + CURRENT_API
 
        MAX_DEVICES             = 16
 
 
        __DEBUG__               = 1
        __DEBUG_LEVEL__         = 2
 
        NUM_TX_DESC             = 6
        NUM_RX_DESC             = 12
 
section '.flat' readable writable executable
 
include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
 
; for different PHY
 
    MysonPHY            = 1
    AhdocPHY            = 2
    SeeqPHY             = 3
    MarvellPHY          = 4
    Myson981            = 5
    LevelOnePHY         = 6
    OtherPHY            = 10
 
; Offsets to the Command and Status Registers.
 
    PAR0                = 0x0           ; physical address 0-3
    PAR1                = 0x04          ; physical address 4-5
    MAR0                = 0x08          ; multicast address 0-3
    MAR1                = 0x0C          ; multicast address 4-7
    FAR0                = 0x10          ; flow-control address 0-3
    FAR1                = 0x14          ; flow-control address 4-5
    TCRRCR              = 0x18          ; receive & transmit configuration
    BCR                 = 0x1C          ; bus command
    TXPDR               = 0x20          ; transmit polling demand
    RXPDR               = 0x24          ; receive polling demand
    RXCWP               = 0x28          ; receive current word pointer
    TXLBA               = 0x2C          ; transmit list base address
    RXLBA               = 0x30          ; receive list base address
    ISR                 = 0x34          ; interrupt status
    IMR                 = 0x38          ; interrupt mask
    FTH                 = 0x3C          ; flow control high/low threshold
    MANAGEMENT          = 0x40          ; bootrom/eeprom and mii management
    TALLY               = 0x44          ; tally counters for crc and mpa
    TSR                 = 0x48          ; tally counter for transmit status
    BMCRSR              = 0x4c          ; basic mode control and status
    PHYIDENTIFIER       = 0x50          ; phy identifier
    ANARANLPAR          = 0x54          ; auto-negotiation advertisement and link partner ability
    ANEROCR             = 0x58          ; auto-negotiation expansion and pci conf.
    BPREMRPSR           = 0x5c          ; bypass & receive error mask and phy status
 
; Bits in the interrupt status/enable registers.
 
    RFCON               = 0x00020000    ; receive flow control xon packet
    RFCOFF              = 0x00010000    ; receive flow control xoff packet
    LSCStatus           = 0x00008000    ; link status change
    ANCStatus           = 0x00004000    ; autonegotiation completed
    FBE                 = 0x00002000    ; fatal bus error
    FBEMask             = 0x00001800    ; mask bit12-11
    ParityErr           = 0x00000000    ; parity error
    TargetErr           = 0x00001000    ; target abort
    MasterErr           = 0x00000800    ; master error
    TUNF                = 0x00000400    ; transmit underflow
    ROVF                = 0x00000200    ; receive overflow
    ETI                 = 0x00000100    ; transmit early int
    ERI                 = 0x00000080    ; receive early int
    CNTOVF              = 0x00000040    ; counter overflow
    RBU                 = 0x00000020    ; receive buffer unavailable
    TBU                 = 0x00000010    ; transmit buffer unavilable
    TI                  = 0x00000008    ; transmit interrupt
    RI                  = 0x00000004    ; receive interrupt
    RxErr               = 0x00000002    ; receive error
 
; Bits in the NetworkConfig register.
 
    RxModeMask          = 0xe0
    AcceptAllPhys       = 0x80          ; promiscuous mode
    AcceptBroadcast     = 0x40          ; accept broadcast
    AcceptMulticast     = 0x20          ; accept mutlicast
    AcceptRunt          = 0x08          ; receive runt pkt
    ALP                 = 0x04          ; receive long pkt
    AcceptErr           = 0x02          ; receive error pkt
 
    AcceptMyPhys        = 0x00000000
    RxEnable            = 0x00000001
    RxFlowCtrl          = 0x00002000
    TxEnable            = 0x00040000
    TxModeFDX           = 0x00100000
    TxThreshold         = 0x00e00000
 
    PS1000              = 0x00010000
    PS10                = 0x00080000
    FD                  = 0x00100000
 
 
; Bits in network_desc.status
 
    RXOWN               = 0x80000000    ; own bit
    FLNGMASK            = 0x0fff0000    ; frame length
    FLNGShift           = 16
    MARSTATUS           = 0x00004000    ; multicast address received
    BARSTATUS           = 0x00002000    ; broadcast address received
    PHYSTATUS           = 0x00001000    ; physical address received
    RXFSD               = 0x00000800    ; first descriptor
    RXLSD               = 0x00000400    ; last descriptor
    ErrorSummary        = 0x80          ; error summary
    RUNT                = 0x40          ; runt packet received
    LONG                = 0x20          ; long packet received
    FAE                 = 0x10          ; frame align error
    CRC                 = 0x08          ; crc error
    RXER                = 0x04          ; receive error
 
; rx_desc_control_bits
 
    RXIC                = 0x00800000    ; interrupt control
    RBSShift            = 0
 
; tx_desc_status_bits
 
    TXOWN               = 0x80000000    ; own bit
    JABTO               = 0x00004000    ; jabber timeout
    CSL                 = 0x00002000    ; carrier sense lost
    LC                  = 0x00001000    ; late collision
    EC                  = 0x00000800    ; excessive collision
    UDF                 = 0x00000400    ; fifo underflow
    DFR                 = 0x00000200    ; deferred
    HF                  = 0x00000100    ; heartbeat fail
    NCRMask             = 0x000000ff    ; collision retry count
    NCRShift            = 0
 
; tx_desc_control_bits
 
    TXIC                = 0x80000000    ; interrupt control
    ETIControl          = 0x40000000    ; early transmit interrupt
    TXLD                = 0x20000000    ; last descriptor
    TXFD                = 0x10000000    ; first descriptor
    CRCEnable           = 0x08000000    ; crc control
    PADEnable           = 0x04000000    ; padding control
    RetryTxLC           = 0x02000000    ; retry late collision
    PKTSMask            = 0x3ff800      ; packet size bit21-11
    PKTSShift           = 11
    TBSMask             = 0x000007ff    ; transmit buffer bit 10-0
    TBSShift            = 0
 
; BootROM/EEPROM/MII Management Register
 
    MASK_MIIR_MII_READ  = 0x00000000
    MASK_MIIR_MII_WRITE = 0x00000008
    MASK_MIIR_MII_MDO   = 0x00000004
    MASK_MIIR_MII_MDI   = 0x00000002
    MASK_MIIR_MII_MDC   = 0x00000001
 
; ST+OP+PHYAD+REGAD+TA
 
    OP_READ             = 0x6000        ; ST:01+OP:10+PHYAD+REGAD+TA:Z0
    OP_WRITE            = 0x5002        ; ST:01+OP:01+PHYAD+REGAD+TA:10
 
; -------------------------------------------------------------------------
;      Constants for Myson PHY
; -------------------------------------------------------------------------
 
    MysonPHYID          = 0xd0000302
    MysonPHYID0         = 0x0302
    StatusRegister      = 18
    SPEED100            = 0x0400        ; bit10
    FULLMODE            = 0x0800        ; bit11
 
; -------------------------------------------------------------------------
;      Constants for Seeq 80225 PHY
; -------------------------------------------------------------------------
 
    SeeqPHYID0          = 0x0016
    MIIRegister18       = 18
    SPD_DET_100         = 0x80
    DPLX_DET_FULL       = 0x40
 
; -------------------------------------------------------------------------
;      Constants for Ahdoc 101 PHY
; -------------------------------------------------------------------------
 
    AhdocPHYID0         = 0x0022
    DiagnosticReg       = 18
    DPLX_FULL           = 0x0800
    Speed_100           = 0x0400
 
; --------------------------------------------------------------------------
;      Constants
; --------------------------------------------------------------------------
 
    MarvellPHYID0               = 0x0141
    LevelOnePHYID0              = 0x0013
 
    MII1000BaseTControlReg      = 9
    MII1000BaseTStatusReg       = 10
    SpecificReg                 = 17
 
; for 1000BaseT Control Register
 
    PHYAbletoPerform1000FullDuplex = 0x0200
    PHYAbletoPerform1000HalfDuplex = 0x0100
    PHY1000AbilityMask             = 0x300
 
; for phy specific status register, marvell phy.
 
    SpeedMask      = 0x0c000
    Speed_1000M    = 0x08000
    Speed_100M     = 0x4000
    Speed_10M      = 0
    Full_Duplex    = 0x2000
 
; for phy specific status register, levelone phy
 
    LXT1000_100M   = 0x08000
    LXT1000_1000M  = 0x0c000
    LXT1000_Full   = 0x200
 
; for PHY
 
    LinkIsUp       = 0x0004
    LinkIsUp2      = 0x00040000
 
 
 
struct  descriptor
        status                  dd ?
        control                 dd ?
        buffer                  dd ?
        next_desc               dd ?
 
        next_desc_logical       dd ?
        skbuff                  dd ?
        reserved1               dd ?
        reserved2               dd ?
ends
 
 
struct  device          ETH_DEVICE
 
        io_addr         dd ?
        pci_bus         dd ?
        pci_dev         dd ?
        irq_line        db ?
        dev_id          dw ?
        flags           dd ?
        crvalue         dd ?
        bcrvalue        dd ?
        cur_rx          dd ?
        cur_tx          dd ?
        default_port    dd ?
        PHYType         dd ?
 
; MII transceiver section.
        mii_cnt         dd ?    ; MII device addresses.
        phys            db ?    ; MII device addresses.
 
; descriptors
        rb 0x100 - ($ and 0xff) ; align 256
        tx_desc         rb NUM_TX_DESC*sizeof.descriptor
        rx_desc         rb NUM_RX_DESC*sizeof.descriptor
 
ends
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
proc START c, reason:dword, cmdline:dword
 
        cmp     [reason], DRV_ENTRY
        jne     .fail
 
        DEBUGF  1,"Loading driver\n"
        invoke  RegService, my_service, service_proc
        ret
 
  .fail:
        xor     eax, eax
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
proc service_proc stdcall, ioctl:dword
 
        mov     edx, [ioctl]
        mov     eax, [edx + IOCTL.io_code]
 
;------------------------------------------------------
 
        cmp     eax, 0 ;SRV_GETVERSION
        jne     @F
 
        cmp     [edx + IOCTL.out_size], 4
        jb      .fail
        mov     eax, [edx + IOCTL.output]
        mov     [eax], dword API_VERSION
 
        xor     eax, eax
        ret
 
;------------------------------------------------------
  @@:
        cmp     eax, 1 ;SRV_HOOK
        jne     .fail
 
        cmp     [edx + IOCTL.inp_size], 3               ; Data input must be at least 3 bytes
        jb      .fail
 
        mov     eax, [edx + IOCTL.input]
        cmp     byte [eax], 1                           ; 1 means device number and bus number (pci) are given
        jne     .fail                                   ; other types arent supported for this card yet
 
; check if the device is already listed
 
        mov     esi, device_list
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .firstdevice
 
;        mov     eax, [edx + IOCTL.input]                ; get the pci bus and device numbers
        mov     ax, [eax+1]                             ;
  .nextdevice:
        mov     ebx, [esi]
        cmp     al, byte[ebx + device.pci_bus]
        jne     @f
        cmp     ah, byte[ebx + device.pci_dev]
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
       @@:
        add     esi, 4
        loop    .nextdevice
 
 
; This device doesnt have its own eth_device structure yet, lets create one
  .firstdevice:
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
        jae     .fail
 
        allocate_and_clear ebx, sizeof.device, .fail
 
; Fill in the direct call addresses into the struct
 
        mov     [ebx + device.reset], reset
        mov     [ebx + device.transmit], transmit
        mov     [ebx + device.unload], unload
        mov     [ebx + device.name], my_service
 
; save the pci bus and device numbers
 
        mov     eax, [edx + IOCTL.input]
        movzx   ecx, byte[eax+1]
        mov     [ebx + device.pci_bus], ecx
        movzx   ecx, byte[eax+2]
        mov     [ebx + device.pci_dev], ecx
 
; Now, it's time to find the base io addres of the PCI device
 
        stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
        mov     [ebx + device.io_addr], eax
 
; We've found the io address, find IRQ now
 
        invoke  PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
        mov     [ebx + device.irq_line], al
 
        DEBUGF  1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
        [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
        mov     eax, [devices]                                          ; Add the device structure to our device list
        mov     [device_list+4*eax], ebx                                ; (IRQ handler uses this list to find device)
        inc     [devices]                                               ;
 
        call    probe                                                   ; this function will output in eax
        test    eax, eax
        jnz     .err2                                                   ; If an error occured, exit
 
        mov     [ebx + device.type], NET_TYPE_ETH
        invoke  NetRegDev
 
        cmp     eax, -1
        je      .destroy
 
        ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
        DEBUGF  2,"Trying to find device number of already registered device\n"
        invoke  NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
                                                                        ; into a device number in edi
        mov     eax, edi                                                ; Application wants it in eax instead
        DEBUGF  2,"Kernel says: %u\n", eax
        ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
        ; todo: reset device into virgin state
 
  .err2:
        dec     [devices]
  .err:
        DEBUGF  2,"removing device structure\n"
        invoke  KernelFree, ebx
  .fail:
        or      eax, -1
        ret
 
;------------------------------------------------------
endp
 
 
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
;;                                                                        ;;
;;        Actual Hardware dependent code starts here                      ;;
;;                                                                        ;;
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
 
 
 
align 4
unload:
        ; TODO: (in this particular order)
        ;
        ; - Stop the device
 
;    /* Disable Tx Rx*/
;    outl( mtdx.crvalue & (~TxEnable) & (~RxEnable), mtdx.ioaddr + TCRRCR );
;
;    /* Reset the chip to erase previous misconfiguration. */
;    mtd_reset(nic);
 
        ; - Detach int handler
        ; - Remove device from local list (device_list)
        ; - call unregister function in kernel
        ; - Remove all allocated structures and buffers the card used
 
        or      eax, -1
 
ret
 
 
;-------
;
; PROBE
;
;-------
align 4
probe:
 
        DEBUGF  1,"Probing\n"
 
; Make the device a bus master
        invoke  PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
        or      al, PCI_CMD_MASTER
        invoke  PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
 
; Check vendor/device id's
        invoke  PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], 0
        cmp     ax, 0x1516
        jne     .notfound
        shr     eax, 16
        mov     [ebx + device.dev_id], ax
        cmp     ax, 0x0800
        je      .mtd800
        cmp     ax, 0x0803
        je      .mtd803
        cmp     ax, 0x0891
        je      .mtd891
 
  .notfound:
        DEBUGF  2,"Device not supported!\n"
        xor     eax, eax
        dec     eax
        ret
 
  .mtd803:
        mov     [ebx + device.name], sz_mtd803
        DEBUGF  1,"Device has chip xcvr\n"
        jmp     .xcvr_set
 
  .mtd800:
        DEBUGF  1,"Device has mii xcvr\n"
        mov     [ebx + device.name], sz_mtd800
        jmp     .xcvr_set
 
  .mtd891:
        DEBUGF  1,"Device has mii xcvr\n"
        mov     [ebx + device.name], sz_mtd800
 
  .xcvr_set:
        call    read_mac
 
; Reset the chip to erase previous misconfiguration.
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], BCR
        xor     eax, eax
        inc     eax
        out     dx, eax
 
; find the connected MII xcvrs
        cmp     [ebx + device.dev_id], 0x0803
        je      .is_803
 
;        int     phy, phy_idx =   0;
;
;        for (phy =   1; phy < 32 && phy_idx < 1; phy++) {
;            int mii_status =   mdio_read(nic, phy, 1);
;
;            if (mii_status !=   0xffff && mii_status !=   0x0000) {
;                mtdx.phys[phy_idx] =   phy;
;
;                DBG ( "%s: MII PHY found at address %d, status "
;                      "0x%4.4x.\n", mtdx.nic_name, phy, mii_status );
;                /* get phy type */
;                {
;                    unsigned int data;
;
;                    data =   mdio_read(nic, mtdx.phys[phy_idx], 2);
;                    if (data equ=   SeeqPHYID0)
;                        mtdx.PHYType =   SeeqPHY;
;                    else if (data equ=   AhdocPHYID0)
;                        mtdx.PHYType =   AhdocPHY;
;                    else if (data equ=   MarvellPHYID0)
;                        mtdx.PHYType =   MarvellPHY;
;                    else if (data equ=   MysonPHYID0)
;                        mtdx.PHYType =   Myson981;
;                    else if (data equ=   LevelOnePHYID0)
;                        mtdx.PHYType =   LevelOnePHY;
;                    else
;                        mtdx.PHYType =   OtherPHY;
;                }
;                phy_idx++;
;            }
;        }
;
;        mtdx.mii_cnt =   phy_idx;
;        if (phy_idx equ=   0) {
;            printf("%s: MII PHY not found -- this device may "
;                   "not operate correctly.\n", mtdx.nic_name);
;        }
 
        jmp     .no_803
 
  .is_803:
        mov     [ebx + device.phys], 32
 
; get phy type
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], PHYIDENTIFIER
        in      eax, dx
 
        cmp     eax, MysonPHYID
        jne     @f
        mov     [ebx + device.PHYType], MysonPHY
        DEBUGF  1,"Myson PHY\n"
        jmp     .no_803
       @@:
 
        mov     [ebx + device.PHYType], OtherPHY
        DEBUGF  1,"Other PHY\n"
  .no_803:
 
;-------
;
; RESET
;
;-------
align 4
reset:
 
        DEBUGF  1,"Resetting\n"
 
; attach irq handler
        movzx   eax, [ebx + device.irq_line]
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
        invoke  AttachIntHandler, eax, int_handler, ebx
        test    eax, eax
        jnz     @f
        DEBUGF  2,"Could not attach int handler!\n"
        or      eax, -1
        ret
  @@:
 
; Reset the chip to erase previous misconfiguration.
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], BCR
        xor     eax, eax
        inc     eax
        out     dx, eax
 
        call    init_ring
 
; Initialize other registers.
; Configure the PCI bus bursts and FIFO thresholds.
        mov     [ebx + device.bcrvalue], 0x10         ; little-endian, 8 burst length
        mov     [ebx + device.crvalue], 0xa00         ; 128 burst length
 
        cmp     [ebx + device.dev_id], 0x891
        jne     @f
        or      [ebx + device.bcrvalue], 0x200       ; set PROG bit
        or      [ebx + device.crvalue], 0x02000000   ; set enhanced bit
       @@:
        or      [ebx + device.crvalue], RxEnable + TxThreshold + TxEnable
 
        call    set_rx_mode
 
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], BCR
        mov     eax, [ebx + device.bcrvalue]
        out     dx, eax
 
        set_io  [ebx + device.io_addr], TCRRCR
        mov     eax, [ebx + device.crvalue]
        out     dx, eax
 
        call    getlinkstatus
 
; Restart Rx engine if stopped.
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], RXPDR
        xor     eax, eax
        out     dx, eax
 
; Enable interrupts
        set_io  [ebx + device.io_addr], ISR
        mov     eax, FBE or TUNF or CNTOVF or RBU or TI or RI
        out     dx, eax
        set_io  [ebx + device.io_addr], IMR
        out     dx, eax
 
; clear packet/byte counters
        xor     eax, eax
        lea     edi, [ebx + device.bytes_tx]
        mov     ecx, 6
        rep     stosd
 
        mov     [ebx + device.mtu], 1514
        xor     eax, eax
        ret
 
 
 
 
align 4
init_ring:
 
        DEBUGF  1,"initializing rx and tx ring\n"
 
; Initialize all Rx descriptors
        lea     esi, [ebx + device.rx_desc]
        mov     [ebx + device.cur_rx], esi
        mov     ecx, NUM_RX_DESC
  .rx_desc_loop:
        mov     [esi + descriptor.status], RXOWN
        mov     [esi + descriptor.control], 1536 shl RBSShift
 
        lea     eax, [esi + sizeof.descriptor]
        mov     [esi + descriptor.next_desc_logical], eax
        push    ecx esi
        invoke  GetPhysAddr
        mov     [esi + descriptor.next_desc], eax
 
        invoke  KernelAlloc, 1536
        pop     esi
        push    esi
        mov     [esi + descriptor.skbuff], eax
        invoke  GetPgAddr
        pop     esi ecx
        mov     [esi + descriptor.buffer], eax
 
        add     esi, sizeof.descriptor
        loop    .rx_desc_loop
 
; Mark the last entry as wrapping the ring.
        lea     eax, [ebx + device.rx_desc]
        mov     [esi - sizeof.descriptor + descriptor.next_desc_logical], eax
        push    esi
        invoke  GetPhysAddr
        pop     esi
        mov     [esi - sizeof.descriptor + descriptor.next_desc], eax
 
        set_io  [ebx + device.io_addr],   0
        set_io  [ebx + device.io_addr],   RXLBA
        out     dx, eax
 
; Initialize all Tx descriptors
        lea     esi, [ebx + device.tx_desc]
        mov     [ebx + device.cur_tx], esi
        mov     ecx, NUM_TX_DESC
  .tx_desc_loop:
        mov     [esi + descriptor.status], 0
 
        lea     eax, [esi + sizeof.descriptor]
        mov     [esi + descriptor.next_desc_logical], eax
        push    ecx esi
        invoke  GetPhysAddr
        pop     esi ecx
        mov     [esi + descriptor.next_desc], eax
        mov     [esi + descriptor.skbuff], 0
        add     esi, sizeof.descriptor
        loop    .tx_desc_loop
 
; Mark the last entry as wrapping the ring.
        lea     eax, [ebx + device.tx_desc]
        mov     [esi - sizeof.descriptor + descriptor.next_desc_logical], eax
        push    esi
        invoke  GetPhysAddr
        pop     esi
        mov     [esi - sizeof.descriptor + descriptor.next_desc], eax
 
        set_io  [ebx + device.io_addr],   0
        set_io  [ebx + device.io_addr],   TXLBA
        out     dx, eax
 
        ret
 
 
align 4
set_rx_mode:
 
        DEBUGF  1,"Setting RX mode\n"
 
; Too many to match, or accept all multicasts.
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], MAR0
        xor     eax, eax
        not     eax
        out     dx, eax
        set_io  [ebx + device.io_addr], MAR1
        out     dx, eax
 
        and     [ebx + device.crvalue], not (RxModeMask)
        or      [ebx + device.crvalue], AcceptBroadcast + AcceptMulticast + AcceptMyPhys
 
        ret
 
 
align 4
getlinkstatus:
 
        DEBUGF  1,"Getting link status\n"
 
        mov     [ebx + device.state], ETH_LINK_DOWN     ; assume link is dead
 
        cmp     [ebx + device.PHYType], MysonPHY
        jne     .no_myson_phy
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], BMCRSR
        in      eax, dx
        test    eax, LinkIsUp2
        jnz     getlinktype
        ret
 
  .no_myson_phy:
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], BMCRSR
        in      eax, dx
        test    eax, LinkIsUp
        jnz     getlinktype
        ret
 
getlinktype:
 
        DEBUGF  1,"Getting link type\n"
        cmp     [ebx + device.PHYType], MysonPHY
        jne     .no_myson_phy
 
        DEBUGF  1,"myson PHY\n"
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], TCRRCR
        in      eax, dx
        test    eax, FD
        jz      @f
        DEBUGF  1,"full duplex\n"
        or      [ebx + device.state], ETH_LINK_FD
       @@:
        test    eax, PS10
        jnz     @f
        DEBUGF  1,"100mbit\n"
        or      [ebx + device.state], ETH_LINK_100M
        ret
       @@:
        DEBUGF  1,"10mbit\n"
        or      [ebx + device.state], ETH_LINK_10M
        ret
 
  .no_myson_phy:
        DEBUGF  1,"not a myson PHY\n"
        mov     [ebx + device.state], ETH_LINK_UNKNOWN
 
;        if (mtdx.PHYType equ=   SeeqPHY) { /* this PHY is SEEQ 80225 */
;            unsigned int data;
;
;            data =   mdio_read(dev, mtdx.phys[0], MIIRegister18);
;            if (data & SPD_DET_100)
;                mtdx.line_speed =   2; /* 100M */
;            else
;                mtdx.line_speed =   1; /* 10M */
;            if (data & DPLX_DET_FULL)
;                mtdx.duplexmode =   2; /* full duplex mode */
;            else
;                mtdx.duplexmode =   1; /* half duplex mode */
;        } else if (mtdx.PHYType equ=   AhdocPHY) {
;            unsigned int data;
;
;            data =   mdio_read(dev, mtdx.phys[0], DiagnosticReg);
;            if (data & Speed_100)
;                mtdx.line_speed =   2; /* 100M */
;            else
;                mtdx.line_speed =   1; /* 10M */
;            if (data & DPLX_FULL)
;                mtdx.duplexmode =   2; /* full duplex mode */
;            else
;                mtdx.duplexmode =   1; /* half duplex mode */
;        }
;        else if (mtdx.PHYType equ=   MarvellPHY) {
;            unsigned int data;
;
;            data =   mdio_read(dev, mtdx.phys[0], SpecificReg);
;            if (data & Full_Duplex)
;                mtdx.duplexmode =   2; /* full duplex mode */
;            else
;                mtdx.duplexmode =   1; /* half duplex mode */
;            data &=   SpeedMask;
;            if (data equ=   Speed_1000M)
;                mtdx.line_speed =   3; /* 1000M */
;            else if (data equ=   Speed_100M)
;                mtdx.line_speed =   2; /* 100M */
;            else
;                mtdx.line_speed =   1; /* 10M */
;        }
;        else if (mtdx.PHYType equ=   Myson981) {
;            unsigned int data;
;
;            data =   mdio_read(dev, mtdx.phys[0], StatusRegister);
;
;            if (data & SPEED100)
;                mtdx.line_speed =   2;
;            else
;                mtdx.line_speed =   1;
;
;            if (data & FULLMODE)
;                mtdx.duplexmode =   2;
;            else
;                mtdx.duplexmode =   1;
;        }
;        else if (mtdx.PHYType equ=   LevelOnePHY) {
;            unsigned int data;
;
;            data =   mdio_read(dev, mtdx.phys[0], SpecificReg);
;            if (data & LXT1000_Full)
;                mtdx.duplexmode =   2; /* full duplex mode */
;            else
;                mtdx.duplexmode =   1; /* half duplex mode */
;            data &=   SpeedMask;
;            if (data equ=   LXT1000_1000M)
;                mtdx.line_speed =   3; /* 1000M */
;            else if (data equ=   LXT1000_100M)
;                mtdx.line_speed =   2; /* 100M */
;            else
 ;               mtdx.line_speed =   1; /* 10M */
  ;      }
 
;        // chage crvalue
;        // mtdx.crvalue&equ(~PS10)&(~FD);
;        mtdx.crvalue &=   (~PS10) & (~FD) & (~PS1000);
;        if (mtdx.line_speed equ=   1)
;            mtdx.crvalue |=   PS10;
;        else if (mtdx.line_speed equ=   3)
;            mtdx.crvalue |=   PS1000;
;        if (mtdx.duplexmode equ=   2)
;            mtdx.crvalue |=   FD;
 
        ret
 
 
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                         ;;
;; Transmit                                ;;
;;                                         ;;
;; In: buffer pointer in [esp+4]           ;;
;;     size of buffer in [esp+8]           ;;
;;     pointer to device structure in ebx  ;;
;;                                         ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
proc transmit stdcall bufferptr, buffersize
 
        pushf
        cli
 
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize]
        mov     eax, [bufferptr]
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
        [eax+13]:2,[eax+12]:2
 
        cmp     [buffersize], 1514
        ja      .fail
        cmp     [buffersize], 60
        jb      .fail
 
        mov     esi, [ebx + device.cur_tx]
 
        test    [esi + descriptor.status], TXOWN
        jnz     .fail
 
        push    [esi + descriptor.next_desc_logical]
        pop     [ebx + device.cur_tx]
 
        mov     eax, [bufferptr]
        mov     [esi + descriptor.skbuff], eax
        invoke  GetPhysAddr
        mov     [esi + descriptor.buffer], eax
 
        mov     eax, [buffersize]
        mov     ecx, eax
        shl     eax, PKTSShift               ; packet size
        shl     ecx, TBSShift
        or      eax, ecx
        or      eax, TXIC + TXLD + TXFD + CRCEnable + PADEnable
        mov     [esi + descriptor.control], eax
        mov     [esi + descriptor.status], TXOWN
 
; Update stats
        inc     [ebx + device.packets_tx]
        mov     eax, [buffersize]
        add     dword[ebx + device.bytes_tx], eax
        adc     dword[ebx + device.bytes_tx + 4], 0
 
; TX Poll
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], TXPDR
        xor     eax, eax
        out     dx, eax
 
        DEBUGF  1,"Transmit OK\n"
        popf
        xor     eax, eax
        ret
 
  .fail:
        DEBUGF  2,"Transmit failed\n"
        invoke  KernelFree, [bufferptr]
        popf
        or      eax, -1
        ret
 
endp
 
 
 
align 4
read_mac:
 
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], PAR0
        lea     edi, [ebx + device.mac]
        insd
        set_io  [ebx + device.io_addr], PAR1
        insw
        DEBUGF  1,"MAC = %x-%x-%x-%x-%x-%x\n",\
        [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
 
        ret
 
align 4
write_mac:
 
        ret
 
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
        push    ebx esi edi
 
        DEBUGF  1,"INT\n"
 
; find pointer of device wich made IRQ occur
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .nothing
        mov     esi, device_list
  .nextdevice:
        mov     ebx, [esi]
 
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], ISR
        in      eax, dx
        out     dx, eax                                 ; send it back to ACK
        test    eax, eax
        jnz     .got_it
  .continue:
        add     esi, 4
        dec     ecx
        jnz     .nextdevice
  .nothing:
        pop     edi esi ebx
        xor     eax, eax
 
        ret                                             ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
 
  .got_it:
 
        DEBUGF  1,"Device: %x Status: %x\n", ebx, ax
 
        test    ax, RI  ; receive interrupt
        jz      .no_rx
        push    ax
  .rx_loop:
        mov     esi, [ebx + device.cur_rx]
        test    [esi + descriptor.status], RXOWN
        jnz     .rx_done
 
        push    ebx
        push    .rx_complete
 
        mov     ecx, [esi + descriptor.status]
        shr     ecx, FLNGShift
        sub     ecx, 4                  ; we dont need CRC
        push    ecx
        DEBUGF  1,"Received %u bytes\n", ecx
 
; Update stats
        add     dword[ebx + device.bytes_rx], ecx
        adc     dword[ebx + device.bytes_rx + 4], 0
        inc     [ebx + device.packets_rx]
 
        push    [esi + descriptor.skbuff]
        jmp     [Eth_input]
 
  .rx_complete:
        pop     ebx
        mov     esi, [ebx + device.cur_rx]
        mov     [esi + descriptor.control], 1536 shl RBSShift
        push    esi
        invoke  KernelAlloc, 1536
        pop     esi
        mov     [esi + descriptor.skbuff], eax
        invoke  GetPgAddr
        mov     [esi + descriptor.buffer], eax
        mov     [esi + descriptor.status], RXOWN
 
        push    [esi + descriptor.next_desc_logical]
        pop     [ebx + device.cur_rx]
 
        jmp     .rx_loop
 
  .rx_done:
        DEBUGF  1,"RX done\n"
 
; Restart Rx engine if stopped.
        set_io  [ebx + device.io_addr], 0
        set_io  [ebx + device.io_addr], RXPDR
        xor     eax, eax
        out     dx, eax
 
        pop     ax
  .no_rx:
 
        test    ax, TI ; transmit interrupt
        jz      .no_tx
        DEBUGF  1,"TX\n"
        push    ax
        lea     esi, [ebx + device.tx_desc]
        mov     ecx, NUM_TX_DESC
  .tx_loop:
        test    [esi + descriptor.status], TXOWN
        jnz     .skip_this_one
        mov     eax, [esi + descriptor.skbuff]
        test    eax, eax
        je      .skip_this_one
        mov     [esi + descriptor.skbuff], 0
        DEBUGF  1,"freeing buffer: 0x%x\n", eax
        invoke  KernelFree, eax
  .skip_this_one:
        mov     esi, [esi + descriptor.next_desc_logical]
        loop    .tx_loop
        pop     ax
  .no_tx:
 
        test    ax, LSCStatus
        jz      .no_link_change
        push    ax
        call    getlinkstatus
        pop     ax
  .no_link_change:
 
;        test    ax, TBU
;        jz      .no_tbu
;        DEBUGF  2,"Transmit buffer unavailable!\n"
;  .no_tbu:
 
  .fail:
        pop     edi esi ebx
        xor     eax, eax
        inc     eax
 
        ret
 
 
; End of code
 
 
data fixups
end data
 
include '../peimport.inc'
 
my_service      db 'mtd80x',0                   ; max 16 chars include zero
 
sz_mtd800       db "Myson MTD800", 0
sz_mtd803       db "Surecom EP-320X", 0
sz_mtd891       db "Myson MTD891", 0
 
 
include_debug_strings                           ; All data wich FDO uses will be included here
 
align 4
devices       dd 0
device_list   rd MAX_DEVICES                    ; This list contains all pointers to device structures the driver is handling

Rev 4629	Rev 4663
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; MTD80x driver for KolibriOS ;;	6	;; MTD80x driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; Based on mtd80x.c from the etherboot project ;;	8	;; Based on mtd80x.c from the etherboot project ;;
9	;; ;;	9	;; ;;
10	;; Written by hidnplayr@kolibrios.org ;;	10	;; Written by hidnplayr@kolibrios.org ;;
11	;; ;;	11	;; ;;
12	;; GNU GENERAL PUBLIC LICENSE ;;	12	;; GNU GENERAL PUBLIC LICENSE ;;
13	;; Version 2, June 1991 ;;	13	;; Version 2, June 1991 ;;
14	;; ;;	14	;; ;;
15	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	15	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
16		16
17	format PE DLL native	17	format PE DLL native
18	entry START	18	entry START
19		19
20	CURRENT_API = 0x0200	20	CURRENT_API = 0x0200
21	COMPATIBLE_API = 0x0100	21	COMPATIBLE_API = 0x0100
22	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API	22	API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
23		23
24	MAX_DEVICES = 16	24	MAX_DEVICES = 16
25		-
26	DEBUG = 1	25
27	__DEBUG__ = 1	26	__DEBUG__ = 1
28	__DEBUG_LEVEL__ = 2	27	__DEBUG_LEVEL__ = 2
29		28
30	NUM_TX_DESC = 6	29	NUM_TX_DESC = 6
31	NUM_RX_DESC = 12	30	NUM_RX_DESC = 12
32		31
33	section '.flat' readable writable executable	32	section '.flat' readable writable executable
34		33
35	include '../proc32.inc'	34	include '../proc32.inc'
36	include '../struct.inc'	35	include '../struct.inc'
37	include '../macros.inc'	36	include '../macros.inc'
38	include '../fdo.inc'	37	include '../fdo.inc'
39	include '../netdrv_pe.inc'	38	include '../netdrv_pe.inc'
40		39
41	; for different PHY	40	; for different PHY
42		41
43	MysonPHY = 1	42	MysonPHY = 1
44	AhdocPHY = 2	43	AhdocPHY = 2
45	SeeqPHY = 3	44	SeeqPHY = 3
46	MarvellPHY = 4	45	MarvellPHY = 4
47	Myson981 = 5	46	Myson981 = 5
48	LevelOnePHY = 6	47	LevelOnePHY = 6
49	OtherPHY = 10	48	OtherPHY = 10
50		49
51	; Offsets to the Command and Status Registers.	50	; Offsets to the Command and Status Registers.
52		51
53	PAR0 = 0x0 ; physical address 0-3	52	PAR0 = 0x0 ; physical address 0-3
54	PAR1 = 0x04 ; physical address 4-5	53	PAR1 = 0x04 ; physical address 4-5
55	MAR0 = 0x08 ; multicast address 0-3	54	MAR0 = 0x08 ; multicast address 0-3
56	MAR1 = 0x0C ; multicast address 4-7	55	MAR1 = 0x0C ; multicast address 4-7
57	FAR0 = 0x10 ; flow-control address 0-3	56	FAR0 = 0x10 ; flow-control address 0-3
58	FAR1 = 0x14 ; flow-control address 4-5	57	FAR1 = 0x14 ; flow-control address 4-5
59	TCRRCR = 0x18 ; receive & transmit configuration	58	TCRRCR = 0x18 ; receive & transmit configuration
60	BCR = 0x1C ; bus command	59	BCR = 0x1C ; bus command
61	TXPDR = 0x20 ; transmit polling demand	60	TXPDR = 0x20 ; transmit polling demand
62	RXPDR = 0x24 ; receive polling demand	61	RXPDR = 0x24 ; receive polling demand
63	RXCWP = 0x28 ; receive current word pointer	62	RXCWP = 0x28 ; receive current word pointer
64	TXLBA = 0x2C ; transmit list base address	63	TXLBA = 0x2C ; transmit list base address
65	RXLBA = 0x30 ; receive list base address	64	RXLBA = 0x30 ; receive list base address
66	ISR = 0x34 ; interrupt status	65	ISR = 0x34 ; interrupt status
67	IMR = 0x38 ; interrupt mask	66	IMR = 0x38 ; interrupt mask
68	FTH = 0x3C ; flow control high/low threshold	67	FTH = 0x3C ; flow control high/low threshold
69	MANAGEMENT = 0x40 ; bootrom/eeprom and mii management	68	MANAGEMENT = 0x40 ; bootrom/eeprom and mii management
70	TALLY = 0x44 ; tally counters for crc and mpa	69	TALLY = 0x44 ; tally counters for crc and mpa
71	TSR = 0x48 ; tally counter for transmit status	70	TSR = 0x48 ; tally counter for transmit status
72	BMCRSR = 0x4c ; basic mode control and status	71	BMCRSR = 0x4c ; basic mode control and status
73	PHYIDENTIFIER = 0x50 ; phy identifier	72	PHYIDENTIFIER = 0x50 ; phy identifier
74	ANARANLPAR = 0x54 ; auto-negotiation advertisement and link partner ability	73	ANARANLPAR = 0x54 ; auto-negotiation advertisement and link partner ability
75	ANEROCR = 0x58 ; auto-negotiation expansion and pci conf.	74	ANEROCR = 0x58 ; auto-negotiation expansion and pci conf.
76	BPREMRPSR = 0x5c ; bypass & receive error mask and phy status	75	BPREMRPSR = 0x5c ; bypass & receive error mask and phy status
77		76
78	; Bits in the interrupt status/enable registers.	77	; Bits in the interrupt status/enable registers.
79		78
80	RFCON = 0x00020000 ; receive flow control xon packet	79	RFCON = 0x00020000 ; receive flow control xon packet
81	RFCOFF = 0x00010000 ; receive flow control xoff packet	80	RFCOFF = 0x00010000 ; receive flow control xoff packet
82	LSCStatus = 0x00008000 ; link status change	81	LSCStatus = 0x00008000 ; link status change
83	ANCStatus = 0x00004000 ; autonegotiation completed	82	ANCStatus = 0x00004000 ; autonegotiation completed
84	FBE = 0x00002000 ; fatal bus error	83	FBE = 0x00002000 ; fatal bus error
85	FBEMask = 0x00001800 ; mask bit12-11	84	FBEMask = 0x00001800 ; mask bit12-11
86	ParityErr = 0x00000000 ; parity error	85	ParityErr = 0x00000000 ; parity error
87	TargetErr = 0x00001000 ; target abort	86	TargetErr = 0x00001000 ; target abort
88	MasterErr = 0x00000800 ; master error	87	MasterErr = 0x00000800 ; master error
89	TUNF = 0x00000400 ; transmit underflow	88	TUNF = 0x00000400 ; transmit underflow
90	ROVF = 0x00000200 ; receive overflow	89	ROVF = 0x00000200 ; receive overflow
91	ETI = 0x00000100 ; transmit early int	90	ETI = 0x00000100 ; transmit early int
92	ERI = 0x00000080 ; receive early int	91	ERI = 0x00000080 ; receive early int
93	CNTOVF = 0x00000040 ; counter overflow	92	CNTOVF = 0x00000040 ; counter overflow
94	RBU = 0x00000020 ; receive buffer unavailable	93	RBU = 0x00000020 ; receive buffer unavailable
95	TBU = 0x00000010 ; transmit buffer unavilable	94	TBU = 0x00000010 ; transmit buffer unavilable
96	TI = 0x00000008 ; transmit interrupt	95	TI = 0x00000008 ; transmit interrupt
97	RI = 0x00000004 ; receive interrupt	96	RI = 0x00000004 ; receive interrupt
98	RxErr = 0x00000002 ; receive error	97	RxErr = 0x00000002 ; receive error
99		98
100	; Bits in the NetworkConfig register.	99	; Bits in the NetworkConfig register.
101		100
102	RxModeMask = 0xe0	101	RxModeMask = 0xe0
103	AcceptAllPhys = 0x80 ; promiscuous mode	102	AcceptAllPhys = 0x80 ; promiscuous mode
104	AcceptBroadcast = 0x40 ; accept broadcast	103	AcceptBroadcast = 0x40 ; accept broadcast
105	AcceptMulticast = 0x20 ; accept mutlicast	104	AcceptMulticast = 0x20 ; accept mutlicast
106	AcceptRunt = 0x08 ; receive runt pkt	105	AcceptRunt = 0x08 ; receive runt pkt
107	ALP = 0x04 ; receive long pkt	106	ALP = 0x04 ; receive long pkt
108	AcceptErr = 0x02 ; receive error pkt	107	AcceptErr = 0x02 ; receive error pkt
109		108
110	AcceptMyPhys = 0x00000000	109	AcceptMyPhys = 0x00000000
111	RxEnable = 0x00000001	110	RxEnable = 0x00000001
112	RxFlowCtrl = 0x00002000	111	RxFlowCtrl = 0x00002000
113	TxEnable = 0x00040000	112	TxEnable = 0x00040000
114	TxModeFDX = 0x00100000	113	TxModeFDX = 0x00100000
115	TxThreshold = 0x00e00000	114	TxThreshold = 0x00e00000
116		115
117	PS1000 = 0x00010000	116	PS1000 = 0x00010000
118	PS10 = 0x00080000	117	PS10 = 0x00080000
119	FD = 0x00100000	118	FD = 0x00100000
120		119
121		120
122	; Bits in network_desc.status	121	; Bits in network_desc.status
123		122
124	RXOWN = 0x80000000 ; own bit	123	RXOWN = 0x80000000 ; own bit
125	FLNGMASK = 0x0fff0000 ; frame length	124	FLNGMASK = 0x0fff0000 ; frame length
126	FLNGShift = 16	125	FLNGShift = 16
127	MARSTATUS = 0x00004000 ; multicast address received	126	MARSTATUS = 0x00004000 ; multicast address received
128	BARSTATUS = 0x00002000 ; broadcast address received	127	BARSTATUS = 0x00002000 ; broadcast address received
129	PHYSTATUS = 0x00001000 ; physical address received	128	PHYSTATUS = 0x00001000 ; physical address received
130	RXFSD = 0x00000800 ; first descriptor	129	RXFSD = 0x00000800 ; first descriptor
131	RXLSD = 0x00000400 ; last descriptor	130	RXLSD = 0x00000400 ; last descriptor
132	ErrorSummary = 0x80 ; error summary	131	ErrorSummary = 0x80 ; error summary
133	RUNT = 0x40 ; runt packet received	132	RUNT = 0x40 ; runt packet received
134	LONG = 0x20 ; long packet received	133	LONG = 0x20 ; long packet received
135	FAE = 0x10 ; frame align error	134	FAE = 0x10 ; frame align error
136	CRC = 0x08 ; crc error	135	CRC = 0x08 ; crc error
137	RXER = 0x04 ; receive error	136	RXER = 0x04 ; receive error
138		137
139	; rx_desc_control_bits	138	; rx_desc_control_bits
140		139
141	RXIC = 0x00800000 ; interrupt control	140	RXIC = 0x00800000 ; interrupt control
142	RBSShift = 0	141	RBSShift = 0
143		142
144	; tx_desc_status_bits	143	; tx_desc_status_bits
145		144
146	TXOWN = 0x80000000 ; own bit	145	TXOWN = 0x80000000 ; own bit
147	JABTO = 0x00004000 ; jabber timeout	146	JABTO = 0x00004000 ; jabber timeout
148	CSL = 0x00002000 ; carrier sense lost	147	CSL = 0x00002000 ; carrier sense lost
149	LC = 0x00001000 ; late collision	148	LC = 0x00001000 ; late collision
150	EC = 0x00000800 ; excessive collision	149	EC = 0x00000800 ; excessive collision
151	UDF = 0x00000400 ; fifo underflow	150	UDF = 0x00000400 ; fifo underflow
152	DFR = 0x00000200 ; deferred	151	DFR = 0x00000200 ; deferred
153	HF = 0x00000100 ; heartbeat fail	152	HF = 0x00000100 ; heartbeat fail
154	NCRMask = 0x000000ff ; collision retry count	153	NCRMask = 0x000000ff ; collision retry count
155	NCRShift = 0	154	NCRShift = 0
156		155
157	; tx_desc_control_bits	156	; tx_desc_control_bits
158		157
159	TXIC = 0x80000000 ; interrupt control	158	TXIC = 0x80000000 ; interrupt control
160	ETIControl = 0x40000000 ; early transmit interrupt	159	ETIControl = 0x40000000 ; early transmit interrupt
161	TXLD = 0x20000000 ; last descriptor	160	TXLD = 0x20000000 ; last descriptor
162	TXFD = 0x10000000 ; first descriptor	161	TXFD = 0x10000000 ; first descriptor
163	CRCEnable = 0x08000000 ; crc control	162	CRCEnable = 0x08000000 ; crc control
164	PADEnable = 0x04000000 ; padding control	163	PADEnable = 0x04000000 ; padding control
165	RetryTxLC = 0x02000000 ; retry late collision	164	RetryTxLC = 0x02000000 ; retry late collision
166	PKTSMask = 0x3ff800 ; packet size bit21-11	165	PKTSMask = 0x3ff800 ; packet size bit21-11
167	PKTSShift = 11	166	PKTSShift = 11
168	TBSMask = 0x000007ff ; transmit buffer bit 10-0	167	TBSMask = 0x000007ff ; transmit buffer bit 10-0
169	TBSShift = 0	168	TBSShift = 0
170		169
171	; BootROM/EEPROM/MII Management Register	170	; BootROM/EEPROM/MII Management Register
172		171
173	MASK_MIIR_MII_READ = 0x00000000	172	MASK_MIIR_MII_READ = 0x00000000
174	MASK_MIIR_MII_WRITE = 0x00000008	173	MASK_MIIR_MII_WRITE = 0x00000008
175	MASK_MIIR_MII_MDO = 0x00000004	174	MASK_MIIR_MII_MDO = 0x00000004
176	MASK_MIIR_MII_MDI = 0x00000002	175	MASK_MIIR_MII_MDI = 0x00000002
177	MASK_MIIR_MII_MDC = 0x00000001	176	MASK_MIIR_MII_MDC = 0x00000001
178		177
179	; ST+OP+PHYAD+REGAD+TA	178	; ST+OP+PHYAD+REGAD+TA
180		179
181	OP_READ = 0x6000 ; ST:01+OP:10+PHYAD+REGAD+TA:Z0	180	OP_READ = 0x6000 ; ST:01+OP:10+PHYAD+REGAD+TA:Z0
182	OP_WRITE = 0x5002 ; ST:01+OP:01+PHYAD+REGAD+TA:10	181	OP_WRITE = 0x5002 ; ST:01+OP:01+PHYAD+REGAD+TA:10
183		182
184	; -------------------------------------------------------------------------	183	; -------------------------------------------------------------------------
185	; Constants for Myson PHY	184	; Constants for Myson PHY
186	; -------------------------------------------------------------------------	185	; -------------------------------------------------------------------------
187		186
188	MysonPHYID = 0xd0000302	187	MysonPHYID = 0xd0000302
189	MysonPHYID0 = 0x0302	188	MysonPHYID0 = 0x0302
190	StatusRegister = 18	189	StatusRegister = 18
191	SPEED100 = 0x0400 ; bit10	190	SPEED100 = 0x0400 ; bit10
192	FULLMODE = 0x0800 ; bit11	191	FULLMODE = 0x0800 ; bit11
193		192
194	; -------------------------------------------------------------------------	193	; -------------------------------------------------------------------------
195	; Constants for Seeq 80225 PHY	194	; Constants for Seeq 80225 PHY
196	; -------------------------------------------------------------------------	195	; -------------------------------------------------------------------------
197		196
198	SeeqPHYID0 = 0x0016	197	SeeqPHYID0 = 0x0016
199	MIIRegister18 = 18	198	MIIRegister18 = 18
200	SPD_DET_100 = 0x80	199	SPD_DET_100 = 0x80
201	DPLX_DET_FULL = 0x40	200	DPLX_DET_FULL = 0x40
202		201
203	; -------------------------------------------------------------------------	202	; -------------------------------------------------------------------------
204	; Constants for Ahdoc 101 PHY	203	; Constants for Ahdoc 101 PHY
205	; -------------------------------------------------------------------------	204	; -------------------------------------------------------------------------
206		205
207	AhdocPHYID0 = 0x0022	206	AhdocPHYID0 = 0x0022
208	DiagnosticReg = 18	207	DiagnosticReg = 18
209	DPLX_FULL = 0x0800	208	DPLX_FULL = 0x0800
210	Speed_100 = 0x0400	209	Speed_100 = 0x0400
211		210
212	; --------------------------------------------------------------------------	211	; --------------------------------------------------------------------------
213	; Constants	212	; Constants
214	; --------------------------------------------------------------------------	213	; --------------------------------------------------------------------------
215		214
216	MarvellPHYID0 = 0x0141	215	MarvellPHYID0 = 0x0141
217	LevelOnePHYID0 = 0x0013	216	LevelOnePHYID0 = 0x0013
218		217
219	MII1000BaseTControlReg = 9	218	MII1000BaseTControlReg = 9
220	MII1000BaseTStatusReg = 10	219	MII1000BaseTStatusReg = 10
221	SpecificReg = 17	220	SpecificReg = 17
222		221
223	; for 1000BaseT Control Register	222	; for 1000BaseT Control Register
224		223
225	PHYAbletoPerform1000FullDuplex = 0x0200	224	PHYAbletoPerform1000FullDuplex = 0x0200
226	PHYAbletoPerform1000HalfDuplex = 0x0100	225	PHYAbletoPerform1000HalfDuplex = 0x0100
227	PHY1000AbilityMask = 0x300	226	PHY1000AbilityMask = 0x300
228		227
229	; for phy specific status register, marvell phy.	228	; for phy specific status register, marvell phy.
230		229
231	SpeedMask = 0x0c000	230	SpeedMask = 0x0c000
232	Speed_1000M = 0x08000	231	Speed_1000M = 0x08000
233	Speed_100M = 0x4000	232	Speed_100M = 0x4000
234	Speed_10M = 0	233	Speed_10M = 0
235	Full_Duplex = 0x2000	234	Full_Duplex = 0x2000
236		235
237	; for phy specific status register, levelone phy	236	; for phy specific status register, levelone phy
238		237
239	LXT1000_100M = 0x08000	238	LXT1000_100M = 0x08000
240	LXT1000_1000M = 0x0c000	239	LXT1000_1000M = 0x0c000
241	LXT1000_Full = 0x200	240	LXT1000_Full = 0x200
242		241
243	; for PHY	242	; for PHY
244		243
245	LinkIsUp = 0x0004	244	LinkIsUp = 0x0004
246	LinkIsUp2 = 0x00040000	245	LinkIsUp2 = 0x00040000
247		246
248		247
249		248
250	struct descriptor	249	struct descriptor
251	status dd ?	250	status dd ?
252	control dd ?	251	control dd ?
253	buffer dd ?	252	buffer dd ?
254	next_desc dd ?	253	next_desc dd ?
255		254
256	next_desc_logical dd ?	255	next_desc_logical dd ?
257	skbuff dd ?	256	skbuff dd ?
258	reserved1 dd ?	257	reserved1 dd ?
259	reserved2 dd ?	258	reserved2 dd ?
260	ends	259	ends
261		260
262		261
263	struct device ETH_DEVICE	262	struct device ETH_DEVICE
264		263
265	io_addr dd ?	264	io_addr dd ?
266	pci_bus dd ?	265	pci_bus dd ?
267	pci_dev dd ?	266	pci_dev dd ?
268	irq_line db ?	267	irq_line db ?
269	dev_id dw ?	268	dev_id dw ?
270	flags dd ?	269	flags dd ?
271	crvalue dd ?	270	crvalue dd ?
272	bcrvalue dd ?	271	bcrvalue dd ?
273	cur_rx dd ?	272	cur_rx dd ?
274	cur_tx dd ?	273	cur_tx dd ?
275	default_port dd ?	274	default_port dd ?
276	PHYType dd ?	275	PHYType dd ?
277		276
278	; MII transceiver section.	277	; MII transceiver section.
279	mii_cnt dd ? ; MII device addresses.	278	mii_cnt dd ? ; MII device addresses.
280	phys db ? ; MII device addresses.	279	phys db ? ; MII device addresses.
281		280
282	; descriptors	281	; descriptors
283	rb 0x100 - ($ and 0xff) ; align 256	282	rb 0x100 - ($ and 0xff) ; align 256
284	tx_desc rb NUM_TX_DESC*sizeof.descriptor	283	tx_desc rb NUM_TX_DESC*sizeof.descriptor
285	rx_desc rb NUM_RX_DESC*sizeof.descriptor	284	rx_desc rb NUM_RX_DESC*sizeof.descriptor
286		285
287	ends	286	ends
288		287
289		288
290	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	289	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
291	;; ;;	290	;; ;;
292	;; proc START ;;	291	;; proc START ;;
293	;; ;;	292	;; ;;
294	;; (standard driver proc) ;;	293	;; (standard driver proc) ;;
295	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	294	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
296		295
297	proc START c, reason:dword, cmdline:dword	296	proc START c, reason:dword, cmdline:dword
298		297
299	cmp [reason], DRV_ENTRY	298	cmp [reason], DRV_ENTRY
300	jne .fail	299	jne .fail
301		300
302	DEBUGF 1,"Loading driver\n"	301	DEBUGF 1,"Loading driver\n"
303	invoke RegService, my_service, service_proc	302	invoke RegService, my_service, service_proc
304	ret	303	ret
305		304
306	.fail:	305	.fail:
307	xor eax, eax	306	xor eax, eax
308	ret	307	ret
309		308
310	endp	309	endp
311		310
312		311
313	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	312	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
314	;; ;;	313	;; ;;
315	;; proc SERVICE_PROC ;;	314	;; proc SERVICE_PROC ;;
316	;; ;;	315	;; ;;
317	;; (standard driver proc) ;;	316	;; (standard driver proc) ;;
318	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	317	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
319		318
320	proc service_proc stdcall, ioctl:dword	319	proc service_proc stdcall, ioctl:dword
321		320
322	mov edx, [ioctl]	321	mov edx, [ioctl]
323	mov eax, [edx + IOCTL.io_code]	322	mov eax, [edx + IOCTL.io_code]
324		323
325	;------------------------------------------------------	324	;------------------------------------------------------
326		325
327	cmp eax, 0 ;SRV_GETVERSION	326	cmp eax, 0 ;SRV_GETVERSION
328	jne @F	327	jne @F
329		328
330	cmp [edx + IOCTL.out_size], 4	329	cmp [edx + IOCTL.out_size], 4
331	jb .fail	330	jb .fail
332	mov eax, [edx + IOCTL.output]	331	mov eax, [edx + IOCTL.output]
333	mov [eax], dword API_VERSION	332	mov [eax], dword API_VERSION
334		333
335	xor eax, eax	334	xor eax, eax
336	ret	335	ret
337		336
338	;------------------------------------------------------	337	;------------------------------------------------------
339	@@:	338	@@:
340	cmp eax, 1 ;SRV_HOOK	339	cmp eax, 1 ;SRV_HOOK
341	jne .fail	340	jne .fail
342		341
343	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	342	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
344	jb .fail	343	jb .fail
345		344
346	mov eax, [edx + IOCTL.input]	345	mov eax, [edx + IOCTL.input]
347	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given	346	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
348	jne .fail ; other types arent supported for this card yet	347	jne .fail ; other types arent supported for this card yet
349		348
350	; check if the device is already listed	349	; check if the device is already listed
351		350
352	mov esi, device_list	351	mov esi, device_list
353	mov ecx, [devices]	352	mov ecx, [devices]
354	test ecx, ecx	353	test ecx, ecx
355	jz .firstdevice	354	jz .firstdevice
356		355
357	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers	356	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
358	mov ax, [eax+1] ;	357	mov ax, [eax+1] ;
359	.nextdevice:	358	.nextdevice:
360	mov ebx, [esi]	359	mov ebx, [esi]
361	cmp al, byte[ebx + device.pci_bus]	360	cmp al, byte[ebx + device.pci_bus]
362	jne @f	361	jne @f
363	cmp ah, byte[ebx + device.pci_dev]	362	cmp ah, byte[ebx + device.pci_dev]
364	je .find_devicenum ; Device is already loaded, let's find it's device number	363	je .find_devicenum ; Device is already loaded, let's find it's device number
365	@@:	364	@@:
366	add esi, 4	365	add esi, 4
367	loop .nextdevice	366	loop .nextdevice
368		367
369		368
370	; This device doesnt have its own eth_device structure yet, lets create one	369	; This device doesnt have its own eth_device structure yet, lets create one
371	.firstdevice:	370	.firstdevice:
372	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	371	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
373	jae .fail	372	jae .fail
374		373
375	allocate_and_clear ebx, sizeof.device, .fail	374	allocate_and_clear ebx, sizeof.device, .fail
376		375
377	; Fill in the direct call addresses into the struct	376	; Fill in the direct call addresses into the struct
378		377
379	mov [ebx + device.reset], reset	378	mov [ebx + device.reset], reset
380	mov [ebx + device.transmit], transmit	379	mov [ebx + device.transmit], transmit
381	mov [ebx + device.unload], unload	380	mov [ebx + device.unload], unload
382	mov [ebx + device.name], my_service	381	mov [ebx + device.name], my_service
383		382
384	; save the pci bus and device numbers	383	; save the pci bus and device numbers
385		384
386	mov eax, [edx + IOCTL.input]	385	mov eax, [edx + IOCTL.input]
387	movzx ecx, byte[eax+1]	386	movzx ecx, byte[eax+1]
388	mov [ebx + device.pci_bus], ecx	387	mov [ebx + device.pci_bus], ecx
389	movzx ecx, byte[eax+2]	388	movzx ecx, byte[eax+2]
390	mov [ebx + device.pci_dev], ecx	389	mov [ebx + device.pci_dev], ecx
391		390
392	; Now, it's time to find the base io addres of the PCI device	391	; Now, it's time to find the base io addres of the PCI device
393		392
394	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]	393	stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
395	mov [ebx + device.io_addr], eax	394	mov [ebx + device.io_addr], eax
396		395
397	; We've found the io address, find IRQ now	396	; We've found the io address, find IRQ now
398		397
399	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line	398	invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
400	mov [ebx + device.irq_line], al	399	mov [ebx + device.irq_line], al
401		400
402	DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	401	DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
403	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8	402	[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:8
404		403
405	; Ok, the eth_device structure is ready, let's probe the device	404	; Ok, the eth_device structure is ready, let's probe the device
406	; Because initialization fires IRQ, IRQ handler must be aware of this device	405	; Because initialization fires IRQ, IRQ handler must be aware of this device
407	mov eax, [devices] ; Add the device structure to our device list	406	mov eax, [devices] ; Add the device structure to our device list
408	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)	407	mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)
409	inc [devices] ;	408	inc [devices] ;
410		409
411	call probe ; this function will output in eax	410	call probe ; this function will output in eax
412	test eax, eax	411	test eax, eax
413	jnz .err2 ; If an error occured, exit	412	jnz .err2 ; If an error occured, exit
414		413
415	mov [ebx + device.type], NET_TYPE_ETH	414	mov [ebx + device.type], NET_TYPE_ETH
416	invoke NetRegDev	415	invoke NetRegDev
417		416
418	cmp eax, -1	417	cmp eax, -1
419	je .destroy	418	je .destroy
420		419
421	ret	420	ret
422		421
423	; If the device was already loaded, find the device number and return it in eax	422	; If the device was already loaded, find the device number and return it in eax
424		423
425	.find_devicenum:	424	.find_devicenum:
426	DEBUGF 2,"Trying to find device number of already registered device\n"	425	DEBUGF 2,"Trying to find device number of already registered device\n"
427	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx	426	invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
428	; into a device number in edi	427	; into a device number in edi
429	mov eax, edi ; Application wants it in eax instead	428	mov eax, edi ; Application wants it in eax instead
430	DEBUGF 2,"Kernel says: %u\n", eax	429	DEBUGF 2,"Kernel says: %u\n", eax
431	ret	430	ret
432		431
433	; If an error occured, remove all allocated data and exit (returning -1 in eax)	432	; If an error occured, remove all allocated data and exit (returning -1 in eax)
434		433
435	.destroy:	434	.destroy:
436	; todo: reset device into virgin state	435	; todo: reset device into virgin state
437		436
438	.err2:	437	.err2:
439	dec [devices]	438	dec [devices]
440	.err:	439	.err:
441	DEBUGF 2,"removing device structure\n"	440	DEBUGF 2,"removing device structure\n"
442	invoke KernelFree, ebx	441	invoke KernelFree, ebx
443	.fail:	442	.fail:
444	or eax, -1	443	or eax, -1
445	ret	444	ret
446		445
447	;------------------------------------------------------	446	;------------------------------------------------------
448	endp	447	endp
449		448
450		449
451	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;	450	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
452	;; ;;	451	;; ;;
453	;; Actual Hardware dependent code starts here ;;	452	;; Actual Hardware dependent code starts here ;;
454	;; ;;	453	;; ;;
455	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;	454	;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
456		455
457		456
458		457
459	align 4	458	align 4
460	unload:	459	unload:
461	; TODO: (in this particular order)	460	; TODO: (in this particular order)
462	;	461	;
463	; - Stop the device	462	; - Stop the device
464		463
465	; /* Disable Tx Rx*/	464	; /* Disable Tx Rx*/
466	; outl( mtdx.crvalue & (~TxEnable) & (~RxEnable), mtdx.ioaddr + TCRRCR );	465	; outl( mtdx.crvalue & (~TxEnable) & (~RxEnable), mtdx.ioaddr + TCRRCR );
467	;	466	;
468	; /* Reset the chip to erase previous misconfiguration. */	467	; /* Reset the chip to erase previous misconfiguration. */
469	; mtd_reset(nic);	468	; mtd_reset(nic);
470		469
471	; - Detach int handler	470	; - Detach int handler
472	; - Remove device from local list (device_list)	471	; - Remove device from local list (device_list)
473	; - call unregister function in kernel	472	; - call unregister function in kernel
474	; - Remove all allocated structures and buffers the card used	473	; - Remove all allocated structures and buffers the card used
475		474
476	or eax, -1	475	or eax, -1
477		476
478	ret	477	ret
479		478
480		479
481	;-------	480	;-------
482	;	481	;
483	; PROBE	482	; PROBE
484	;	483	;
485	;-------	484	;-------
486	align 4	485	align 4
487	probe:	486	probe:
488		487
489	DEBUGF 1,"Probing\n"	488	DEBUGF 1,"Probing\n"
490		489
491	; Make the device a bus master	490	; Make the device a bus master
492	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command	491	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
493	or al, PCI_CMD_MASTER	492	or al, PCI_CMD_MASTER
494	invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax	493	invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
495		494
496	; Check vendor/device id's	495	; Check vendor/device id's
497	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], 0	496	invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], 0
498	cmp ax, 0x1516	497	cmp ax, 0x1516
499	jne .notfound	498	jne .notfound
500	shr eax, 16	499	shr eax, 16

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(root)/drivers/ethernet/mtd80x.asm – Rev 4629 → 4663