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1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
2 | ;; ;; |
3 | ;; Copyright (C) KolibriOS team 2004-2017. All rights reserved. ;; |
3 | ;; Copyright (C) KolibriOS team 2004-2018. All rights reserved. ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
5 | ;; ;; |
6 | ;; i8254x driver for KolibriOS ;; |
6 | ;; i8254x driver for KolibriOS ;; |
7 | ;; ;; |
7 | ;; ;; |
8 | ;; based on i8254x.asm from baremetal os ;; |
8 | ;; based on i8254x.asm from baremetal os ;; |
9 | ;; ;; |
9 | ;; ;; |
10 | ;; Written by hidnplayr (hidnplayr@gmail.com) ;; |
10 | ;; Written by hidnplayr (hidnplayr@gmail.com) ;; |
11 | ;; ;; |
11 | ;; ;; |
12 | ;; GNU GENERAL PUBLIC LICENSE ;; |
12 | ;; GNU GENERAL PUBLIC LICENSE ;; |
13 | ;; Version 2, June 1991 ;; |
13 | ;; Version 2, June 1991 ;; |
14 | ;; ;; |
14 | ;; ;; |
15 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
15 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
16 | 16 | ||
17 | format PE DLL native |
17 | format PE DLL native |
18 | entry START |
18 | entry START |
19 | 19 | ||
20 | CURRENT_API = 0x0200 |
20 | CURRENT_API = 0x0200 |
21 | COMPATIBLE_API = 0x0100 |
21 | COMPATIBLE_API = 0x0100 |
22 | API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API |
22 | API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API |
23 | 23 | ||
24 | MAX_DEVICES = 16 |
24 | MAX_DEVICES = 16 |
25 | 25 | ||
26 | __DEBUG__ = 1 |
26 | __DEBUG__ = 1 |
27 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
27 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
28 | 28 | ||
29 | MAX_PKT_SIZE = 1514 ; Maximum packet size |
29 | MAX_PKT_SIZE = 1514 ; Maximum packet size |
30 | 30 | ||
31 | RX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
31 | RX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
32 | TX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
32 | TX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
33 | 33 | ||
34 | section '.flat' readable writable executable |
34 | section '.flat' readable writable executable |
35 | 35 | ||
36 | include '../proc32.inc' |
36 | include '../proc32.inc' |
37 | include '../struct.inc' |
37 | include '../struct.inc' |
38 | include '../macros.inc' |
38 | include '../macros.inc' |
39 | include '../fdo.inc' |
39 | include '../fdo.inc' |
40 | include '../netdrv.inc' |
40 | include '../netdrv.inc' |
41 | 41 | ||
42 | ; Register list |
42 | ; Register list |
43 | REG_CTRL = 0x0000 ; Control Register |
43 | REG_CTRL = 0x0000 ; Control Register |
44 | REG_STATUS = 0x0008 ; Device Status Register |
44 | REG_STATUS = 0x0008 ; Device Status Register |
45 | REG_CTRLEXT = 0x0018 ; Extended Control Register |
45 | REG_CTRLEXT = 0x0018 ; Extended Control Register |
46 | REG_MDIC = 0x0020 ; MDI Control Register |
46 | REG_MDIC = 0x0020 ; MDI Control Register |
47 | REG_FCAL = 0x0028 ; Flow Control Address Low |
47 | REG_FCAL = 0x0028 ; Flow Control Address Low |
48 | REG_FCAH = 0x002C ; Flow Control Address High |
48 | REG_FCAH = 0x002C ; Flow Control Address High |
49 | REG_FCT = 0x0030 ; Flow Control Type |
49 | REG_FCT = 0x0030 ; Flow Control Type |
50 | REG_VET = 0x0038 ; VLAN Ether Type |
50 | REG_VET = 0x0038 ; VLAN Ether Type |
51 | REG_ICR = 0x00C0 ; Interrupt Cause Read |
51 | REG_ICR = 0x00C0 ; Interrupt Cause Read |
52 | REG_ITR = 0x00C4 ; Interrupt Throttling Register |
52 | REG_ITR = 0x00C4 ; Interrupt Throttling Register |
53 | REG_ICS = 0x00C8 ; Interrupt Cause Set Register |
53 | REG_ICS = 0x00C8 ; Interrupt Cause Set Register |
54 | REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register |
54 | REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register |
55 | REG_IMC = 0x00D8 ; Interrupt Mask Clear Register |
55 | REG_IMC = 0x00D8 ; Interrupt Mask Clear Register |
56 | REG_RCTL = 0x0100 ; Receive Control Register |
56 | REG_RCTL = 0x0100 ; Receive Control Register |
57 | REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value |
57 | REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value |
58 | REG_TXCW = 0x0178 ; Transmit Configuration Word |
58 | REG_TXCW = 0x0178 ; Transmit Configuration Word |
59 | REG_RXCW = 0x0180 ; Receive Configuration Word |
59 | REG_RXCW = 0x0180 ; Receive Configuration Word |
60 | REG_TCTL = 0x0400 ; Transmit Control Register |
60 | REG_TCTL = 0x0400 ; Transmit Control Register |
61 | REG_TIPG = 0x0410 ; Transmit Inter Packet Gap |
61 | REG_TIPG = 0x0410 ; Transmit Inter Packet Gap |
62 | 62 | ||
63 | REG_LEDCTL = 0x0E00 ; LED Control |
63 | REG_LEDCTL = 0x0E00 ; LED Control |
64 | REG_PBA = 0x1000 ; Packet Buffer Allocation |
64 | REG_PBA = 0x1000 ; Packet Buffer Allocation |
65 | 65 | ||
66 | REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low |
66 | REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low |
67 | REG_RDBAH = 0x2804 ; RX Descriptor Base Address High |
67 | REG_RDBAH = 0x2804 ; RX Descriptor Base Address High |
68 | REG_RDLEN = 0x2808 ; RX Descriptor Length |
68 | REG_RDLEN = 0x2808 ; RX Descriptor Length |
69 | REG_RDH = 0x2810 ; RX Descriptor Head |
69 | REG_RDH = 0x2810 ; RX Descriptor Head |
70 | REG_RDT = 0x2818 ; RX Descriptor Tail |
70 | REG_RDT = 0x2818 ; RX Descriptor Tail |
71 | REG_RDTR = 0x2820 ; RX Delay Timer Register |
71 | REG_RDTR = 0x2820 ; RX Delay Timer Register |
72 | REG_RXDCTL = 0x3828 ; RX Descriptor Control |
72 | REG_RXDCTL = 0x3828 ; RX Descriptor Control |
73 | REG_RADV = 0x282C ; RX Int. Absolute Delay Timer |
73 | REG_RADV = 0x282C ; RX Int. Absolute Delay Timer |
74 | REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt |
74 | REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt |
75 | 75 | ||
76 | REG_TXDMAC = 0x3000 ; TX DMA Control |
76 | REG_TXDMAC = 0x3000 ; TX DMA Control |
77 | REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low |
77 | REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low |
78 | REG_TDBAH = 0x3804 ; TX Descriptor Base Address High |
78 | REG_TDBAH = 0x3804 ; TX Descriptor Base Address High |
79 | REG_TDLEN = 0x3808 ; TX Descriptor Length |
79 | REG_TDLEN = 0x3808 ; TX Descriptor Length |
80 | REG_TDH = 0x3810 ; TX Descriptor Head |
80 | REG_TDH = 0x3810 ; TX Descriptor Head |
81 | REG_TDT = 0x3818 ; TX Descriptor Tail |
81 | REG_TDT = 0x3818 ; TX Descriptor Tail |
82 | REG_TIDV = 0x3820 ; TX Interrupt Delay Value |
82 | REG_TIDV = 0x3820 ; TX Interrupt Delay Value |
83 | REG_TXDCTL = 0x3828 ; TX Descriptor Control |
83 | REG_TXDCTL = 0x3828 ; TX Descriptor Control |
84 | REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value |
84 | REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value |
85 | REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold |
85 | REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold |
86 | 86 | ||
87 | REG_RXCSUM = 0x5000 ; RX Checksum Control |
87 | REG_RXCSUM = 0x5000 ; RX Checksum Control |
88 | 88 | ||
89 | ; Register list for i8254x |
89 | ; Register list for i8254x |
90 | I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register |
90 | I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register |
91 | I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low |
91 | I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low |
92 | I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High |
92 | I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High |
93 | I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length |
93 | I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length |
94 | I82542_REG_RDH = 0x0120 ; RDH for i82542 |
94 | I82542_REG_RDH = 0x0120 ; RDH for i82542 |
95 | I82542_REG_RDT = 0x0128 ; RDT for i82542 |
95 | I82542_REG_RDT = 0x0128 ; RDT for i82542 |
96 | I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low |
96 | I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low |
97 | I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low |
97 | I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low |
98 | I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length |
98 | I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length |
99 | I82542_REG_TDH = 0x0430 ; TDH for i82542 |
99 | I82542_REG_TDH = 0x0430 ; TDH for i82542 |
100 | I82542_REG_TDT = 0x0438 ; TDT for i82542 |
100 | I82542_REG_TDT = 0x0438 ; TDT for i82542 |
101 | 101 | ||
102 | ; CTRL - Control Register (0x0000) |
102 | ; CTRL - Control Register (0x0000) |
103 | CTRL_FD = 0x00000001 ; Full Duplex |
103 | CTRL_FD = 0x00000001 ; Full Duplex |
104 | CTRL_LRST = 0x00000008 ; Link Reset |
104 | CTRL_LRST = 0x00000008 ; Link Reset |
105 | CTRL_ASDE = 0x00000020 ; Auto-speed detection |
105 | CTRL_ASDE = 0x00000020 ; Auto-speed detection |
106 | CTRL_SLU = 0x00000040 ; Set Link Up |
106 | CTRL_SLU = 0x00000040 ; Set Link Up |
107 | CTRL_ILOS = 0x00000080 ; Invert Loss of Signal |
107 | CTRL_ILOS = 0x00000080 ; Invert Loss of Signal |
108 | CTRL_SPEED_MASK = 0x00000300 ; Speed selection |
108 | CTRL_SPEED_MASK = 0x00000300 ; Speed selection |
109 | CTRL_SPEED_SHIFT = 8 |
109 | CTRL_SPEED_SHIFT = 8 |
110 | CTRL_FRCSPD = 0x00000800 ; Force Speed |
110 | CTRL_FRCSPD = 0x00000800 ; Force Speed |
111 | CTRL_FRCDPLX = 0x00001000 ; Force Duplex |
111 | CTRL_FRCDPLX = 0x00001000 ; Force Duplex |
112 | CTRL_SDP0_DATA = 0x00040000 ; SDP0 data |
112 | CTRL_SDP0_DATA = 0x00040000 ; SDP0 data |
113 | CTRL_SDP1_DATA = 0x00080000 ; SDP1 data |
113 | CTRL_SDP1_DATA = 0x00080000 ; SDP1 data |
114 | CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction |
114 | CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction |
115 | CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction |
115 | CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction |
116 | CTRL_RST = 0x04000000 ; Device Reset |
116 | CTRL_RST = 0x04000000 ; Device Reset |
117 | CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable |
117 | CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable |
118 | CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable |
118 | CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable |
119 | CTRL_VME = 0x40000000 ; VLAN Mode Enable |
119 | CTRL_VME = 0x40000000 ; VLAN Mode Enable |
120 | CTRL_PHY_RST = 0x80000000 ; PHY reset |
120 | CTRL_PHY_RST = 0x80000000 ; PHY reset |
121 | 121 | ||
122 | ; STATUS - Device Status Register (0x0008) |
122 | ; STATUS - Device Status Register (0x0008) |
123 | STATUS_FD = 0x00000001 ; Full Duplex |
123 | STATUS_FD = 0x00000001 ; Full Duplex |
124 | STATUS_LU = 0x00000002 ; Link Up |
124 | STATUS_LU = 0x00000002 ; Link Up |
125 | STATUS_TXOFF = 0x00000010 ; Transmit paused |
125 | STATUS_TXOFF = 0x00000010 ; Transmit paused |
126 | STATUS_TBIMODE = 0x00000020 ; TBI Mode |
126 | STATUS_TBIMODE = 0x00000020 ; TBI Mode |
127 | STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting |
127 | STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting |
128 | STATUS_SPEED_SHIFT = 6 |
128 | STATUS_SPEED_SHIFT = 6 |
129 | STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection |
129 | STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection |
130 | STATUS_ASDV_SHIFT = 8 |
130 | STATUS_ASDV_SHIFT = 8 |
131 | STATUS_PCI66 = 0x00000800 ; PCI bus speed |
131 | STATUS_PCI66 = 0x00000800 ; PCI bus speed |
132 | STATUS_BUS64 = 0x00001000 ; PCI bus width |
132 | STATUS_BUS64 = 0x00001000 ; PCI bus width |
133 | STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode |
133 | STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode |
134 | STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed |
134 | STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed |
135 | STATUS_PCIXSPD_SHIFT = 14 |
135 | STATUS_PCIXSPD_SHIFT = 14 |
136 | 136 | ||
137 | ; CTRL_EXT - Extended Device Control Register (0x0018) |
137 | ; CTRL_EXT - Extended Device Control Register (0x0018) |
138 | CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt |
138 | CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt |
139 | CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data |
139 | CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data |
140 | CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data |
140 | CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data |
141 | CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction |
141 | CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction |
142 | CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction |
142 | CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction |
143 | CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk |
143 | CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk |
144 | CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset |
144 | CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset |
145 | CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass |
145 | CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass |
146 | CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis. |
146 | CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis. |
147 | CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode |
147 | CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode |
148 | CTRLEXT_LNKMOD_SHIFT = 22 |
148 | CTRLEXT_LNKMOD_SHIFT = 22 |
149 | 149 | ||
150 | ; MDIC - MDI Control Register (0x0020) |
150 | ; MDIC - MDI Control Register (0x0020) |
151 | MDIC_DATA_MASK = 0x0000FFFF ; Data |
151 | MDIC_DATA_MASK = 0x0000FFFF ; Data |
152 | MDIC_REG_MASK = 0x001F0000 ; PHY Register |
152 | MDIC_REG_MASK = 0x001F0000 ; PHY Register |
153 | MDIC_REG_SHIFT = 16 |
153 | MDIC_REG_SHIFT = 16 |
154 | MDIC_PHY_MASK = 0x03E00000 ; PHY Address |
154 | MDIC_PHY_MASK = 0x03E00000 ; PHY Address |
155 | MDIC_PHY_SHIFT = 21 |
155 | MDIC_PHY_SHIFT = 21 |
156 | MDIC_OP_MASK = 0x0C000000 ; Opcode |
156 | MDIC_OP_MASK = 0x0C000000 ; Opcode |
157 | MDIC_OP_SHIFT = 26 |
157 | MDIC_OP_SHIFT = 26 |
158 | MDIC_R = 0x10000000 ; Ready |
158 | MDIC_R = 0x10000000 ; Ready |
159 | MDIC_I = 0x20000000 ; Interrupt Enable |
159 | MDIC_I = 0x20000000 ; Interrupt Enable |
160 | MDIC_E = 0x40000000 ; Error |
160 | MDIC_E = 0x40000000 ; Error |
161 | 161 | ||
162 | ; ICR - Interrupt Cause Read (0x00c0) |
162 | ; ICR - Interrupt Cause Read (0x00c0) |
163 | ICR_TXDW = 0x00000001 ; TX Desc Written back |
163 | ICR_TXDW = 0x00000001 ; TX Desc Written back |
164 | ICR_TXQE = 0x00000002 ; TX Queue Empty |
164 | ICR_TXQE = 0x00000002 ; TX Queue Empty |
165 | ICR_LSC = 0x00000004 ; Link Status Change |
165 | ICR_LSC = 0x00000004 ; Link Status Change |
166 | ICR_RXSEQ = 0x00000008 ; RX Sence Error |
166 | ICR_RXSEQ = 0x00000008 ; RX Sence Error |
167 | ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached |
167 | ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached |
168 | ICR_RXO = 0x00000040 ; RX Overrun |
168 | ICR_RXO = 0x00000040 ; RX Overrun |
169 | ICR_RXT0 = 0x00000080 ; RX Timer Interrupt |
169 | ICR_RXT0 = 0x00000080 ; RX Timer Interrupt |
170 | ICR_MDAC = 0x00000200 ; MDIO Access Complete |
170 | ICR_MDAC = 0x00000200 ; MDIO Access Complete |
171 | ICR_RXCFG = 0x00000400 |
171 | ICR_RXCFG = 0x00000400 |
172 | ICR_PHY_INT = 0x00001000 ; PHY Interrupt |
172 | ICR_PHY_INT = 0x00001000 ; PHY Interrupt |
173 | ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6 |
173 | ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6 |
174 | ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7 |
174 | ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7 |
175 | ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit |
175 | ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit |
176 | ICR_SRPD = 0x00010000 ; Small RX packet detected |
176 | ICR_SRPD = 0x00010000 ; Small RX packet detected |
177 | 177 | ||
178 | ; RCTL - Receive Control Register (0x0100) |
178 | ; RCTL - Receive Control Register (0x0100) |
179 | RCTL_EN = 0x00000002 ; Receiver Enable |
179 | RCTL_EN = 0x00000002 ; Receiver Enable |
180 | RCTL_SBP = 0x00000004 ; Store Bad Packets |
180 | RCTL_SBP = 0x00000004 ; Store Bad Packets |
181 | RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled |
181 | RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled |
182 | RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled |
182 | RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled |
183 | RCTL_LPE = 0x00000020 ; Long Packet Reception Enable |
183 | RCTL_LPE = 0x00000020 ; Long Packet Reception Enable |
184 | RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode |
184 | RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode |
185 | RCTL_LBM_SHIFT = 6 |
185 | RCTL_LBM_SHIFT = 6 |
186 | RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size |
186 | RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size |
187 | RCTL_RDMTS_SHIFT = 8 |
187 | RCTL_RDMTS_SHIFT = 8 |
188 | RCTL_MO_MASK = 0x00003000 ; Multicast Offset |
188 | RCTL_MO_MASK = 0x00003000 ; Multicast Offset |
189 | RCTL_MO_SHIFT = 12 |
189 | RCTL_MO_SHIFT = 12 |
190 | RCTL_BAM = 0x00008000 ; Broadcast Accept Mode |
190 | RCTL_BAM = 0x00008000 ; Broadcast Accept Mode |
191 | RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size |
191 | RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size |
192 | RCTL_BSIZE_SHIFT = 16 |
192 | RCTL_BSIZE_SHIFT = 16 |
193 | RCTL_VFE = 0x00040000 ; VLAN Filter Enable |
193 | RCTL_VFE = 0x00040000 ; VLAN Filter Enable |
194 | RCTL_CFIEN = 0x00080000 ; CFI Enable |
194 | RCTL_CFIEN = 0x00080000 ; CFI Enable |
195 | RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit |
195 | RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit |
196 | RCTL_DPF = 0x00400000 ; Discard Pause Frames |
196 | RCTL_DPF = 0x00400000 ; Discard Pause Frames |
197 | RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames |
197 | RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames |
198 | RCTL_BSEX = 0x02000000 ; Buffer Size Extension |
198 | RCTL_BSEX = 0x02000000 ; Buffer Size Extension |
199 | RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC |
199 | RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC |
200 | 200 | ||
201 | ; TCTL - Transmit Control Register (0x0400) |
201 | ; TCTL - Transmit Control Register (0x0400) |
202 | TCTL_EN = 0x00000002 ; Transmit Enable |
202 | TCTL_EN = 0x00000002 ; Transmit Enable |
203 | TCTL_PSP = 0x00000008 ; Pad short packets |
203 | TCTL_PSP = 0x00000008 ; Pad short packets |
204 | TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission |
204 | TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission |
205 | 205 | ||
206 | ; PBA - Packet Buffer Allocation (0x1000) |
206 | ; PBA - Packet Buffer Allocation (0x1000) |
207 | PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer |
207 | PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer |
208 | PBA_RXA_SHIFT = 0 |
208 | PBA_RXA_SHIFT = 0 |
209 | PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer |
209 | PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer |
210 | PBA_TXA_SHIFT = 16 |
210 | PBA_TXA_SHIFT = 16 |
211 | 211 | ||
212 | ; Flow Control Type |
212 | ; Flow Control Type |
213 | FCT_TYPE_DEFAULT = 0x8808 |
213 | FCT_TYPE_DEFAULT = 0x8808 |
214 | 214 | ||
215 | 215 | ||
216 | 216 | ||
217 | ; === TX Descriptor === |
217 | ; === TX Descriptor === |
218 | 218 | ||
219 | struct TDESC |
219 | struct TDESC |
220 | addr_l dd ? |
220 | addr_l dd ? |
221 | addr_h dd ? |
221 | addr_h dd ? |
222 | length_cso_cmd dd ? ; 16 bits length + 8 bits cso + 8 bits cmd |
222 | length_cso_cmd dd ? ; 16 bits length + 8 bits cso + 8 bits cmd |
223 | status dd ? ; status, checksum start field, special |
223 | status dd ? ; status, checksum start field, special |
224 | ends |
224 | ends |
225 | 225 | ||
226 | ; TX Packet Length (word 2) |
226 | ; TX Packet Length (word 2) |
227 | TXDESC_LEN_MASK = 0x0000ffff |
227 | TXDESC_LEN_MASK = 0x0000ffff |
228 | 228 | ||
229 | ; TX Descriptor CMD field (word 2) |
229 | ; TX Descriptor CMD field (word 2) |
230 | TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable |
230 | TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable |
231 | TXDESC_VLE = 0x40000000 ; VLAN Packet Enable |
231 | TXDESC_VLE = 0x40000000 ; VLAN Packet Enable |
232 | TXDESC_DEXT = 0x20000000 ; Extension |
232 | TXDESC_DEXT = 0x20000000 ; Extension |
233 | TXDESC_RPS = 0x10000000 ; Report Packet Sent |
233 | TXDESC_RPS = 0x10000000 ; Report Packet Sent |
234 | TXDESC_RS = 0x08000000 ; Report Status |
234 | TXDESC_RS = 0x08000000 ; Report Status |
235 | TXDESC_IC = 0x04000000 ; Insert Checksum |
235 | TXDESC_IC = 0x04000000 ; Insert Checksum |
236 | TXDESC_IFCS = 0x02000000 ; Insert FCS |
236 | TXDESC_IFCS = 0x02000000 ; Insert FCS |
237 | TXDESC_EOP = 0x01000000 ; End Of Packet |
237 | TXDESC_EOP = 0x01000000 ; End Of Packet |
238 | 238 | ||
239 | ; TX Descriptor STA field (word 3) |
239 | ; TX Descriptor STA field (word 3) |
240 | TXDESC_TU = 0x00000008 ; Transmit Underrun |
240 | TXDESC_TU = 0x00000008 ; Transmit Underrun |
241 | TXDESC_LC = 0x00000004 ; Late Collision |
241 | TXDESC_LC = 0x00000004 ; Late Collision |
242 | TXDESC_EC = 0x00000002 ; Excess Collisions |
242 | TXDESC_EC = 0x00000002 ; Excess Collisions |
243 | TXDESC_DD = 0x00000001 ; Descriptor Done |
243 | TXDESC_DD = 0x00000001 ; Descriptor Done |
244 | 244 | ||
245 | 245 | ||
246 | 246 | ||
247 | ; === RX Descriptor === |
247 | ; === RX Descriptor === |
248 | 248 | ||
249 | struct RDESC |
249 | struct RDESC |
250 | addr_l dd ? |
250 | addr_l dd ? |
251 | addr_h dd ? |
251 | addr_h dd ? |
252 | status_l dd ? |
252 | status_l dd ? |
253 | status_h dd ? |
253 | status_h dd ? |
254 | ends |
254 | ends |
255 | 255 | ||
256 | ; RX Packet Length (word 2) |
256 | ; RX Packet Length (word 2) |
257 | RXDESC_LEN_MASK = 0x0000ffff |
257 | RXDESC_LEN_MASK = 0x0000ffff |
258 | 258 | ||
259 | ; RX Descriptor STA field (word 3) |
259 | ; RX Descriptor STA field (word 3) |
260 | RXDESC_PIF = 0x00000080 ; Passed In-exact Filter |
260 | RXDESC_PIF = 0x00000080 ; Passed In-exact Filter |
261 | RXDESC_IPCS = 0x00000040 ; IP cksum calculated |
261 | RXDESC_IPCS = 0x00000040 ; IP cksum calculated |
262 | RXDESC_TCPCS = 0x00000020 ; TCP cksum calculated |
262 | RXDESC_TCPCS = 0x00000020 ; TCP cksum calculated |
263 | RXDESC_VP = 0x00000008 ; Packet is 802.1Q |
263 | RXDESC_VP = 0x00000008 ; Packet is 802.1Q |
264 | RXDESC_IXSM = 0x00000004 ; Ignore cksum indication |
264 | RXDESC_IXSM = 0x00000004 ; Ignore cksum indication |
265 | RXDESC_EOP = 0x00000002 ; End Of Packet |
265 | RXDESC_EOP = 0x00000002 ; End Of Packet |
266 | RXDESC_DD = 0x00000001 ; Descriptor Done |
266 | RXDESC_DD = 0x00000001 ; Descriptor Done |
267 | 267 | ||
268 | struct device ETH_DEVICE |
268 | struct device ETH_DEVICE |
269 | 269 | ||
270 | mmio_addr dd ? |
270 | mmio_addr dd ? |
271 | pci_bus dd ? |
271 | pci_bus dd ? |
272 | pci_dev dd ? |
272 | pci_dev dd ? |
273 | irq_line db ? |
273 | irq_line db ? |
274 | 274 | ||
275 | cur_rx dd ? |
275 | cur_rx dd ? |
276 | cur_tx dd ? |
276 | cur_tx dd ? |
277 | last_tx dd ? |
277 | last_tx dd ? |
278 | 278 | ||
279 | rb 0x100 - ($ and 0xff) ; align 256 |
279 | rb 0x100 - ($ and 0xff) ; align 256 |
280 | rx_desc rb RX_RING_SIZE*sizeof.RDESC*2 |
280 | rx_desc rb RX_RING_SIZE*sizeof.RDESC*2 |
281 | 281 | ||
282 | rb 0x100 - ($ and 0xff) ; align 256 |
282 | rb 0x100 - ($ and 0xff) ; align 256 |
283 | tx_desc rb TX_RING_SIZE*sizeof.TDESC*2 |
283 | tx_desc rb TX_RING_SIZE*sizeof.TDESC*2 |
284 | 284 | ||
285 | ends |
285 | ends |
286 | 286 | ||
287 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
287 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
288 | ;; ;; |
288 | ;; ;; |
289 | ;; proc START ;; |
289 | ;; proc START ;; |
290 | ;; ;; |
290 | ;; ;; |
291 | ;; (standard driver proc) ;; |
291 | ;; (standard driver proc) ;; |
292 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
292 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
293 | 293 | ||
294 | proc START c, reason:dword, cmdline:dword |
294 | proc START c, reason:dword, cmdline:dword |
295 | 295 | ||
296 | cmp [reason], DRV_ENTRY |
296 | cmp [reason], DRV_ENTRY |
297 | jne .fail |
297 | jne .fail |
298 | 298 | ||
299 | DEBUGF 1,"Loading driver\n" |
299 | DEBUGF 1,"Loading driver\n" |
300 | invoke RegService, my_service, service_proc |
300 | invoke RegService, my_service, service_proc |
301 | ret |
301 | ret |
302 | 302 | ||
303 | .fail: |
303 | .fail: |
304 | xor eax, eax |
304 | xor eax, eax |
305 | ret |
305 | ret |
306 | 306 | ||
307 | endp |
307 | endp |
308 | 308 | ||
309 | 309 | ||
310 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
310 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
311 | ;; ;; |
311 | ;; ;; |
312 | ;; proc SERVICE_PROC ;; |
312 | ;; proc SERVICE_PROC ;; |
313 | ;; ;; |
313 | ;; ;; |
314 | ;; (standard driver proc) ;; |
314 | ;; (standard driver proc) ;; |
315 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
315 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
316 | 316 | ||
317 | align 4 |
317 | align 4 |
318 | proc service_proc stdcall, ioctl:dword |
318 | proc service_proc stdcall, ioctl:dword |
319 | 319 | ||
320 | mov edx, [ioctl] |
320 | mov edx, [ioctl] |
321 | mov eax, [edx + IOCTL.io_code] |
321 | mov eax, [edx + IOCTL.io_code] |
322 | 322 | ||
323 | ;------------------------------------------------------ |
323 | ;------------------------------------------------------ |
324 | 324 | ||
325 | cmp eax, 0 ;SRV_GETVERSION |
325 | cmp eax, 0 ;SRV_GETVERSION |
326 | jne @F |
326 | jne @F |
327 | 327 | ||
328 | cmp [edx + IOCTL.out_size], 4 |
328 | cmp [edx + IOCTL.out_size], 4 |
329 | jb .fail |
329 | jb .fail |
330 | mov eax, [edx + IOCTL.output] |
330 | mov eax, [edx + IOCTL.output] |
331 | mov dword[eax], API_VERSION |
331 | mov dword[eax], API_VERSION |
332 | 332 | ||
333 | xor eax, eax |
333 | xor eax, eax |
334 | ret |
334 | ret |
335 | 335 | ||
336 | ;------------------------------------------------------ |
336 | ;------------------------------------------------------ |
337 | @@: |
337 | @@: |
338 | cmp eax, 1 ;SRV_HOOK |
338 | cmp eax, 1 ;SRV_HOOK |
339 | jne .fail |
339 | jne .fail |
340 | 340 | ||
341 | cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
341 | cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
342 | jb .fail |
342 | jb .fail |
343 | 343 | ||
344 | mov eax, [edx + IOCTL.input] |
344 | mov eax, [edx + IOCTL.input] |
345 | cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given |
345 | cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given |
346 | jne .fail ; other types arent supported for this card yet |
346 | jne .fail ; other types arent supported for this card yet |
347 | 347 | ||
348 | ; check if the device is already listed |
348 | ; check if the device is already listed |
349 | 349 | ||
350 | mov esi, device_list |
350 | mov esi, device_list |
351 | mov ecx, [devices] |
351 | mov ecx, [devices] |
352 | test ecx, ecx |
352 | test ecx, ecx |
353 | jz .firstdevice |
353 | jz .firstdevice |
354 | 354 | ||
355 | ; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers |
355 | ; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers |
356 | mov ax, [eax+1] ; |
356 | mov ax, [eax+1] ; |
357 | .nextdevice: |
357 | .nextdevice: |
358 | mov ebx, [esi] |
358 | mov ebx, [esi] |
359 | cmp al, byte[ebx + device.pci_bus] |
359 | cmp al, byte[ebx + device.pci_bus] |
360 | jne .next |
360 | jne .next |
361 | cmp ah, byte[ebx + device.pci_dev] |
361 | cmp ah, byte[ebx + device.pci_dev] |
362 | je .find_devicenum ; Device is already loaded, let's find it's device number |
362 | je .find_devicenum ; Device is already loaded, let's find it's device number |
363 | .next: |
363 | .next: |
364 | add esi, 4 |
364 | add esi, 4 |
365 | loop .nextdevice |
365 | loop .nextdevice |
366 | 366 | ||
367 | 367 | ||
368 | ; This device doesnt have its own eth_device structure yet, lets create one |
368 | ; This device doesnt have its own eth_device structure yet, lets create one |
369 | .firstdevice: |
369 | .firstdevice: |
370 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
370 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
371 | jae .fail |
371 | jae .fail |
372 | 372 | ||
373 | allocate_and_clear ebx, sizeof.device, .fail ; Allocate the buffer for device structure |
373 | allocate_and_clear ebx, sizeof.device, .fail ; Allocate the buffer for device structure |
374 | 374 | ||
375 | ; Fill in the direct call addresses into the struct |
375 | ; Fill in the direct call addresses into the struct |
376 | 376 | ||
377 | mov [ebx + device.reset], reset |
377 | mov [ebx + device.reset], reset |
378 | mov [ebx + device.transmit], transmit |
378 | mov [ebx + device.transmit], transmit |
379 | mov [ebx + device.unload], unload |
379 | mov [ebx + device.unload], unload |
380 | mov [ebx + device.name], my_service |
380 | mov [ebx + device.name], my_service |
381 | 381 | ||
382 | ; save the pci bus and device numbers |
382 | ; save the pci bus and device numbers |
383 | 383 | ||
384 | mov eax, [edx + IOCTL.input] |
384 | mov eax, [edx + IOCTL.input] |
385 | movzx ecx, byte[eax+1] |
385 | movzx ecx, byte[eax+1] |
386 | mov [ebx + device.pci_bus], ecx |
386 | mov [ebx + device.pci_bus], ecx |
387 | movzx ecx, byte[eax+2] |
387 | movzx ecx, byte[eax+2] |
388 | mov [ebx + device.pci_dev], ecx |
388 | mov [ebx + device.pci_dev], ecx |
389 | 389 | ||
390 | ; Now, it's time to find the base mmio addres of the PCI device |
390 | ; Now, it's time to find the base mmio addres of the PCI device |
391 | 391 | ||
- | 392 | stdcall PCI_find_mmio, [ebx + device.pci_bus], [ebx + device.pci_dev] ; returns in eax |
|
- | 393 | test eax, eax |
|
392 | stdcall PCI_find_mmio32, [ebx + device.pci_bus], [ebx + device.pci_dev] ; returns in eax |
394 | jz .destroy |
393 | 395 | ||
394 | ; Create virtual mapping of the physical memory |
396 | ; Create virtual mapping of the physical memory |
395 | 397 | ||
396 | invoke MapIoMem, eax, 10000h, PG_SW+PG_NOCACHE |
398 | invoke MapIoMem, eax, 10000h, PG_SW+PG_NOCACHE |
397 | mov [ebx + device.mmio_addr], eax |
399 | mov [ebx + device.mmio_addr], eax |
398 | 400 | ||
399 | ; We've found the mmio address, find IRQ now |
401 | ; We've found the mmio address, find IRQ now |
400 | 402 | ||
401 | invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line |
403 | invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line |
402 | mov [ebx + device.irq_line], al |
404 | mov [ebx + device.irq_line], al |
403 | 405 | ||
404 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
406 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
405 | [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.mmio_addr]:8 |
407 | [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.mmio_addr]:8 |
406 | 408 | ||
407 | ; Ok, the eth_device structure is ready, let's probe the device |
409 | ; Ok, the eth_device structure is ready, let's probe the device |
408 | call probe ; this function will output in eax |
410 | call probe ; this function will output in eax |
409 | test eax, eax |
411 | test eax, eax |
410 | jnz .err ; If an error occured, exit |
412 | jnz .err ; If an error occured, exit |
411 | 413 | ||
412 | mov eax, [devices] ; Add the device structure to our device list |
414 | mov eax, [devices] ; Add the device structure to our device list |
413 | mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device) |
415 | mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device) |
414 | inc [devices] ; |
416 | inc [devices] ; |
415 | 417 | ||
416 | call start_i8254x |
418 | call start_i8254x |
417 | test eax, eax |
419 | test eax, eax |
418 | jnz .destroy |
420 | jnz .destroy |
419 | 421 | ||
420 | mov [ebx + device.type], NET_TYPE_ETH |
422 | mov [ebx + device.type], NET_TYPE_ETH |
421 | invoke NetRegDev |
423 | invoke NetRegDev |
422 | cmp eax, -1 |
424 | cmp eax, -1 |
423 | je .destroy |
425 | je .destroy |
424 | 426 | ||
425 | ret |
427 | ret |
426 | 428 | ||
427 | ; If the device was already loaded, find the device number and return it in eax |
429 | ; If the device was already loaded, find the device number and return it in eax |
428 | 430 | ||
429 | .find_devicenum: |
431 | .find_devicenum: |
430 | DEBUGF 1,"Trying to find device number of already registered device\n" |
432 | DEBUGF 1,"Trying to find device number of already registered device\n" |
431 | invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
433 | invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
432 | ; into a device number in edi |
434 | ; into a device number in edi |
433 | mov eax, edi ; Application wants it in eax instead |
435 | mov eax, edi ; Application wants it in eax instead |
434 | DEBUGF 1,"Kernel says: %u\n", eax |
436 | DEBUGF 1,"Kernel says: %u\n", eax |
435 | ret |
437 | ret |
436 | 438 | ||
437 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
439 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
438 | 440 | ||
439 | .destroy: |
441 | .destroy: |
440 | ; todo: reset device into virgin state |
442 | ; todo: reset device into virgin state |
441 | 443 | ||
442 | .err: |
444 | .err: |
443 | invoke KernelFree, ebx |
445 | invoke KernelFree, ebx |
444 | 446 | ||
445 | .fail: |
447 | .fail: |
446 | DEBUGF 2,"Loading driver failed\n" |
448 | DEBUGF 2,"Loading driver failed\n" |
447 | or eax, -1 |
449 | or eax, -1 |
448 | ret |
450 | ret |
449 | 451 | ||
450 | ;------------------------------------------------------ |
452 | ;------------------------------------------------------ |
451 | endp |
453 | endp |
452 | 454 | ||
453 | 455 | ||
454 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
456 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
455 | ;; ;; |
457 | ;; ;; |
456 | ;; Actual Hardware dependent code starts here ;; |
458 | ;; Actual Hardware dependent code starts here ;; |
457 | ;; ;; |
459 | ;; ;; |
458 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
460 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
459 | 461 | ||
460 | 462 | ||
461 | align 4 |
463 | align 4 |
462 | unload: |
464 | unload: |
463 | 465 | ||
464 | DEBUGF 1,"Unload\n" |
466 | DEBUGF 1,"Unload\n" |
465 | 467 | ||
466 | ; TODO: (in this particular order) |
468 | ; TODO: (in this particular order) |
467 | ; |
469 | ; |
468 | ; - Stop the device |
470 | ; - Stop the device |
469 | ; - Detach int handler |
471 | ; - Detach int handler |
470 | ; - Remove device from local list (device_list) |
472 | ; - Remove device from local list (device_list) |
471 | ; - call unregister function in kernel |
473 | ; - call unregister function in kernel |
472 | ; - Remove all allocated structures and buffers the card used |
474 | ; - Remove all allocated structures and buffers the card used |
473 | 475 | ||
474 | or eax, -1 |
476 | or eax, -1 |
475 | ret |
477 | ret |
476 | 478 | ||
477 | 479 | ||
478 | 480 | ||
479 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
481 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
480 | ;; |
482 | ;; |
481 | ;; probe: enables the device (if it really is I8254X) |
483 | ;; probe: enables the device (if it really is I8254X) |
482 | ;; |
484 | ;; |
483 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
485 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
484 | align 4 |
486 | align 4 |
485 | probe: |
487 | probe: |
486 | 488 | ||
487 | DEBUGF 1,"Probe\n" |
489 | DEBUGF 1,"Probe\n" |
488 | 490 | ||
489 | ; Make the device a bus master |
491 | ; Make the device a bus master |
490 | invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command |
492 | invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command |
491 | or al, PCI_CMD_MASTER |
493 | or al, PCI_CMD_MASTER |
492 | invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax |
494 | invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax |
493 | 495 | ||
494 | ; TODO: validate the device |
496 | ; TODO: validate the device |
495 | 497 | ||
496 | call read_mac |
498 | call read_mac |
497 | 499 | ||
498 | movzx eax, [ebx + device.irq_line] |
500 | movzx eax, [ebx + device.irq_line] |
499 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
501 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
500 | invoke AttachIntHandler, eax, int_handler, ebx |
502 | invoke AttachIntHandler, eax, int_handler, ebx |
501 | test eax, eax |
503 | test eax, eax |
502 | jnz @f |
504 | jnz @f |
503 | DEBUGF 2,"Could not attach int handler!\n" |
505 | DEBUGF 2,"Could not attach int handler!\n" |
504 | or eax, -1 |
506 | or eax, -1 |
505 | ret |
507 | ret |
506 | @@: |
508 | @@: |
507 | 509 | ||
508 | 510 | ||
509 | reset_dontstart: |
511 | reset_dontstart: |
510 | DEBUGF 1,"Reset\n" |
512 | DEBUGF 1,"Reset\n" |
511 | 513 | ||
512 | mov esi, [ebx + device.mmio_addr] |
514 | mov esi, [ebx + device.mmio_addr] |
513 | 515 | ||
514 | or dword[esi + REG_CTRL], CTRL_RST ; reset device |
516 | or dword[esi + REG_CTRL], CTRL_RST ; reset device |
515 | .loop: |
517 | .loop: |
516 | push esi |
518 | push esi |
517 | xor esi, esi |
519 | xor esi, esi |
518 | inc esi |
520 | inc esi |
519 | invoke Sleep |
521 | invoke Sleep |
520 | pop esi |
522 | pop esi |
521 | test dword[esi + REG_CTRL], CTRL_RST |
523 | test dword[esi + REG_CTRL], CTRL_RST |
522 | jnz .loop |
524 | jnz .loop |
523 | 525 | ||
524 | mov dword[esi + REG_IMC], 0xffffffff ; Disable all interrupt causes |
526 | mov dword[esi + REG_IMC], 0xffffffff ; Disable all interrupt causes |
525 | mov eax, dword [esi + REG_ICR] ; Clear any pending interrupts |
527 | mov eax, dword [esi + REG_ICR] ; Clear any pending interrupts |
526 | mov dword[esi + REG_ITR], 0 ; Disable interrupt throttling logic |
528 | mov dword[esi + REG_ITR], 0 ; Disable interrupt throttling logic |
527 | 529 | ||
528 | mov dword[esi + REG_PBA], 0x00000004 ; PBA: set the RX buffer size to 4KB (TX buffer is calculated as 64-RX buffer) |
530 | mov dword[esi + REG_PBA], 0x00000004 ; PBA: set the RX buffer size to 4KB (TX buffer is calculated as 64-RX buffer) |
529 | mov dword[esi + REG_RDTR], 0 ; RDTR: set no delay |
531 | mov dword[esi + REG_RDTR], 0 ; RDTR: set no delay |
530 | 532 | ||
531 | mov dword[esi + REG_TXCW], 0x00008060 ; TXCW: TxConfigWord (Half/Full duplex, Next Page Reqest) |
533 | mov dword[esi + REG_TXCW], 0x00008060 ; TXCW: TxConfigWord (Half/Full duplex, Next Page Reqest) |
532 | 534 | ||
533 | mov eax, [esi + REG_CTRL] |
535 | mov eax, [esi + REG_CTRL] |
534 | or eax, 1 shl 6 + 1 shl 5 |
536 | or eax, 1 shl 6 + 1 shl 5 |
535 | and eax, not (1 shl 3 + 1 shl 7 + 1 shl 30 + 1 shl 31) |
537 | and eax, not (1 shl 3 + 1 shl 7 + 1 shl 30 + 1 shl 31) |
536 | mov dword [esi + REG_CTRL], eax ; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS |
538 | mov dword [esi + REG_CTRL], eax ; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS |
537 | 539 | ||
538 | lea edi, [esi + 0x5200] ; MTA: reset |
540 | lea edi, [esi + 0x5200] ; MTA: reset |
539 | mov eax, 0xffffffff |
541 | mov eax, 0xffffffff |
540 | stosd |
542 | stosd |
541 | stosd |
543 | stosd |
542 | stosd |
544 | stosd |
543 | stosd |
545 | stosd |
544 | 546 | ||
545 | call init_rx |
547 | call init_rx |
546 | test eax, eax |
548 | test eax, eax |
547 | jnz .fail |
549 | jnz .fail |
548 | call init_tx |
550 | call init_tx |
549 | 551 | ||
550 | xor eax, eax |
552 | xor eax, eax |
551 | .fail: |
553 | .fail: |
552 | ret |
554 | ret |
553 | 555 | ||
554 | 556 | ||
555 | 557 | ||
556 | align 4 |
558 | align 4 |
557 | init_rx: |
559 | init_rx: |
558 | 560 | ||
559 | lea edi, [ebx + device.rx_desc] |
561 | lea edi, [ebx + device.rx_desc] |
560 | mov ecx, RX_RING_SIZE |
562 | mov ecx, RX_RING_SIZE |
561 | .loop: |
563 | .loop: |
562 | push ecx |
564 | push ecx |
563 | push edi |
565 | push edi |
564 | invoke NetAlloc, MAX_PKT_SIZE+NET_BUFF.data |
566 | invoke NetAlloc, MAX_PKT_SIZE+NET_BUFF.data |
565 | test eax, eax |
567 | test eax, eax |
566 | jz .out_of_mem |
568 | jz .out_of_mem |
567 | DEBUGF 1,"RX buffer: 0x%x\n", eax |
569 | DEBUGF 1,"RX buffer: 0x%x\n", eax |
568 | pop edi |
570 | pop edi |
569 | mov dword[edi + RX_RING_SIZE*sizeof.RDESC], eax |
571 | mov dword[edi + RX_RING_SIZE*sizeof.RDESC], eax |
570 | push edi |
572 | push edi |
571 | invoke GetPhysAddr |
573 | invoke GetPhysAddr |
572 | pop edi |
574 | pop edi |
573 | add eax, NET_BUFF.data |
575 | add eax, NET_BUFF.data |
574 | mov [edi + RDESC.addr_l], eax |
576 | mov [edi + RDESC.addr_l], eax |
575 | mov [edi + RDESC.addr_h], 0 |
577 | mov [edi + RDESC.addr_h], 0 |
576 | mov [edi + RDESC.status_l], 0 |
578 | mov [edi + RDESC.status_l], 0 |
577 | mov [edi + RDESC.status_h], 0 |
579 | mov [edi + RDESC.status_h], 0 |
578 | add edi, sizeof.RDESC |
580 | add edi, sizeof.RDESC |
579 | pop ecx |
581 | pop ecx |
580 | dec ecx |
582 | dec ecx |
581 | jnz .loop |
583 | jnz .loop |
582 | 584 | ||
583 | mov [ebx + device.cur_rx], 0 |
585 | mov [ebx + device.cur_rx], 0 |
584 | 586 | ||
585 | lea eax, [ebx + device.rx_desc] |
587 | lea eax, [ebx + device.rx_desc] |
586 | invoke GetPhysAddr |
588 | invoke GetPhysAddr |
587 | mov dword[esi + REG_RDBAL], eax ; Receive Descriptor Base Address Low |
589 | mov dword[esi + REG_RDBAL], eax ; Receive Descriptor Base Address Low |
588 | mov dword[esi + REG_RDBAH], 0 ; Receive Descriptor Base Address High |
590 | mov dword[esi + REG_RDBAH], 0 ; Receive Descriptor Base Address High |
589 | mov dword[esi + REG_RDLEN], RX_RING_SIZE*sizeof.RDESC ; Receive Descriptor Length |
591 | mov dword[esi + REG_RDLEN], RX_RING_SIZE*sizeof.RDESC ; Receive Descriptor Length |
590 | mov dword[esi + REG_RDH], 0 ; Receive Descriptor Head |
592 | mov dword[esi + REG_RDH], 0 ; Receive Descriptor Head |
591 | mov dword[esi + REG_RDT], RX_RING_SIZE-1 ; Receive Descriptor Tail |
593 | mov dword[esi + REG_RDT], RX_RING_SIZE-1 ; Receive Descriptor Tail |
592 | mov dword[esi + REG_RCTL], RCTL_SBP or RCTL_BAM or RCTL_SECRC or RCTL_UPE or RCTL_MPE |
594 | mov dword[esi + REG_RCTL], RCTL_SBP or RCTL_BAM or RCTL_SECRC or RCTL_UPE or RCTL_MPE |
593 | ; Store Bad Packets, Broadcast Accept Mode, Strip Ethernet CRC from incoming packet, Promiscuous mode |
595 | ; Store Bad Packets, Broadcast Accept Mode, Strip Ethernet CRC from incoming packet, Promiscuous mode |
594 | xor eax, eax ; success! |
596 | xor eax, eax ; success! |
595 | ret |
597 | ret |
596 | 598 | ||
597 | .out_of_mem: |
599 | .out_of_mem: |
598 | DEBUGF 2,"Out of memory!\n" |
600 | DEBUGF 2,"Out of memory!\n" |
599 | pop edi ecx |
601 | pop edi ecx |
600 | or eax, -1 ; error! |
602 | or eax, -1 ; error! |
601 | ret |
603 | ret |
602 | 604 | ||
603 | 605 | ||
604 | 606 | ||
605 | align 4 |
607 | align 4 |
606 | init_tx: |
608 | init_tx: |
607 | 609 | ||
608 | lea edi, [ebx + device.tx_desc] |
610 | lea edi, [ebx + device.tx_desc] |
609 | mov ecx, TX_RING_SIZE |
611 | mov ecx, TX_RING_SIZE |
610 | .loop: |
612 | .loop: |
611 | mov [edi + TDESC.addr_l], eax |
613 | mov [edi + TDESC.addr_l], eax |
612 | mov [edi + TDESC.addr_h], 0 |
614 | mov [edi + TDESC.addr_h], 0 |
613 | mov [edi + TDESC.length_cso_cmd], 0 |
615 | mov [edi + TDESC.length_cso_cmd], 0 |
614 | mov [edi + TDESC.status], 0 |
616 | mov [edi + TDESC.status], 0 |
615 | add edi, sizeof.TDESC |
617 | add edi, sizeof.TDESC |
616 | dec ecx |
618 | dec ecx |
617 | jnz .loop |
619 | jnz .loop |
618 | 620 | ||
619 | mov [ebx + device.cur_tx], 0 |
621 | mov [ebx + device.cur_tx], 0 |
620 | mov [ebx + device.last_tx], 0 |
622 | mov [ebx + device.last_tx], 0 |
621 | 623 | ||
622 | lea eax, [ebx + device.tx_desc] |
624 | lea eax, [ebx + device.tx_desc] |
623 | invoke GetPhysAddr |
625 | invoke GetPhysAddr |
624 | mov dword[esi + REG_TDBAL], eax ; Transmit Descriptor Base Address Low |
626 | mov dword[esi + REG_TDBAL], eax ; Transmit Descriptor Base Address Low |
625 | mov dword[esi + REG_TDBAH], 0 ; Transmit Descriptor Base Address High |
627 | mov dword[esi + REG_TDBAH], 0 ; Transmit Descriptor Base Address High |
626 | mov dword[esi + REG_TDLEN], RX_RING_SIZE*sizeof.TDESC ; Transmit Descriptor Length |
628 | mov dword[esi + REG_TDLEN], RX_RING_SIZE*sizeof.TDESC ; Transmit Descriptor Length |
627 | mov dword[esi + REG_TDH], 0 ; Transmit Descriptor Head |
629 | mov dword[esi + REG_TDH], 0 ; Transmit Descriptor Head |
628 | mov dword[esi + REG_TDT], 0 ; Transmit Descriptor Tail |
630 | mov dword[esi + REG_TDT], 0 ; Transmit Descriptor Tail |
629 | mov dword[esi + REG_TCTL], 0x010400fa ; Enabled, Pad Short Packets, 15 retrys, 64-byte COLD, Re-transmit on Late Collision |
631 | mov dword[esi + REG_TCTL], 0x010400fa ; Enabled, Pad Short Packets, 15 retrys, 64-byte COLD, Re-transmit on Late Collision |
630 | mov dword[esi + REG_TIPG], 0x0060200A ; IPGT 10, IPGR1 8, IPGR2 6 |
632 | mov dword[esi + REG_TIPG], 0x0060200A ; IPGT 10, IPGR1 8, IPGR2 6 |
631 | 633 | ||
632 | ret |
634 | ret |
633 | 635 | ||
634 | 636 | ||
635 | align 4 |
637 | align 4 |
636 | reset: |
638 | reset: |
637 | call reset_dontstart |
639 | call reset_dontstart |
638 | test eax, eax |
640 | test eax, eax |
639 | je start_i8254x |
641 | je start_i8254x |
640 | 642 | ||
641 | ret |
643 | ret |
642 | 644 | ||
643 | align 4 |
645 | align 4 |
644 | start_i8254x: |
646 | start_i8254x: |
645 | 647 | ||
646 | mov esi, [ebx + device.mmio_addr] |
648 | mov esi, [ebx + device.mmio_addr] |
647 | or dword[esi + REG_RCTL], RCTL_EN ; Enable the receiver |
649 | or dword[esi + REG_RCTL], RCTL_EN ; Enable the receiver |
648 | 650 | ||
649 | xor eax, eax |
651 | xor eax, eax |
650 | mov [esi + REG_RDTR], eax ; Clear the Receive Delay Timer Register |
652 | mov [esi + REG_RDTR], eax ; Clear the Receive Delay Timer Register |
651 | mov [esi + REG_RADV], eax ; Clear the Receive Interrupt Absolute Delay Timer |
653 | mov [esi + REG_RADV], eax ; Clear the Receive Interrupt Absolute Delay Timer |
652 | mov [esi + REG_RSRPD], eax ; Clear the Receive Small Packet Detect Interrupt |
654 | mov [esi + REG_RSRPD], eax ; Clear the Receive Small Packet Detect Interrupt |
653 | 655 | ||
654 | mov dword[esi + REG_IMS], 0x1F6DC ; Enable interrupt types |
656 | mov dword[esi + REG_IMS], 0x1F6DC ; Enable interrupt types |
655 | mov eax, [esi + REG_ICR] ; Clear pending interrupts |
657 | mov eax, [esi + REG_ICR] ; Clear pending interrupts |
656 | 658 | ||
657 | mov [ebx + device.mtu], 1514 |
659 | mov [ebx + device.mtu], 1514 |
658 | call link_status |
660 | call link_status |
659 | 661 | ||
660 | xor eax, eax |
662 | xor eax, eax |
661 | ret |
663 | ret |
662 | 664 | ||
663 | 665 | ||
664 | 666 | ||
665 | 667 | ||
666 | align 4 |
668 | align 4 |
667 | read_mac: |
669 | read_mac: |
668 | 670 | ||
669 | DEBUGF 1,"Read MAC\n" |
671 | DEBUGF 1,"Read MAC\n" |
670 | 672 | ||
671 | mov esi, [ebx + device.mmio_addr] |
673 | mov esi, [ebx + device.mmio_addr] |
672 | 674 | ||
673 | mov eax, [esi+0x5400] ; RAL |
675 | mov eax, [esi+0x5400] ; RAL |
674 | test eax, eax |
676 | test eax, eax |
675 | jz .try_eeprom |
677 | jz .try_eeprom |
676 | 678 | ||
677 | mov dword[ebx + device.mac], eax |
679 | mov dword[ebx + device.mac], eax |
678 | mov eax, [esi+0x5404] ; RAH |
680 | mov eax, [esi+0x5404] ; RAH |
679 | mov word[ebx + device.mac+4], ax |
681 | mov word[ebx + device.mac+4], ax |
680 | 682 | ||
681 | jmp .mac_ok |
683 | jmp .mac_ok |
682 | 684 | ||
683 | .try_eeprom: |
685 | .try_eeprom: |
684 | mov dword[esi+0x14], 0x00000001 |
686 | mov dword[esi+0x14], 0x00000001 |
685 | mov eax, [esi+0x14] |
687 | mov eax, [esi+0x14] |
686 | shr eax, 16 |
688 | shr eax, 16 |
687 | mov word[ebx + device.mac], ax |
689 | mov word[ebx + device.mac], ax |
688 | 690 | ||
689 | mov dword[esi+0x14], 0x00000101 |
691 | mov dword[esi+0x14], 0x00000101 |
690 | mov eax, [esi+0x14] |
692 | mov eax, [esi+0x14] |
691 | shr eax, 16 |
693 | shr eax, 16 |
692 | mov word[ebx + device.mac+2], ax |
694 | mov word[ebx + device.mac+2], ax |
693 | 695 | ||
694 | mov dword[esi+0x14], 0x00000201 |
696 | mov dword[esi+0x14], 0x00000201 |
695 | mov eax, [esi+0x14] |
697 | mov eax, [esi+0x14] |
696 | shr eax, 16 |
698 | shr eax, 16 |
697 | mov word[ebx + device.mac+4], ax |
699 | mov word[ebx + device.mac+4], ax |
698 | 700 | ||
699 | .mac_ok: |
701 | .mac_ok: |
700 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
702 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
701 | [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\ |
703 | [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\ |
702 | [ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2 |
704 | [ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2 |
703 | 705 | ||
704 | ret |
706 | ret |
705 | 707 | ||
706 | 708 | ||
707 | link_status: |
709 | link_status: |
708 | 710 | ||
709 | DEBUGF 1,"Verifying link status\n" |
711 | DEBUGF 1,"Verifying link status\n" |
710 | 712 | ||
711 | xor ecx, ecx ; ETH_LINK_DOWN |
713 | xor ecx, ecx ; ETH_LINK_DOWN |
712 | mov esi, [ebx + device.mmio_addr] |
714 | mov esi, [ebx + device.mmio_addr] |
713 | mov eax, [esi + REG_STATUS] |
715 | mov eax, [esi + REG_STATUS] |
714 | test eax, STATUS_LU |
716 | test eax, STATUS_LU |
715 | jz .ok |
717 | jz .ok |
716 | 718 | ||
717 | test eax, STATUS_FD |
719 | test eax, STATUS_FD |
718 | jz @f |
720 | jz @f |
719 | or cl, ETH_LINK_FD |
721 | or cl, ETH_LINK_FD |
720 | @@: |
722 | @@: |
721 | shr eax, STATUS_SPEED_SHIFT |
723 | shr eax, STATUS_SPEED_SHIFT |
722 | and al, 3 |
724 | and al, 3 |
723 | test al, al |
725 | test al, al |
724 | jnz @f |
726 | jnz @f |
725 | or cl, ETH_LINK_10M |
727 | or cl, ETH_LINK_10M |
726 | jmp .ok |
728 | jmp .ok |
727 | @@: |
729 | @@: |
728 | cmp al, 1 |
730 | cmp al, 1 |
729 | jne @f |
731 | jne @f |
730 | or cl, ETH_LINK_100M |
732 | or cl, ETH_LINK_100M |
731 | jmp .ok |
733 | jmp .ok |
732 | @@: |
734 | @@: |
733 | or cl, ETH_LINK_1G |
735 | or cl, ETH_LINK_1G |
734 | ; jmp .ok |
736 | ; jmp .ok |
735 | 737 | ||
736 | .ok: |
738 | .ok: |
737 | mov [ebx + device.state], ecx |
739 | mov [ebx + device.state], ecx |
738 | invoke NetLinkChanged |
740 | invoke NetLinkChanged |
739 | ret |
741 | ret |
740 | 742 | ||
741 | 743 | ||
742 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
744 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
743 | ;; ;; |
745 | ;; ;; |
744 | ;; Transmit ;; |
746 | ;; Transmit ;; |
745 | ;; ;; |
747 | ;; ;; |
746 | ;; In: ebx = pointer to device structure ;; |
748 | ;; In: ebx = pointer to device structure ;; |
747 | ;; Out: eax = 0 on success ;; |
749 | ;; Out: eax = 0 on success ;; |
748 | ;; ;; |
750 | ;; ;; |
749 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
751 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
750 | 752 | ||
751 | proc transmit stdcall bufferptr |
753 | proc transmit stdcall bufferptr |
752 | 754 | ||
753 | pushf |
755 | pushf |
754 | cli |
756 | cli |
755 | 757 | ||
756 | mov esi, [bufferptr] |
758 | mov esi, [bufferptr] |
757 | DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length] |
759 | DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length] |
758 | lea eax, [esi + NET_BUFF.data] |
760 | lea eax, [esi + NET_BUFF.data] |
759 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
761 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
760 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
762 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
761 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
763 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
762 | [eax+13]:2,[eax+12]:2 |
764 | [eax+13]:2,[eax+12]:2 |
763 | 765 | ||
764 | cmp [esi + NET_BUFF.length], 1514 |
766 | cmp [esi + NET_BUFF.length], 1514 |
765 | ja .fail |
767 | ja .fail |
766 | cmp [esi + NET_BUFF.length], 60 |
768 | cmp [esi + NET_BUFF.length], 60 |
767 | jb .fail |
769 | jb .fail |
768 | 770 | ||
769 | ; Program the descriptor (use legacy mode) |
771 | ; Program the descriptor (use legacy mode) |
770 | mov edi, [ebx + device.cur_tx] |
772 | mov edi, [ebx + device.cur_tx] |
771 | DEBUGF 1, "Using TX desc: %u\n", edi |
773 | DEBUGF 1, "Using TX desc: %u\n", edi |
772 | shl edi, 4 ; edi = edi * sizeof.TDESC |
774 | shl edi, 4 ; edi = edi * sizeof.TDESC |
773 | lea edi, [ebx + device.tx_desc + edi] |
775 | lea edi, [ebx + device.tx_desc + edi] |
774 | mov eax, esi |
776 | mov eax, esi |
775 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], eax ; Store the data location (for driver) |
777 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], eax ; Store the data location (for driver) |
776 | add eax, [eax + NET_BUFF.offset] |
778 | add eax, [eax + NET_BUFF.offset] |
777 | invoke GetPhysAddr |
779 | invoke GetPhysAddr |
778 | mov [edi + TDESC.addr_l], eax ; Data location (for hardware) |
780 | mov [edi + TDESC.addr_l], eax ; Data location (for hardware) |
779 | mov [edi + TDESC.addr_h], 0 |
781 | mov [edi + TDESC.addr_h], 0 |
780 | 782 | ||
781 | mov ecx, [esi + NET_BUFF.length] |
783 | mov ecx, [esi + NET_BUFF.length] |
782 | or ecx, TXDESC_EOP + TXDESC_IFCS + TXDESC_RS |
784 | or ecx, TXDESC_EOP + TXDESC_IFCS + TXDESC_RS |
783 | mov [edi + TDESC.length_cso_cmd], ecx |
785 | mov [edi + TDESC.length_cso_cmd], ecx |
784 | mov [edi + TDESC.status], 0 |
786 | mov [edi + TDESC.status], 0 |
785 | 787 | ||
786 | ; Tell i8254x wich descriptor(s) we programmed, by moving the tail |
788 | ; Tell i8254x wich descriptor(s) we programmed, by moving the tail |
787 | mov edi, [ebx + device.mmio_addr] |
789 | mov edi, [ebx + device.mmio_addr] |
788 | mov eax, [ebx + device.cur_tx] |
790 | mov eax, [ebx + device.cur_tx] |
789 | inc eax |
791 | inc eax |
790 | and eax, TX_RING_SIZE-1 |
792 | and eax, TX_RING_SIZE-1 |
791 | mov [ebx + device.cur_tx], eax |
793 | mov [ebx + device.cur_tx], eax |
792 | mov dword[edi + REG_TDT], eax ; TDT - Transmit Descriptor Tail |
794 | mov dword[edi + REG_TDT], eax ; TDT - Transmit Descriptor Tail |
793 | 795 | ||
794 | ; Update stats |
796 | ; Update stats |
795 | inc [ebx + device.packets_tx] |
797 | inc [ebx + device.packets_tx] |
796 | mov eax, [esi + NET_BUFF.length] |
798 | mov eax, [esi + NET_BUFF.length] |
797 | add dword[ebx + device.bytes_tx], eax |
799 | add dword[ebx + device.bytes_tx], eax |
798 | adc dword[ebx + device.bytes_tx + 4], 0 |
800 | adc dword[ebx + device.bytes_tx + 4], 0 |
799 | 801 | ||
800 | call clean_tx |
802 | call clean_tx |
801 | 803 | ||
802 | popf |
804 | popf |
803 | xor eax, eax |
805 | xor eax, eax |
804 | ret |
806 | ret |
805 | 807 | ||
806 | .fail: |
808 | .fail: |
807 | call clean_tx |
809 | call clean_tx |
808 | 810 | ||
809 | DEBUGF 2,"Send failed\n" |
811 | DEBUGF 2,"Send failed\n" |
810 | invoke NetFree, [bufferptr] |
812 | invoke NetFree, [bufferptr] |
811 | popf |
813 | popf |
812 | or eax, -1 |
814 | or eax, -1 |
813 | ret |
815 | ret |
814 | 816 | ||
815 | endp |
817 | endp |
816 | 818 | ||
817 | 819 | ||
818 | ;;;;;;;;;;;;;;;;;;;;;;; |
820 | ;;;;;;;;;;;;;;;;;;;;;;; |
819 | ;; ;; |
821 | ;; ;; |
820 | ;; Interrupt handler ;; |
822 | ;; Interrupt handler ;; |
821 | ;; ;; |
823 | ;; ;; |
822 | ;;;;;;;;;;;;;;;;;;;;;;; |
824 | ;;;;;;;;;;;;;;;;;;;;;;; |
823 | 825 | ||
824 | align 4 |
826 | align 4 |
825 | int_handler: |
827 | int_handler: |
826 | 828 | ||
827 | push ebx esi edi |
829 | push ebx esi edi |
828 | 830 | ||
829 | DEBUGF 1,"INT\n" |
831 | DEBUGF 1,"INT\n" |
830 | ;------------------------------------------- |
832 | ;------------------------------------------- |
831 | ; Find pointer of device wich made IRQ occur |
833 | ; Find pointer of device wich made IRQ occur |
832 | 834 | ||
833 | mov ecx, [devices] |
835 | mov ecx, [devices] |
834 | test ecx, ecx |
836 | test ecx, ecx |
835 | jz .nothing |
837 | jz .nothing |
836 | mov esi, device_list |
838 | mov esi, device_list |
837 | .nextdevice: |
839 | .nextdevice: |
838 | mov ebx, [esi] |
840 | mov ebx, [esi] |
839 | mov edi, [ebx + device.mmio_addr] |
841 | mov edi, [ebx + device.mmio_addr] |
840 | mov eax, [edi + REG_ICR] |
842 | mov eax, [edi + REG_ICR] |
841 | test eax, eax |
843 | test eax, eax |
842 | jnz .got_it |
844 | jnz .got_it |
843 | .continue: |
845 | .continue: |
844 | add esi, 4 |
846 | add esi, 4 |
845 | dec ecx |
847 | dec ecx |
846 | jnz .nextdevice |
848 | jnz .nextdevice |
847 | .nothing: |
849 | .nothing: |
848 | pop edi esi ebx |
850 | pop edi esi ebx |
849 | xor eax, eax |
851 | xor eax, eax |
850 | 852 | ||
851 | ret |
853 | ret |
852 | 854 | ||
853 | .got_it: |
855 | .got_it: |
854 | DEBUGF 1,"Device: %x Status: %x\n", ebx, eax |
856 | DEBUGF 1,"Device: %x Status: %x\n", ebx, eax |
855 | 857 | ||
856 | ;--------- |
858 | ;--------- |
857 | ; RX done? |
859 | ; RX done? |
858 | 860 | ||
859 | test eax, ICR_RXDMT0 + ICR_RXT0 |
861 | test eax, ICR_RXDMT0 + ICR_RXT0 |
860 | jz .no_rx |
862 | jz .no_rx |
861 | 863 | ||
862 | push eax ebx |
864 | push eax ebx |
863 | .retaddr: |
865 | .retaddr: |
864 | pop ebx eax |
866 | pop ebx eax |
865 | ; Get last descriptor addr |
867 | ; Get last descriptor addr |
866 | mov esi, [ebx + device.cur_rx] |
868 | mov esi, [ebx + device.cur_rx] |
867 | shl esi, 4 ; esi = esi * sizeof.RDESC |
869 | shl esi, 4 ; esi = esi * sizeof.RDESC |
868 | lea esi, [ebx + device.rx_desc + esi] |
870 | lea esi, [ebx + device.rx_desc + esi] |
869 | cmp byte[esi + RDESC.status_h], 0 ; Check status field |
871 | cmp byte[esi + RDESC.status_h], 0 ; Check status field |
870 | je .no_rx |
872 | je .no_rx |
871 | 873 | ||
872 | push eax ebx |
874 | push eax ebx |
873 | push .retaddr |
875 | push .retaddr |
874 | movzx ecx, word[esi + 8] ; Get the packet length |
876 | movzx ecx, word[esi + 8] ; Get the packet length |
875 | DEBUGF 1,"got %u bytes\n", ecx |
877 | DEBUGF 1,"got %u bytes\n", ecx |
876 | mov eax, [esi + RX_RING_SIZE*sizeof.RDESC] ; Get packet pointer |
878 | mov eax, [esi + RX_RING_SIZE*sizeof.RDESC] ; Get packet pointer |
877 | push eax |
879 | push eax |
878 | mov [eax + NET_BUFF.length], ecx |
880 | mov [eax + NET_BUFF.length], ecx |
879 | mov [eax + NET_BUFF.device], ebx |
881 | mov [eax + NET_BUFF.device], ebx |
880 | mov [eax + NET_BUFF.offset], NET_BUFF.data |
882 | mov [eax + NET_BUFF.offset], NET_BUFF.data |
881 | 883 | ||
882 | ; Update stats |
884 | ; Update stats |
883 | add dword[ebx + device.bytes_rx], ecx |
885 | add dword[ebx + device.bytes_rx], ecx |
884 | adc dword[ebx + device.bytes_rx + 4], 0 |
886 | adc dword[ebx + device.bytes_rx + 4], 0 |
885 | inc [ebx + device.packets_rx] |
887 | inc [ebx + device.packets_rx] |
886 | 888 | ||
887 | ; Allocate new descriptor |
889 | ; Allocate new descriptor |
888 | push esi |
890 | push esi |
889 | invoke NetAlloc, MAX_PKT_SIZE+NET_BUFF.data |
891 | invoke NetAlloc, MAX_PKT_SIZE+NET_BUFF.data |
890 | pop esi |
892 | pop esi |
891 | test eax, eax |
893 | test eax, eax |
892 | jz .out_of_mem |
894 | jz .out_of_mem |
893 | mov dword[esi + RX_RING_SIZE*sizeof.RDESC], eax |
895 | mov dword[esi + RX_RING_SIZE*sizeof.RDESC], eax |
894 | invoke GetPhysAddr |
896 | invoke GetPhysAddr |
895 | add eax, NET_BUFF.data |
897 | add eax, NET_BUFF.data |
896 | mov [esi + RDESC.addr_l], eax |
898 | mov [esi + RDESC.addr_l], eax |
897 | mov [esi + RDESC.status_l], 0 |
899 | mov [esi + RDESC.status_l], 0 |
898 | mov [esi + RDESC.status_h], 0 |
900 | mov [esi + RDESC.status_h], 0 |
899 | 901 | ||
900 | ; Move the receive descriptor tail |
902 | ; Move the receive descriptor tail |
901 | mov esi, [ebx + device.mmio_addr] |
903 | mov esi, [ebx + device.mmio_addr] |
902 | mov eax, [ebx + device.cur_rx] |
904 | mov eax, [ebx + device.cur_rx] |
903 | mov [esi + REG_RDT], eax |
905 | mov [esi + REG_RDT], eax |
904 | 906 | ||
905 | ; Move to next rx desc |
907 | ; Move to next rx desc |
906 | inc [ebx + device.cur_rx] |
908 | inc [ebx + device.cur_rx] |
907 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
909 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
908 | 910 | ||
909 | jmp [EthInput] |
911 | jmp [EthInput] |
910 | 912 | ||
911 | .out_of_mem: |
913 | .out_of_mem: |
912 | DEBUGF 2,"Out of memory!\n" |
914 | DEBUGF 2,"Out of memory!\n" |
913 | 915 | ||
914 | ; Move to next rx desc |
916 | ; Move to next rx desc |
915 | inc [ebx + device.cur_rx] |
917 | inc [ebx + device.cur_rx] |
916 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
918 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
917 | 919 | ||
918 | jmp [EthInput] |
920 | jmp [EthInput] |
919 | .no_rx: |
921 | .no_rx: |
920 | 922 | ||
921 | ;-------------- |
923 | ;-------------- |
922 | ; Link Changed? |
924 | ; Link Changed? |
923 | 925 | ||
924 | test eax, ICR_LSC |
926 | test eax, ICR_LSC |
925 | jz .no_link |
927 | jz .no_link |
926 | 928 | ||
927 | DEBUGF 2,"Link Changed\n" |
929 | DEBUGF 2,"Link Changed\n" |
928 | 930 | ||
929 | call link_status |
931 | call link_status |
930 | 932 | ||
931 | .no_link: |
933 | .no_link: |
932 | 934 | ||
933 | ;--------------- |
935 | ;--------------- |
934 | ; Transmit done? |
936 | ; Transmit done? |
935 | 937 | ||
936 | test eax, ICR_TXDW |
938 | test eax, ICR_TXDW |
937 | jz .no_tx |
939 | jz .no_tx |
938 | 940 | ||
939 | DEBUGF 1,"Transmit done\n" |
941 | DEBUGF 1,"Transmit done\n" |
940 | 942 | ||
941 | ; call clean_tx |
943 | ; call clean_tx |
942 | 944 | ||
943 | .no_tx: |
945 | .no_tx: |
944 | pop edi esi ebx |
946 | pop edi esi ebx |
945 | xor eax, eax |
947 | xor eax, eax |
946 | inc eax |
948 | inc eax |
947 | ret |
949 | ret |
948 | 950 | ||
949 | 951 | ||
950 | 952 | ||
951 | clean_tx: |
953 | clean_tx: |
952 | 954 | ||
953 | .txdesc_loop: |
955 | .txdesc_loop: |
954 | mov edi, [ebx + device.last_tx] |
956 | mov edi, [ebx + device.last_tx] |
955 | shl edi, 4 ; edi = edi * sizeof.TDESC |
957 | shl edi, 4 ; edi = edi * sizeof.TDESC |
956 | lea edi, [ebx + device.tx_desc + edi] |
958 | lea edi, [ebx + device.tx_desc + edi] |
957 | test [edi + TDESC.status], TXDESC_DD ; Descriptor done? |
959 | test [edi + TDESC.status], TXDESC_DD ; Descriptor done? |
958 | jz .no_tx |
960 | jz .no_tx |
959 | cmp dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
961 | cmp dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
960 | je .no_tx |
962 | je .no_tx |
961 | 963 | ||
962 | DEBUGF 1,"Cleaning up TX desc: 0x%x\n", edi |
964 | DEBUGF 1,"Cleaning up TX desc: 0x%x\n", edi |
963 | 965 | ||
964 | push ebx |
966 | push ebx |
965 | push dword[edi + TX_RING_SIZE*sizeof.TDESC] |
967 | push dword[edi + TX_RING_SIZE*sizeof.TDESC] |
966 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
968 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
967 | invoke NetFree |
969 | invoke NetFree |
968 | pop ebx |
970 | pop ebx |
969 | 971 | ||
970 | inc [ebx + device.last_tx] |
972 | inc [ebx + device.last_tx] |
971 | and [ebx + device.last_tx], TX_RING_SIZE-1 |
973 | and [ebx + device.last_tx], TX_RING_SIZE-1 |
972 | jmp .txdesc_loop |
974 | jmp .txdesc_loop |
973 | 975 | ||
974 | .no_tx: |
976 | .no_tx: |
975 | 977 | ||
976 | ret |
978 | ret |
977 | 979 | ||
978 | 980 | ||
979 | 981 | ||
980 | 982 | ||
981 | ; End of code |
983 | ; End of code |
982 | 984 | ||
983 | data fixups |
985 | data fixups |
984 | end data |
986 | end data |
985 | 987 | ||
986 | include '../peimport.inc' |
988 | include '../peimport.inc' |
987 | 989 | ||
988 | include_debug_strings |
990 | include_debug_strings |
989 | my_service db 'I8254X', 0 ; max 16 chars include zero |
991 | my_service db 'I8254X', 0 ; max 16 chars include zero |
990 | 992 | ||
991 | align 4 |
993 | align 4 |
992 | devices dd 0 |
994 | devices dd 0 |
993 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |
995 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |