WebSVN – Kolibri OS – Diff – /drivers/ethernet/RTL8169.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  RTL8169 driver for KolibriOS                                   ;;
;;                                                                 ;;
;;  Copyright 2007 mike.dld,                                       ;;
;;   mike.dld@gmail.com                                            ;;
;;                                                                 ;;
;; port to net branch by hidnplayr                                 ;;
;;                                                                 ;;
;;  References:                                                    ;;
;;    r8169.c - linux driver (etherboot project)                   ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format MS COFF
 
        API_VERSION             = 0x01000100
        DRIVER_VERSION          = 5
 
        MAX_DEVICES             = 16
 
        DEBUG                   = 1
        __DEBUG__               = 1
        __DEBUG_LEVEL__         = 2
 
        NUM_TX_DESC             = 4
        NUM_RX_DESC             = 4
 
include '../struct.inc'
include '../macros.inc'
include '../proc32.inc'
include '../imports.inc'
include '../fdo.inc'
include '../netdrv.inc'
 
public START
public service_proc
public version
 
 
        REG_MAC0                = 0x0 ; Ethernet hardware address
        REG_MAR0                = 0x8 ; Multicast filter
        REG_TxDescStartAddr     = 0x20
        REG_TxHDescStartAddr    = 0x28
        REG_FLASH               = 0x30
        REG_ERSR                = 0x36
        REG_ChipCmd             = 0x37
        REG_TxPoll              = 0x38
        REG_IntrMask            = 0x3C
        REG_IntrStatus          = 0x3E
        REG_TxConfig            = 0x40
        REG_RxConfig            = 0x44
        REG_RxMissed            = 0x4C
        REG_Cfg9346             = 0x50
        REG_Config0             = 0x51
        REG_Config1             = 0x52
        REG_Config2             = 0x53
        REG_Config3             = 0x54
        REG_Config4             = 0x55
        REG_Config5             = 0x56
        REG_MultiIntr           = 0x5C
        REG_PHYAR               = 0x60
        REG_TBICSR              = 0x64
        REG_TBI_ANAR            = 0x68
        REG_TBI_LPAR            = 0x6A
        REG_PHYstatus           = 0x6C
        REG_RxMaxSize           = 0xDA
        REG_CPlusCmd            = 0xE0
        REG_RxDescStartAddr     = 0xE4
        REG_ETThReg             = 0xEC
        REG_FuncEvent           = 0xF0
        REG_FuncEventMask       = 0xF4
        REG_FuncPresetState     = 0xF8
        REG_FuncForceEvent      = 0xFC
 
        ; InterruptStatusBits
        ISB_SYSErr              = 0x8000
        ISB_PCSTimeout          = 0x4000
        ISB_SWInt               = 0x0100
        ISB_TxDescUnavail       = 0x80
        ISB_RxFIFOOver          = 0x40
        ISB_LinkChg             = 0x20
        ISB_RxOverflow          = 0x10
        ISB_TxErr               = 0x08
        ISB_TxOK                = 0x04
        ISB_RxErr               = 0x02
        ISB_RxOK                = 0x01
 
        ; RxStatusDesc
        SD_RxRES                = 0x00200000
        SD_RxCRC                = 0x00080000
        SD_RxRUNT               = 0x00100000
        SD_RxRWT                = 0x00400000
 
        ; ChipCmdBits
        CMD_Reset               = 0x10
        CMD_RxEnb               = 0x08
        CMD_TxEnb               = 0x04
        CMD_RxBufEmpty          = 0x01
 
        ; Cfg9346Bits
        CFG_9346_Lock           = 0x00
        CFG_9346_Unlock         = 0xC0
 
        ; rx_mode_bits
        RXM_AcceptErr           = 0x20
        RXM_AcceptRunt          = 0x10
        RXM_AcceptBroadcast     = 0x08
        RXM_AcceptMulticast     = 0x04
        RXM_AcceptMyPhys        = 0x02
        RXM_AcceptAllPhys       = 0x01
 
        ; RxConfigBits
        RXC_FIFOShift           = 13
        RXC_DMAShift            = 8
 
        ; TxConfigBits
        TXC_InterFrameGapShift  = 24
        TXC_DMAShift            = 8    ; DMA burst value (0-7) is shift this many bits
 
        ; PHYstatus
        PHYS_TBI_Enable         = 0x80
        PHYS_TxFlowCtrl         = 0x40
        PHYS_RxFlowCtrl         = 0x20
        PHYS_1000bpsF           = 0x10
        PHYS_100bps             = 0x08
        PHYS_10bps              = 0x04
        PHYS_LinkStatus         = 0x02
        PHYS_FullDup            = 0x01
 
        ; GIGABIT_PHY_registers
        PHY_CTRL_REG            = 0
        PHY_STAT_REG            = 1
        PHY_AUTO_NEGO_REG       = 4
        PHY_1000_CTRL_REG       = 9
 
        ; GIGABIT_PHY_REG_BIT
        PHY_Restart_Auto_Nego   = 0x0200
        PHY_Enable_Auto_Nego    = 0x1000
 
        ; PHY_STAT_REG = 1
        PHY_Auto_Neco_Comp      = 0x0020
 
        ; PHY_AUTO_NEGO_REG = 4
        PHY_Cap_10_Half         = 0x0020
        PHY_Cap_10_Full         = 0x0040
        PHY_Cap_100_Half        = 0x0080
        PHY_Cap_100_Full        = 0x0100
 
        ; PHY_1000_CTRL_REG = 9
        PHY_Cap_1000_Full       = 0x0200
        PHY_Cap_1000_Half       = 0x0100
 
        PHY_Cap_PAUSE           = 0x0400
        PHY_Cap_ASYM_PAUSE      = 0x0800
 
        PHY_Cap_Null            = 0x0
 
        ; _MediaType
        MT_10_Half              = 0x01
        MT_10_Full              = 0x02
        MT_100_Half             = 0x04
        MT_100_Full             = 0x08
        MT_1000_Full            = 0x10
 
        ; _TBICSRBit
        TBI_LinkOK              = 0x02000000
 
        ; _DescStatusBit
        DSB_OWNbit              = 0x80000000
        DSB_EORbit              = 0x40000000
        DSB_FSbit               = 0x20000000
        DSB_LSbit               = 0x10000000
 
        RX_BUF_SIZE             = 1536          ; Rx Buffer size
 
; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
        MAX_ETH_FRAME_SIZE      = 1536
 
        TX_FIFO_THRESH          = 256           ; In bytes
 
        RX_FIFO_THRESH          = 7             ; 7 means NO threshold, Rx buffer level before first PCI xfer
        RX_DMA_BURST            = 7             ; Maximum PCI burst, '6' is 1024
        TX_DMA_BURST            = 7             ; Maximum PCI burst, '6' is 1024
        ETTh                    = 0x3F          ; 0x3F means NO threshold
 
        EarlyTxThld             = 0x3F          ; 0x3F means NO early transmit
        RxPacketMaxSize         = 0x0800        ; Maximum size supported is 16K-1
        InterFrameGap           = 0x03          ; 3 means InterFrameGap = the shortest one
 
        HZ                      = 1000
 
        RTL_MIN_IO_SIZE         = 0x80
        TX_TIMEOUT              = (6*HZ)
 
        TIMER_EXPIRE_TIME       = 100
 
        ETH_HDR_LEN             = 14
        DEFAULT_MTU             = 1500
        DEFAULT_RX_BUF_LEN      = 1536
 
 
;ifdef   JUMBO_FRAME_SUPPORT
;        MAX_JUMBO_FRAME_MTU     = 10000
;        MAX_RX_SKBDATA_SIZE     = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
;else
        MAX_RX_SKBDATA_SIZE     = 1600
;end if
 
        MCFG_METHOD_01          = 0x01
        MCFG_METHOD_02          = 0x02
        MCFG_METHOD_03          = 0x03
        MCFG_METHOD_04          = 0x04
        MCFG_METHOD_05          = 0x05
        MCFG_METHOD_11          = 0x0b
        MCFG_METHOD_12          = 0x0c
        MCFG_METHOD_13          = 0x0d
        MCFG_METHOD_14          = 0x0e
        MCFG_METHOD_15          = 0x0f
 
        PCFG_METHOD_1           = 0x01          ; PHY Reg 0x03 bit0-3 == 0x0000
        PCFG_METHOD_2           = 0x02          ; PHY Reg 0x03 bit0-3 == 0x0001
        PCFG_METHOD_3           = 0x03          ; PHY Reg 0x03 bit0-3 == 0x0002
 
virtual at 0
  tx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb    (NUM_TX_DESC-1)*tx_desc.size
  .buf_soft_addr        dd ?
end virtual
 
virtual at 0
  rx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb    (NUM_RX_DESC-1)*rx_desc.size
  .buf_soft_addr        dd ?
end virtual
 
virtual at ebx
 
        device:
 
        ETH_DEVICE
 
        .io_addr        dd ?
        .pci_bus        dd ?
        .pci_dev        dd ?
        .irq_line       db ?
 
        rb 256-(($ - device) and 255)              ;        align 256
        .tx_ring rb NUM_TX_DESC * tx_desc.size * 2
 
        rb 256-(($ - device) and 255)              ;        align 256
        .rx_ring rb NUM_RX_DESC * rx_desc.size * 2
 
        tpc:
        .mmio_addr      dd ? ; memory map physical address
        .chipset        dd ?
        .pcfg           dd ?
        .mcfg           dd ?
        .cur_rx         dd ? ; Index into the Rx descriptor buffer of next Rx pkt
        .cur_tx         dd ? ; Index into the Tx descriptor buffer of next Rx pkt
        .TxDescArrays   dd ? ; Index of Tx Descriptor buffer
        .RxDescArrays   dd ? ; Index of Rx Descriptor buffer
        .TxDescArray    dd ? ; Index of 256-alignment Tx Descriptor buffer
        .RxDescArray    dd ? ; Index of 256-alignment Rx Descriptor buffer
 
        device_size = $ - device
 
end virtual
 
        intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
        rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
 
 
macro   udelay msec {
 
        push    esi
        mov     esi, msec
        call    Sleep
        pop     esi
 
}
 
macro   WRITE_GMII_REG  RegAddr, value {
 
        set_io  REG_PHYAR
        if      value eq ax
        and     eax, 0x0000ffff
        or      eax, 0x80000000 + (RegAddr shl 16)
        else
        mov     eax, 0x80000000 + (RegAddr shl 16) + value
        end if
        out     dx, eax
 
        call    PHY_WAIT_WRITE
}
 
macro   READ_GMII_REG  RegAddr {
 
local   .error, .done
 
        set_io  REG_PHYAR
        mov     eax, RegAddr shl 16
        out     dx, eax
 
        call    PHY_WAIT_READ
        jz      .error
 
        in      eax, dx
        and     eax, 0xFFFF
        jmp     .done
 
  .error:
        or      eax, -1
  .done:
}
 
align 4
PHY_WAIT_READ:       ; io addr must already be set to REG_PHYAR
 
        udelay  1        ;;;1000
 
        push    ecx
        mov     ecx, 2000
        ; Check if the RTL8169 has completed writing/reading to the specified MII register
    @@:
        in      eax, dx
        test    eax, 0x80000000
        jnz     .exit
        udelay  1        ;;;100
        loop    @b
  .exit:
        pop     ecx
        ret
 
align 4
PHY_WAIT_WRITE:       ; io addr must already be set to REG_PHYAR
 
        udelay  1        ;;;1000
 
        push    ecx
        mov     ecx, 2000
        ; Check if the RTL8169 has completed writing/reading to the specified MII register
    @@:
        in      eax, dx
        test    eax, 0x80000000
        jz      .exit
        udelay  1        ;;;100
        loop    @b
  .exit:
        pop     ecx
        ret
 
 
 
section '.flat' code readable align 16
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc START stdcall, state:dword
 
        cmp [state], 1
        jne .exit
 
  .entry:
 
        DEBUGF  2,"Loading %s driver\n", my_service
        stdcall RegService, my_service, service_proc
        ret
 
  .fail:
  .exit:
        xor eax, eax
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc service_proc stdcall, ioctl:dword
 
        mov     edx, [ioctl]
        mov     eax, [edx + IOCTL.io_code]
 
;------------------------------------------------------
 
        cmp     eax, 0 ;SRV_GETVERSION
        jne     @F
 
        cmp     [edx + IOCTL.out_size], 4
        jb      .fail
        mov     eax, [edx + IOCTL.output]
        mov     [eax], dword API_VERSION
 
        xor     eax, eax
        ret
 
;------------------------------------------------------
  @@:
        cmp     eax, 1 ;SRV_HOOK
        jne     .fail
 
        cmp     [edx + IOCTL.inp_size], 3               ; Data input must be at least 3 bytes
        jb      .fail
 
        mov     eax, [edx + IOCTL.input]
        cmp     byte [eax], 1                           ; 1 means device number and bus number (pci) are given
        jne     .fail                                   ; other types arent supported for this card yet
 
; check if the device is already listed
 
        mov     esi, device_list
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .firstdevice
 
;        mov     eax, [edx + IOCTL.input]                ; get the pci bus and device numbers
        mov     ax, [eax+1]                             ;
  .nextdevice:
        mov     ebx, [esi]
        cmp     al, byte[device.pci_bus]
        jne     @f
        cmp     ah, byte[device.pci_dev]
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
       @@:
        add     esi, 4
        loop    .nextdevice
 
 
; This device doesnt have its own eth_device structure yet, lets create one
  .firstdevice:
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
        jae     .fail
 
        allocate_and_clear ebx, device_size, .fail      ; Allocate memory to put the device structure in
 
; Fill in the direct call addresses into the struct
 
        mov     [device.reset], reset
        mov     [device.transmit], transmit
        mov     [device.unload], unload
        mov     [device.name], my_service
 
; save the pci bus and device numbers
 
        mov     eax, [edx + IOCTL.input]
        movzx   ecx, byte[eax+1]
        mov     [device.pci_bus], ecx
        movzx   ecx, byte[eax+2]
        mov     [device.pci_dev], ecx
 
; Now, it's time to find the base io addres of the PCI device
 
        PCI_find_io
        mov     [tpc.mmio_addr], eax    ; CHECKME
 
; We've found the io address, find IRQ now
 
        PCI_find_irq
 
        DEBUGF  2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
        [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
        mov     eax, [devices]                                          ; Add the device structure to our device list
        mov     [device_list + 4*eax], ebx                              ; (IRQ handler uses this list to find device)
        inc     [devices]                                               ;
 
        call    probe                                                   ; this function will output in eax
        test    eax, eax
        jnz     .err2                                                   ; If an error occured, exit
 
        mov     [device.type], NET_TYPE_ETH
        call    NetRegDev
 
        cmp     eax, -1
        je      .destroy
 
        ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
        DEBUGF  2,"Trying to find device number of already registered device\n"
        call    NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
                                                                        ; into a device number in edi
        mov     eax, edi                                                ; Application wants it in eax instead
        DEBUGF  2,"Kernel says: %u\n", eax
        ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
        ; todo: reset device into virgin state
 
  .err2:
        dec     [devices]
  .err:
        DEBUGF  2,"removing device structure\n"
        stdcall KernelFree, ebx
  .fail:
        or      eax, -1
        ret
 
;------------------------------------------------------
endp
 
 
align 4
unload:
 
        ret
 
 
align 4
init_board:
 
        DEBUGF  1,"init_board\n"
 
        PCI_make_bus_master
 
        ; Soft reset the chip
        set_io  0
        set_io  REG_ChipCmd
        mov     al, CMD_Reset
        out     dx, al
 
        ; Check that the chip has finished the reset
        mov     ecx, 1000
        set_io  REG_ChipCmd
    @@: in      al, dx
        test    al, CMD_Reset
        jz      @f
        udelay  10
        loop    @b
    @@:
        ; identify config method
        set_io  REG_TxConfig
        in      eax, dx
        and     eax, 0x7c800000
        DEBUGF  1,"init_board: TxConfig & 0x7c800000 = 0x%x\n", eax
        mov     esi, mac_info-8
    @@: add     esi, 8
        mov     ecx, eax
        and     ecx, [esi]
        cmp     ecx, [esi]
        jne     @b
        mov     eax, [esi+4]
        mov     [tpc.mcfg], eax
 
        mov     [tpc.pcfg], PCFG_METHOD_3
        READ_GMII_REG 3
        and     al, 0x0f
        or      al, al
        jnz     @f
        mov     [tpc.pcfg], PCFG_METHOD_1
        jmp     .pconf
    @@: dec     al
        jnz     .pconf
        mov     [tpc.pcfg], PCFG_METHOD_2
  .pconf:
 
        ; identify chip attached to board
        mov     ecx, 10
        mov     eax, [tpc.mcfg]
    @@: dec     ecx
        js      @f
        cmp     eax, [rtl_chip_info + ecx*8]
        jne     @b
        mov     [tpc.chipset], ecx
        jmp     .match
    @@:
        ; if unknown chip, assume array element #0, original RTL-8169 in this case
        DEBUGF  1,"init_board: PCI device: unknown chip version, assuming RTL-8169\n"
        set_io  REG_TxConfig
        in      eax, dx
        DEBUGF  1,"init_board: PCI device: TxConfig = 0x%x\n", eax
 
        mov     [tpc.chipset],  0
 
        xor     eax, eax
        inc     eax
        ret
 
  .match:
        DEBUGF  1,"init_board: chipset=%u\n", ecx
        xor     eax,eax
        ret
 
 
 
;***************************************************************************
;   Function
;      probe
;   Description
;      Searches for an ethernet card, enables it and clears the rx buffer
;      If a card was found, it enables the ethernet -> TCPIP link
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
probe:
 
        DEBUGF  1,"probe\n"
 
        call    init_board
        call    read_mac
        call    PHY_config
 
        DEBUGF  1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
        set_io  0
        set_io  0x82
        mov     al, 0x01
        out     dx, al
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jae     @f
        DEBUGF  1,"Set PCI Latency=0x40\n"
        PCI_adjust_latency 0x40
   @@:
        cmp     [tpc.mcfg], MCFG_METHOD_02
        jne     @f
        DEBUGF  1,"Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
        set_io  0x82
        mov     al, 0x01
        out     dx, al
        DEBUGF  1,"Set PHY Reg 0x0bh = 0x00h\n"
        WRITE_GMII_REG 0x0b, 0x0000      ; w 0x0b 15 0 0
    @@:
        ; if TBI is not enabled
        set_io  0
        set_io  REG_PHYstatus
        in      al, dx
        test    al, PHYS_TBI_Enable
        jz      .tbi_dis
        READ_GMII_REG PHY_AUTO_NEGO_REG
 
        ; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
        and     eax, 0x0C1F
        or      eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
        WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
 
        ; enable 1000 Full Mode
        WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
 
        ; Enable auto-negotiation and restart auto-nigotiation
        WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
 
        udelay  100
        mov     ecx, 10000
        ; wait for auto-negotiation process
    @@: dec     ecx
        jz      @f
        set_io  0
        READ_GMII_REG PHY_STAT_REG
        udelay  100
        test    eax, PHY_Auto_Neco_Comp
        jz      @b
        set_io  REG_PHYstatus
        in      al, dx
        jmp     @f
  .tbi_dis:
        udelay  100
    @@:
 
 
;***************************************************************************
;   Function
;      rt8169_reset
;   Description
;      Place the chip (ie, the ethernet card) into a virgin state
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
reset:
 
        DEBUGF  1,"reset\n"
 
        lea     eax, [device.tx_ring]
        mov     [tpc.TxDescArrays], eax
        mov     [tpc.TxDescArray], eax
 
        lea     eax, [device.rx_ring]
        mov     [tpc.RxDescArrays], eax
        mov     [tpc.RxDescArray], eax
 
        call    init_ring
        call    hw_start
 
; clear packet/byte counters
 
        xor     eax, eax
        lea     edi, [device.bytes_tx]
        mov     ecx, 6
        rep     stosd
 
        mov     [device.mtu], 1500
 
; Set link state to unknown
        mov     [device.state], ETH_LINK_UNKOWN
 
        xor     eax, eax
        ret
 
 
 
 
 
align 4
PHY_config:
 
        DEBUGF  1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n", [tpc.mcfg], [tpc.pcfg]
 
        cmp     [tpc.mcfg], MCFG_METHOD_04
        jne     .not_4
        set_io  0
;       WRITE_GMII_REG 0x1F, 0x0001
;       WRITE_GMII_REG 0x1b, 0x841e
;       WRITE_GMII_REG 0x0e, 0x7bfb
;       WRITE_GMII_REG 0x09, 0x273a
        WRITE_GMII_REG 0x1F, 0x0002
        WRITE_GMII_REG 0x01, 0x90D0
        WRITE_GMII_REG 0x1F, 0x0000
        jmp     .exit
  .not_4:
        cmp     [tpc.mcfg], MCFG_METHOD_02
        je      @f
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jne     .not_2_or_3
    @@:
        set_io  0
        WRITE_GMII_REG 0x1F, 0x0001
        WRITE_GMII_REG 0x15, 0x1000
        WRITE_GMII_REG 0x18, 0x65C7
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x03, 0x00A1
        WRITE_GMII_REG 0x02, 0x0008
        WRITE_GMII_REG 0x01, 0x1020
        WRITE_GMII_REG 0x00, 0x1000
        WRITE_GMII_REG 0x04, 0x0800
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x04, 0x7000
        WRITE_GMII_REG 0x03, 0xFF41
        WRITE_GMII_REG 0x02, 0xDE60
        WRITE_GMII_REG 0x01, 0x0140
        WRITE_GMII_REG 0x00, 0x0077
        WRITE_GMII_REG 0x04, 0x7800
        WRITE_GMII_REG 0x04, 0x7000
        WRITE_GMII_REG 0x04, 0xA000
        WRITE_GMII_REG 0x03, 0xDF01
        WRITE_GMII_REG 0x02, 0xDF20
        WRITE_GMII_REG 0x01, 0xFF95
        WRITE_GMII_REG 0x00, 0xFA00
        WRITE_GMII_REG 0x04, 0xA800
        WRITE_GMII_REG 0x04, 0xA000
        WRITE_GMII_REG 0x04, 0xB000
        WRITE_GMII_REG 0x03, 0xFF41
        WRITE_GMII_REG 0x02, 0xDE20
        WRITE_GMII_REG 0x01, 0x0140
        WRITE_GMII_REG 0x00, 0x00BB
        WRITE_GMII_REG 0x04, 0xB800
        WRITE_GMII_REG 0x04, 0xB000
        WRITE_GMII_REG 0x04, 0xF000
        WRITE_GMII_REG 0x03, 0xDF01
        WRITE_GMII_REG 0x02, 0xDF20
        WRITE_GMII_REG 0x01, 0xFF95
        WRITE_GMII_REG 0x00, 0xBF00
        WRITE_GMII_REG 0x04, 0xF800
        WRITE_GMII_REG 0x04, 0xF000
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x1F, 0x0000
        WRITE_GMII_REG 0x0B, 0x0000
        jmp     .exit
  .not_2_or_3:
        DEBUGF  1,"tpc.mcfg=%d, discard hw PHY config\n", [tpc.mcfg]
  .exit:
        ret
 
 
 
align 4
set_rx_mode:
 
        DEBUGF  1,"set_rx_mode\n"
 
        ; IFF_ALLMULTI
        ; Too many to filter perfectly -- accept all multicasts
        set_io  0
        set_io  REG_RxConfig
        in      eax, dx
        mov     ecx, [tpc.chipset]
        and     eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
        or      eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
        out     dx, eax
 
        ; Multicast hash filter
        set_io  REG_MAR0 + 0
        or      eax, -1
        out     dx, eax
        set_io  REG_MAR0 + 4
        out     dx, eax
 
        ret
 
 
align 4
init_ring:
 
        DEBUGF  1,"init_ring\n"
 
        xor     eax, eax
        mov     [tpc.cur_rx], eax
        mov     [tpc.cur_tx], eax
 
        lea     edi, [device.tx_ring]
        mov     ecx, (NUM_TX_DESC * tx_desc.size) / 4
        rep     stosd
 
        lea     edi, [device.rx_ring]
        mov     ecx, (NUM_RX_DESC * rx_desc.size) / 4
        rep     stosd
 
        mov     edi, [tpc.RxDescArray]
        mov     ecx, NUM_RX_DESC
  .loop:
        push    ecx
        stdcall KernelAlloc, RX_BUF_SIZE
        mov     [edi + rx_desc.buf_soft_addr], eax
        call    GetPgAddr
        mov     dword [edi + rx_desc.buf_addr], eax
        mov     [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
        add     edi, rx_desc.size
        pop     ecx
        loop    .loop
        or      [edi - rx_desc.size + rx_desc.status], DSB_EORbit
 
        ret
 
 
align 4
hw_start:
 
        DEBUGF  1,"hw_start\n"
 
; attach int handler
        movzx   eax, [device.irq_line]
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
        stdcall AttachIntHandler, eax, int_handler, dword 0
 
        ; Soft reset the chip
        set_io  0
        set_io  REG_ChipCmd
        mov     al, CMD_Reset
        out     dx, al
 
        DEBUGF  1,"Waiting for chip to reset... "
        ; Check that the chip has finished the reset
        mov     ecx, 1000
        set_io  REG_ChipCmd
    @@: in      al, dx
        test    al, CMD_Reset
        jz      @f
        udelay  10
        loop    @b
    @@:
        DEBUGF  1,"done!\n"
 
        set_io  REG_Cfg9346
        mov     al, CFG_9346_Unlock
        out     dx, al
 
        set_io  REG_ChipCmd
        mov     al, CMD_TxEnb or CMD_RxEnb
        out     dx, al
 
        set_io  REG_ETThReg
        mov     al, ETTh
        out     dx, al
 
        ; For gigabit rtl8169
        set_io  REG_RxMaxSize
        mov     ax, RxPacketMaxSize
        out     dx, ax
 
        ; Set Rx Config register
        set_io  REG_RxConfig
        in      ax, dx
        mov     ecx, [tpc.chipset]
        and     eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
        or      eax, rx_config
        out     dx, eax
 
        ; Set DMA burst size and Interframe Gap Time
        set_io  REG_TxConfig
        mov     eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
        out     dx, eax
 
        set_io  REG_CPlusCmd
        in      ax, dx
        out     dx, ax
 
        in      ax, dx
        or      ax, 1 shl 3
        cmp     [tpc.mcfg], MCFG_METHOD_02
        jne     @f
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jne     @f
        or      ax,1 shl 14
        DEBUGF  1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
        jmp     .set
    @@:
        DEBUGF  1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
  .set:
        set_io  REG_CPlusCmd
        out     dx, ax
 
        set_io  0xE2
;        mov     ax, 0x1517
;        out     dx, ax
;        mov     ax, 0x152a
;        out     dx, ax
;        mov     ax, 0x282a
;        out     dx, ax
        xor     ax, ax
        out     dx, ax
 
        xor     eax, eax
        mov     [tpc.cur_rx], eax
        lea     eax, [device.tx_ring]
        GetRealAddr
        set_io  REG_TxDescStartAddr
        out     dx, eax
        set_io  REG_TxDescStartAddr + 4
        xor     eax, eax
        out     dx, eax
 
        lea     eax, [device.rx_ring]
        GetRealAddr
        set_io  REG_RxDescStartAddr
        out     dx, eax
        xor     eax, eax
        set_io  REG_RxDescStartAddr + 4
        out     dx, eax
 
        set_io  REG_Cfg9346
        mov     al, CFG_9346_Lock
        out     dx, al
 
        udelay  10
 
        xor     eax, eax
        set_io  REG_RxMissed
        out     dx, eax
 
        call    set_rx_mode
 
        set_io  0
        ; no early-rx interrupts
        set_io  REG_MultiIntr
        in      ax, dx
        and     ax, 0xF000
        out     dx, ax
 
        ; set interrupt mask
        set_io  REG_IntrMask
        mov     ax, intr_mask
        out     dx, ax
 
        xor     eax, eax
        ret
 
 
align 4
read_mac:
 
        set_io  0
        set_io  REG_MAC0
        xor     ecx, ecx
        lea     edi, [device.mac]
        mov     ecx, 6
 
        ; Get MAC address. FIXME: read EEPROM
    @@: in      al, dx
        stosb
        inc     edx
        loop    @r
 
        DEBUGF  1,"MAC = %x-%x-%x-%x-%x-%x\n",\
        [device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2
 
        ret
 
align 4
write_mac:
 
        ret     6
 
 
 
 
 
;***************************************************************************
;   Function
;      transmit
;   Description
;      Transmits a packet of data via the ethernet card
;
;   Destroyed registers
;      eax, edx, esi, edi
;
;***************************************************************************
align 4
transmit:
 
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
        mov     eax, [esp+4]
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
        [eax+13]:2,[eax+12]:2
 
        cmp     dword [esp+8], MAX_ETH_FRAME_SIZE
        ja      .fail
 
;----------------------------------
; Find currentTX descriptor address
 
        mov     eax, tx_desc.size
        mul     [tpc.cur_tx]
        lea     esi, [eax + device.tx_ring]
 
        DEBUGF  1,"Using TX desc: %x\n", esi
 
;---------------------------
; Program the packet pointer
 
        mov     eax, [esp + 4]
        mov     [esi + tx_desc.buf_soft_addr], eax
        GetRealAddr
        mov     dword [esi + tx_desc.buf_addr], eax
 
;------------------------
; Program the packet size
 
        mov     eax, [esp + 8]
    @@: or      eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
        cmp     [tpc.cur_tx], NUM_TX_DESC - 1
        jne     @f
        or      eax, DSB_EORbit
    @@: mov     [esi + tx_desc.status], eax
 
;-----------------------------------------
; Set the polling bit (start transmission)
 
        set_io  0
        set_io  REG_TxPoll
        mov     al, 0x40     ; set polling bit
        out     dx, al
 
;-----------------------
; Update TX descriptor
 
        inc     [tpc.cur_tx]
        and     [tpc.cur_tx], NUM_TX_DESC - 1
 
;-------------
; Update stats
 
        inc     [device.packets_tx]
        mov     eax, [esp + 8]
        add     dword [device.bytes_tx], eax
        adc     dword [device.bytes_tx + 4], 0
 
        xor     eax, eax
        ret     8
 
  .fail:
        DEBUGF  1,"transmit failed\n"
        stdcall KernelFree, [esp+4]
        or      eax, -1
        ret     8
 
 
;;;DSB_OWNbit
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
        push    ebx esi edi
 
        DEBUGF  1,"INT\n"
 
; find pointer of device wich made IRQ occur
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .nothing
        mov     esi, device_list
  .nextdevice:
        mov     ebx, [esi]
 
        set_io  0
        set_io  REG_IntrStatus
        in      ax, dx
        test    ax, ax
        jnz     .got_it
  .continue:
        add     esi, 4
        dec     ecx
        jnz     .nextdevice
  .nothing:
        pop     edi esi ebx
        xor     eax, eax
 
        ret                                             ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
 
  .got_it:
 
        DEBUGF  1,"Device: %x Status: %x ", ebx, ax
 
        cmp     ax, 0xFFFF      ; if so, hardware is no longer present
        je      .fail
 
;--------
; Receive
 
        test    ax, ISB_RxOK
        jz      .no_rx
 
        push    ax
        push    ebx
 
  .check_more:
        pop     ebx
        DEBUGF  1,"ebx = 0x%x\n", ebx
        mov     eax, rx_desc.size
        mul     [tpc.cur_rx]
        lea     esi, [eax + device.rx_ring]
 
        DEBUGF  1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
 
        mov     eax, [esi + rx_desc.status]
        test    eax, DSB_OWNbit ;;;
        jnz     .rx_return
 
        DEBUGF  1,"tpc.cur_rx = %u\n", [tpc.cur_rx]
 
        test    eax, SD_RxRES
        jnz     .rx_return      ;;;;; RX error!
 
        push    ebx
        push    .check_more
        and     eax, 0x00001FFF
        add     eax, -4                         ; we dont need CRC
        push    eax
        DEBUGF  1,"data length = %u\n", ax
 
;-------------
; Update stats
 
        add     dword [device.bytes_rx], eax
        adc     dword [device.bytes_rx + 4], 0
        inc     dword [device.packets_rx]
 
        push    [esi + rx_desc.buf_soft_addr]
 
;----------------------
; Allocate a new buffer
 
        stdcall KernelAlloc, RX_BUF_SIZE
        mov     [esi + rx_desc.buf_soft_addr], eax
        GetRealAddr
        mov     dword [esi + rx_desc.buf_addr], eax
 
;---------------
; re set OWN bit
 
        mov     eax, DSB_OWNbit or RX_BUF_SIZE
        cmp     [tpc.cur_rx], NUM_RX_DESC - 1
        jne     @f
        or      eax, DSB_EORbit
    @@: mov     [esi + rx_desc.status], eax
 
;--------------
; Update rx ptr
 
        inc     [tpc.cur_rx]
        and     [tpc.cur_rx], NUM_RX_DESC - 1
 
        jmp     Eth_input
  .rx_return:
 
        pop     ax
  .no_rx:
 
;---------
; Transmit
 
        test    ax, ISB_TxOK
        jz      .no_tx
        push    ax
 
        DEBUGF  1,"TX ok!\n"
 
        mov     ecx, NUM_TX_DESC
        lea     esi, [device.tx_ring]
  .txloop:
        cmp     [esi + tx_desc.buf_soft_addr], 0
        jz      .maybenext
 
        test    [esi + tx_desc.status], DSB_OWNbit
        jnz     .maybenext
 
        push    ecx
        DEBUGF  1,"Freeing up TX desc: %x\n", esi
        stdcall KernelFree, [esi + tx_desc.buf_soft_addr]
        pop     ecx
        and     [esi + tx_desc.buf_soft_addr], 0
 
  .maybenext:
        add     esi, tx_desc.size
        dec     ecx
        jnz     .txloop
 
        pop     ax
  .no_tx:
 
;-------
; Finish
 
        set_io  0
        set_io  REG_IntrStatus
        out     dx, ax                  ; ACK all interrupts
 
  .fail:
        pop     edi esi ebx
        xor     eax, eax
        inc     eax
 
        ret
 
 
 
 
 
 
 
 
 
; End of code
align 4                                         ; Place all initialised data here
 
devices       dd 0
version       dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF)
my_service    db 'RTL8169',0                    ; max 16 chars include zero
 
include_debug_strings                           ; All data wich FDO uses will be included here
 
rtl_chip_info dd \
  MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169
  MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb
  MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc
  MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e         // PCI-E 8139
  MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e         // PCI-E 8139
  MCFG_METHOD_15, 0xff7e1880    ; RTL8100e         // PCI-E 8139
 
mac_info dd \
  0x38800000, MCFG_METHOD_15, \
  0x38000000, MCFG_METHOD_12, \
  0x34000000, MCFG_METHOD_13, \
  0x30800000, MCFG_METHOD_14, \
  0x30000000, MCFG_METHOD_11, \
  0x18000000, MCFG_METHOD_05, \
  0x10000000, MCFG_METHOD_04, \
  0x04000000, MCFG_METHOD_03, \
  0x00800000, MCFG_METHOD_02, \
  0x00000000, MCFG_METHOD_01    ; catch-all
 
name_01         db "RTL8169", 0
name_02_03      db "RTL8169s/8110s", 0
name_04         db "RTL8169sb/8110sb", 0
name_05         db "RTL8169sc/8110sc", 0
name_11_12      db "RTL8168b/8111b", 0  ; PCI-E
name_13         db "RTL8101e", 0        ; PCI-E 8139
name_14_15      db "RTL8100e", 0        ; PCI-E 8139
 
 
section '.data' data readable writable align 16 ; place all uninitialized data place here
 
device_list rd MAX_DEVICES                     ; This list contains all pointers to device structures the driver is handling

Rev 4467	Rev 4470
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; RTL8169 driver for KolibriOS ;;	6	;; RTL8169 driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; Copyright 2007 mike.dld, ;;	8	;; Copyright 2007 mike.dld, ;;
9	;; mike.dld@gmail.com ;;	9	;; mike.dld@gmail.com ;;
10	;; ;;	10	;; ;;
11	;; port to net branch by hidnplayr ;;	11	;; port to net branch by hidnplayr ;;
12	;; ;;	12	;; ;;
13	;; References: ;;	13	;; References: ;;
14	;; r8169.c - linux driver (etherboot project) ;;	14	;; r8169.c - linux driver (etherboot project) ;;
15	;; ;;	15	;; ;;
16	;; GNU GENERAL PUBLIC LICENSE ;;	16	;; GNU GENERAL PUBLIC LICENSE ;;
17	;; Version 2, June 1991 ;;	17	;; Version 2, June 1991 ;;
18	;; ;;	18	;; ;;
19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
20		20
21	format MS COFF	21	format MS COFF
22		22
23	API_VERSION = 0x01000100	23	API_VERSION = 0x01000100
24	DRIVER_VERSION = 5	24	DRIVER_VERSION = 5
25		25
26	MAX_DEVICES = 16	26	MAX_DEVICES = 16
27		27
28	DEBUG = 1	28	DEBUG = 1
29	__DEBUG__ = 1	29	__DEBUG__ = 1
30	__DEBUG_LEVEL__ = 2	30	__DEBUG_LEVEL__ = 2
31		31
32	NUM_TX_DESC = 4	32	NUM_TX_DESC = 4
33	NUM_RX_DESC = 4	33	NUM_RX_DESC = 4
34		34
35	include '../struct.inc'	35	include '../struct.inc'
36	include '../macros.inc'	36	include '../macros.inc'
37	include '../proc32.inc'	37	include '../proc32.inc'
38	include '../imports.inc'	38	include '../imports.inc'
39	include '../fdo.inc'	39	include '../fdo.inc'
40	include '../netdrv.inc'	40	include '../netdrv.inc'
41		41
42	public START	42	public START
43	public service_proc	43	public service_proc
44	public version	44	public version
45		45
46		46
47	REG_MAC0 = 0x0 ; Ethernet hardware address	47	REG_MAC0 = 0x0 ; Ethernet hardware address
48	REG_MAR0 = 0x8 ; Multicast filter	48	REG_MAR0 = 0x8 ; Multicast filter
49	REG_TxDescStartAddr = 0x20	49	REG_TxDescStartAddr = 0x20
50	REG_TxHDescStartAddr = 0x28	50	REG_TxHDescStartAddr = 0x28
51	REG_FLASH = 0x30	51	REG_FLASH = 0x30
52	REG_ERSR = 0x36	52	REG_ERSR = 0x36
53	REG_ChipCmd = 0x37	53	REG_ChipCmd = 0x37
54	REG_TxPoll = 0x38	54	REG_TxPoll = 0x38
55	REG_IntrMask = 0x3C	55	REG_IntrMask = 0x3C
56	REG_IntrStatus = 0x3E	56	REG_IntrStatus = 0x3E
57	REG_TxConfig = 0x40	57	REG_TxConfig = 0x40
58	REG_RxConfig = 0x44	58	REG_RxConfig = 0x44
59	REG_RxMissed = 0x4C	59	REG_RxMissed = 0x4C
60	REG_Cfg9346 = 0x50	60	REG_Cfg9346 = 0x50
61	REG_Config0 = 0x51	61	REG_Config0 = 0x51
62	REG_Config1 = 0x52	62	REG_Config1 = 0x52
63	REG_Config2 = 0x53	63	REG_Config2 = 0x53
64	REG_Config3 = 0x54	64	REG_Config3 = 0x54
65	REG_Config4 = 0x55	65	REG_Config4 = 0x55
66	REG_Config5 = 0x56	66	REG_Config5 = 0x56
67	REG_MultiIntr = 0x5C	67	REG_MultiIntr = 0x5C
68	REG_PHYAR = 0x60	68	REG_PHYAR = 0x60
69	REG_TBICSR = 0x64	69	REG_TBICSR = 0x64
70	REG_TBI_ANAR = 0x68	70	REG_TBI_ANAR = 0x68
71	REG_TBI_LPAR = 0x6A	71	REG_TBI_LPAR = 0x6A
72	REG_PHYstatus = 0x6C	72	REG_PHYstatus = 0x6C
73	REG_RxMaxSize = 0xDA	73	REG_RxMaxSize = 0xDA
74	REG_CPlusCmd = 0xE0	74	REG_CPlusCmd = 0xE0
75	REG_RxDescStartAddr = 0xE4	75	REG_RxDescStartAddr = 0xE4
76	REG_ETThReg = 0xEC	76	REG_ETThReg = 0xEC
77	REG_FuncEvent = 0xF0	77	REG_FuncEvent = 0xF0
78	REG_FuncEventMask = 0xF4	78	REG_FuncEventMask = 0xF4
79	REG_FuncPresetState = 0xF8	79	REG_FuncPresetState = 0xF8
80	REG_FuncForceEvent = 0xFC	80	REG_FuncForceEvent = 0xFC
81		81
82	; InterruptStatusBits	82	; InterruptStatusBits
83	ISB_SYSErr = 0x8000	83	ISB_SYSErr = 0x8000
84	ISB_PCSTimeout = 0x4000	84	ISB_PCSTimeout = 0x4000
85	ISB_SWInt = 0x0100	85	ISB_SWInt = 0x0100
86	ISB_TxDescUnavail = 0x80	86	ISB_TxDescUnavail = 0x80
87	ISB_RxFIFOOver = 0x40	87	ISB_RxFIFOOver = 0x40
88	ISB_LinkChg = 0x20	88	ISB_LinkChg = 0x20
89	ISB_RxOverflow = 0x10	89	ISB_RxOverflow = 0x10
90	ISB_TxErr = 0x08	90	ISB_TxErr = 0x08
91	ISB_TxOK = 0x04	91	ISB_TxOK = 0x04
92	ISB_RxErr = 0x02	92	ISB_RxErr = 0x02
93	ISB_RxOK = 0x01	93	ISB_RxOK = 0x01
94		94
95	; RxStatusDesc	95	; RxStatusDesc
96	SD_RxRES = 0x00200000	96	SD_RxRES = 0x00200000
97	SD_RxCRC = 0x00080000	97	SD_RxCRC = 0x00080000
98	SD_RxRUNT = 0x00100000	98	SD_RxRUNT = 0x00100000
99	SD_RxRWT = 0x00400000	99	SD_RxRWT = 0x00400000
100		100
101	; ChipCmdBits	101	; ChipCmdBits
102	CMD_Reset = 0x10	102	CMD_Reset = 0x10
103	CMD_RxEnb = 0x08	103	CMD_RxEnb = 0x08
104	CMD_TxEnb = 0x04	104	CMD_TxEnb = 0x04
105	CMD_RxBufEmpty = 0x01	105	CMD_RxBufEmpty = 0x01
106		106
107	; Cfg9346Bits	107	; Cfg9346Bits
108	CFG_9346_Lock = 0x00	108	CFG_9346_Lock = 0x00
109	CFG_9346_Unlock = 0xC0	109	CFG_9346_Unlock = 0xC0
110		110
111	; rx_mode_bits	111	; rx_mode_bits
112	RXM_AcceptErr = 0x20	112	RXM_AcceptErr = 0x20
113	RXM_AcceptRunt = 0x10	113	RXM_AcceptRunt = 0x10
114	RXM_AcceptBroadcast = 0x08	114	RXM_AcceptBroadcast = 0x08
115	RXM_AcceptMulticast = 0x04	115	RXM_AcceptMulticast = 0x04
116	RXM_AcceptMyPhys = 0x02	116	RXM_AcceptMyPhys = 0x02
117	RXM_AcceptAllPhys = 0x01	117	RXM_AcceptAllPhys = 0x01
118		118
119	; RxConfigBits	119	; RxConfigBits
120	RXC_FIFOShift = 13	120	RXC_FIFOShift = 13
121	RXC_DMAShift = 8	121	RXC_DMAShift = 8
122		122
123	; TxConfigBits	123	; TxConfigBits
124	TXC_InterFrameGapShift = 24	124	TXC_InterFrameGapShift = 24
125	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits	125	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
126		126
127	; PHYstatus	127	; PHYstatus
128	PHYS_TBI_Enable = 0x80	128	PHYS_TBI_Enable = 0x80
129	PHYS_TxFlowCtrl = 0x40	129	PHYS_TxFlowCtrl = 0x40
130	PHYS_RxFlowCtrl = 0x20	130	PHYS_RxFlowCtrl = 0x20
131	PHYS_1000bpsF = 0x10	131	PHYS_1000bpsF = 0x10
132	PHYS_100bps = 0x08	132	PHYS_100bps = 0x08
133	PHYS_10bps = 0x04	133	PHYS_10bps = 0x04
134	PHYS_LinkStatus = 0x02	134	PHYS_LinkStatus = 0x02
135	PHYS_FullDup = 0x01	135	PHYS_FullDup = 0x01
136		136
137	; GIGABIT_PHY_registers	137	; GIGABIT_PHY_registers
138	PHY_CTRL_REG = 0	138	PHY_CTRL_REG = 0
139	PHY_STAT_REG = 1	139	PHY_STAT_REG = 1
140	PHY_AUTO_NEGO_REG = 4	140	PHY_AUTO_NEGO_REG = 4
141	PHY_1000_CTRL_REG = 9	141	PHY_1000_CTRL_REG = 9
142		142
143	; GIGABIT_PHY_REG_BIT	143	; GIGABIT_PHY_REG_BIT
144	PHY_Restart_Auto_Nego = 0x0200	144	PHY_Restart_Auto_Nego = 0x0200
145	PHY_Enable_Auto_Nego = 0x1000	145	PHY_Enable_Auto_Nego = 0x1000
146		146
147	; PHY_STAT_REG = 1	147	; PHY_STAT_REG = 1
148	PHY_Auto_Neco_Comp = 0x0020	148	PHY_Auto_Neco_Comp = 0x0020
149		149
150	; PHY_AUTO_NEGO_REG = 4	150	; PHY_AUTO_NEGO_REG = 4
151	PHY_Cap_10_Half = 0x0020	151	PHY_Cap_10_Half = 0x0020
152	PHY_Cap_10_Full = 0x0040	152	PHY_Cap_10_Full = 0x0040
153	PHY_Cap_100_Half = 0x0080	153	PHY_Cap_100_Half = 0x0080
154	PHY_Cap_100_Full = 0x0100	154	PHY_Cap_100_Full = 0x0100
155		155
156	; PHY_1000_CTRL_REG = 9	156	; PHY_1000_CTRL_REG = 9
157	PHY_Cap_1000_Full = 0x0200	157	PHY_Cap_1000_Full = 0x0200
158	PHY_Cap_1000_Half = 0x0100	158	PHY_Cap_1000_Half = 0x0100
159		159
160	PHY_Cap_PAUSE = 0x0400	160	PHY_Cap_PAUSE = 0x0400
161	PHY_Cap_ASYM_PAUSE = 0x0800	161	PHY_Cap_ASYM_PAUSE = 0x0800
162		162
163	PHY_Cap_Null = 0x0	163	PHY_Cap_Null = 0x0
164		164
165	; _MediaType	165	; _MediaType
166	MT_10_Half = 0x01	166	MT_10_Half = 0x01
167	MT_10_Full = 0x02	167	MT_10_Full = 0x02
168	MT_100_Half = 0x04	168	MT_100_Half = 0x04
169	MT_100_Full = 0x08	169	MT_100_Full = 0x08
170	MT_1000_Full = 0x10	170	MT_1000_Full = 0x10
171		171
172	; _TBICSRBit	172	; _TBICSRBit
173	TBI_LinkOK = 0x02000000	173	TBI_LinkOK = 0x02000000
174		174
175	; _DescStatusBit	175	; _DescStatusBit
176	DSB_OWNbit = 0x80000000	176	DSB_OWNbit = 0x80000000
177	DSB_EORbit = 0x40000000	177	DSB_EORbit = 0x40000000
178	DSB_FSbit = 0x20000000	178	DSB_FSbit = 0x20000000
179	DSB_LSbit = 0x10000000	179	DSB_LSbit = 0x10000000
180		180
181	RX_BUF_SIZE = 1536 ; Rx Buffer size	181	RX_BUF_SIZE = 1536 ; Rx Buffer size
182		182
183	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)	183	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
184	MAX_ETH_FRAME_SIZE = 1536	184	MAX_ETH_FRAME_SIZE = 1536
185		185
186	TX_FIFO_THRESH = 256 ; In bytes	186	TX_FIFO_THRESH = 256 ; In bytes
187		187
188	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer	188	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
189	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024	189	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
190	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024	190	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
191	ETTh = 0x3F ; 0x3F means NO threshold	191	ETTh = 0x3F ; 0x3F means NO threshold
192		192
193	EarlyTxThld = 0x3F ; 0x3F means NO early transmit	193	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
194	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1	194	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
195	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one	195	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
196		196
197	HZ = 1000	197	HZ = 1000
198		198
199	RTL_MIN_IO_SIZE = 0x80	199	RTL_MIN_IO_SIZE = 0x80
200	TX_TIMEOUT = (6*HZ)	200	TX_TIMEOUT = (6*HZ)
201		201
202	TIMER_EXPIRE_TIME = 100	202	TIMER_EXPIRE_TIME = 100
203		203
204	ETH_HDR_LEN = 14	204	ETH_HDR_LEN = 14
205	DEFAULT_MTU = 1500	205	DEFAULT_MTU = 1500
206	DEFAULT_RX_BUF_LEN = 1536	206	DEFAULT_RX_BUF_LEN = 1536
207		207
208		208
209	;ifdef JUMBO_FRAME_SUPPORT	209	;ifdef JUMBO_FRAME_SUPPORT
210	; MAX_JUMBO_FRAME_MTU = 10000	210	; MAX_JUMBO_FRAME_MTU = 10000
211	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )	211	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
212	;else	212	;else
213	MAX_RX_SKBDATA_SIZE = 1600	213	MAX_RX_SKBDATA_SIZE = 1600
214	;end if	214	;end if
215		215
216	MCFG_METHOD_01 = 0x01	216	MCFG_METHOD_01 = 0x01
217	MCFG_METHOD_02 = 0x02	217	MCFG_METHOD_02 = 0x02
218	MCFG_METHOD_03 = 0x03	218	MCFG_METHOD_03 = 0x03
219	MCFG_METHOD_04 = 0x04	219	MCFG_METHOD_04 = 0x04
220	MCFG_METHOD_05 = 0x05	220	MCFG_METHOD_05 = 0x05
221	MCFG_METHOD_11 = 0x0b	221	MCFG_METHOD_11 = 0x0b
222	MCFG_METHOD_12 = 0x0c	222	MCFG_METHOD_12 = 0x0c
223	MCFG_METHOD_13 = 0x0d	223	MCFG_METHOD_13 = 0x0d
224	MCFG_METHOD_14 = 0x0e	224	MCFG_METHOD_14 = 0x0e
225	MCFG_METHOD_15 = 0x0f	225	MCFG_METHOD_15 = 0x0f
226		226
227	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000	227	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
228	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001	228	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
229	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002	229	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
230		230
231	virtual at 0	231	virtual at 0
232	tx_desc:	232	tx_desc:
233	.status dd ?	233	.status dd ?
234	.vlan_tag dd ?	234	.vlan_tag dd ?
235	.buf_addr dq ?	235	.buf_addr dq ?
236	.size = $	236	.size = $
237	rb (NUM_TX_DESC-1)*tx_desc.size	237	rb (NUM_TX_DESC-1)*tx_desc.size
238	.buf_soft_addr dd ?	238	.buf_soft_addr dd ?
239	end virtual	239	end virtual
240		240
241	virtual at 0	241	virtual at 0
242	rx_desc:	242	rx_desc:
243	.status dd ?	243	.status dd ?
244	.vlan_tag dd ?	244	.vlan_tag dd ?
245	.buf_addr dq ?	245	.buf_addr dq ?
246	.size = $	246	.size = $
247	rb (NUM_RX_DESC-1)*rx_desc.size	247	rb (NUM_RX_DESC-1)*rx_desc.size
248	.buf_soft_addr dd ?	248	.buf_soft_addr dd ?
249	end virtual	249	end virtual
250		250
251	virtual at ebx	251	virtual at ebx
252		252
253	device:	253	device:
254		254
255	ETH_DEVICE	255	ETH_DEVICE
256		256
257	.io_addr dd ?	257	.io_addr dd ?
258	.pci_bus dd ?	258	.pci_bus dd ?
259	.pci_dev dd ?	259	.pci_dev dd ?
260	.irq_line db ?	260	.irq_line db ?
261		261
262	rb 256-(($ - device) and 255) ; align 256	262	rb 256-(($ - device) and 255) ; align 256
263	.tx_ring rb NUM_TX_DESC * tx_desc.size * 2	263	.tx_ring rb NUM_TX_DESC * tx_desc.size * 2
264		264
265	rb 256-(($ - device) and 255) ; align 256	265	rb 256-(($ - device) and 255) ; align 256
266	.rx_ring rb NUM_RX_DESC * rx_desc.size * 2	266	.rx_ring rb NUM_RX_DESC * rx_desc.size * 2
267		267
268	tpc:	268	tpc:
269	.mmio_addr dd ? ; memory map physical address	269	.mmio_addr dd ? ; memory map physical address
270	.chipset dd ?	270	.chipset dd ?
271	.pcfg dd ?	271	.pcfg dd ?
272	.mcfg dd ?	272	.mcfg dd ?
273	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt	273	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
274	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt	274	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
275	.TxDescArrays dd ? ; Index of Tx Descriptor buffer	275	.TxDescArrays dd ? ; Index of Tx Descriptor buffer
276	.RxDescArrays dd ? ; Index of Rx Descriptor buffer	276	.RxDescArrays dd ? ; Index of Rx Descriptor buffer
277	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer	277	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
278	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer	278	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
279		279
280	device_size = $ - device	280	device_size = $ - device
281		281
282	end virtual	282	end virtual
283		283
284	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK	284	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
285	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E	285	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
286		286
287		287
288	macro udelay msec {	288	macro udelay msec {
289		289
290	push esi	290	push esi
291	mov esi, msec	291	mov esi, msec
292	call Sleep	292	call Sleep
293	pop esi	293	pop esi
294		294
295	}	295	}
296		296
297	macro WRITE_GMII_REG RegAddr, value {	297	macro WRITE_GMII_REG RegAddr, value {
298		298
299	set_io REG_PHYAR	299	set_io REG_PHYAR
300	if value eq ax	300	if value eq ax
301	and eax, 0x0000ffff	301	and eax, 0x0000ffff
302	or eax, 0x80000000 + (RegAddr shl 16)	302	or eax, 0x80000000 + (RegAddr shl 16)
303	else	303	else
304	mov eax, 0x80000000 + (RegAddr shl 16) + value	304	mov eax, 0x80000000 + (RegAddr shl 16) + value
305	end if	305	end if
306	out dx, eax	306	out dx, eax
307		307
308	call PHY_WAIT_WRITE	308	call PHY_WAIT_WRITE
309	}	309	}
310		310
311	macro READ_GMII_REG RegAddr {	311	macro READ_GMII_REG RegAddr {
312		312
313	local .error, .done	313	local .error, .done
314		314
315	set_io REG_PHYAR	315	set_io REG_PHYAR
316	mov eax, RegAddr shl 16	316	mov eax, RegAddr shl 16
317	out dx, eax	317	out dx, eax
318		318
319	call PHY_WAIT_READ	319	call PHY_WAIT_READ
320	jz .error	320	jz .error
321		321
322	in eax, dx	322	in eax, dx
323	and eax, 0xFFFF	323	and eax, 0xFFFF
324	jmp .done	324	jmp .done
325		325
326	.error:	326	.error:
327	or eax, -1	327	or eax, -1
328	.done:	328	.done:
329	}	329	}
330		330
331	align 4	331	align 4
332	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR	332	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
333		333
334	udelay 1 ;;;1000	334	udelay 1 ;;;1000
335		335
336	push ecx	336	push ecx
337	mov ecx, 2000	337	mov ecx, 2000
338	; Check if the RTL8169 has completed writing/reading to the specified MII register	338	; Check if the RTL8169 has completed writing/reading to the specified MII register
339	@@:	339	@@:
340	in eax, dx	340	in eax, dx
341	test eax, 0x80000000	341	test eax, 0x80000000
342	jnz .exit	342	jnz .exit
343	udelay 1 ;;;100	343	udelay 1 ;;;100
344	loop @b	344	loop @b
345	.exit:	345	.exit:
346	pop ecx	346	pop ecx
347	ret	347	ret
348		348
349	align 4	349	align 4
350	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR	350	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
351		351
352	udelay 1 ;;;1000	352	udelay 1 ;;;1000
353		353
354	push ecx	354	push ecx
355	mov ecx, 2000	355	mov ecx, 2000
356	; Check if the RTL8169 has completed writing/reading to the specified MII register	356	; Check if the RTL8169 has completed writing/reading to the specified MII register
357	@@:	357	@@:
358	in eax, dx	358	in eax, dx
359	test eax, 0x80000000	359	test eax, 0x80000000
360	jz .exit	360	jz .exit
361	udelay 1 ;;;100	361	udelay 1 ;;;100
362	loop @b	362	loop @b
363	.exit:	363	.exit:
364	pop ecx	364	pop ecx
365	ret	365	ret
366		366
367		367
368		368
369	section '.flat' code readable align 16	369	section '.flat' code readable align 16
370		370
371	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	371	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
372	;; ;;	372	;; ;;
373	;; proc START ;;	373	;; proc START ;;
374	;; ;;	374	;; ;;
375	;; (standard driver proc) ;;	375	;; (standard driver proc) ;;
376	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	376	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
377		377
378	align 4	378	align 4
379	proc START stdcall, state:dword	379	proc START stdcall, state:dword
380		380
381	cmp [state], 1	381	cmp [state], 1
382	jne .exit	382	jne .exit
383		383
384	.entry:	384	.entry:
385		385
386	DEBUGF 2,"Loading %s driver\n", my_service	386	DEBUGF 2,"Loading %s driver\n", my_service
387	stdcall RegService, my_service, service_proc	387	stdcall RegService, my_service, service_proc
388	ret	388	ret
389		389
390	.fail:	390	.fail:
391	.exit:	391	.exit:
392	xor eax, eax	392	xor eax, eax
393	ret	393	ret
394		394
395	endp	395	endp
396		396
397		397
398	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	398	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
399	;; ;;	399	;; ;;
400	;; proc SERVICE_PROC ;;	400	;; proc SERVICE_PROC ;;
401	;; ;;	401	;; ;;
402	;; (standard driver proc) ;;	402	;; (standard driver proc) ;;
403	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	403	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
404		404
405	align 4	405	align 4
406	proc service_proc stdcall, ioctl:dword	406	proc service_proc stdcall, ioctl:dword
407		407
408	mov edx, [ioctl]	408	mov edx, [ioctl]
409	mov eax, [IOCTL.io_code]	409	mov eax, [edx + IOCTL.io_code]
410		410
411	;------------------------------------------------------	411	;------------------------------------------------------
412		412
413	cmp eax, 0 ;SRV_GETVERSION	413	cmp eax, 0 ;SRV_GETVERSION
414	jne @F	414	jne @F
415		415
416	cmp [IOCTL.out_size], 4	416	cmp [edx + IOCTL.out_size], 4
417	jb .fail	417	jb .fail
418	mov eax, [IOCTL.output]	418	mov eax, [edx + IOCTL.output]
419	mov [eax], dword API_VERSION	419	mov [eax], dword API_VERSION
420		420
421	xor eax, eax	421	xor eax, eax
422	ret	422	ret
423		423
424	;------------------------------------------------------	424	;------------------------------------------------------
425	@@:	425	@@:
426	cmp eax, 1 ;SRV_HOOK	426	cmp eax, 1 ;SRV_HOOK
427	jne .fail	427	jne .fail
428		428
429	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	429	cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
430	jb .fail	430	jb .fail
431		431
432	mov eax, [IOCTL.input]	432	mov eax, [edx + IOCTL.input]
433	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given	433	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
434	jne .fail ; other types arent supported for this card yet	434	jne .fail ; other types arent supported for this card yet
435		435
436	; check if the device is already listed	436	; check if the device is already listed
437		437
438	mov esi, device_list	438	mov esi, device_list
439	mov ecx, [devices]	439	mov ecx, [devices]
440	test ecx, ecx	440	test ecx, ecx
441	jz .firstdevice	441	jz .firstdevice
442		442
443	; mov eax, [IOCTL.input] ; get the pci bus and device numbers	443	; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
444	mov ax , [eax+1] ;	444	mov ax, [eax+1] ;
445	.nextdevice:	445	.nextdevice:
446	mov ebx, [esi]	446	mov ebx, [esi]
447	cmp al, byte[device.pci_bus]	447	cmp al, byte[device.pci_bus]
448	jne @f	448	jne @f
449	cmp ah, byte[device.pci_dev]	449	cmp ah, byte[device.pci_dev]
450	je .find_devicenum ; Device is already loaded, let's find it's device number	450	je .find_devicenum ; Device is already loaded, let's find it's device number
451	@@:	451	@@:
452	add esi, 4	452	add esi, 4
453	loop .nextdevice	453	loop .nextdevice
454		454
455		455
456	; This device doesnt have its own eth_device structure yet, lets create one	456	; This device doesnt have its own eth_device structure yet, lets create one
457	.firstdevice:	457	.firstdevice:
458	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	458	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
459	jae .fail	459	jae .fail
460		460
461	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in	461	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in
462		462
463	; Fill in the direct call addresses into the struct	463	; Fill in the direct call addresses into the struct
464		464
465	mov [device.reset], reset	465	mov [device.reset], reset
466	mov [device.transmit], transmit	466	mov [device.transmit], transmit
467	mov [device.unload], unload	467	mov [device.unload], unload
468	mov [device.name], my_service	468	mov [device.name], my_service
469		469
470	; save the pci bus and device numbers	470	; save the pci bus and device numbers
471		471
472	mov eax, [IOCTL.input]	472	mov eax, [edx + IOCTL.input]
473	movzx ecx, byte[eax+1]	473	movzx ecx, byte[eax+1]
474	mov [device.pci_bus], ecx	474	mov [device.pci_bus], ecx
475	movzx ecx, byte[eax+2]	475	movzx ecx, byte[eax+2]
476	mov [device.pci_dev], ecx	476	mov [device.pci_dev], ecx
477		477
478	; Now, it's time to find the base io addres of the PCI device	478	; Now, it's time to find the base io addres of the PCI device
479		479
480	PCI_find_io	480	PCI_find_io
481	mov [tpc.mmio_addr], eax ; CHECKME	481	mov [tpc.mmio_addr], eax ; CHECKME
482		482
483	; We've found the io address, find IRQ now	483	; We've found the io address, find IRQ now
484		484
485	PCI_find_irq	485	PCI_find_irq
486		486
487	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	487	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
488	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8	488	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
489		489
490	; Ok, the eth_device structure is ready, let's probe the device	490	; Ok, the eth_device structure is ready, let's probe the device
491	; Because initialization fires IRQ, IRQ handler must be aware of this device	491	; Because initialization fires IRQ, IRQ handler must be aware of this device
492	mov eax, [devices] ; Add the device structure to our device list	492	mov eax, [devices] ; Add the device structure to our device list
493	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)	493	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
494	inc [devices] ;	494	inc [devices] ;
495		495
496	call probe ; this function will output in eax	496	call probe ; this function will output in eax
497	test eax, eax	497	test eax, eax
498	jnz .err2 ; If an error occured, exit	498	jnz .err2 ; If an error occured, exit
499		499
500	mov [device.type], NET_TYPE_ETH	500	mov [device.type], NET_TYPE_ETH

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(root)/drivers/ethernet/RTL8169.asm – Rev 4467 → 4470