WebSVN – Kolibri OS – Diff – /drivers/ethernet/RTL8169.asm


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2013. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;  RTL8169 driver for KolibriOS                                   ;;
;;                                                                 ;;
;;  Copyright 2007 mike.dld,                                       ;;
;;   mike.dld@gmail.com                                            ;;
;;                                                                 ;;
;; port to net branch by hidnplayr                                 ;;
;;                                                                 ;;
;;  References:                                                    ;;
;;    r8169.c - linux driver (etherboot project)                   ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
format MS COFF
 
        API_VERSION             = 0x01000100
        DRIVER_VERSION          = 5
 
        MAX_DEVICES             = 16
 
        DEBUG                   = 1
        __DEBUG__               = 1
        __DEBUG_LEVEL__         = 2
 
        NUM_TX_DESC             = 4
        NUM_RX_DESC             = 4
 
include '../proc32.inc'
include '../imports.inc'
include '../fdo.inc'
include '../netdrv.inc'
 
public START
public service_proc
public version
 
 
        REG_MAC0                = 0x0 ; Ethernet hardware address
        REG_MAR0                = 0x8 ; Multicast filter
        REG_TxDescStartAddr     = 0x20
        REG_TxHDescStartAddr    = 0x28
        REG_FLASH               = 0x30
        REG_ERSR                = 0x36
        REG_ChipCmd             = 0x37
        REG_TxPoll              = 0x38
        REG_IntrMask            = 0x3C
        REG_IntrStatus          = 0x3E
        REG_TxConfig            = 0x40
        REG_RxConfig            = 0x44
        REG_RxMissed            = 0x4C
        REG_Cfg9346             = 0x50
        REG_Config0             = 0x51
        REG_Config1             = 0x52
        REG_Config2             = 0x53
        REG_Config3             = 0x54
        REG_Config4             = 0x55
        REG_Config5             = 0x56
        REG_MultiIntr           = 0x5C
        REG_PHYAR               = 0x60
        REG_TBICSR              = 0x64
        REG_TBI_ANAR            = 0x68
        REG_TBI_LPAR            = 0x6A
        REG_PHYstatus           = 0x6C
        REG_RxMaxSize           = 0xDA
        REG_CPlusCmd            = 0xE0
        REG_RxDescStartAddr     = 0xE4
        REG_ETThReg             = 0xEC
        REG_FuncEvent           = 0xF0
        REG_FuncEventMask       = 0xF4
        REG_FuncPresetState     = 0xF8
        REG_FuncForceEvent      = 0xFC
 
        ; InterruptStatusBits
        ISB_SYSErr              = 0x8000
        ISB_PCSTimeout          = 0x4000
        ISB_SWInt               = 0x0100
        ISB_TxDescUnavail       = 0x80
        ISB_RxFIFOOver          = 0x40
        ISB_LinkChg             = 0x20
        ISB_RxOverflow          = 0x10
        ISB_TxErr               = 0x08
        ISB_TxOK                = 0x04
        ISB_RxErr               = 0x02
        ISB_RxOK                = 0x01
 
        ; RxStatusDesc
        SD_RxRES                = 0x00200000
        SD_RxCRC                = 0x00080000
        SD_RxRUNT               = 0x00100000
        SD_RxRWT                = 0x00400000
 
        ; ChipCmdBits
        CMD_Reset               = 0x10
        CMD_RxEnb               = 0x08
        CMD_TxEnb               = 0x04
        CMD_RxBufEmpty          = 0x01
 
        ; Cfg9346Bits
        CFG_9346_Lock           = 0x00
        CFG_9346_Unlock         = 0xC0
 
        ; rx_mode_bits
        RXM_AcceptErr           = 0x20
        RXM_AcceptRunt          = 0x10
        RXM_AcceptBroadcast     = 0x08
        RXM_AcceptMulticast     = 0x04
        RXM_AcceptMyPhys        = 0x02
        RXM_AcceptAllPhys       = 0x01
 
        ; RxConfigBits
        RXC_FIFOShift           = 13
        RXC_DMAShift            = 8
 
        ; TxConfigBits
        TXC_InterFrameGapShift  = 24
        TXC_DMAShift            = 8    ; DMA burst value (0-7) is shift this many bits
 
        ; PHYstatus
        PHYS_TBI_Enable         = 0x80
        PHYS_TxFlowCtrl         = 0x40
        PHYS_RxFlowCtrl         = 0x20
        PHYS_1000bpsF           = 0x10
        PHYS_100bps             = 0x08
        PHYS_10bps              = 0x04
        PHYS_LinkStatus         = 0x02
        PHYS_FullDup            = 0x01
 
        ; GIGABIT_PHY_registers
        PHY_CTRL_REG            = 0
        PHY_STAT_REG            = 1
        PHY_AUTO_NEGO_REG       = 4
        PHY_1000_CTRL_REG       = 9
 
        ; GIGABIT_PHY_REG_BIT
        PHY_Restart_Auto_Nego   = 0x0200
        PHY_Enable_Auto_Nego    = 0x1000
 
        ; PHY_STAT_REG = 1
        PHY_Auto_Neco_Comp      = 0x0020
 
        ; PHY_AUTO_NEGO_REG = 4
        PHY_Cap_10_Half         = 0x0020
        PHY_Cap_10_Full         = 0x0040
        PHY_Cap_100_Half        = 0x0080
        PHY_Cap_100_Full        = 0x0100
 
        ; PHY_1000_CTRL_REG = 9
        PHY_Cap_1000_Full       = 0x0200
        PHY_Cap_1000_Half       = 0x0100
 
        PHY_Cap_PAUSE           = 0x0400
        PHY_Cap_ASYM_PAUSE      = 0x0800
 
        PHY_Cap_Null            = 0x0
 
        ; _MediaType
        MT_10_Half              = 0x01
        MT_10_Full              = 0x02
        MT_100_Half             = 0x04
        MT_100_Full             = 0x08
        MT_1000_Full            = 0x10
 
        ; _TBICSRBit
        TBI_LinkOK              = 0x02000000
 
        ; _DescStatusBit
        DSB_OWNbit              = 0x80000000
        DSB_EORbit              = 0x40000000
        DSB_FSbit               = 0x20000000
        DSB_LSbit               = 0x10000000
 
        RX_BUF_SIZE             = 1536          ; Rx Buffer size
 
; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
        MAX_ETH_FRAME_SIZE      = 1536
 
        TX_FIFO_THRESH          = 256           ; In bytes
 
        RX_FIFO_THRESH          = 7             ; 7 means NO threshold, Rx buffer level before first PCI xfer
        RX_DMA_BURST            = 7             ; Maximum PCI burst, '6' is 1024
        TX_DMA_BURST            = 7             ; Maximum PCI burst, '6' is 1024
        ETTh                    = 0x3F          ; 0x3F means NO threshold
 
        EarlyTxThld             = 0x3F          ; 0x3F means NO early transmit
        RxPacketMaxSize         = 0x0800        ; Maximum size supported is 16K-1
        InterFrameGap           = 0x03          ; 3 means InterFrameGap = the shortest one
 
        HZ                      = 1000
 
        RTL_MIN_IO_SIZE         = 0x80
        TX_TIMEOUT              = (6*HZ)
 
        TIMER_EXPIRE_TIME       = 100
 
        ETH_HDR_LEN             = 14
        DEFAULT_MTU             = 1500
        DEFAULT_RX_BUF_LEN      = 1536
 
 
;ifdef   JUMBO_FRAME_SUPPORT
;        MAX_JUMBO_FRAME_MTU     = 10000
;        MAX_RX_SKBDATA_SIZE     = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
;else
        MAX_RX_SKBDATA_SIZE     = 1600
;end if
 
        MCFG_METHOD_01          = 0x01
        MCFG_METHOD_02          = 0x02
        MCFG_METHOD_03          = 0x03
        MCFG_METHOD_04          = 0x04
        MCFG_METHOD_05          = 0x05
        MCFG_METHOD_11          = 0x0b
        MCFG_METHOD_12          = 0x0c
        MCFG_METHOD_13          = 0x0d
        MCFG_METHOD_14          = 0x0e
        MCFG_METHOD_15          = 0x0f
 
        PCFG_METHOD_1           = 0x01          ; PHY Reg 0x03 bit0-3 == 0x0000
        PCFG_METHOD_2           = 0x02          ; PHY Reg 0x03 bit0-3 == 0x0001
        PCFG_METHOD_3           = 0x03          ; PHY Reg 0x03 bit0-3 == 0x0002
 
virtual at 0
  tx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb    (NUM_TX_DESC-1)*tx_desc.size
  .buf_soft_addr        dd ?
end virtual
 
virtual at 0
  rx_desc:
  .status    dd ?
  .vlan_tag  dd ?
  .buf_addr  dq ?
  .size = $
  rb    (NUM_RX_DESC-1)*rx_desc.size
  .buf_soft_addr        dd ?
end virtual
 
virtual at ebx
 
        device:
 
        ETH_DEVICE
 
        .io_addr        dd ?
        .pci_bus        dd ?
        .pci_dev        dd ?
        .irq_line       db ?
 
        rb 256-(($ - device) and 255)              ;        align 256
        .tx_ring rb NUM_TX_DESC * tx_desc.size * 2
 
        rb 256-(($ - device) and 255)              ;        align 256
        .rx_ring rb NUM_RX_DESC * rx_desc.size * 2
 
        tpc:
        .mmio_addr      dd ? ; memory map physical address
        .chipset        dd ?
        .pcfg           dd ?
        .mcfg           dd ?
        .cur_rx         dd ? ; Index into the Rx descriptor buffer of next Rx pkt
        .cur_tx         dd ? ; Index into the Tx descriptor buffer of next Rx pkt
        .TxDescArrays   dd ? ; Index of Tx Descriptor buffer
        .RxDescArrays   dd ? ; Index of Rx Descriptor buffer
        .TxDescArray    dd ? ; Index of 256-alignment Tx Descriptor buffer
        .RxDescArray    dd ? ; Index of 256-alignment Rx Descriptor buffer
 
        device_size = $ - device
 
end virtual
 
        intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
        rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
 
 
macro   udelay msec {
 
        push    esi
        mov     esi, msec
        call    Sleep
        pop     esi
 
}
 
macro   WRITE_GMII_REG  RegAddr, value {
 
        set_io  REG_PHYAR
        if      value eq ax
        and     eax, 0x0000ffff
        or      eax, 0x80000000 + (RegAddr shl 16)
        else
        mov     eax, 0x80000000 + (RegAddr shl 16) + value
        end if
        out     dx, eax
 
        call    PHY_WAIT_WRITE
}
 
macro   READ_GMII_REG  RegAddr {
 
local   .error, .done
 
        set_io  REG_PHYAR
        mov     eax, RegAddr shl 16
        out     dx, eax
 
        call    PHY_WAIT_READ
        jz      .error
 
        in      eax, dx
        and     eax, 0xFFFF
        jmp     .done
 
  .error:
        or      eax, -1
  .done:
}
 
align 4
PHY_WAIT_READ:       ; io addr must already be set to REG_PHYAR
 
        udelay  1        ;;;1000
 
        push    ecx
        mov     ecx, 2000
        ; Check if the RTL8169 has completed writing/reading to the specified MII register
    @@:
        in      eax, dx
        test    eax, 0x80000000
        jnz     .exit
        udelay  1        ;;;100
        loop    @b
  .exit:
        pop     ecx
        ret
 
align 4
PHY_WAIT_WRITE:       ; io addr must already be set to REG_PHYAR
 
        udelay  1        ;;;1000
 
        push    ecx
        mov     ecx, 2000
        ; Check if the RTL8169 has completed writing/reading to the specified MII register
    @@:
        in      eax, dx
        test    eax, 0x80000000
        jz      .exit
        udelay  1        ;;;100
        loop    @b
  .exit:
        pop     ecx
        ret
 
 
 
section '.flat' code readable align 16
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc START             ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc START stdcall, state:dword
 
        cmp [state], 1
        jne .exit
 
  .entry:
 
        DEBUGF  2,"Loading %s driver\n", my_service
        stdcall RegService, my_service, service_proc
        ret
 
  .fail:
  .exit:
        xor eax, eax
        ret
 
endp
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                        ;;
;; proc SERVICE_PROC      ;;
;;                        ;;
;; (standard driver proc) ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
proc service_proc stdcall, ioctl:dword
 
        mov     edx, [ioctl]
        mov     eax, [IOCTL.io_code]
 
;------------------------------------------------------
 
        cmp     eax, 0 ;SRV_GETVERSION
        jne     @F
 
        cmp     [IOCTL.out_size], 4
        jb      .fail
        mov     eax, [IOCTL.output]
        mov     [eax], dword API_VERSION
 
        xor     eax, eax
        ret
 
;------------------------------------------------------
  @@:
        cmp     eax, 1 ;SRV_HOOK
        jne     .fail
 
        cmp     [IOCTL.inp_size], 3                     ; Data input must be at least 3 bytes
        jb      .fail
 
        mov     eax, [IOCTL.input]
        cmp     byte [eax], 1                           ; 1 means device number and bus number (pci) are given
        jne     .fail                                   ; other types arent supported for this card yet
 
; check if the device is already listed
 
        mov     esi, device_list
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .firstdevice
 
;        mov     eax, [IOCTL.input]                     ; get the pci bus and device numbers
        mov     ax , [eax+1]                            ;
  .nextdevice:
        mov     ebx, [esi]
        cmp     al, byte[device.pci_bus]
        jne     @f
        cmp     ah, byte[device.pci_dev]
        je      .find_devicenum                         ; Device is already loaded, let's find it's device number
       @@:
        add     esi, 4
        loop    .nextdevice
 
 
; This device doesnt have its own eth_device structure yet, lets create one
  .firstdevice:
        cmp     [devices], MAX_DEVICES                  ; First check if the driver can handle one more card
        jae     .fail
 
        allocate_and_clear ebx, device_size, .fail      ; Allocate memory to put the device structure in
 
; Fill in the direct call addresses into the struct
 
        mov     [device.reset], reset
        mov     [device.transmit], transmit
        mov     [device.unload], unload
        mov     [device.name], my_service
 
; save the pci bus and device numbers
 
        mov     eax, [IOCTL.input]
        movzx   ecx, byte[eax+1]
        mov     [device.pci_bus], ecx
        movzx   ecx, byte[eax+2]
        mov     [device.pci_dev], ecx
 
; Now, it's time to find the base io addres of the PCI device
 
        PCI_find_io
        mov     [tpc.mmio_addr], eax    ; CHECKME
 
; We've found the io address, find IRQ now
 
        PCI_find_irq
 
        DEBUGF  2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
        [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
 
; Ok, the eth_device structure is ready, let's probe the device
; Because initialization fires IRQ, IRQ handler must be aware of this device
        mov     eax, [devices]                                          ; Add the device structure to our device list
        mov     [device_list + 4*eax], ebx                              ; (IRQ handler uses this list to find device)
        inc     [devices]                                               ;
 
        call    probe                                                   ; this function will output in eax
        test    eax, eax
        jnz     .err2                                                   ; If an error occured, exit
 
        mov     [device.type], NET_TYPE_ETH
        call    NetRegDev
 
        cmp     eax, -1
        je      .destroy
 
        ret
 
; If the device was already loaded, find the device number and return it in eax
 
  .find_devicenum:
        DEBUGF  2,"Trying to find device number of already registered device\n"
        call    NetPtrToNum                                             ; This kernel procedure converts a pointer to device struct in ebx
                                                                        ; into a device number in edi
        mov     eax, edi                                                ; Application wants it in eax instead
        DEBUGF  2,"Kernel says: %u\n", eax
        ret
 
; If an error occured, remove all allocated data and exit (returning -1 in eax)
 
  .destroy:
        ; todo: reset device into virgin state
 
  .err2:
        dec     [devices]
  .err:
        DEBUGF  2,"removing device structure\n"
        stdcall KernelFree, ebx
  .fail:
        or      eax, -1
        ret
 
;------------------------------------------------------
endp
 
 
align 4
unload:
 
        ret
 
 
align 4
init_board:
 
        DEBUGF  1,"init_board\n"
 
        PCI_make_bus_master
 
        ; Soft reset the chip
        set_io  0
        set_io  REG_ChipCmd
        mov     al, CMD_Reset
        out     dx, al
 
        ; Check that the chip has finished the reset
        mov     ecx, 1000
        set_io  REG_ChipCmd
    @@: in      al, dx
        test    al, CMD_Reset
        jz      @f
        udelay  10
        loop    @b
    @@:
        ; identify config method
        set_io  REG_TxConfig
        in      eax, dx
        and     eax, 0x7c800000
        DEBUGF  1,"init_board: TxConfig & 0x7c800000 = 0x%x\n", eax
        mov     esi, mac_info-8
    @@: add     esi, 8
        mov     ecx, eax
        and     ecx, [esi]
        cmp     ecx, [esi]
        jne     @b
        mov     eax, [esi+4]
        mov     [tpc.mcfg], eax
 
        mov     [tpc.pcfg], PCFG_METHOD_3
        READ_GMII_REG 3
        and     al, 0x0f
        or      al, al
        jnz     @f
        mov     [tpc.pcfg], PCFG_METHOD_1
        jmp     .pconf
    @@: dec     al
        jnz     .pconf
        mov     [tpc.pcfg], PCFG_METHOD_2
  .pconf:
 
        ; identify chip attached to board
        mov     ecx, 10
        mov     eax, [tpc.mcfg]
    @@: dec     ecx
        js      @f
        cmp     eax, [rtl_chip_info + ecx*8]
        jne     @b
        mov     [tpc.chipset], ecx
        jmp     .match
    @@:
        ; if unknown chip, assume array element #0, original RTL-8169 in this case
        DEBUGF  1,"init_board: PCI device: unknown chip version, assuming RTL-8169\n"
        set_io  REG_TxConfig
        in      eax, dx
        DEBUGF  1,"init_board: PCI device: TxConfig = 0x%x\n", eax
 
        mov     [tpc.chipset],  0
 
        xor     eax, eax
        inc     eax
        ret
 
  .match:
        DEBUGF  1,"init_board: chipset=%u\n", ecx
        xor     eax,eax
        ret
 
 
 
;***************************************************************************
;   Function
;      probe
;   Description
;      Searches for an ethernet card, enables it and clears the rx buffer
;      If a card was found, it enables the ethernet -> TCPIP link
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
probe:
 
        DEBUGF  1,"probe\n"
 
        call    init_board
        call    read_mac
        call    PHY_config
 
;       DEBUGF  1,"K :   Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
        set_io  0
        set_io  0x82
        mov     al, 0x01
        out     dx, al
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jae     @f
;       DEBUGF  1,"K :   Set PCI Latency=0x40\n"
;       stdcall pci_write_config_byte,PCI_LATENCY_TIMER,0x40
   @@:
        cmp     [tpc.mcfg], MCFG_METHOD_02
        jne     @f
;       DEBUGF  1,"K :   Set MAC Reg C+CR Offset 0x82h = 0x01h\n"
        set_io  0x82
        mov     al, 0x01
        out     dx, al
;       DEBUGF  1,"K :   Set PHY Reg 0x0bh = 0x00h\n"
        WRITE_GMII_REG 0x0b, 0x0000      ; w 0x0b 15 0 0
    @@:
        ; if TBI is not enabled
        set_io  0
        set_io  REG_PHYstatus
        in      al, dx
        test    al, PHYS_TBI_Enable
        jz      .tbi_dis
        READ_GMII_REG PHY_AUTO_NEGO_REG
 
        ; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
        and     eax, 0x0C1F
        or      eax, PHY_Cap_10_Half or PHY_Cap_10_Full or PHY_Cap_100_Half or PHY_Cap_100_Full
        WRITE_GMII_REG PHY_AUTO_NEGO_REG, ax
 
        ; enable 1000 Full Mode
        WRITE_GMII_REG PHY_1000_CTRL_REG, PHY_Cap_1000_Full or PHY_Cap_1000_Half ; rtl8168
 
        ; Enable auto-negotiation and restart auto-nigotiation
        WRITE_GMII_REG PHY_CTRL_REG, PHY_Enable_Auto_Nego or PHY_Restart_Auto_Nego
 
        udelay  100
        mov     ecx, 10000
        ; wait for auto-negotiation process
    @@: dec     ecx
        jz      @f
        set_io  0
        READ_GMII_REG PHY_STAT_REG
        udelay  100
        test    eax, PHY_Auto_Neco_Comp
        jz      @b
        set_io  REG_PHYstatus
        in      al, dx
        jmp     @f
  .tbi_dis:
        udelay  100
    @@:
 
 
;***************************************************************************
;   Function
;      rt8169_reset
;   Description
;      Place the chip (ie, the ethernet card) into a virgin state
;   Destroyed registers
;      eax, ebx, ecx, edx
;
;***************************************************************************
align 4
reset:
 
        DEBUGF  1,"reset\n"
 
        lea     eax, [device.tx_ring]
        mov     [tpc.TxDescArrays], eax
        mov     [tpc.TxDescArray], eax
 
        lea     eax, [device.rx_ring]
        mov     [tpc.RxDescArrays], eax
        mov     [tpc.RxDescArray], eax
 
        call    init_ring
        call    hw_start
 
; clear packet/byte counters
 
        xor     eax, eax
        lea     edi, [device.bytes_tx]
        mov     ecx, 6
        rep     stosd
 
        mov     [device.mtu], 1500
 
; Set link state to unknown
        mov     [device.state], ETH_LINK_UNKOWN
 
        xor     eax, eax
        ret
 
 
 
 
 
align 4
PHY_config:
 
        DEBUGF  1,"hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n",[tpc.mcfg],[tpc.pcfg]
 
        cmp     [tpc.mcfg], MCFG_METHOD_04
        jne     .not_4
        set_io  0
;       WRITE_GMII_REG 0x1F, 0x0001
;       WRITE_GMII_REG 0x1b, 0x841e
;       WRITE_GMII_REG 0x0e, 0x7bfb
;       WRITE_GMII_REG 0x09, 0x273a
        WRITE_GMII_REG 0x1F, 0x0002
        WRITE_GMII_REG 0x01, 0x90D0
        WRITE_GMII_REG 0x1F, 0x0000
        jmp     .exit
  .not_4:
        cmp     [tpc.mcfg], MCFG_METHOD_02
        je      @f
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jne     .not_2_or_3
    @@:
        set_io  0
        WRITE_GMII_REG 0x1F, 0x0001
        WRITE_GMII_REG 0x15, 0x1000
        WRITE_GMII_REG 0x18, 0x65C7
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x03, 0x00A1
        WRITE_GMII_REG 0x02, 0x0008
        WRITE_GMII_REG 0x01, 0x1020
        WRITE_GMII_REG 0x00, 0x1000
        WRITE_GMII_REG 0x04, 0x0800
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x04, 0x7000
        WRITE_GMII_REG 0x03, 0xFF41
        WRITE_GMII_REG 0x02, 0xDE60
        WRITE_GMII_REG 0x01, 0x0140
        WRITE_GMII_REG 0x00, 0x0077
        WRITE_GMII_REG 0x04, 0x7800
        WRITE_GMII_REG 0x04, 0x7000
        WRITE_GMII_REG 0x04, 0xA000
        WRITE_GMII_REG 0x03, 0xDF01
        WRITE_GMII_REG 0x02, 0xDF20
        WRITE_GMII_REG 0x01, 0xFF95
        WRITE_GMII_REG 0x00, 0xFA00
        WRITE_GMII_REG 0x04, 0xA800
        WRITE_GMII_REG 0x04, 0xA000
        WRITE_GMII_REG 0x04, 0xB000
        WRITE_GMII_REG 0x03, 0xFF41
        WRITE_GMII_REG 0x02, 0xDE20
        WRITE_GMII_REG 0x01, 0x0140
        WRITE_GMII_REG 0x00, 0x00BB
        WRITE_GMII_REG 0x04, 0xB800
        WRITE_GMII_REG 0x04, 0xB000
        WRITE_GMII_REG 0x04, 0xF000
        WRITE_GMII_REG 0x03, 0xDF01
        WRITE_GMII_REG 0x02, 0xDF20
        WRITE_GMII_REG 0x01, 0xFF95
        WRITE_GMII_REG 0x00, 0xBF00
        WRITE_GMII_REG 0x04, 0xF800
        WRITE_GMII_REG 0x04, 0xF000
        WRITE_GMII_REG 0x04, 0x0000
        WRITE_GMII_REG 0x1F, 0x0000
        WRITE_GMII_REG 0x0B, 0x0000
        jmp     .exit
  .not_2_or_3:
        DEBUGF  1,"tpc.mcfg=%d, discard hw PHY config\n", [tpc.mcfg]
  .exit:
        ret
 
 
 
align 4
set_rx_mode:
 
        DEBUGF  1,"set_rx_mode\n"
 
        ; IFF_ALLMULTI
        ; Too many to filter perfectly -- accept all multicasts
        set_io  0
        set_io  REG_RxConfig
        in      eax, dx
        mov     ecx, [tpc.chipset]
        and     eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
        or      eax, rx_config or (RXM_AcceptBroadcast or RXM_AcceptMulticast or RXM_AcceptMyPhys)
        out     dx, eax
 
        ; Multicast hash filter
        set_io  REG_MAR0 + 0
        or      eax, -1
        out     dx, eax
        set_io  REG_MAR0 + 4
        out     dx, eax
 
        ret
 
 
align 4
init_ring:
 
        DEBUGF  1,"init_ring\n"
 
        xor     eax, eax
        mov     [tpc.cur_rx], eax
        mov     [tpc.cur_tx], eax
 
        lea     edi, [device.tx_ring]
        mov     ecx, (NUM_TX_DESC * tx_desc.size) / 4
        rep     stosd
 
        lea     edi, [device.rx_ring]
        mov     ecx, (NUM_RX_DESC * rx_desc.size) / 4
        rep     stosd
 
        mov     edi, [tpc.RxDescArray]
        mov     ecx, NUM_RX_DESC
  .loop:
        push    ecx
        stdcall KernelAlloc, RX_BUF_SIZE
        mov     [edi + rx_desc.buf_soft_addr], eax
        call    GetPgAddr
        mov     dword [edi + rx_desc.buf_addr], eax
        mov     [edi + rx_desc.status], DSB_OWNbit or RX_BUF_SIZE
        add     edi, rx_desc.size
        pop     ecx
        loop    .loop
        or      [edi - rx_desc.size + rx_desc.status], DSB_EORbit
 
        ret
 
 
align 4
hw_start:
 
        DEBUGF  1,"hw_start\n"
 
; attach int handler
        movzx   eax, [device.irq_line]
        DEBUGF  1,"Attaching int handler to irq %x\n", eax:1
        stdcall AttachIntHandler, eax, int_handler, dword 0
 
        ; Soft reset the chip
        set_io  0
        set_io  REG_ChipCmd
        mov     al, CMD_Reset
        out     dx, al
 
        DEBUGF  1,"Waiting for chip to reset... "
        ; Check that the chip has finished the reset
        mov     ecx, 1000
        set_io  REG_ChipCmd
    @@: in      al, dx
        test    al, CMD_Reset
        jz      @f
        udelay  10
        loop    @b
    @@:
        DEBUGF  1,"done!\n"
 
        set_io  REG_Cfg9346
        mov     al, CFG_9346_Unlock
        out     dx, al
 
        set_io  REG_ChipCmd
        mov     al, CMD_TxEnb or CMD_RxEnb
        out     dx, al
 
        set_io  REG_ETThReg
        mov     al, ETTh
        out     dx, al
 
        ; For gigabit rtl8169
        set_io  REG_RxMaxSize
        mov     ax, RxPacketMaxSize
        out     dx, ax
 
        ; Set Rx Config register
        set_io  REG_RxConfig
        in      ax, dx
        mov     ecx, [tpc.chipset]
        and     eax, [rtl_chip_info + ecx * 8 + 4] ; RxConfigMask
        or      eax, rx_config
        out     dx, eax
 
        ; Set DMA burst size and Interframe Gap Time
        set_io  REG_TxConfig
        mov     eax, (TX_DMA_BURST shl TXC_DMAShift) or (InterFrameGap shl TXC_InterFrameGapShift)
        out     dx, eax
 
        set_io  REG_CPlusCmd
        in      ax, dx
        out     dx, ax
 
        in      ax, dx
        or      ax, 1 shl 3
        cmp     [tpc.mcfg], MCFG_METHOD_02
        jne     @f
        cmp     [tpc.mcfg], MCFG_METHOD_03
        jne     @f
        or      ax,1 shl 14
        DEBUGF  1,"Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n"
        jmp     .set
    @@:
        DEBUGF  1,"Set MAC Reg C+CR Offset 0xE0: bit-3\n"
  .set:
        set_io  REG_CPlusCmd
        out     dx, ax
 
        set_io  0xE2
;        mov     ax, 0x1517
;        out     dx, ax
;        mov     ax, 0x152a
;        out     dx, ax
;        mov     ax, 0x282a
;        out     dx, ax
        xor     ax, ax
        out     dx, ax
 
        xor     eax, eax
        mov     [tpc.cur_rx], eax
        lea     eax, [device.tx_ring]
        GetRealAddr
        set_io  REG_TxDescStartAddr
        out     dx, eax
        set_io  REG_TxDescStartAddr + 4
        xor     eax, eax
        out     dx, eax
 
        lea     eax, [device.rx_ring]
        GetRealAddr
        set_io  REG_RxDescStartAddr
        out     dx, eax
        xor     eax, eax
        set_io  REG_RxDescStartAddr + 4
        out     dx, eax
 
        set_io  REG_Cfg9346
        mov     al, CFG_9346_Lock
        out     dx, al
 
        udelay  10
 
        xor     eax, eax
        set_io  REG_RxMissed
        out     dx, eax
 
        call    set_rx_mode
 
        set_io  0
        ; no early-rx interrupts
        set_io  REG_MultiIntr
        in      ax, dx
        and     ax, 0xF000
        out     dx, ax
 
        ; set interrupt mask
        set_io  REG_IntrMask
        mov     ax, intr_mask
        out     dx, ax
 
        xor     eax, eax
        ret
 
 
align 4
read_mac:
 
        set_io  0
        set_io  REG_MAC0
        xor     ecx, ecx
        lea     edi, [device.mac]
        mov     ecx, 6
 
        ; Get MAC address. FIXME: read EEPROM
    @@: in      al, dx
        stosb
        inc     edx
        loop    @r
 
        DEBUGF  1,"MAC = %x-%x-%x-%x-%x-%x\n",\
        [device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2
 
        ret
 
align 4
write_mac:
 
        ret     6
 
 
 
 
 
;***************************************************************************
;   Function
;      transmit
;   Description
;      Transmits a packet of data via the ethernet card
;
;   Destroyed registers
;      eax, edx, esi, edi
;
;***************************************************************************
align 4
transmit:
 
        DEBUGF  1,"Transmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
        mov     eax, [esp+4]
        DEBUGF  1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
        [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
        [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
        [eax+13]:2,[eax+12]:2
 
        cmp     dword [esp+8], MAX_ETH_FRAME_SIZE
        ja      .fail
 
;----------------------------------
; Find currentTX descriptor address
 
        mov     eax, tx_desc.size
        mul     [tpc.cur_tx]
        lea     esi, [eax + device.tx_ring]
 
        DEBUGF  1,"Using TX desc: %x\n", esi
 
;---------------------------
; Program the packet pointer
 
        mov     eax, [esp + 4]
        mov     [esi + tx_desc.buf_soft_addr], eax
        GetRealAddr
        mov     dword [esi + tx_desc.buf_addr], eax
 
;------------------------
; Program the packet size
 
        mov     eax, [esp + 8]
    @@: or      eax, DSB_OWNbit or DSB_FSbit or DSB_LSbit
        cmp     [tpc.cur_tx], NUM_TX_DESC - 1
        jne     @f
        or      eax, DSB_EORbit
    @@: mov     [esi + tx_desc.status], eax
 
;-----------------------------------------
; Set the polling bit (start transmission)
 
        set_io  0
        set_io  REG_TxPoll
        mov     al, 0x40     ; set polling bit
        out     dx, al
 
;-----------------------
; Update TX descriptor
 
        inc     [tpc.cur_tx]
        and     [tpc.cur_tx], NUM_TX_DESC - 1
 
;-------------
; Update stats
 
        inc     [device.packets_tx]
        mov     eax, [esp + 8]
        add     dword [device.bytes_tx], eax
        adc     dword [device.bytes_tx + 4], 0
 
        xor     eax, eax
        ret     8
 
  .fail:
        DEBUGF  1,"transmit failed\n"
        or      eax, -1
        stdcall KernelFree, [esp+4]
        ret     8
 
 
;;;DSB_OWNbit
 
 
;;;;;;;;;;;;;;;;;;;;;;;
;;                   ;;
;; Interrupt handler ;;
;;                   ;;
;;;;;;;;;;;;;;;;;;;;;;;
 
align 4
int_handler:
 
        push    ebx esi edi
 
        DEBUGF  1,"\n%s int\n", my_service
 
; find pointer of device wich made IRQ occur
 
        mov     ecx, [devices]
        test    ecx, ecx
        jz      .nothing
        mov     esi, device_list
  .nextdevice:
        mov     ebx, [esi]
 
        set_io  0
        set_io  REG_IntrStatus
        in      ax, dx
        test    ax, ax
        jnz     .got_it
  .continue:
        add     esi, 4
        dec     ecx
        jnz     .nextdevice
  .nothing:
        pop     edi esi ebx
        xor     eax, eax
 
        ret                                             ; If no device was found, abort (The irq was probably for a device, not registered to this driver)
 
  .got_it:
 
        DEBUGF  1,"Device: %x Status: %x ", ebx, ax
 
        cmp     ax, 0xFFFF      ; if so, hardware is no longer present
        je      .fail
 
;--------
; Receive
 
        test    ax, ISB_RxOK
        jz      .no_rx
 
        push    ax
        push    ebx
 
  .check_more:
        pop     ebx
        DEBUGF  1,"ebx = 0x%x\n", ebx
        mov     eax, rx_desc.size
        mul     [tpc.cur_rx]
        lea     esi, [eax + device.rx_ring]
 
        DEBUGF  1,"RxDesc.status = 0x%x\n", [esi + rx_desc.status]
 
        mov     eax, [esi + rx_desc.status]
        test    eax, DSB_OWNbit ;;;
        jnz     .rx_return
 
        DEBUGF  1,"tpc.cur_rx = %u\n", [tpc.cur_rx]
 
        test    eax, SD_RxRES
        jnz     .rx_return      ;;;;; RX error!
 
        push    ebx
        push    .check_more
        and     eax, 0x00001FFF
        add     eax, -4                         ; we dont need CRC
        push    eax
        DEBUGF  1,"data length = %u\n", ax
 
;-------------
; Update stats
 
        add     dword [device.bytes_rx], eax
        adc     dword [device.bytes_rx + 4], 0
        inc     dword [device.packets_rx]
 
        push    [esi + rx_desc.buf_soft_addr]
 
;----------------------
; Allocate a new buffer
 
        stdcall KernelAlloc, RX_BUF_SIZE
        mov     [esi + rx_desc.buf_soft_addr], eax
        GetRealAddr
        mov     dword [esi + rx_desc.buf_addr], eax
 
;---------------
; re set OWN bit
 
        mov     eax, DSB_OWNbit or RX_BUF_SIZE
        cmp     [tpc.cur_rx], NUM_RX_DESC - 1
        jne     @f
        or      eax, DSB_EORbit
    @@: mov     [esi + rx_desc.status], eax
 
;--------------
; Update rx ptr
 
        inc     [tpc.cur_rx]
        and     [tpc.cur_rx], NUM_RX_DESC - 1
 
        jmp     Eth_input
  .rx_return:
 
        pop     ax
  .no_rx:
 
;---------
; Transmit
 
        test    ax, ISB_TxOK
        jz      .no_tx
        push    ax
 
        DEBUGF  1,"TX ok!\n"
 
        mov     ecx, NUM_TX_DESC
        lea     esi, [device.tx_ring]
  .txloop:
        cmp     [esi + tx_desc.buf_soft_addr], 0
        jz      .maybenext
 
        test    [esi + tx_desc.status], DSB_OWNbit
        jnz     .maybenext
 
        push    ecx
        DEBUGF  1,"Freeing up TX desc: %x\n", esi
        stdcall KernelFree, [esi + tx_desc.buf_soft_addr]
        pop     ecx
        and     [esi + tx_desc.buf_soft_addr], 0
 
  .maybenext:
        add     esi, tx_desc.size
        dec     ecx
        jnz     .txloop
 
        pop     ax
  .no_tx:
 
;-------
; Finish
 
        set_io  0
        set_io  REG_IntrStatus
        out     dx, ax                  ; ACK all interrupts
 
  .fail:
        pop     edi esi ebx
        xor     eax, eax
        inc     eax
 
        ret
 
 
 
 
 
 
 
 
 
; End of code
align 4                                         ; Place all initialised data here
 
devices       dd 0
version       dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF)
my_service    db 'RTL8169',0                    ; max 16 chars include zero
 
include_debug_strings                           ; All data wich FDO uses will be included here
 
rtl_chip_info dd \
  MCFG_METHOD_01, 0xff7e1880, \ ; RTL8169
  MCFG_METHOD_02, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_03, 0xff7e1880, \ ; RTL8169s/8110s
  MCFG_METHOD_04, 0xff7e1880, \ ; RTL8169sb/8110sb
  MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc
  MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b   // PCI-E
  MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e         // PCI-E 8139
  MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e         // PCI-E 8139
  MCFG_METHOD_15, 0xff7e1880    ; RTL8100e         // PCI-E 8139
 
mac_info dd \
  0x38800000, MCFG_METHOD_15, \
  0x38000000, MCFG_METHOD_12, \
  0x34000000, MCFG_METHOD_13, \
  0x30800000, MCFG_METHOD_14, \
  0x30000000, MCFG_METHOD_11, \
  0x18000000, MCFG_METHOD_05, \
  0x10000000, MCFG_METHOD_04, \
  0x04000000, MCFG_METHOD_03, \
  0x00800000, MCFG_METHOD_02, \
  0x00000000, MCFG_METHOD_01    ; catch-all
 
name_01         db "RTL8169", 0
name_02_03      db "RTL8169s/8110s", 0
name_04         db "RTL8169sb/8110sb", 0
name_05         db "RTL8169sc/8110sc", 0
name_11_12      db "RTL8168b/8111b", 0  ; PCI-E
name_13         db "RTL8101e", 0        ; PCI-E 8139
name_14_15      db "RTL8100e", 0        ; PCI-E 8139
 
 
section '.data' data readable writable align 16 ; place all uninitialized data place here
 
device_list rd MAX_DEVICES                     ; This list contains all pointers to device structures the driver is handling

Rev 3545	Rev 4301
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; RTL8169 driver for KolibriOS ;;	6	;; RTL8169 driver for KolibriOS ;;
7	;; ;;	7	;; ;;
8	;; Copyright 2007 mike.dld, ;;	8	;; Copyright 2007 mike.dld, ;;
9	;; mike.dld@gmail.com ;;	9	;; mike.dld@gmail.com ;;
10	;; ;;	10	;; ;;
11	;; port to net branch by hidnplayr ;;	11	;; port to net branch by hidnplayr ;;
12	;; ;;	12	;; ;;
13	;; References: ;;	13	;; References: ;;
14	;; r8169.c - linux driver (etherboot project) ;;	14	;; r8169.c - linux driver (etherboot project) ;;
15	;; ;;	15	;; ;;
16	;; GNU GENERAL PUBLIC LICENSE ;;	16	;; GNU GENERAL PUBLIC LICENSE ;;
17	;; Version 2, June 1991 ;;	17	;; Version 2, June 1991 ;;
18	;; ;;	18	;; ;;
19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	19	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
20		20
21	format MS COFF	21	format MS COFF
22		22
23	API_VERSION = 0x01000100	23	API_VERSION = 0x01000100
24	DRIVER_VERSION = 5	24	DRIVER_VERSION = 5
25		25
26	MAX_DEVICES = 16	26	MAX_DEVICES = 16
27		27
28	DEBUG = 1	28	DEBUG = 1
29	__DEBUG__ = 1	29	__DEBUG__ = 1
30	__DEBUG_LEVEL__ = 2	30	__DEBUG_LEVEL__ = 2
31		31
32	NUM_TX_DESC = 4	32	NUM_TX_DESC = 4
33	NUM_RX_DESC = 4	33	NUM_RX_DESC = 4
34		34
35	include '../proc32.inc'	35	include '../proc32.inc'
36	include '../imports.inc'	36	include '../imports.inc'
37	include '../fdo.inc'	37	include '../fdo.inc'
38	include '../netdrv.inc'	38	include '../netdrv.inc'
39		39
40	public START	40	public START
41	public service_proc	41	public service_proc
42	public version	42	public version
43		43
44		44
45	REG_MAC0 = 0x0 ; Ethernet hardware address	45	REG_MAC0 = 0x0 ; Ethernet hardware address
46	REG_MAR0 = 0x8 ; Multicast filter	46	REG_MAR0 = 0x8 ; Multicast filter
47	REG_TxDescStartAddr = 0x20	47	REG_TxDescStartAddr = 0x20
48	REG_TxHDescStartAddr = 0x28	48	REG_TxHDescStartAddr = 0x28
49	REG_FLASH = 0x30	49	REG_FLASH = 0x30
50	REG_ERSR = 0x36	50	REG_ERSR = 0x36
51	REG_ChipCmd = 0x37	51	REG_ChipCmd = 0x37
52	REG_TxPoll = 0x38	52	REG_TxPoll = 0x38
53	REG_IntrMask = 0x3C	53	REG_IntrMask = 0x3C
54	REG_IntrStatus = 0x3E	54	REG_IntrStatus = 0x3E
55	REG_TxConfig = 0x40	55	REG_TxConfig = 0x40
56	REG_RxConfig = 0x44	56	REG_RxConfig = 0x44
57	REG_RxMissed = 0x4C	57	REG_RxMissed = 0x4C
58	REG_Cfg9346 = 0x50	58	REG_Cfg9346 = 0x50
59	REG_Config0 = 0x51	59	REG_Config0 = 0x51
60	REG_Config1 = 0x52	60	REG_Config1 = 0x52
61	REG_Config2 = 0x53	61	REG_Config2 = 0x53
62	REG_Config3 = 0x54	62	REG_Config3 = 0x54
63	REG_Config4 = 0x55	63	REG_Config4 = 0x55
64	REG_Config5 = 0x56	64	REG_Config5 = 0x56
65	REG_MultiIntr = 0x5C	65	REG_MultiIntr = 0x5C
66	REG_PHYAR = 0x60	66	REG_PHYAR = 0x60
67	REG_TBICSR = 0x64	67	REG_TBICSR = 0x64
68	REG_TBI_ANAR = 0x68	68	REG_TBI_ANAR = 0x68
69	REG_TBI_LPAR = 0x6A	69	REG_TBI_LPAR = 0x6A
70	REG_PHYstatus = 0x6C	70	REG_PHYstatus = 0x6C
71	REG_RxMaxSize = 0xDA	71	REG_RxMaxSize = 0xDA
72	REG_CPlusCmd = 0xE0	72	REG_CPlusCmd = 0xE0
73	REG_RxDescStartAddr = 0xE4	73	REG_RxDescStartAddr = 0xE4
74	REG_ETThReg = 0xEC	74	REG_ETThReg = 0xEC
75	REG_FuncEvent = 0xF0	75	REG_FuncEvent = 0xF0
76	REG_FuncEventMask = 0xF4	76	REG_FuncEventMask = 0xF4
77	REG_FuncPresetState = 0xF8	77	REG_FuncPresetState = 0xF8
78	REG_FuncForceEvent = 0xFC	78	REG_FuncForceEvent = 0xFC
79		79
80	; InterruptStatusBits	80	; InterruptStatusBits
81	ISB_SYSErr = 0x8000	81	ISB_SYSErr = 0x8000
82	ISB_PCSTimeout = 0x4000	82	ISB_PCSTimeout = 0x4000
83	ISB_SWInt = 0x0100	83	ISB_SWInt = 0x0100
84	ISB_TxDescUnavail = 0x80	84	ISB_TxDescUnavail = 0x80
85	ISB_RxFIFOOver = 0x40	85	ISB_RxFIFOOver = 0x40
86	ISB_LinkChg = 0x20	86	ISB_LinkChg = 0x20
87	ISB_RxOverflow = 0x10	87	ISB_RxOverflow = 0x10
88	ISB_TxErr = 0x08	88	ISB_TxErr = 0x08
89	ISB_TxOK = 0x04	89	ISB_TxOK = 0x04
90	ISB_RxErr = 0x02	90	ISB_RxErr = 0x02
91	ISB_RxOK = 0x01	91	ISB_RxOK = 0x01
92		92
93	; RxStatusDesc	93	; RxStatusDesc
94	SD_RxRES = 0x00200000	94	SD_RxRES = 0x00200000
95	SD_RxCRC = 0x00080000	95	SD_RxCRC = 0x00080000
96	SD_RxRUNT = 0x00100000	96	SD_RxRUNT = 0x00100000
97	SD_RxRWT = 0x00400000	97	SD_RxRWT = 0x00400000
98		98
99	; ChipCmdBits	99	; ChipCmdBits
100	CMD_Reset = 0x10	100	CMD_Reset = 0x10
101	CMD_RxEnb = 0x08	101	CMD_RxEnb = 0x08
102	CMD_TxEnb = 0x04	102	CMD_TxEnb = 0x04
103	CMD_RxBufEmpty = 0x01	103	CMD_RxBufEmpty = 0x01
104		104
105	; Cfg9346Bits	105	; Cfg9346Bits
106	CFG_9346_Lock = 0x00	106	CFG_9346_Lock = 0x00
107	CFG_9346_Unlock = 0xC0	107	CFG_9346_Unlock = 0xC0
108		108
109	; rx_mode_bits	109	; rx_mode_bits
110	RXM_AcceptErr = 0x20	110	RXM_AcceptErr = 0x20
111	RXM_AcceptRunt = 0x10	111	RXM_AcceptRunt = 0x10
112	RXM_AcceptBroadcast = 0x08	112	RXM_AcceptBroadcast = 0x08
113	RXM_AcceptMulticast = 0x04	113	RXM_AcceptMulticast = 0x04
114	RXM_AcceptMyPhys = 0x02	114	RXM_AcceptMyPhys = 0x02
115	RXM_AcceptAllPhys = 0x01	115	RXM_AcceptAllPhys = 0x01
116		116
117	; RxConfigBits	117	; RxConfigBits
118	RXC_FIFOShift = 13	118	RXC_FIFOShift = 13
119	RXC_DMAShift = 8	119	RXC_DMAShift = 8
120		120
121	; TxConfigBits	121	; TxConfigBits
122	TXC_InterFrameGapShift = 24	122	TXC_InterFrameGapShift = 24
123	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits	123	TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
124		124
125	; PHYstatus	125	; PHYstatus
126	PHYS_TBI_Enable = 0x80	126	PHYS_TBI_Enable = 0x80
127	PHYS_TxFlowCtrl = 0x40	127	PHYS_TxFlowCtrl = 0x40
128	PHYS_RxFlowCtrl = 0x20	128	PHYS_RxFlowCtrl = 0x20
129	PHYS_1000bpsF = 0x10	129	PHYS_1000bpsF = 0x10
130	PHYS_100bps = 0x08	130	PHYS_100bps = 0x08
131	PHYS_10bps = 0x04	131	PHYS_10bps = 0x04
132	PHYS_LinkStatus = 0x02	132	PHYS_LinkStatus = 0x02
133	PHYS_FullDup = 0x01	133	PHYS_FullDup = 0x01
134		134
135	; GIGABIT_PHY_registers	135	; GIGABIT_PHY_registers
136	PHY_CTRL_REG = 0	136	PHY_CTRL_REG = 0
137	PHY_STAT_REG = 1	137	PHY_STAT_REG = 1
138	PHY_AUTO_NEGO_REG = 4	138	PHY_AUTO_NEGO_REG = 4
139	PHY_1000_CTRL_REG = 9	139	PHY_1000_CTRL_REG = 9
140		140
141	; GIGABIT_PHY_REG_BIT	141	; GIGABIT_PHY_REG_BIT
142	PHY_Restart_Auto_Nego = 0x0200	142	PHY_Restart_Auto_Nego = 0x0200
143	PHY_Enable_Auto_Nego = 0x1000	143	PHY_Enable_Auto_Nego = 0x1000
144		144
145	; PHY_STAT_REG = 1	145	; PHY_STAT_REG = 1
146	PHY_Auto_Neco_Comp = 0x0020	146	PHY_Auto_Neco_Comp = 0x0020
147		147
148	; PHY_AUTO_NEGO_REG = 4	148	; PHY_AUTO_NEGO_REG = 4
149	PHY_Cap_10_Half = 0x0020	149	PHY_Cap_10_Half = 0x0020
150	PHY_Cap_10_Full = 0x0040	150	PHY_Cap_10_Full = 0x0040
151	PHY_Cap_100_Half = 0x0080	151	PHY_Cap_100_Half = 0x0080
152	PHY_Cap_100_Full = 0x0100	152	PHY_Cap_100_Full = 0x0100
153		153
154	; PHY_1000_CTRL_REG = 9	154	; PHY_1000_CTRL_REG = 9
155	PHY_Cap_1000_Full = 0x0200	155	PHY_Cap_1000_Full = 0x0200
156	PHY_Cap_1000_Half = 0x0100	156	PHY_Cap_1000_Half = 0x0100
157		157
158	PHY_Cap_PAUSE = 0x0400	158	PHY_Cap_PAUSE = 0x0400
159	PHY_Cap_ASYM_PAUSE = 0x0800	159	PHY_Cap_ASYM_PAUSE = 0x0800
160		160
161	PHY_Cap_Null = 0x0	161	PHY_Cap_Null = 0x0
162		162
163	; _MediaType	163	; _MediaType
164	MT_10_Half = 0x01	164	MT_10_Half = 0x01
165	MT_10_Full = 0x02	165	MT_10_Full = 0x02
166	MT_100_Half = 0x04	166	MT_100_Half = 0x04
167	MT_100_Full = 0x08	167	MT_100_Full = 0x08
168	MT_1000_Full = 0x10	168	MT_1000_Full = 0x10
169		169
170	; _TBICSRBit	170	; _TBICSRBit
171	TBI_LinkOK = 0x02000000	171	TBI_LinkOK = 0x02000000
172		172
173	; _DescStatusBit	173	; _DescStatusBit
174	DSB_OWNbit = 0x80000000	174	DSB_OWNbit = 0x80000000
175	DSB_EORbit = 0x40000000	175	DSB_EORbit = 0x40000000
176	DSB_FSbit = 0x20000000	176	DSB_FSbit = 0x20000000
177	DSB_LSbit = 0x10000000	177	DSB_LSbit = 0x10000000
178		178
179	RX_BUF_SIZE = 1536 ; Rx Buffer size	179	RX_BUF_SIZE = 1536 ; Rx Buffer size
180		180
181	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)	181	; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
182	MAX_ETH_FRAME_SIZE = 1536	182	MAX_ETH_FRAME_SIZE = 1536
183		183
184	TX_FIFO_THRESH = 256 ; In bytes	184	TX_FIFO_THRESH = 256 ; In bytes
185		185
186	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer	186	RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
187	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024	187	RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
188	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024	188	TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
189	ETTh = 0x3F ; 0x3F means NO threshold	189	ETTh = 0x3F ; 0x3F means NO threshold
190		190
191	EarlyTxThld = 0x3F ; 0x3F means NO early transmit	191	EarlyTxThld = 0x3F ; 0x3F means NO early transmit
192	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1	192	RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
193	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one	193	InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
194		194
195	HZ = 1000	195	HZ = 1000
196		196
197	RTL_MIN_IO_SIZE = 0x80	197	RTL_MIN_IO_SIZE = 0x80
198	TX_TIMEOUT = (6*HZ)	198	TX_TIMEOUT = (6*HZ)
199		199
200	TIMER_EXPIRE_TIME = 100	200	TIMER_EXPIRE_TIME = 100
201		201
202	ETH_HDR_LEN = 14	202	ETH_HDR_LEN = 14
203	DEFAULT_MTU = 1500	203	DEFAULT_MTU = 1500
204	DEFAULT_RX_BUF_LEN = 1536	204	DEFAULT_RX_BUF_LEN = 1536
205		205
206		206
207	;ifdef JUMBO_FRAME_SUPPORT	207	;ifdef JUMBO_FRAME_SUPPORT
208	; MAX_JUMBO_FRAME_MTU = 10000	208	; MAX_JUMBO_FRAME_MTU = 10000
209	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )	209	; MAX_RX_SKBDATA_SIZE = (MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
210	;else	210	;else
211	MAX_RX_SKBDATA_SIZE = 1600	211	MAX_RX_SKBDATA_SIZE = 1600
212	;end if	212	;end if
213		213
214	MCFG_METHOD_01 = 0x01	214	MCFG_METHOD_01 = 0x01
215	MCFG_METHOD_02 = 0x02	215	MCFG_METHOD_02 = 0x02
216	MCFG_METHOD_03 = 0x03	216	MCFG_METHOD_03 = 0x03
217	MCFG_METHOD_04 = 0x04	217	MCFG_METHOD_04 = 0x04
218	MCFG_METHOD_05 = 0x05	218	MCFG_METHOD_05 = 0x05
219	MCFG_METHOD_11 = 0x0b	219	MCFG_METHOD_11 = 0x0b
220	MCFG_METHOD_12 = 0x0c	220	MCFG_METHOD_12 = 0x0c
221	MCFG_METHOD_13 = 0x0d	221	MCFG_METHOD_13 = 0x0d
222	MCFG_METHOD_14 = 0x0e	222	MCFG_METHOD_14 = 0x0e
223	MCFG_METHOD_15 = 0x0f	223	MCFG_METHOD_15 = 0x0f
224		224
225	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000	225	PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
226	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001	226	PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
227	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002	227	PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
228		228
229	virtual at 0	229	virtual at 0
230	tx_desc:	230	tx_desc:
231	.status dd ?	231	.status dd ?
232	.vlan_tag dd ?	232	.vlan_tag dd ?
233	.buf_addr dq ?	233	.buf_addr dq ?
234	.size = $	234	.size = $
235	rb (NUM_TX_DESC-1)*tx_desc.size	235	rb (NUM_TX_DESC-1)*tx_desc.size
236	.buf_soft_addr dd ?	236	.buf_soft_addr dd ?
237	end virtual	237	end virtual
238		238
239	virtual at 0	239	virtual at 0
240	rx_desc:	240	rx_desc:
241	.status dd ?	241	.status dd ?
242	.vlan_tag dd ?	242	.vlan_tag dd ?
243	.buf_addr dq ?	243	.buf_addr dq ?
244	.size = $	244	.size = $
245	rb (NUM_RX_DESC-1)*rx_desc.size	245	rb (NUM_RX_DESC-1)*rx_desc.size
246	.buf_soft_addr dd ?	246	.buf_soft_addr dd ?
247	end virtual	247	end virtual
248		248
249	virtual at ebx	249	virtual at ebx
250		250
251	device:	251	device:
252		252
253	ETH_DEVICE	253	ETH_DEVICE
254		254
255	.io_addr dd ?	255	.io_addr dd ?
256	.pci_bus dd ?	256	.pci_bus dd ?
257	.pci_dev dd ?	257	.pci_dev dd ?
258	.irq_line db ?	258	.irq_line db ?
259		259
260	rb 256-(($ - device) and 255) ; align 256	260	rb 256-(($ - device) and 255) ; align 256
261	.tx_ring rb NUM_TX_DESC * tx_desc.size * 2	261	.tx_ring rb NUM_TX_DESC * tx_desc.size * 2
262		262
263	rb 256-(($ - device) and 255) ; align 256	263	rb 256-(($ - device) and 255) ; align 256
264	.rx_ring rb NUM_RX_DESC * rx_desc.size * 2	264	.rx_ring rb NUM_RX_DESC * rx_desc.size * 2
265		265
266	tpc:	266	tpc:
267	.mmio_addr dd ? ; memory map physical address	267	.mmio_addr dd ? ; memory map physical address
268	.chipset dd ?	268	.chipset dd ?
269	.pcfg dd ?	269	.pcfg dd ?
270	.mcfg dd ?	270	.mcfg dd ?
271	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt	271	.cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt
272	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt	272	.cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt
273	.TxDescArrays dd ? ; Index of Tx Descriptor buffer	273	.TxDescArrays dd ? ; Index of Tx Descriptor buffer
274	.RxDescArrays dd ? ; Index of Rx Descriptor buffer	274	.RxDescArrays dd ? ; Index of Rx Descriptor buffer
275	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer	275	.TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer
276	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer	276	.RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer
277		277
278	device_size = $ - device	278	device_size = $ - device
279		279
280	end virtual	280	end virtual
281		281
282	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK	282	intr_mask = ISB_LinkChg or ISB_RxOverflow or ISB_RxFIFOOver or ISB_TxErr or ISB_TxOK or ISB_RxErr or ISB_RxOK
283	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E	283	rx_config = (RX_FIFO_THRESH shl RXC_FIFOShift) or (RX_DMA_BURST shl RXC_DMAShift) or 0x0000000E
284		284
285		285
286	macro udelay msec {	286	macro udelay msec {
287		287
288	push esi	288	push esi
289	mov esi, msec	289	mov esi, msec
290	call Sleep	290	call Sleep
291	pop esi	291	pop esi
292		292
293	}	293	}
294		294
295	macro WRITE_GMII_REG RegAddr, value {	295	macro WRITE_GMII_REG RegAddr, value {
296		296
297	set_io REG_PHYAR	297	set_io REG_PHYAR
298	if value eq ax	298	if value eq ax
299	and eax, 0x0000ffff	299	and eax, 0x0000ffff
300	or eax, 0x80000000 + (RegAddr shl 16)	300	or eax, 0x80000000 + (RegAddr shl 16)
301	else	301	else
302	mov eax, 0x80000000 + (RegAddr shl 16) + value	302	mov eax, 0x80000000 + (RegAddr shl 16) + value
303	end if	303	end if
304	out dx, eax	304	out dx, eax
305		305
306	call PHY_WAIT_WRITE	306	call PHY_WAIT_WRITE
307	}	307	}
308		308
309	macro READ_GMII_REG RegAddr {	309	macro READ_GMII_REG RegAddr {
310		310
311	local .error, .done	311	local .error, .done
312		312
313	set_io REG_PHYAR	313	set_io REG_PHYAR
314	mov eax, RegAddr shl 16	314	mov eax, RegAddr shl 16
315	out dx, eax	315	out dx, eax
316		316
317	call PHY_WAIT_READ	317	call PHY_WAIT_READ
318	jz .error	318	jz .error
319		319
320	in eax, dx	320	in eax, dx
321	and eax, 0xFFFF	321	and eax, 0xFFFF
322	jmp .done	322	jmp .done
323		323
324	.error:	324	.error:
325	or eax, -1	325	or eax, -1
326	.done:	326	.done:
327	}	327	}
328		328
329	align 4	329	align 4
330	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR	330	PHY_WAIT_READ: ; io addr must already be set to REG_PHYAR
331		331
332	udelay 1 ;;;1000	332	udelay 1 ;;;1000
333		333
334	push ecx	334	push ecx
335	mov ecx, 2000	335	mov ecx, 2000
336	; Check if the RTL8169 has completed writing/reading to the specified MII register	336	; Check if the RTL8169 has completed writing/reading to the specified MII register
337	@@:	337	@@:
338	in eax, dx	338	in eax, dx
339	test eax, 0x80000000	339	test eax, 0x80000000
340	jnz .exit	340	jnz .exit
341	udelay 1 ;;;100	341	udelay 1 ;;;100
342	loop @b	342	loop @b
343	.exit:	343	.exit:
344	pop ecx	344	pop ecx
345	ret	345	ret
346		346
347	align 4	347	align 4
348	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR	348	PHY_WAIT_WRITE: ; io addr must already be set to REG_PHYAR
349		349
350	udelay 1 ;;;1000	350	udelay 1 ;;;1000
351		351
352	push ecx	352	push ecx
353	mov ecx, 2000	353	mov ecx, 2000
354	; Check if the RTL8169 has completed writing/reading to the specified MII register	354	; Check if the RTL8169 has completed writing/reading to the specified MII register
355	@@:	355	@@:
356	in eax, dx	356	in eax, dx
357	test eax, 0x80000000	357	test eax, 0x80000000
358	jz .exit	358	jz .exit
359	udelay 1 ;;;100	359	udelay 1 ;;;100
360	loop @b	360	loop @b
361	.exit:	361	.exit:
362	pop ecx	362	pop ecx
363	ret	363	ret
364		364
365		365
366		366
367	section '.flat' code readable align 16	367	section '.flat' code readable align 16
368		368
369	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	369	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
370	;; ;;	370	;; ;;
371	;; proc START ;;	371	;; proc START ;;
372	;; ;;	372	;; ;;
373	;; (standard driver proc) ;;	373	;; (standard driver proc) ;;
374	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	374	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
375		375
376	align 4	376	align 4
377	proc START stdcall, state:dword	377	proc START stdcall, state:dword
378		378
379	cmp [state], 1	379	cmp [state], 1
380	jne .exit	380	jne .exit
381		381
382	.entry:	382	.entry:
383		383
384	DEBUGF 2,"Loading %s driver\n", my_service	384	DEBUGF 2,"Loading %s driver\n", my_service
385	stdcall RegService, my_service, service_proc	385	stdcall RegService, my_service, service_proc
386	ret	386	ret
387		387
388	.fail:	388	.fail:
389	.exit:	389	.exit:
390	xor eax, eax	390	xor eax, eax
391	ret	391	ret
392		392
393	endp	393	endp
394		394
395		395
396	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	396	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
397	;; ;;	397	;; ;;
398	;; proc SERVICE_PROC ;;	398	;; proc SERVICE_PROC ;;
399	;; ;;	399	;; ;;
400	;; (standard driver proc) ;;	400	;; (standard driver proc) ;;
401	;;;;;;;;;;;;;;;;;;;;;;;;;;;;	401	;;;;;;;;;;;;;;;;;;;;;;;;;;;;
402		402
403	align 4	403	align 4
404	proc service_proc stdcall, ioctl:dword	404	proc service_proc stdcall, ioctl:dword
405		405
406	mov edx, [ioctl]	406	mov edx, [ioctl]
407	mov eax, [IOCTL.io_code]	407	mov eax, [IOCTL.io_code]
408		408
409	;------------------------------------------------------	409	;------------------------------------------------------
410		410
411	cmp eax, 0 ;SRV_GETVERSION	411	cmp eax, 0 ;SRV_GETVERSION
412	jne @F	412	jne @F
413		413
414	cmp [IOCTL.out_size], 4	414	cmp [IOCTL.out_size], 4
415	jb .fail	415	jb .fail
416	mov eax, [IOCTL.output]	416	mov eax, [IOCTL.output]
417	mov [eax], dword API_VERSION	417	mov [eax], dword API_VERSION
418		418
419	xor eax, eax	419	xor eax, eax
420	ret	420	ret
421		421
422	;------------------------------------------------------	422	;------------------------------------------------------
423	@@:	423	@@:
424	cmp eax, 1 ;SRV_HOOK	424	cmp eax, 1 ;SRV_HOOK
425	jne .fail	425	jne .fail
426		426
427	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes	427	cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
428	jb .fail	428	jb .fail
429		429
430	mov eax, [IOCTL.input]	430	mov eax, [IOCTL.input]
431	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given	431	cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given
432	jne .fail ; other types arent supported for this card yet	432	jne .fail ; other types arent supported for this card yet
433		433
434	; check if the device is already listed	434	; check if the device is already listed
435		435
436	mov esi, device_list	436	mov esi, device_list
437	mov ecx, [devices]	437	mov ecx, [devices]
438	test ecx, ecx	438	test ecx, ecx
439	jz .firstdevice	439	jz .firstdevice
440		440
441	; mov eax, [IOCTL.input] ; get the pci bus and device numbers	441	; mov eax, [IOCTL.input] ; get the pci bus and device numbers
442	mov ax , [eax+1] ;	442	mov ax , [eax+1] ;
443	.nextdevice:	443	.nextdevice:
444	mov ebx, [esi]	444	mov ebx, [esi]
445	cmp al, byte[device.pci_bus]	445	cmp al, byte[device.pci_bus]
446	jne @f	446	jne @f
447	cmp ah, byte[device.pci_dev]	447	cmp ah, byte[device.pci_dev]
448	je .find_devicenum ; Device is already loaded, let's find it's device number	448	je .find_devicenum ; Device is already loaded, let's find it's device number
449	@@:	449	@@:
450	add esi, 4	450	add esi, 4
451	loop .nextdevice	451	loop .nextdevice
452		452
453		453
454	; This device doesnt have its own eth_device structure yet, lets create one	454	; This device doesnt have its own eth_device structure yet, lets create one
455	.firstdevice:	455	.firstdevice:
456	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card	456	cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
457	jae .fail	457	jae .fail
458		458
459	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in	459	allocate_and_clear ebx, device_size, .fail ; Allocate memory to put the device structure in
460		460
461	; Fill in the direct call addresses into the struct	461	; Fill in the direct call addresses into the struct
462		462
463	mov [device.reset], reset	463	mov [device.reset], reset
464	mov [device.transmit], transmit	464	mov [device.transmit], transmit
465	mov [device.unload], unload	465	mov [device.unload], unload
466	mov [device.name], my_service	466	mov [device.name], my_service
467		467
468	; save the pci bus and device numbers	468	; save the pci bus and device numbers
469		469
470	mov eax, [IOCTL.input]	470	mov eax, [IOCTL.input]
471	movzx ecx, byte[eax+1]	471	movzx ecx, byte[eax+1]
472	mov [device.pci_bus], ecx	472	mov [device.pci_bus], ecx
473	movzx ecx, byte[eax+2]	473	movzx ecx, byte[eax+2]
474	mov [device.pci_dev], ecx	474	mov [device.pci_dev], ecx
475		475
476	; Now, it's time to find the base io addres of the PCI device	476	; Now, it's time to find the base io addres of the PCI device
477		477
478	PCI_find_io	478	PCI_find_io
479	mov [tpc.mmio_addr], eax ; CHECKME	479	mov [tpc.mmio_addr], eax ; CHECKME
480		480
481	; We've found the io address, find IRQ now	481	; We've found the io address, find IRQ now
482		482
483	PCI_find_irq	483	PCI_find_irq
484		484
485	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\	485	DEBUGF 2,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
486	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8	486	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:8
487		487
488	; Ok, the eth_device structure is ready, let's probe the device	488	; Ok, the eth_device structure is ready, let's probe the device
489	; Because initialization fires IRQ, IRQ handler must be aware of this device	489	; Because initialization fires IRQ, IRQ handler must be aware of this device
490	mov eax, [devices] ; Add the device structure to our device list	490	mov eax, [devices] ; Add the device structure to our device list
491	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)	491	mov [device_list + 4*eax], ebx ; (IRQ handler uses this list to find device)
492	inc [devices] ;	492	inc [devices] ;
493		493
494	call probe ; this function will output in eax	494	call probe ; this function will output in eax
495	test eax, eax	495	test eax, eax
496	jnz .err2 ; If an error occured, exit	496	jnz .err2 ; If an error occured, exit
497		497
498	mov [device.type], NET_TYPE_ETH	498	mov [device.type], NET_TYPE_ETH
499	call NetRegDev	499	call NetRegDev
500		500

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(root)/drivers/ethernet/RTL8169.asm – Rev 3545 → 4301