WebSVN – Kolibri OS – Diff – /drivers/audio/a5536/pci.h


typedef int Bool;
 
#define TRUE   1
#define FALSE  0
 
#pragma pack(push, 1)
typedef struct
{
     u16_t device;
     u16_t ChipSet;
}PciChipset_t;
#pragma pack(pop)
 
#define VENDOR_ATI 0x1002
 
 
#define PCI_CLASS_DISPLAY_VGA      0x0300
/*
 * Under PCI, each device has 256 bytes of configuration address space,
 * of which the first 64 bytes are standardized as follows:
 */
#define PCI_VENDOR_ID                0x00    /* 16 bits */
#define PCI_DEVICE_ID                0x02    /* 16 bits */
#define PCI_COMMAND                  0x04    /* 16 bits */
#define  PCI_COMMAND_IO              0x01    /* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY          0x02    /* Enable response in Memory space */
#define  PCI_COMMAND_MASTER          0x04    /* Enable bus mastering */
#define  PCI_COMMAND_SPECIAL         0x08    /* Enable response to special cycles */
#define  PCI_COMMAND_INVALIDATE      0x10    /* Use memory write and invalidate */
#define  PCI_COMMAND_VGA_PALETTE     0x20    /* Enable palette snooping */
#define  PCI_COMMAND_PARITY          0x40    /* Enable parity checking */
#define  PCI_COMMAND_WAIT            0x80    /* Enable address/data stepping */
#define  PCI_COMMAND_SERR           0x100    /* Enable SERR */
#define  PCI_COMMAND_FAST_BACK      0x200    /* Enable back-to-back writes */
#define  PCI_COMMAND_INTX_DISABLE   0x400    /* INTx Emulation Disable */
 
#define PCI_STATUS                  0x06    /* 16 bits */
#define  PCI_STATUS_CAP_LIST        0x10    /* Support Capability List */
#define  PCI_STATUS_66MHZ           0x20    /* Support 66 Mhz PCI 2.1 bus */
#define  PCI_STATUS_UDF             0x40    /* Support User Definable Features [obsolete] */
#define  PCI_STATUS_FAST_BACK       0x80    /* Accept fast-back to back */
#define  PCI_STATUS_PARITY          0x100   /* Detected parity error */
#define  PCI_STATUS_DEVSEL_MASK     0x600   /* DEVSEL timing */
#define  PCI_STATUS_DEVSEL_FAST		0x000
#define  PCI_STATUS_DEVSEL_MEDIUM	0x200
#define  PCI_STATUS_DEVSEL_SLOW		0x400
#define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
#define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
#define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
#define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
#define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
 
#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID		0x08	/* Revision ID */
#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE	0x0a	/* Device class */
 
#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL		0
#define  PCI_HEADER_TYPE_BRIDGE		1
#define  PCI_HEADER_TYPE_CARDBUS	2
 
#define PCI_BIST            0x0f    /* 8 bits */
#define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
#define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
#define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
 
#define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
#define PCI_CB_CAPABILITY_LIST  0x14
/* Capability lists */
 
#define PCI_CAP_LIST_ID     0       /* Capability ID */
#define  PCI_CAP_ID_PM		0x01	/* Power Management */
#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific capability */
#define  PCI_CAP_ID_SHPC 	0x0C	/* PCI Standard Hot-Plug Controller */
#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
#define PCI_CAP_LIST_NEXT   1       /* Next capability in the list */
#define PCI_CAP_FLAGS       2       /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF		4
 
 
/* AGP registers */
 
#define PCI_AGP_VERSION          2   /* BCD version number */
#define PCI_AGP_RFU              3   /* Rest of capability flags */
#define PCI_AGP_STATUS           4   /* Status register */
#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
#define  PCI_AGP_STATUS_SBA     0x0200   /* Sideband addressing supported */
#define  PCI_AGP_STATUS_64BIT   0x0020   /* 64-bit addressing supported */
#define  PCI_AGP_STATUS_FW      0x0010   /* FW transfers supported */
#define  PCI_AGP_STATUS_RATE4   0x0004   /* 4x transfer rate supported */
#define  PCI_AGP_STATUS_RATE2   0x0002   /* 2x transfer rate supported */
#define  PCI_AGP_STATUS_RATE1   0x0001   /* 1x transfer rate supported */
#define PCI_AGP_COMMAND              8   /* Control register */
#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
#define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
#define PCI_AGP_SIZEOF		12
 
 
#define PCI_MAP_REG_START             0x10
#define PCI_MAP_REG_END               0x28
#define PCI_MAP_ROM_REG               0x30
 
#define PCI_MAP_MEMORY                0x00000000
#define PCI_MAP_IO                    0x00000001
 
#define PCI_MAP_MEMORY_TYPE           0x00000007
#define PCI_MAP_IO_TYPE               0x00000003
 
#define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
#define PCI_MAP_MEMORY_TYPE_32BIT_1M	0x00000002
#define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
#define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
#define PCI_MAP_MEMORY_CACHABLE       0x00000008
#define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
#define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
 
#define PCI_MAP_IO_ATTR_MASK          0x00000003
 
#define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
#define PCI_MAP_IS_MEM(b)	(!PCI_MAP_IS_IO(b))
 
#define PCI_MAP_IS64BITMEM(b)	\
	(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
 
#define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
#define PCIGETMEMORY64HIGH(b)	(*((CARD32*)&b + 1))
#define PCIGETMEMORY64(b)	\
	(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
 
#define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
 
#define PCIGETIO(b)		((b) & PCI_MAP_IO_ADDRESS_MASK)
 
#define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
#define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
 
#define PCIGETROM(b)		((b) & PCI_MAP_ROM_ADDRESS_MASK)
 
 
#ifndef PCI_DOM_MASK
# define PCI_DOM_MASK 0x0ffu
#endif
#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
 
#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
			      (((d) & 0x00001fu) << 11) | \
			      (((f) & 0x000007u) << 8))
 
#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
 
 
typedef unsigned int PCITAG;
 
extern inline PCITAG
pciTag(int busnum, int devnum, int funcnum)
{
	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
}
 
const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list);
u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);
 
#define PCI_ANY_ID (~0)
 
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)

Rev 1028	Rev 1692
-		1	typedef int Bool;
-		2
-		3	#define TRUE 1
-		4	#define FALSE 0
1	#pragma pack(push, 1)	5
2	typedef struct	6	#pragma pack(push, 1)
3	{	7	typedef struct
4	u16_t device;	8	{
5	u16_t ChipSet;	9	u16_t device;
6	}PciChipset_t;	10	u16_t ChipSet;
7	#pragma pack(pop)	11	}PciChipset_t;
8		12	#pragma pack(pop)
9	#define VENDOR_ATI 0x1002	13
10		14	#define VENDOR_ATI 0x1002
11		15
12	#define PCI_CLASS_DISPLAY_VGA 0x0300	16
13	/*	17	#define PCI_CLASS_DISPLAY_VGA 0x0300
14	* Under PCI, each device has 256 bytes of configuration address space,	18	/*
15	* of which the first 64 bytes are standardized as follows:	19	* Under PCI, each device has 256 bytes of configuration address space,
16	*/	20	* of which the first 64 bytes are standardized as follows:
17	#define PCI_VENDOR_ID 0x00 /* 16 bits */	21	*/
18	#define PCI_DEVICE_ID 0x02 /* 16 bits */	22	#define PCI_VENDOR_ID 0x00 /* 16 bits */
19	#define PCI_COMMAND 0x04 /* 16 bits */	23	#define PCI_DEVICE_ID 0x02 /* 16 bits */
20	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */	24	#define PCI_COMMAND 0x04 /* 16 bits */
21	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */	25	#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
22	#define PCI_COMMAND_MASTER 0x04 /* Enable bus mastering */	26	#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
23	#define PCI_COMMAND_SPECIAL 0x08 /* Enable response to special cycles */	27	#define PCI_COMMAND_MASTER 0x04 /* Enable bus mastering */
24	#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */	28	#define PCI_COMMAND_SPECIAL 0x08 /* Enable response to special cycles */
25	#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */	29	#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
26	#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */	30	#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
27	#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */	31	#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
28	#define PCI_COMMAND_SERR 0x100 /* Enable SERR */	32	#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
29	#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */	33	#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
30	#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */	34	#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
31		35	#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
32	#define PCI_STATUS 0x06 /* 16 bits */	36
33	#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */	37	#define PCI_STATUS 0x06 /* 16 bits */
34	#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */	38	#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
35	#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */	39	#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
36	#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */	40	#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
37	#define PCI_STATUS_PARITY 0x100 /* Detected parity error */	41	#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
38	#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */	42	#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
39	#define PCI_STATUS_DEVSEL_FAST 0x000	43	#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
40	#define PCI_STATUS_DEVSEL_MEDIUM 0x200	44	#define PCI_STATUS_DEVSEL_FAST 0x000
41	#define PCI_STATUS_DEVSEL_SLOW 0x400	45	#define PCI_STATUS_DEVSEL_MEDIUM 0x200
42	#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */	46	#define PCI_STATUS_DEVSEL_SLOW 0x400
43	#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */	47	#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
44	#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */	48	#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
45	#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */	49	#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
46	#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */	50	#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
47		51	#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
48	#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */	52
49	#define PCI_REVISION_ID 0x08 /* Revision ID */	53	#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
50	#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */	54	#define PCI_REVISION_ID 0x08 /* Revision ID */
51	#define PCI_CLASS_DEVICE 0x0a /* Device class */	55	#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
52		56	#define PCI_CLASS_DEVICE 0x0a /* Device class */
53	#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */	57
54	#define PCI_LATENCY_TIMER 0x0d /* 8 bits */	58	#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
55	#define PCI_HEADER_TYPE 0x0e /* 8 bits */	59	#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
56	#define PCI_HEADER_TYPE_NORMAL 0	60	#define PCI_HEADER_TYPE 0x0e /* 8 bits */
57	#define PCI_HEADER_TYPE_BRIDGE 1	61	#define PCI_HEADER_TYPE_NORMAL 0
58	#define PCI_HEADER_TYPE_CARDBUS 2	62	#define PCI_HEADER_TYPE_BRIDGE 1
59		63	#define PCI_HEADER_TYPE_CARDBUS 2
60	#define PCI_BIST 0x0f /* 8 bits */	64
61	#define PCI_BIST_CODE_MASK 0x0f /* Return result */	65	#define PCI_BIST 0x0f /* 8 bits */
62	#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */	66	#define PCI_BIST_CODE_MASK 0x0f /* Return result */
63	#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */	67	#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
64		68	#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
65	#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */	69
66	#define PCI_CB_CAPABILITY_LIST 0x14	70	#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
67	/* Capability lists */	71	#define PCI_CB_CAPABILITY_LIST 0x14
68		72	/* Capability lists */
69	#define PCI_CAP_LIST_ID 0 /* Capability ID */	73
70	#define PCI_CAP_ID_PM 0x01 /* Power Management */	74	#define PCI_CAP_LIST_ID 0 /* Capability ID */
71	#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */	75	#define PCI_CAP_ID_PM 0x01 /* Power Management */
72	#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */	76	#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
73	#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */	77	#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
74	#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */	78	#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
75	#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */	79	#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
76	#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */	80	#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
77	#define PCI_CAP_ID_HT 0x08 /* HyperTransport */	81	#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
78	#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */	82	#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
79	#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */	83	#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */
80	#define PCI_CAP_ID_EXP 0x10 /* PCI Express */	84	#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
81	#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */	85	#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
82	#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */	86	#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
83	#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */	87	#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
84	#define PCI_CAP_SIZEOF 4	88	#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
85		89	#define PCI_CAP_SIZEOF 4
86		90
87	/* AGP registers */	91
88		92	/* AGP registers */
89	#define PCI_AGP_VERSION 2 /* BCD version number */	93
90	#define PCI_AGP_RFU 3 /* Rest of capability flags */	94	#define PCI_AGP_VERSION 2 /* BCD version number */
91	#define PCI_AGP_STATUS 4 /* Status register */	95	#define PCI_AGP_RFU 3 /* Rest of capability flags */
92	#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */	96	#define PCI_AGP_STATUS 4 /* Status register */
93	#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */	97	#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
94	#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */	98	#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
95	#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */	99	#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
96	#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */	100	#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
97	#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */	101	#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
98	#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */	102	#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
99	#define PCI_AGP_COMMAND 8 /* Control register */	103	#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
100	#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */	104	#define PCI_AGP_COMMAND 8 /* Control register */
101	#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */	105	#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
102	#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */	106	#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
103	#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */	107	#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
104	#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */	108	#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
105	#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */	109	#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
106	#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */	110	#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
107	#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */	111	#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
108	#define PCI_AGP_SIZEOF 12	112	#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
109		113	#define PCI_AGP_SIZEOF 12
110		114
111	#define PCI_MAP_REG_START 0x10	115
112	#define PCI_MAP_REG_END 0x28	116	#define PCI_MAP_REG_START 0x10
113	#define PCI_MAP_ROM_REG 0x30	117	#define PCI_MAP_REG_END 0x28
114		118	#define PCI_MAP_ROM_REG 0x30
115	#define PCI_MAP_MEMORY 0x00000000	119
116	#define PCI_MAP_IO 0x00000001	120	#define PCI_MAP_MEMORY 0x00000000
117		121	#define PCI_MAP_IO 0x00000001
118	#define PCI_MAP_MEMORY_TYPE 0x00000007	122
119	#define PCI_MAP_IO_TYPE 0x00000003	123	#define PCI_MAP_MEMORY_TYPE 0x00000007
120		124	#define PCI_MAP_IO_TYPE 0x00000003
121	#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000	125
122	#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002	126	#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
123	#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004	127	#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
124	#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006	128	#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
125	#define PCI_MAP_MEMORY_CACHABLE 0x00000008	129	#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
126	#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e	130	#define PCI_MAP_MEMORY_CACHABLE 0x00000008
127	#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0	131	#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
128		132	#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
129	#define PCI_MAP_IO_ATTR_MASK 0x00000003	133
130		134	#define PCI_MAP_IO_ATTR_MASK 0x00000003
131	#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)	135
132	#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))	136	#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
133		137	#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
134	#define PCI_MAP_IS64BITMEM(b) \	138
135	(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)	139	#define PCI_MAP_IS64BITMEM(b) \
136		140	(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
137	#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)	141
138	#define PCIGETMEMORY64HIGH(b) (((CARD32)&b + 1))	142	#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
139	#define PCIGETMEMORY64(b) \	143	#define PCIGETMEMORY64HIGH(b) (((CARD32)&b + 1))
140	(PCIGETMEMORY(b) \| ((CARD64)PCIGETMEMORY64HIGH(b) << 32))	144	#define PCIGETMEMORY64(b) \
141		145	(PCIGETMEMORY(b) \| ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
142	#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc	146
143		147	#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
144	#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)	148
145		149	#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
146	#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001	150
147	#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800	151	#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
148		152	#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
149	#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)	153
150		154	#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
151		155
152	#ifndef PCI_DOM_MASK	156
153	# define PCI_DOM_MASK 0x0ffu	157	#ifndef PCI_DOM_MASK
154	#endif	158	# define PCI_DOM_MASK 0x0ffu
155	#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) \| 0x0ffu)	159	#endif
156		160	#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) \| 0x0ffu)
157	#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) \| \	161
158	(((d) & 0x00001fu) << 11) \| \	162	#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) \| \
159	(((f) & 0x000007u) << 8))	163	(((d) & 0x00001fu) << 11) \| \
160		164	(((f) & 0x000007u) << 8))
161	#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK))	165
162	#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11)	166	#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK))
163	#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)	167	#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11)
164	#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)	168	#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
165		169	#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)
166		170
167	typedef unsigned int PCITAG;	171
168		172	typedef unsigned int PCITAG;
169	extern inline PCITAG	173
170	pciTag(int busnum, int devnum, int funcnum)	174	extern inline PCITAG
171	{	175	pciTag(int busnum, int devnum, int funcnum)
172	return(PCI_MAKE_TAG(busnum,devnum,funcnum));	176	{
173	}	177	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
174		178	}
175	const PciChipset_t PciDevMatch(u16_t dev,const PciChipset_t list);	179
176	u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);	180	const PciChipset_t PciDevMatch(u16_t dev,const PciChipset_t list);
177		181	u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);
178	#define PCI_ANY_ID (~0)	182
179		183	#define PCI_ANY_ID (~0)
180	#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)	184
-		185	#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)

Subversion Repositories Kolibri OS

(root)/drivers/audio/a5536/pci.h – Rev 1028 → 1692