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        2.1.21  AVX instructions

        2.1.22  AVX2 instructions

        2.1.23  Auxiliary sets of computational instructions

        2.1.24  Other extensions of instruction set

  | xword    | 128  | 16    |

  | qqword   | 256  | 32    |

  | yword    | 256  | 32    |

  | SSE     | 128  | xmm0  xmm1  xmm2  xmm3  xmm4  xmm5  xmm6  xmm7 |

  |---------|------|------------------------------------------------|

The "rva" and "plt" are special unary operators that perform conversions

  The arithmetical and logical calculations are usually processed as if they

operated on infinite precision 2-adic numbers, and assembler signalizes an

overflow error if because of its limitations it is not table to perform the

required calculation, or if the result is too large number to fit in either

signed or unsigned range for the destination unit size. However "not", "xor"

and "shr" operators are exceptions from this rule - if the value specified

by numerical expression has to fit in a unit of specified size, and the

arguments for operation fit into that size, the operation will be performed

with precision limited to that size.

operation. The "fstenvw", "fnstenvw", "fldenvw", "fsavew", "fnsavew" and

"frstorw" mnemonics force the instruction to perform operation as in the 16-bit

mode, while "fstenvd", "fnstenvd", "fldenvd", "fsaved", "fnsaved" and "frstord"

force the operation as in 32-bit mode.

  "finit" and "fninit" set the FPU operating environment into its default

packed double precision floating point values, the source can be a 64-bit 

memory location or SSE register, destination has to be SSE register.

  "movdqa" and "movdqu" transfer a double quad word operand containing packed

SSE3 instructions (SSSE3). They generally follow the same rules for operands

as all the MMX operations extended by SSE.

  "phaddw" and "phaddd" perform the horizontal additional of the pairs of

adjacent values from both the source and destination operand, and stores the

sums into the destination (sums from the source operand go into lower part of

destination register). They operate on 16-bit or 32-bit chunks, respectively.

"phaddsw" performs the same operation on signed 16-bit packed values, but the

result of each addition is saturated. "phsubw" and "phsubd" analogously

perform the horizontal substraction of 16-bit or 32-bit packed value, and

"phsubsw" performs the horizontal substraction of signed 16-bit packed values

with saturation.

  "pabsb", "pabsw" and "pabsd" calculate the absolute value of each signed

packed signed value in source operand and stores them into the destination

register. They operator on 8-bit, 16-bit and 32-bit elements respectively.

  "pmaddubsw" multiplies signed 8-bit values from the source operand with the

corresponding unsigned 8-bit values from the destination operand to produce

intermediate 16-bit values, and every adjacent pair of those intermediate

values is then added horizontally and those 16-bit sums are stored into the

destination operand.

  "pmulhrsw" multiplies corresponding 16-bit integers from the source and

destination operand to produce intermediate 32-bit values, and the 16 bits

next to the highest bit of each of those values are then rounded and packed

into the destination operand.

  "pshufb" shuffles the bytes in the destination operand according to the

mask provided by source operand - each of the bytes in source operand is

an index of the target position for the corresponding byte in the destination.

  "psignb", "psignw" and "psignd" perform the operation on 8-bit, 16-bit or

32-bit integers in destination operand, depending on the signs of the values

in the source. If the value in source is negative, the corresponding value in

the destination register is negated, if the value in source is positive, no

operation is performed on the corresponding value is performed, and if the

value in source is zero, the value in destination is zeroed, too.

  "palignr" appends the source operand to the destination operand to form the

intermediate value of twice the size, and then extracts into the destination

register the 64 or 128 bits that are right-aligned to the byte offset

specified by the third operand, which should be an 8-bit immediate value. This

is the only SSSE3 instruction that takes three arguments.

instructions, available only in long mode, which use a different format of

storage area in order to store some pointers in full 64-bit size.  

  "swapgs" is the new instruction, which swaps the contents of GS register and

64-bit versions of "sysexit" and "sysret" instructions.

  The "rdmsrq" and "wrmsrq" mnemonics are the 64-bit variants of the "rdmsr"

and "wrmsr" instructions.

2.1.20  SSE4 instructions

There are actually three different sets of instructions under the name SSE4.

Intel designed two of them, SSE4.1 and SSE4.2, with latter extending the

former into the full Intel's SSE4 set. On the other hand, the implementation

by AMD includes only a few instructions from this set, but also contains

some additional instructions, that are called the SSE4a set.

  The SSE4.1 instructions mostly follow the same rules for operands, as

the basic SSE operations, so they require destination operand to be SSE

register and source operand to be 128-bit memory location or SSE register,

and some operations require a third operand, the 8-bit immediate value.

  "pmulld" performs a signed multiplication of the packed double words and

stores the low double words of the results in the destination operand.

"pmuldq" performs a two signed multiplications of the corresponding double

words in the lower quad words of operands, and stores the results as

packed quad words into the destination register. "pminsb" and "pmaxsb"

return the minimum or maximum values of packed signed bytes, "pminuw" and

"pmaxuw" return the minimum and maximum values of packed unsigned words,

"pminud", "pmaxud", "pminsd" and "pmaxsd" return minimum or maximum values

of packed unsigned or signed words. These instruction complement the

instructions computing packed minimum or maximum introduced by SSE.

  "ptest" sets the ZF flag to one when the result of bitwise AND of the

both operands is zero, and zeroes the ZF otherwise. It also sets CF flag

to one, when the result of bitwise AND of the destination operand with

the bitwise NOT of the source operand is zero, and zeroes the CF otherwise.

"pcmpeqq" compares packed quad words for equality, and fills the

corresponding elements of destination operand with either ones or zeros,

depending on the result of comparison.

  "packusdw" converts packed signed double words from both the source and

destination operand into the unsigned words using saturation, and stores

the eight resulting word values into the destination register.

  "phminposuw" finds the minimum unsigned word value in source operand and

places it into the lowest word of destination operand, setting the remaining

upper bits of destination to zero.

  "roundps", "roundss", "roundpd" and "roundsd" perform the rounding of packed

or individual floating point value of single or double precision, using the

rounding mode specified by the third operand.

    roundsd xmm0,xmm1,0011b ; round toward zero

  "dpps" calculates dot product of packed single precision floating point

values, that is it multiplies the corresponding pairs of values from source and

destination operand and then sums the products up. The high four bits of the

8-bit immediate third operand control which products are calculated and taken

to the sum, and the low four bits control, into which elements of destination

the resulting dot product is copied (the other elements are filled with zero).

"dppd" calculates dot product of packed double precision floating point values.

The bits 4 and 5 of third operand control, which products are calculated and

added, and bits 0 and 1 of this value control, which elements in destination

register should get filled with the result. "mpsadbw" calculates multiple sums

of absolute differences of unsigned bytes. The third operand controls, with

value in bits 0-1, which of the four-byte blocks in source operand is taken to

calculate the absolute differencies, and with value in bit 2, at which of the

two first four-byte block in destination operand start calculating multiple

sums. The sum is calculated from four absolute differencies between the

corresponding unsigned bytes in the source and destination block, and each next

sum is calculated in the same way, but taking the four bytes from destination

at the position one byte after the position of previous block. The four bytes

from the source stay the same each time. This way eight sums of absolute

differencies are calculated and stored as packed word values into the

destination operand. The instructions described in this paragraph follow the

same rules for operands, as "roundps" instruction.

  "blendps", "blendvps", "blendpd" and "blendvpd" conditionally copy the

values from source operand into the destination operand, depending on the bits

of the mask provided by third operand. If a mask bit is set, the corresponding

element of source is copied into the same place in destination, otherwise this

position is destination is left unchanged. The rules for the first two operands

are the same, as for general SSE instructions. "blendps" and "blendpd" need

third operand to be 8-bit immediate, and they operate on single or double

precision values, respectively. "blendvps" and "blendvpd" require third operand

to be the XMM0 register.

    blendvps xmm3,xmm7,xmm0 ; blend according to mask

  "pblendw" conditionally copies word elements from the source operand into the

destination, depending on the bits of mask provided by third operand, which

needs to be 8-bit immediate value. "pblendvb" conditionally copies byte

elements from the source operands into destination, depending on mask defined

by the third operand, which has to be XMM0 register. These instructions follow

the same rules for operands as "blendps" and "blendvps" instructions,

respectively.

  "insertps" inserts a single precision floating point value taken from the

position in source operand specified by bits 6-7 of third operand into location

in destination register selected by bits 4-5 of third operand. Additionally,

the low four bits of third operand control, which elements in destination

register will be set to zero. The first two operands follow the same rules as

for the general SSE operation, the third operand should be 8-bit immediate.

  "extractps" extracts a single precision floating point value taken from the

location in source operand specified by low two bits of third operand, and

stores it into the destination operand. The destination can be a 32-bit memory

value or general purpose register, the source operand must be SSE register,

and the third operand should be 8-bit immediate value.

    extractps edx,xmm3,3 ; extract the highest value

  "pinsrb", "pinsrd" and "pinsrq" copy a byte, double word or quad word from

the source operand into the location of destination operand determined by the

third operand. The destination operand has to be SSE register, the source

operand can be a memory location of appropriate size, or the 32-bit general

purpose register (but 64-bit general purpose register for "pinsrq", which is

only available in long mode), and the third operand has to be 8-bit immediate

value. These instructions complement the "pinsrw" instruction operating on SSE

register destination, which was introduced by SSE2.

    pinsrd xmm4,eax,1 ; insert double word into second position

  "pextrb", "pextrw", "pextrd" and "pextrq" copy a byte, word, double word or

quad word from the location in source operand specified by third operand, into

the destination. The source operand should be SSE register, the third operand

should be 8-bit immediate, and the destination operand can be memory location

of appropriate size, or the 32-bit general purpose register (but 64-bit general

purpose register for "pextrq", which is only available in long mode). The

"pextrw" instruction with SSE register as source was already introduced by

SSE2, but SSE4 extends it to allow memory operand as destination.

    pextrw [ebx],xmm3,7 ; extract highest word into memory

  "pmovsxbw" and "pmovzxbw" perform sign extension or zero extension of eight 

byte values from the source operand into packed word values in destination 

operand, which has to be SSE register. The source can be 64-bit memory or SSE 

register - when it is register, only its low portion is used. "pmovsxbd" and 

"pmovzxbd" perform sign extension or zero extension of the four byte values 

from the source operand into packed double word values in destination operand, 

the source can be 32-bit memory or SSE register. "pmovsxbq" and "pmovzxbq" 

perform sign extension or zero extension of the two byte values from the 

source operand into packed quad word values in destination operand, the source

can be 16-bit memory or SSE register. "pmovsxwd" and "pmovzxwd" perform sign

extension or zero extension of the four word values from the source operand 

into packed double words in destination operand, the source can be 64-bit 

memory or SSE register. "pmovsxwq" and "pmovzxwq" perform sign extension or 

zero extension of the two word values from the source operand into packed quad

words in destination operand, the source can be 32-bit memory or SSE register. 

"pmovsxdq" and "pmovzxdq" perform sign extension or zero extension of the two 

double word values from the source operand into packed quad words in 

destination operand, the source can be 64-bit memory or SSE register.

    pmovzxbq xmm0,word [si]  ; zero-extend bytes to quad words

    pmovsxwq xmm0,xmm1       ; sign-extend words to quad words 

  "movntdqa" loads double quad word from the source operand to the destination

using a non-temporal hint. The destination operand should be SSE register,

and the source operand should be 128-bit memory location.

  The SSE4.2, described below, adds not only some new operations on SSE

registers, but also introduces some completely new instructions operating on

general purpose registers only.

  "pcmpistri" compares two zero-ended (implicit length) strings provided in

its source and destination operand and generates an index stored to ECX;

"pcmpistrm" performs the same comparison and generates a mask stored to XMM0.

"pcmpestri" compares two strings of explicit lengths, with length provided

in EAX for the destination operand and in EDX for the source operand, and

generates an index stored to ECX; "pcmpestrm" performs the same comparision

and generates a mask stored to XMM0. The source and destination operand follow

the same rules as for general SSE instructions, the third operand should be

8-bit immediate value determining the details of performed operation - refer to

Intel documentation for information on those details.

  "pcmpgtq" compares packed quad words, and fills the corresponding elements of

destination operand with either ones or zeros, depending on whether the value

in destination is greater than the one in source, or not. This instruction

follows the same rules for operands as "pcmpeqq".

  "crc32" accumulates a CRC32 value for the source operand starting with

initial value provided by destination operand, and stores the result in

destination. Unless in long mode, the destination operand should be a 32-bit

general purpose register, and the source operand can be a byte, word, or double

word register or memory location. In long mode the destination operand can

also be a 64-bit general purpose register, and the source operand in such case

can be a byte or quad word register or memory location.

    crc32 eax,dl          ; accumulate CRC32 on byte value

    crc32 eax,word [ebx]  ; accumulate CRC32 on word value

    crc32 rax,qword [rbx] ; accumulate CRC32 on quad word value

  "popcnt" calculates the number of bits set in the source operand, which can

be 16-bit, 32-bit, or 64-bit general purpose register or memory location,

and stores this count in the destination operand, which has to be register of

the same size as source operand. The 64-bit variant is available only in long

mode.

    popcnt ecx,eax        ; count bits set to 1

  The SSE4a extension, which also includes the "popcnt" instruction introduced

by SSE4.2, at the same time adds the "lzcnt" instruction, which follows the

same syntax, and calculates the count of leading zero bits in source operand

(if the source operand is all zero bits, the total number of bits in source

operand is stored in destination).

  "extrq" extract the sequence of bits from the low quad word of SSE register

provided as first operand and stores them at the low end of this register,

filling the remaining bits in the low quad word with zeros. The position of bit

string and its length can either be provided with two 8-bit immediate values

as second and third operand, or by SSE register as second operand (and there

is no third operand in such case), which should contain position value in bits

8-13 and length of bit string in bits 0-5.

    extrq xmm0,8,7        ; extract 8 bits from position 7

    extrq xmm0,xmm5       ; extract bits defined by register

  "insertq" writes the sequence of bits from the low quad word of the source

operand into specified position in low quad word of the destination operand,

leaving the other bits in low quad word of destination intact. The position

where bits should be written and the length of bit string can either be

provided with two 8-bit immediate values as third and fourth operand, or by

the bit fields in source operand (and there are only two operands in such

case), which should contain position value in bits 72-77 and length of bit

string in bits 64-69.

    insertq xmm1,xmm0,4,2 ; insert 4 bits at position 2

    insertq xmm1,xmm0     ; insert bits defined by register

  "movntss" and "movntsd" store single or double precision floating point

value from the source SSE register into 32-bit or 64-bit destination memory

location respectively, using non-temporal hint.

2.1.21  AVX instructions

The Advanced Vector Extensions introduce instructions that are new variants 

of SSE instructions, with new scheme of encoding that allows extended syntax 

having a destination operand separate from all the source operands. It also 

introduces 256-bit AVX registers, which extend up the old 128-bit SSE 

registers. Any AVX instruction that puts some result into SSE register, puts 

zero bits into high portion of the AVX register containing it.

  The AVX version of SSE instruction has the mnemonic obtained by prepending

SSE instruction name with "v". For any SSE arithmetic instruction which had a

destination operand also being used as one of the source values, the AVX 

variant has a new syntax with three operands - the destination and two sources. 

The destination and first source can be SSE registers, and second source can be

SSE register or memory. If the operation is performed on single pair of values,

the remaining bits of first source SSE register are copied into the the 

destination register.

    vsubss xmm0,xmm2,xmm3         ; substract two 32-bit floats

    vmulsd xmm0,xmm7,qword [esi]  ; multiply two 64-bit floats 

In case of packed operations, each instruction can also operate on the 256-bit 

data size when the AVX registers are specified instead of SSE registers, and 

the size of memory operand is also doubled then.

    vaddps ymm1,ymm5,yword [esi]  ; eight sums of 32-bit float pairs 

The instructions that operate on packed integer types (in particular the ones

that earlier had been promoted from MMX to SSE) also acquired the new syntax

with three operands, however they are only allowed to operate on 128-bit 

packed types and thus cannot use the whole AVX registers.

    vpavgw xmm3,xmm0,xmm2         ; average of 16-bit integers

    vpslld xmm1,xmm0,1            ; shift double words left

If the SSE version of instruction had a syntax with three operands, the third

one being an immediate value, the AVX version of such instruction takes four

operands, with immediate remaining the last one.

    vshufpd ymm0,ymm1,ymm2,10010011b ; shuffle 64-bit floats

    vpalignr xmm0,xmm4,xmm2,3        ; extract byte aligned value

The promotion to new syntax according to the rules described above has been 

applied to all the instructions from SSE extensions up to SSE4, with the 

exceptions described below.   

  "vdppd" instruction has syntax extended to four operans, but it does not 

have a 256-bit version.

  The are a few instructions, namely "vsqrtpd", "vsqrtps", "vrcpps" and

"vrsqrtps", which can operate on 256-bit data size, but retained the syntax 

with only two operands, because they use data from only one source:

    vsqrtpd ymm1,ymm0         ; put square roots into other register

In a similar way "vroundpd" and "vroundps" retained the syntax with three 

operands, the last one being immediate value.   

    vroundps ymm0,ymm1,0011b  ; round toward zero

  Also some of the operations on packed integers kept their two-operand or

three-operand syntax while being promoted to AVX version. In such case these

instructions follow exactly the same rules for operands as their SSE 

counterparts (since operations on packed integers do not have 256-bit variants

in AVX extension). These include "vpcmpestri", "vpcmpestrm", "vpcmpistri",

"vpcmpistrm", "vphminposuw", "vpshufd", "vpshufhw", "vpshuflw". And there are 

more instructions that in AVX versions keep exactly the same syntax for 

operands as the one from SSE, without any additional options: "vcomiss", 

"vcomisd", "vcvtss2si", "vcvtsd2si", "vcvttss2si", "vcvttsd2si", "vextractps", 

"vpextrb", "vpextrw", "vpextrd", "vpextrq", "vmovd", "vmovq", "vmovntdqa", 

"vmaskmovdqu", "vpmovmskb", "vpmovsxbw", "vpmovsxbd", "vpmovsxbq", "vpmovsxwd", 

"vpmovsxwq", "vpmovsxdq", "vpmovzxbw", "vpmovzxbd", "vpmovzxbq", "vpmovzxwd", 

"vpmovzxwq" and "vpmovzxdq".

  The move and conversion instructions have mostly been promoted to allow

256-bit size operands in addition to the 128-bit variant with syntax identical

to that from SSE version of the same instruction. Each of the "vcvtdq2ps", 

"vcvtps2dq" and "vcvttps2dq", "vmovaps", "vmovapd", "vmovups", "vmovupd",

"vmovdqa", "vmovdqu", "vlddqu", "vmovntps", "vmovntpd", "vmovntdq", 

"vmovsldup", "vmovshdup", "vmovmskps" and "vmovmskpd" inherits the 128-bit 

syntax from SSE without any changes, and also allows a new form with 256-bit 

operands in place of 128-bit ones.  

    vmovups [edi],ymm6        ; store unaligned 256-bit data

  "vmovddup" has the identical 128-bit syntax as its SSE version, and it also 

has a 256-bit version, which stores the duplicates of the lowest quad word 

from the source operand in the lower half of destination operand, and in the 

upper half of destination the duplicates of the low quad word from the upper 

half of source. Both source and destination operands need then to be 256-bit 

values.

  "vmovlhps" and "vmovhlps" have only 128-bit versions, and each takes three

operands, which all must be SSE registers. "vmovlhps" copies two single 

precision values from the low quad word of second source register to the high 

quad word of destination register, and copies the low quad word of first 

source register into the low quad word of destination register. "vmovhlps" 

copies two single  precision values from the high quad word of second source 

register to the low quad word of destination register, and copies the high 

quad word of first source register into the high quad word of destination 

register. 

  "vmovlps", "vmovhps", "vmovlpd" and "vmovhpd" have only 128-bit versions and

their syntax varies depending on whether memory operand is a destination or

source. When memory is destination, the syntax is identical to the one of

equivalent SSE instruction, and when memory is source, the instruction requires

three operands, first two being SSE registers and the third one 64-bit memory.

The value put into destination is then the value copied from first source with

either low or high quad word replaced with value from second source (the

memory operand).

    vmovhps [esi],xmm7       ; store upper half to memory

    vmovlps xmm0,xmm7,[ebx]  ; low from memory, rest from register  

  "vmovss" and "vmovsd" have syntax identical to their SSE equivalents as long

as one of the operands is memory, while the versions that operate purely on 

registers require three operands (each being SSE register). The value stored

in destination is then the value copied from first source with lowest data

element replaced with the lowest value from second source.

    vmovss xmm3,[edi]        ; low from memory, rest zeroed

    vmovss xmm0,xmm1,xmm2    ; one value from xmm2, three from xmm1 

  "vcvtss2sd", "vcvtsd2ss", "vcvtsi2ss" and "vcvtsi2d" use the three-operand

syntax, where destination and first source are always SSE registers, and the

second source follows the same rules and the source in syntax of equivalent

SSE instruction. The value stored in destination is then the value copied from

first source with lowest data element replaced with the result of conversion. 

    vcvtsi2sd xmm4,xmm4,ecx  ; 32-bit integer to 64-bit float

    vcvtsi2ss xmm0,xmm0,rax  ; 64-bit integer to 32-bit float

  "vcvtdq2pd" and "vcvtps2pd" allow the same syntax as their SSE equivalents, 

plus the new variants with AVX register as destination and SSE register or 

128-bit memory as source. Analogously "vcvtpd2dq", "vcvttpd2dq" and 

"vcvtpd2ps", in addition to variant with syntax identical to SSE version, 

allow a variant with SSE register as destination and AVX register or 256-bit 

memory as source.          

  "vinsertps", "vpinsrb", "vpinsrw", "vpinsrd", "vpinsrq" and "vpblendw" use 

a syntax with four operands, where destination and first source have to be SSE

registers, and the third and fourth operand follow the same rules as second 

and third operand in the syntax of equivalent SSE instruction. Value stored in 

destination is the the value copied from first source with some data elements 

replaced with values extracted from the second source, analogously to the 

operation of corresponding SSE instruction.   

    vpinsrd xmm0,xmm0,eax,3  ; insert double word

  "vblendvps", "vblendvpd" and "vpblendvb" use a new syntax with four register

operands: destination, two sources and a mask, where second source can also be

a memory operand. "vblendvps" and "vblendvpd" have 256-bit variant, where 

operands are AVX registers or 256-bit memory, as well as 128-bit variant, 

which has operands being SSE registers or 128-bit memory. "vpblendvb" has only

a 128-bit variant. Value stored in destination is the value copied from the

first source with some data elements replaced, according to mask, by values 

from the second source.

    vblendvps ymm3,ymm1,ymm2,ymm7  ; blend according to mask     

  "vptest" allows the same syntax as its SSE version and also has a 256-bit

version, with both operands doubled in size. There are also two new 

instructions, "vtestps" and "vtestpd", which perform analogous tests, but only

of the sign bits of corresponding single precision or double precision values,

and set the ZF and CF accordingly. They follow the same syntax rules as 

"vptest".

    vptest ymm0,yword [ebx]  ; test 256-bit values

    vtestpd xmm0,xmm1        ; test sign bits of 64-bit floats

  "vbroadcastss", "vbroadcastsd" and "vbroadcastf128" are new instructions, 

which broadcast the data element defined by source operand into all elements

of corresponing size in the destination register. "vbroadcastss" needs

source to be 32-bit memory and destination to be either SSE or AVX register. 

"vbroadcastsd" requires 64-bit memory as source, and AVX register as 

destination. "vbroadcastf128" requires 128-bit memory as source, and AVX

register as destination.

    vbroadcastss ymm0,dword [eax]  ; get eight copies of value          

  "vinsertf128" is the new instruction, which takes four operands. The

destination and first source have to be AVX registers, second source can be 

SSE register or 128-bit memory location, and fourth operand should be an 

immediate value. It stores in destination the value obtained by taking 

contents of first source and replacing one of its 128-bit units with value of

the second source. The lowest bit of fourth operand specifies at which 

position that replacement is done (either 0 or 1). 

  "vextractf128" is the new instruction with three operands. The destination

needs to be SSE register or 128-bit memory location, the source must be AVX

register, and the third operand should be an immediate value. It extracts

into destination one of the 128-bit units from source. The lowest bit of third

operand specifies, which unit is extracted.  

  "vmaskmovps" and "vmaskmovpd" are the new instructions with three operands

that selectively store in destination the elements from second source 

depending on the sign bits of corresponding elements from first source. These

instructions can operate on either 128-bit data (SSE registers) or 256-bit 

data (AVX registers). Either destination or second source has to be a memory

location of appropriate size, the two other operands should be registers.   

    vmaskmovps [edi],xmm0,xmm5  ; conditionally store

    vmaskmovpd ymm5,ymm0,[esi]  ; conditionally load   

  "vpermilpd" and "vpermilps" are the new instructions with three operands 

that permute the values from first source according to the control fields from 

second source and put the result into destination operand. It allows to use

either three SSE registers or three AVX registers as its operands, the second

source can be a memory of size equal to the registers used. In alternative

form the second source can be immediate value and then the first source

can be a memory location of the size equal to destination register.

  "vperm2f128" is the new instruction with four operands, which selects 

128-bit blocks of floating point data from first and second source according

to the bit fields from fourth operand, and stores them in destination.

Destination and first source need to be AVX registers, second source can be

AVX register or 256-bit memory area, and fourth operand should be an immediate

value.

    vperm2f128 ymm0,ymm6,ymm7,12h  ; permute 128-bit blocks

  "vzeroall" instruction sets all the AVX registers to zero. "vzeroupper" sets

the upper 128-bit portions of all AVX registers to zero, leaving the SSE 

registers intact. These new instructions take no operands.

  "vldmxcsr" and "vstmxcsr" are the AVX versions of "ldmxcsr" and "stmxcsr"

instructions. The rules for their operands remain unchanged.  

2.1.22  AVX2 instructions

The AVX2 extension allows all the AVX instructions operating on packed integers

to use 256-bit data types, and introduces some new instructions as well.

  The AVX instructions that operate on packed integers and had only a 128-bit

variants, have been supplemented with 256-bit variants, and thus their syntax

rules became analogous to AVX instructions operating on packed floating point

types.

    vpsubb ymm0,ymm0,[esi]   ; substract 32 packed bytes

    vpavgw ymm3,ymm0,ymm2    ; average of 16-bit integers

However there are some instructions that have not been equipped with the 

256-bit variants. "vpcmpestri", "vpcmpestrm", "vpcmpistri", "vpcmpistrm", 

"vpextrb", "vpextrw", "vpextrd", "vpextrq", "vpinsrb", "vpinsrw", "vpinsrd", 

"vpinsrq" and "vphminposuw" are not affected by AVX2 and allow only the 

128-bit operands.

  The packed shift instructions, which allowed the third operand specifying

amount to be SSE register or 128-bit memory location, use the same rules

for the third operand in their 256-bit variant.

    vpsllw ymm2,ymm2,xmm4        ; shift words left

    vpsrad ymm0,ymm3,xword [ebx] ; shift double words right

  There are also new packed shift instructions with standard three-operand AVX

syntax, which shift each element from first source by the amount specified in 

corresponding element of second source, and store the results in destination. 

"vpsllvd" shifts 32-bit elements left, "vpsllvq" shifts 64-bit elements left, 

"vpsrlvd" shifts 32-bit elements right logically, "vpsrlvq" shifts 64-bit 

elements right logically and "vpsravd" shifts 32-bit elements right 

arithmetically.

  The sign-extend and zero-extend instructions, which in AVX versions allowed

source operand to be SSE register or a memory of specific size, in the new

256-bit variant need memory of that size doubled or SSE register as source and

AVX register as destination.

    vpmovzxbq ymm0,dword [esi]   ; bytes to quad words

  Also "vmovntdqa" has been upgraded with 256-bit variant, so it allows to 

transfer 256-bit value from memory to AVX register, it needs memory address 

to be aligned to 32 bytes.   

  "vpmaskmovd" and "vpmaskmovq" are the new instructions with syntax identical

to "vmaskmovps" or "vmaskmovpd", and they performs analogous operation on

packed 32-bit or 64-bit values.    

  "vinserti128", "vextracti128", "vbroadcasti128" and "vperm2i128" are the new 

instructions with syntax identical to "vinsertf128", "vextractf128",

"vbroadcastf128" and "vperm2f128" respectively, and they perform analogous 

operations on 128-bit blocks of integer data.

  "vbroadcastss" and "vbroadcastsd" instructions have been extended to allow

SSE register as a source operand (which in AVX could only be a memory).

  "vpbroadcastb", "vpbroadcastw", "vpbroadcastd" and "vpbroadcastq" are the 

new instructions which broadcast the byte, word, double word or quad word from

the source operand into all elements of corresponing size in the destination 

register. The destination operand can be either SSE or AVX register, and the

source operand can be SSE register or memory of size equal to the size of data

element.

    vpbroadcastb ymm0,byte [ebx]  ; get 32 identical bytes

  "vpermd" and "vpermps" are new three-operand instructions, which use each 

32-bit element from first source as an index of element in second source which

is copied into destination at position corresponding to element containing

index. The destination and first source have to be AVX registers, and the

second source can be AVX register or 256-bit memory.

  "vpermq" and "vpermpd" are new three-operand instructions, which use 2-bit

indexes from the immediate value specified as third operand to determine which

element from source store at given position in destination. The destination

has to be AVX register, source can be AVX register or 256-bit memory, and the

third operand must be 8-bit immediate value.    

  The family of new instructions performing "gather" operation have special

syntax, as in their memory operand they use addressing mode that is unique to

them. The base of address can be a 32-bit or 64-bit general purpose register

(the latter only in long mode), and the index (possibly multiplied by scale

value, as in standard addressing) is specified by SSE or AVX register. It is

possible to use only index without base and any numerical displacement can be