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/* Opcode decoder for the Renesas RX
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/* Opcode decoder for the Renesas RX
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   Copyright 2008, 2009, 2010
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   Free Software Foundation, Inc.
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   Copyright (C) 2008-2015 Free Software Foundation, Inc.
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   Written by DJ Delorie 
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   Written by DJ Delorie 
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   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
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   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
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/* The RX decoder in libopcodes is used by the simulator, gdb's
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/* The RX decoder in libopcodes is used by the simulator, gdb's
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   analyzer, and the disassembler.  Given an opcode data source,
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   analyzer, and the disassembler.  Given an opcode data source,
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   it decodes the next opcode into the following structures.  */
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#ifdef __cplusplus
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extern "C" {
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   it decodes the next opcode into the following structures.  */
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#endif
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typedef enum
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typedef enum
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{
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{
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  RX_AnySize = 0,
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  RX_AnySize = 0,
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  RX_Word, /* undefined extension */
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  RX_Word, /* undefined extension */
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  RX_UWord,
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  RX_UWord,
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  RX_SWord,
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  RX_SWord,
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  RX_3Byte,
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  RX_3Byte,
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  RX_Long,
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  RX_Long,
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  RX_Bad_Size,
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  RX_MAX_SIZE
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} RX_Size;
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} RX_Size;
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typedef enum
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typedef enum
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{
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{
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  RX_Operand_None,
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  RX_Operand_None,
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  RX_Operand_Immediate,	/* #addend */
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  RX_Operand_Immediate,	/* #addend */
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  RX_Operand_Register,	/* Rn */
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  RX_Operand_Register,	/* Rn */
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  RX_Operand_Indirect,	/* [Rn + addend] */
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  RX_Operand_Indirect,	/* [Rn + addend] */
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  RX_Operand_Zero_Indirect,/* [Rn] */
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  RX_Operand_Postinc,	/* [Rn+] */
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  RX_Operand_Postinc,	/* [Rn+] */
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  RX_Operand_Predec,	/* [-Rn] */
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  RX_Operand_Predec,	/* [-Rn] */
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  RX_Operand_Condition,	/* eq, gtu, etc */
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  RX_Operand_Condition,	/* eq, gtu, etc */
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  RX_Operand_Flag,	/* [UIOSZC] */
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  RX_Operand_Flag,	/* [UIOSZC] */
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  RXO_jsrrel,	/* pc += d */
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  RXO_jsrrel,	/* pc += d */
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  RXO_rts,
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  RXO_rts,
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  RXO_nop,
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  RXO_nop,
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  RXO_nop2,
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  RXO_nop2,
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  RXO_nop3,
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  RXO_nop3,
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  RXO_nop4,
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  RXO_nop5,
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  RXO_nop6,
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  RXO_nop7,
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  RXO_scmpu,
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  RXO_scmpu,
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  RXO_smovu,
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  RXO_smovu,
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  RXO_smovb,
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  RXO_smovb,
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   Register numbers 0..15 are general registers.  16..31 are control
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   Register numbers 0..15 are general registers.  16..31 are control
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   registers.  32..47 are condition codes.  */
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   registers.  32..47 are condition codes.  */
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int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
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#ifdef __cplusplus