WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/opcode/i386.h


/* opcode/i386.h -- Intel 80386 opcode macros
 
 
   Copyright (C) 1989-2015 Free Software Foundation, Inc.
 
   This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */
 
/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
   ix86 Unix assemblers, generate floating point instructions with
   reversed source and destination registers in certain cases.
   Unfortunately, gcc and possibly many other programs use this
   reversed syntax, so we're stuck with it.
 
   eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
   `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
   the expected st(3) = st(3) - st
 
   This happens with all the non-commutative arithmetic floating point
   operations with two register operands, where the source register is
   %st, and destination register is %st(i).
 
   The affected opcode map is dceX, dcfX, deeX, defX.  */
 
#ifndef OPCODE_I386_H
#define OPCODE_I386_H
 
#ifndef SYSV386_COMPAT
/* Set non-zero for broken, compatible instructions.  Set to zero for
   non-broken opcodes at your peril.  gcc generates SystemV/386
   compatible instructions.  */
#define SYSV386_COMPAT 1
#endif
#ifndef OLDGCC_COMPAT
/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
   generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
   reversed.  */
#define OLDGCC_COMPAT SYSV386_COMPAT
#endif
 
#define MOV_AX_DISP32 0xa0
#define POP_SEG_SHORT 0x07
#define JUMP_PC_RELATIVE 0xeb
#define INT_OPCODE  0xcd
#define INT3_OPCODE 0xcc
/* The opcode for the fwait instruction, which disassembler treats as a
   prefix when it can.  */
#define FWAIT_OPCODE 0x9b
 
/* Instruction prefixes.
   NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
   part of the opcode.  Other prefixes may still appear between them
   and the 0x0f part of the opcode.  */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0
#define CS_PREFIX_OPCODE 0x2e
#define DS_PREFIX_OPCODE 0x3e
#define ES_PREFIX_OPCODE 0x26
#define FS_PREFIX_OPCODE 0x64
#define GS_PREFIX_OPCODE 0x65
#define SS_PREFIX_OPCODE 0x36
#define REPNE_PREFIX_OPCODE 0xf2
#define REPE_PREFIX_OPCODE  0xf3
#define XACQUIRE_PREFIX_OPCODE 0xf2
#define XRELEASE_PREFIX_OPCODE 0xf3
#define BND_PREFIX_OPCODE 0xf2
 
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90
 
/* register numbers */
#define EAX_REG_NUM 0
#define ECX_REG_NUM 1
#define EDX_REG_NUM 2
#define EBX_REG_NUM 3
#define ESP_REG_NUM 4
#define EBP_REG_NUM 5
#define ESI_REG_NUM 6
#define EDI_REG_NUM 7
 
/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
/* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
#define NO_BASE_REGISTER_16 6
 
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 
/* Extract fields from the mod/rm byte.  */
#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
#define MODRM_RM_FIELD(modrm)  (((modrm) >> 0) & 7)
 
/* Extract fields from the sib byte.  */
#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
#define SIB_BASE_FIELD(sib)  (((sib) >> 0) & 7)
 
/* x86-64 extension prefix.  */
#define REX_OPCODE	0x40
 
/* Non-zero if OPCODE is the rex prefix.  */
#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
 
/* Indicates 64 bit operand size.  */
#define REX_W	8
/* High extension to reg field of modrm byte.  */
#define REX_R	4
/* High extension to SIB index field.  */
#define REX_X	2
/* High extension to base field of modrm or SIB, or reg field of opcode.  */
#define REX_B	1
 
/* max operands per insn */
#define MAX_OPERANDS 5
 
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
#define MAX_IMMEDIATE_OPERANDS 2
 
/* max memory refs per insn (string ops) */
#define MAX_MEMORY_OPERANDS 2
 
/* max size of insn mnemonics.  */
#define MAX_MNEM_SIZE 20
 
/* max size of register name in insn mnemonics.  */
#define MAX_REG_NAME_SIZE 8
 
#endif /* OPCODE_I386_H */

Subversion Repositories Kolibri OS

(root)/contrib/toolchain/binutils/include/opcode/i386.h – Rev 5191 → 6324

Rev 5191		Rev 6324
1	/* opcode/i386.h -- Intel 80386 opcode macros	1	/* opcode/i386.h -- Intel 80386 opcode macros
2	Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,	-
3	2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010	-
4	Free Software Foundation, Inc.	2	Copyright (C) 1989-2015 Free Software Foundation, Inc.
5		3
6	This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.	4	This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
7		5
8	This program is free software; you can redistribute it and/or modify	6	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by	7	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 3 of the License, or	8	the Free Software Foundation; either version 3 of the License, or
11	(at your option) any later version.	9	(at your option) any later version.
12		10
13	This program is distributed in the hope that it will be useful,	11	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.	14	GNU General Public License for more details.
17		15
18	You should have received a copy of the GNU General Public License	16	You should have received a copy of the GNU General Public License
19	along with this program; if not, write to the Free Software	17	along with this program; if not, write to the Free Software
20	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,	18	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21	MA 02110-1301, USA. */	19	MA 02110-1301, USA. */
22		20
23	/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived	21	/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
24	ix86 Unix assemblers, generate floating point instructions with	22	ix86 Unix assemblers, generate floating point instructions with
25	reversed source and destination registers in certain cases.	23	reversed source and destination registers in certain cases.
26	Unfortunately, gcc and possibly many other programs use this	24	Unfortunately, gcc and possibly many other programs use this
27	reversed syntax, so we're stuck with it.	25	reversed syntax, so we're stuck with it.
28		26
29	eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but	27	eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
30	`fsub %st,%st(3)' results in st(3) = st - st(3), rather than	28	`fsub %st,%st(3)' results in st(3) = st - st(3), rather than
31	the expected st(3) = st(3) - st	29	the expected st(3) = st(3) - st
32		30
33	This happens with all the non-commutative arithmetic floating point	31	This happens with all the non-commutative arithmetic floating point
34	operations with two register operands, where the source register is	32	operations with two register operands, where the source register is
35	%st, and destination register is %st(i).	33	%st, and destination register is %st(i).
36		34
37	The affected opcode map is dceX, dcfX, deeX, defX. */	35	The affected opcode map is dceX, dcfX, deeX, defX. */
38		36
39	#ifndef OPCODE_I386_H	37	#ifndef OPCODE_I386_H
40	#define OPCODE_I386_H	38	#define OPCODE_I386_H
41		39
42	#ifndef SYSV386_COMPAT	40	#ifndef SYSV386_COMPAT
43	/* Set non-zero for broken, compatible instructions. Set to zero for	41	/* Set non-zero for broken, compatible instructions. Set to zero for
44	non-broken opcodes at your peril. gcc generates SystemV/386	42	non-broken opcodes at your peril. gcc generates SystemV/386
45	compatible instructions. */	43	compatible instructions. */
46	#define SYSV386_COMPAT 1	44	#define SYSV386_COMPAT 1
47	#endif	45	#endif
48	#ifndef OLDGCC_COMPAT	46	#ifndef OLDGCC_COMPAT
49	/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could	47	/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
50	generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands	48	generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
51	reversed. */	49	reversed. */
52	#define OLDGCC_COMPAT SYSV386_COMPAT	50	#define OLDGCC_COMPAT SYSV386_COMPAT
53	#endif	51	#endif
54		52
55	#define MOV_AX_DISP32 0xa0	53	#define MOV_AX_DISP32 0xa0
56	#define POP_SEG_SHORT 0x07	54	#define POP_SEG_SHORT 0x07
57	#define JUMP_PC_RELATIVE 0xeb	55	#define JUMP_PC_RELATIVE 0xeb
58	#define INT_OPCODE 0xcd	56	#define INT_OPCODE 0xcd
59	#define INT3_OPCODE 0xcc	57	#define INT3_OPCODE 0xcc
60	/* The opcode for the fwait instruction, which disassembler treats as a	58	/* The opcode for the fwait instruction, which disassembler treats as a
61	prefix when it can. */	59	prefix when it can. */
62	#define FWAIT_OPCODE 0x9b	60	#define FWAIT_OPCODE 0x9b
63		61
64	/* Instruction prefixes.	62	/* Instruction prefixes.
65	NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as	63	NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
66	part of the opcode. Other prefixes may still appear between them	64	part of the opcode. Other prefixes may still appear between them
67	and the 0x0f part of the opcode. */	65	and the 0x0f part of the opcode. */
68	#define ADDR_PREFIX_OPCODE 0x67	66	#define ADDR_PREFIX_OPCODE 0x67
69	#define DATA_PREFIX_OPCODE 0x66	67	#define DATA_PREFIX_OPCODE 0x66
70	#define LOCK_PREFIX_OPCODE 0xf0	68	#define LOCK_PREFIX_OPCODE 0xf0
71	#define CS_PREFIX_OPCODE 0x2e	69	#define CS_PREFIX_OPCODE 0x2e
72	#define DS_PREFIX_OPCODE 0x3e	70	#define DS_PREFIX_OPCODE 0x3e
73	#define ES_PREFIX_OPCODE 0x26	71	#define ES_PREFIX_OPCODE 0x26
74	#define FS_PREFIX_OPCODE 0x64	72	#define FS_PREFIX_OPCODE 0x64
75	#define GS_PREFIX_OPCODE 0x65	73	#define GS_PREFIX_OPCODE 0x65
76	#define SS_PREFIX_OPCODE 0x36	74	#define SS_PREFIX_OPCODE 0x36
77	#define REPNE_PREFIX_OPCODE 0xf2	75	#define REPNE_PREFIX_OPCODE 0xf2
78	#define REPE_PREFIX_OPCODE 0xf3	76	#define REPE_PREFIX_OPCODE 0xf3
79	#define XACQUIRE_PREFIX_OPCODE 0xf2	77	#define XACQUIRE_PREFIX_OPCODE 0xf2
80	#define XRELEASE_PREFIX_OPCODE 0xf3	78	#define XRELEASE_PREFIX_OPCODE 0xf3
81	#define BND_PREFIX_OPCODE 0xf2	79	#define BND_PREFIX_OPCODE 0xf2
82		80
83	#define TWO_BYTE_OPCODE_ESCAPE 0x0f	81	#define TWO_BYTE_OPCODE_ESCAPE 0x0f
84	#define NOP_OPCODE (char) 0x90	82	#define NOP_OPCODE (char) 0x90
85		83
86	/* register numbers */	84	/* register numbers */
87	#define EAX_REG_NUM 0	85	#define EAX_REG_NUM 0
88	#define ECX_REG_NUM 1	86	#define ECX_REG_NUM 1
89	#define EDX_REG_NUM 2	87	#define EDX_REG_NUM 2
90	#define EBX_REG_NUM 3	88	#define EBX_REG_NUM 3
91	#define ESP_REG_NUM 4	89	#define ESP_REG_NUM 4
92	#define EBP_REG_NUM 5	90	#define EBP_REG_NUM 5
93	#define ESI_REG_NUM 6	91	#define ESI_REG_NUM 6
94	#define EDI_REG_NUM 7	92	#define EDI_REG_NUM 7
95		93
96	/* modrm_byte.regmem for twobyte escape */	94	/* modrm_byte.regmem for twobyte escape */
97	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM	95	#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
98	/* index_base_byte.index for no index register addressing */	96	/* index_base_byte.index for no index register addressing */
99	#define NO_INDEX_REGISTER ESP_REG_NUM	97	#define NO_INDEX_REGISTER ESP_REG_NUM
100	/* index_base_byte.base for no base register addressing */	98	/* index_base_byte.base for no base register addressing */
101	#define NO_BASE_REGISTER EBP_REG_NUM	99	#define NO_BASE_REGISTER EBP_REG_NUM
102	#define NO_BASE_REGISTER_16 6	100	#define NO_BASE_REGISTER_16 6
103		101
104	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */	102	/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
105	#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */	103	#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
106	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)	104	#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
107		105
108	/* Extract fields from the mod/rm byte. */	106	/* Extract fields from the mod/rm byte. */
109	#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)	107	#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
110	#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)	108	#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
111	#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)	109	#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
112		110
113	/* Extract fields from the sib byte. */	111	/* Extract fields from the sib byte. */
114	#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)	112	#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
115	#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)	113	#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
116	#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)	114	#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
117		115
118	/* x86-64 extension prefix. */	116	/* x86-64 extension prefix. */
119	#define REX_OPCODE 0x40	117	#define REX_OPCODE 0x40
120		118
121	/* Non-zero if OPCODE is the rex prefix. */	119	/* Non-zero if OPCODE is the rex prefix. */
122	#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)	120	#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
123		121
124	/* Indicates 64 bit operand size. */	122	/* Indicates 64 bit operand size. */
125	#define REX_W 8	123	#define REX_W 8
126	/* High extension to reg field of modrm byte. */	124	/* High extension to reg field of modrm byte. */
127	#define REX_R 4	125	#define REX_R 4
128	/* High extension to SIB index field. */	126	/* High extension to SIB index field. */
129	#define REX_X 2	127	#define REX_X 2
130	/* High extension to base field of modrm or SIB, or reg field of opcode. */	128	/* High extension to base field of modrm or SIB, or reg field of opcode. */
131	#define REX_B 1	129	#define REX_B 1
132		130
133	/* max operands per insn */	131	/* max operands per insn */
134	#define MAX_OPERANDS 5	132	#define MAX_OPERANDS 5
135		133
136	/* max immediates per insn (lcall, ljmp, insertq, extrq) */	134	/* max immediates per insn (lcall, ljmp, insertq, extrq) */
137	#define MAX_IMMEDIATE_OPERANDS 2	135	#define MAX_IMMEDIATE_OPERANDS 2
138		136
139	/* max memory refs per insn (string ops) */	137	/* max memory refs per insn (string ops) */
140	#define MAX_MEMORY_OPERANDS 2	138	#define MAX_MEMORY_OPERANDS 2
141		139
142	/* max size of insn mnemonics. */	140	/* max size of insn mnemonics. */
143	#define MAX_MNEM_SIZE 20	141	#define MAX_MNEM_SIZE 20
144		142
145	/* max size of register name in insn mnemonics. */	143	/* max size of register name in insn mnemonics. */
146	#define MAX_REG_NAME_SIZE 8	144	#define MAX_REG_NAME_SIZE 8
147		145
148	#endif /* OPCODE_I386_H */	146	#endif /* OPCODE_I386_H */