WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/opcode/d30v.h


/* d30v.h -- Header file for D30V opcode table
 
   Copyright (C) 1997-2015 Free Software Foundation, Inc.
   Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
 
   This file is part of GDB, GAS, and the GNU binutils.
 
   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version 3,
   or (at your option) any later version.
 
   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING3.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */
 
#ifndef D30V_H
#define D30V_H
 
#define NOP 0x00F00000
 
/* Structure to hold information about predefined registers.  */
struct pd_reg
{
  char *name;		/* name to recognize */
  char *pname;		/* name to print for this register */
  int value;
};
 
extern const struct pd_reg pre_defined_registers[];
int reg_name_cnt (void);
 
/* the number of control registers */
#define MAX_CONTROL_REG	64
 
/* define the format specifiers */
#define FM00	0
#define FM01	0x80000000
#define FM10	0x8000000000000000LL
#define FM11	0x8000000080000000LL
 
/* define the opcode classes */
#define BRA	0
#define LOGIC	1
#define IMEM	2
#define IALU1	4
#define IALU2	5
 
/* define the execution condition codes */
#define ECC_AL	0	/* ALways (default) */
#define ECC_TX	1	/* F0=True, F1=Don't care */
#define ECC_FX	2	/* F0=False, F1=Don't care */
#define ECC_XT	3	/* F0=Don't care, F1=True */
#define ECC_XF	4	/* F0=Don't care, F1=False */
#define ECC_TT	5	/* F0=True, F1=True */
#define ECC_TF	6	/* F0=True, F1=False */
#define ECC_RESERVED	7	/* reserved */
#define ECC_MAX	ECC_RESERVED
 
extern const char *d30v_ecc_names[];
 
/* condition code table for CMP and CMPU */
extern const char *d30v_cc_names[];
 
/* The opcode table is an array of struct d30v_opcode.  */
struct d30v_opcode
{
  /* The opcode name.  */
  const char *name;
 
  /* the opcode */
  int op1;	/* first part, "IALU1" for example */
  int op2;	/* the rest of the opcode */
 
  /* opcode format(s).  These numbers correspond to entries */
  /* in the d30v_format_table */
  unsigned char format[4];
 
#define SHORT_M		1
#define SHORT_M2	5	/* for ld2w and st2w */
#define SHORT_A		9
#define SHORT_B1	11
#define SHORT_B2	12
#define SHORT_B2r     13
#define SHORT_B3      14
#define SHORT_B3r     16
#define SHORT_B3b     18
#define SHORT_B3br    20
#define SHORT_D1r     22
#define SHORT_D2      24
#define SHORT_D2r     26
#define SHORT_D2Br    28
#define SHORT_U       30      /* unary SHORT_A.  ABS for example */
#define SHORT_F       31      /* SHORT_A with flag registers */
#define SHORT_AF      33      /* SHORT_A with only the first register a flag register */
#define SHORT_T       35      /* for trap instruction */
#define SHORT_A5      36      /* SHORT_A with a 5-bit immediate instead of 6 */
#define SHORT_CMP     38      /* special form for CMPcc */
#define SHORT_CMPU    40      /* special form for CMPUcc */
#define SHORT_A1      42      /* special form of SHORT_A for MACa opcodes where a=1 */
#define SHORT_AA      44      /* SHORT_A with the first register an accumulator */
#define SHORT_RA      46      /* SHORT_A with the second register an accumulator */
#define SHORT_MODINC  48      
#define SHORT_MODDEC  49
#define SHORT_C1      50
#define SHORT_C2      51
#define SHORT_UF      52
#define SHORT_A2      53
#define SHORT_NONE    55      /* no operands */
#define SHORT_AR      56      /* like SHORT_AA but only accept register as third parameter  */
#define LONG          57
#define LONG_U        58      /* unary LONG */
#define LONG_Ur       59      /* LONG pc-relative */
#define LONG_CMP      60      /* special form for CMPcc and CMPUcc */
#define LONG_M        61      /* Memory long for ldb, stb */
#define LONG_M2       62      /* Memory long for ld2w, st2w */
#define LONG_2        63      /* LONG with 2 operands; jmptnz */
#define LONG_2r       64      /* LONG with 2 operands; bratnz */
#define LONG_2b       65      /* LONG_2 with modifier of 3 */
#define LONG_2br      66      /* LONG_2r with modifier of 3 */
#define LONG_D        67      /* for DJMPI */
#define LONG_Dr       68      /* for DBRAI */
#define LONG_Dbr      69      /* for repeati */
 
  /* the execution unit(s) used */
  int unit;
#define EITHER	0
#define IU	1
#define MU	2
#define EITHER_BUT_PREFER_MU 3
 
  /* this field is used to decide if two instructions */
  /* can be executed in parallel */
  long flags_used;
  long flags_set;
#define FLAG_0		(1L<<0)
#define FLAG_1		(1L<<1)
#define FLAG_2		(1L<<2)
#define FLAG_3		(1L<<3)
#define FLAG_4		(1L<<4)		/* S (saturation) */
#define FLAG_5		(1L<<5)		/* V (overflow) */
#define FLAG_6		(1L<<6)		/* VA (accumulated overflow) */
#define FLAG_7		(1L<<7)		/* C (carry/borrow) */
#define FLAG_SM		(1L<<8)		/* SM (stack mode) */
#define FLAG_RP		(1L<<9)		/* RP (repeat enable) */
#define FLAG_CONTROL	(1L<<10)	/* control registers */
#define FLAG_A0		(1L<<11)	/* A0 */
#define FLAG_A1		(1L<<12)	/* A1 */
#define FLAG_JMP	(1L<<13)	/* instruction is a branch */
#define FLAG_JSR	(1L<<14)	/* subroutine call.  must be aligned */
#define FLAG_MEM	(1L<<15)	/* reads/writes memory */
#define FLAG_NOT_WITH_ADDSUBppp	 (1L<<16) /* Old meaning: a 2 word 4 byter operation
					   New meaning: operation cannot be 
					   combined in parallel with ADD/SUBppp. */
#define FLAG_MUL16	(1L<<17)	/* 16 bit multiply */
#define FLAG_MUL32	(1L<<18)	/* 32 bit multiply */
#define FLAG_ADDSUBppp	(1L<<19)	/* ADDppp or SUBppp */
#define FLAG_DELAY	(1L<<20)	/* This is a delayed branch or jump */
#define FLAG_LKR	(1L<<21)	/* insn in left slot kills right slot */
#define FLAG_CVVA	(FLAG_5|FLAG_6|FLAG_7)
#define FLAG_C		FLAG_7
#define FLAG_ALL	(FLAG_0 | \
			 FLAG_1 | \
			 FLAG_2 | \
			 FLAG_3 | \
			 FLAG_4 | \
			 FLAG_5 | \
			 FLAG_6 | \
			 FLAG_7 | \
			 FLAG_SM | \
			 FLAG_RP | \
			 FLAG_CONTROL)
 
  int reloc_flag;
#define RELOC_PCREL	1
#define RELOC_ABS	2
};
 
extern const struct d30v_opcode d30v_opcode_table[];
extern const int d30v_num_opcodes;
 
/* The operands table is an array of struct d30v_operand.  */
struct d30v_operand
{
  /* the length of the field */
  int length;
 
  /* The number of significant bits in the operand.  */
  int bits;
 
  /* position relative to Ra */
  int position;
 
  /* syntax flags.  */
  long flags;
};
extern const struct d30v_operand d30v_operand_table[];
 
/* Values defined for the flags field of a struct d30v_operand.  */
 
/* this is the destination register; it will be modified */
/* this is used by the optimizer */
#define OPERAND_DEST	(1)
 
/* number or symbol */
#define OPERAND_NUM	(2)
 
/* address or label */
#define OPERAND_ADDR	(4)
 
/* register */
#define OPERAND_REG	(8)
 
/* postincrement +  */
#define OPERAND_PLUS	(0x10)
 
/* postdecrement -  */
#define OPERAND_MINUS	(0x20)
 
/* signed number */
#define OPERAND_SIGNED	(0x40)
 
/* this operand must be shifted left by 3 */
#define OPERAND_SHIFT	(0x80)
 
/* flag register */
#define OPERAND_FLAG	(0x100)
 
/* control register  */
#define OPERAND_CONTROL	(0x200)
 
/* accumulator */
#define OPERAND_ACC	(0x400)
 
/* @  */
#define OPERAND_ATSIGN	(0x800)
 
/* @(  */
#define OPERAND_ATPAR	(0x1000)
 
/* predecrement mode '@-sp'  */
#define OPERAND_ATMINUS	(0x2000)
 
/* this operand changes the instruction name */
/* for example, CPMcc, CMPUcc */
#define OPERAND_NAME	(0x4000)
 
/* fake operand for mvtsys and mvfsys */
#define OPERAND_SPECIAL	(0x8000)
 
/* let the optimizer know that two registers are affected */
#define OPERAND_2REG	(0x10000)
 
/* This operand is pc-relative.  Note that repeati can have two immediate
   operands, one of which is pcrel, the other (the IMM6U one) is not.  */
#define OPERAND_PCREL	(0x20000)
 
/* The format table is an array of struct d30v_format.  */
struct d30v_format
{
  int	form;		/* SHORT_A, LONG, etc */
  int	modifier;	/* two bit modifier following opcode */
  unsigned char operands[5];
};
extern const struct d30v_format d30v_format_table[];
 
 
/* an instruction is defined by an opcode and a format */
/* for example, "add" has one opcode, but three different */
/* formats, 2 SHORT_A forms and a LONG form. */
struct d30v_insn
{
  struct d30v_opcode *op;	/* pointer to an entry in the opcode table */
  struct d30v_format *form;	/* pointer to an entry in the format table */
  int ecc;			/* execution condition code */
};
 
/* an expressionS only has one register type, so we fake it */
/* by setting high bits to indicate type */
#define REGISTER_MASK	0xFF
 
#endif /* D30V_H */
#define>
#define>
#define>
#define>
#define>
#define>
#define>
#define>

Rev 5191	Rev 6324
1	/* d30v.h -- Header file for D30V opcode table	1	/* d30v.h -- Header file for D30V opcode table
2	Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010	-
3	Free Software Foundation, Inc.	2	Copyright (C) 1997-2015 Free Software Foundation, Inc.
4	Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions	3	Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
5		4
6	This file is part of GDB, GAS, and the GNU binutils.	5	This file is part of GDB, GAS, and the GNU binutils.
7		6
8	GDB, GAS, and the GNU binutils are free software; you can redistribute	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
9	them and/or modify them under the terms of the GNU General Public	8	them and/or modify them under the terms of the GNU General Public
10	License as published by the Free Software Foundation; either version 3,	9	License as published by the Free Software Foundation; either version 3,
11	or (at your option) any later version.	10	or (at your option) any later version.
12		11
13	GDB, GAS, and the GNU binutils are distributed in the hope that they	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
14	will be useful, but WITHOUT ANY WARRANTY; without even the implied	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
15	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16	the GNU General Public License for more details.	15	the GNU General Public License for more details.
17		16
18	You should have received a copy of the GNU General Public License	17	You should have received a copy of the GNU General Public License
19	along with this file; see the file COPYING3. If not, write to the Free	18	along with this file; see the file COPYING3. If not, write to the Free
20	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21	MA 02110-1301, USA. */	20	MA 02110-1301, USA. */
22		21
23	#ifndef D30V_H	22	#ifndef D30V_H
24	#define D30V_H	23	#define D30V_H
25		24
26	#define NOP 0x00F00000	25	#define NOP 0x00F00000
27		26
28	/* Structure to hold information about predefined registers. */	27	/* Structure to hold information about predefined registers. */
29	struct pd_reg	28	struct pd_reg
30	{	29	{
31	char name; / name to recognize */	30	char name; / name to recognize */
32	char pname; / name to print for this register */	31	char pname; / name to print for this register */
33	int value;	32	int value;
34	};	33	};
35		34
36	extern const struct pd_reg pre_defined_registers[];	35	extern const struct pd_reg pre_defined_registers[];
37	int reg_name_cnt (void);	36	int reg_name_cnt (void);
38		37
39	/* the number of control registers */	38	/* the number of control registers */
40	#define MAX_CONTROL_REG 64	39	#define MAX_CONTROL_REG 64
41		40
42	/* define the format specifiers */	41	/* define the format specifiers */
43	#define FM00 0	42	#define FM00 0
44	#define FM01 0x80000000	43	#define FM01 0x80000000
45	#define FM10 0x8000000000000000LL	44	#define FM10 0x8000000000000000LL
46	#define FM11 0x8000000080000000LL	45	#define FM11 0x8000000080000000LL
47		46
48	/* define the opcode classes */	47	/* define the opcode classes */
49	#define BRA 0	48	#define BRA 0
50	#define LOGIC 1	49	#define LOGIC 1
51	#define IMEM 2	50	#define IMEM 2
52	#define IALU1 4	51	#define IALU1 4
53	#define IALU2 5	52	#define IALU2 5
54		53
55	/* define the execution condition codes */	54	/* define the execution condition codes */
56	#define ECC_AL 0 /* ALways (default) */	55	#define ECC_AL 0 /* ALways (default) */
57	#define ECC_TX 1 /* F0=True, F1=Don't care */	56	#define ECC_TX 1 /* F0=True, F1=Don't care */
58	#define ECC_FX 2 /* F0=False, F1=Don't care */	57	#define ECC_FX 2 /* F0=False, F1=Don't care */
59	#define ECC_XT 3 /* F0=Don't care, F1=True */	58	#define ECC_XT 3 /* F0=Don't care, F1=True */
60	#define ECC_XF 4 /* F0=Don't care, F1=False */	59	#define ECC_XF 4 /* F0=Don't care, F1=False */
61	#define ECC_TT 5 /* F0=True, F1=True */	60	#define ECC_TT 5 /* F0=True, F1=True */
62	#define ECC_TF 6 /* F0=True, F1=False */	61	#define ECC_TF 6 /* F0=True, F1=False */
63	#define ECC_RESERVED 7 /* reserved */	62	#define ECC_RESERVED 7 /* reserved */
64	#define ECC_MAX ECC_RESERVED	63	#define ECC_MAX ECC_RESERVED
65		64
66	extern const char *d30v_ecc_names[];	65	extern const char *d30v_ecc_names[];
67		66
68	/* condition code table for CMP and CMPU */	67	/* condition code table for CMP and CMPU */
69	extern const char *d30v_cc_names[];	68	extern const char *d30v_cc_names[];
70		69
71	/* The opcode table is an array of struct d30v_opcode. */	70	/* The opcode table is an array of struct d30v_opcode. */
72	struct d30v_opcode	71	struct d30v_opcode
73	{	72	{
74	/* The opcode name. */	73	/* The opcode name. */
75	const char *name;	74	const char *name;
76		75
77	/* the opcode */	76	/* the opcode */
78	int op1; /* first part, "IALU1" for example */	77	int op1; /* first part, "IALU1" for example */
79	int op2; /* the rest of the opcode */	78	int op2; /* the rest of the opcode */
80		79
81	/* opcode format(s). These numbers correspond to entries */	80	/* opcode format(s). These numbers correspond to entries */
82	/* in the d30v_format_table */	81	/* in the d30v_format_table */
83	unsigned char format[4];	82	unsigned char format[4];
84		83
85	#define SHORT_M 1	84	#define SHORT_M 1
86	#define SHORT_M2 5 /* for ld2w and st2w */	85	#define SHORT_M2 5 /* for ld2w and st2w */
87	#define SHORT_A 9	86	#define SHORT_A 9
88	#define SHORT_B1 11	87	#define SHORT_B1 11
89	#define SHORT_B2 12	88	#define SHORT_B2 12
90	#define SHORT_B2r 13	89	#define SHORT_B2r 13
91	#define SHORT_B3 14	90	#define SHORT_B3 14
92	#define SHORT_B3r 16	91	#define SHORT_B3r 16
93	#define SHORT_B3b 18	92	#define SHORT_B3b 18
94	#define SHORT_B3br 20	93	#define SHORT_B3br 20
95	#define SHORT_D1r 22	94	#define SHORT_D1r 22
96	#define SHORT_D2 24	95	#define SHORT_D2 24
97	#define SHORT_D2r 26	96	#define SHORT_D2r 26
98	#define SHORT_D2Br 28	97	#define SHORT_D2Br 28
99	#define SHORT_U 30 /* unary SHORT_A. ABS for example */	98	#define SHORT_U 30 /* unary SHORT_A. ABS for example */
100	#define SHORT_F 31 /* SHORT_A with flag registers */	99	#define SHORT_F 31 /* SHORT_A with flag registers */
101	#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */	100	#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */
102	#define SHORT_T 35 /* for trap instruction */	101	#define SHORT_T 35 /* for trap instruction */
103	#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */	102	#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */
104	#define SHORT_CMP 38 /* special form for CMPcc */	103	#define SHORT_CMP 38 /* special form for CMPcc */
105	#define SHORT_CMPU 40 /* special form for CMPUcc */	104	#define SHORT_CMPU 40 /* special form for CMPUcc */
106	#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */	105	#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */
107	#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */	106	#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */
108	#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */	107	#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */
109	#define SHORT_MODINC 48	108	#define SHORT_MODINC 48
110	#define SHORT_MODDEC 49	109	#define SHORT_MODDEC 49
111	#define SHORT_C1 50	110	#define SHORT_C1 50
112	#define SHORT_C2 51	111	#define SHORT_C2 51
113	#define SHORT_UF 52	112	#define SHORT_UF 52
114	#define SHORT_A2 53	113	#define SHORT_A2 53
115	#define SHORT_NONE 55 /* no operands */	114	#define SHORT_NONE 55 /* no operands */
116	#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */	115	#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */
117	#define LONG 57	116	#define LONG 57
118	#define LONG_U 58 /* unary LONG */	117	#define LONG_U 58 /* unary LONG */
119	#define LONG_Ur 59 /* LONG pc-relative */	118	#define LONG_Ur 59 /* LONG pc-relative */
120	#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */	119	#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */
121	#define LONG_M 61 /* Memory long for ldb, stb */	120	#define LONG_M 61 /* Memory long for ldb, stb */
122	#define LONG_M2 62 /* Memory long for ld2w, st2w */	121	#define LONG_M2 62 /* Memory long for ld2w, st2w */
123	#define LONG_2 63 /* LONG with 2 operands; jmptnz */	122	#define LONG_2 63 /* LONG with 2 operands; jmptnz */
124	#define LONG_2r 64 /* LONG with 2 operands; bratnz */	123	#define LONG_2r 64 /* LONG with 2 operands; bratnz */
125	#define LONG_2b 65 /* LONG_2 with modifier of 3 */	124	#define LONG_2b 65 /* LONG_2 with modifier of 3 */
126	#define LONG_2br 66 /* LONG_2r with modifier of 3 */	125	#define LONG_2br 66 /* LONG_2r with modifier of 3 */
127	#define LONG_D 67 /* for DJMPI */	126	#define LONG_D 67 /* for DJMPI */
128	#define LONG_Dr 68 /* for DBRAI */	127	#define LONG_Dr 68 /* for DBRAI */
129	#define LONG_Dbr 69 /* for repeati */	128	#define LONG_Dbr 69 /* for repeati */
130		129
131	/* the execution unit(s) used */	130	/* the execution unit(s) used */
132	int unit;	131	int unit;
133	#define EITHER 0	132	#define EITHER 0
134	#define IU 1	133	#define IU 1
135	#define MU 2	134	#define MU 2
136	#define EITHER_BUT_PREFER_MU 3	135	#define EITHER_BUT_PREFER_MU 3
137		136
138	/* this field is used to decide if two instructions */	137	/* this field is used to decide if two instructions */
139	/* can be executed in parallel */	138	/* can be executed in parallel */
140	long flags_used;	139	long flags_used;
141	long flags_set;	140	long flags_set;
142	#define FLAG_0 (1L<<0)	141	#define FLAG_0 (1L<<0)
143	#define FLAG_1 (1L<<1)	142	#define FLAG_1 (1L<<1)
144	#define FLAG_2 (1L<<2)	143	#define FLAG_2 (1L<<2)
145	#define FLAG_3 (1L<<3)	144	#define FLAG_3 (1L<<3)
146	#define FLAG_4 (1L<<4) /* S (saturation) */	145	#define FLAG_4 (1L<<4) /* S (saturation) */
147	#define FLAG_5 (1L<<5) /* V (overflow) */	146	#define FLAG_5 (1L<<5) /* V (overflow) */
148	#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */	147	#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */
149	#define FLAG_7 (1L<<7) /* C (carry/borrow) */	148	#define FLAG_7 (1L<<7) /* C (carry/borrow) */
150	#define FLAG_SM (1L<<8) /* SM (stack mode) */	149	#define FLAG_SM (1L<<8) /* SM (stack mode) */
151	#define FLAG_RP (1L<<9) /* RP (repeat enable) */	150	#define FLAG_RP (1L<<9) /* RP (repeat enable) */
152	#define FLAG_CONTROL (1L<<10) /* control registers */	151	#define FLAG_CONTROL (1L<<10) /* control registers */
153	#define FLAG_A0 (1L<<11) /* A0 */	152	#define FLAG_A0 (1L<<11) /* A0 */
154	#define FLAG_A1 (1L<<12) /* A1 */	153	#define FLAG_A1 (1L<<12) /* A1 */
155	#define FLAG_JMP (1L<<13) /* instruction is a branch */	154	#define FLAG_JMP (1L<<13) /* instruction is a branch */
156	#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */	155	#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
157	#define FLAG_MEM (1L<<15) /* reads/writes memory */	156	#define FLAG_MEM (1L<<15) /* reads/writes memory */
158	#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation	157	#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation
159	New meaning: operation cannot be	158	New meaning: operation cannot be
160	combined in parallel with ADD/SUBppp. */	159	combined in parallel with ADD/SUBppp. */
161	#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */	160	#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
162	#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */	161	#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
163	#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */	162	#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */
164	#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */	163	#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */
165	#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */	164	#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */
166	#define FLAG_CVVA (FLAG_5\|FLAG_6\|FLAG_7)	165	#define FLAG_CVVA (FLAG_5\|FLAG_6\|FLAG_7)
167	#define FLAG_C FLAG_7	166	#define FLAG_C FLAG_7
168	#define FLAG_ALL (FLAG_0 \| \	167	#define FLAG_ALL (FLAG_0 \| \
169	FLAG_1 \| \	168	FLAG_1 \| \
170	FLAG_2 \| \	169	FLAG_2 \| \
171	FLAG_3 \| \	170	FLAG_3 \| \
172	FLAG_4 \| \	171	FLAG_4 \| \
173	FLAG_5 \| \	172	FLAG_5 \| \
174	FLAG_6 \| \	173	FLAG_6 \| \
175	FLAG_7 \| \	174	FLAG_7 \| \
176	FLAG_SM \| \	175	FLAG_SM \| \
177	FLAG_RP \| \	176	FLAG_RP \| \
178	FLAG_CONTROL)	177	FLAG_CONTROL)
179		178
180	int reloc_flag;	179	int reloc_flag;
181	#define RELOC_PCREL 1	180	#define RELOC_PCREL 1
182	#define RELOC_ABS 2	181	#define RELOC_ABS 2
183	};	182	};
184		183
185	extern const struct d30v_opcode d30v_opcode_table[];	184	extern const struct d30v_opcode d30v_opcode_table[];
186	extern const int d30v_num_opcodes;	185	extern const int d30v_num_opcodes;
187		186
188	/* The operands table is an array of struct d30v_operand. */	187	/* The operands table is an array of struct d30v_operand. */
189	struct d30v_operand	188	struct d30v_operand
190	{	189	{
191	/* the length of the field */	190	/* the length of the field */
192	int length;	191	int length;
193		192
194	/* The number of significant bits in the operand. */	193	/* The number of significant bits in the operand. */
195	int bits;	194	int bits;
196		195
197	/* position relative to Ra */	196	/* position relative to Ra */
198	int position;	197	int position;
199		198
200	/* syntax flags. */	199	/* syntax flags. */
201	long flags;	200	long flags;
202	};	201	};
203	extern const struct d30v_operand d30v_operand_table[];	202	extern const struct d30v_operand d30v_operand_table[];
204		203
205	/* Values defined for the flags field of a struct d30v_operand. */	204	/* Values defined for the flags field of a struct d30v_operand. */
206		205
207	/* this is the destination register; it will be modified */	206	/* this is the destination register; it will be modified */
208	/* this is used by the optimizer */	207	/* this is used by the optimizer */
209	#define OPERAND_DEST (1)	208	#define OPERAND_DEST (1)
210		209
211	/* number or symbol */	210	/* number or symbol */
212	#define OPERAND_NUM (2)	211	#define OPERAND_NUM (2)
213		212
214	/* address or label */	213	/* address or label */
215	#define OPERAND_ADDR (4)	214	#define OPERAND_ADDR (4)
216		215
217	/* register */	216	/* register */
218	#define OPERAND_REG (8)	217	#define OPERAND_REG (8)
219		218
220	/* postincrement + */	219	/* postincrement + */
221	#define OPERAND_PLUS (0x10)	220	#define OPERAND_PLUS (0x10)
222		221
223	/* postdecrement - */	222	/* postdecrement - */
224	#define OPERAND_MINUS (0x20)	223	#define OPERAND_MINUS (0x20)
225		224
226	/* signed number */	225	/* signed number */
227	#define OPERAND_SIGNED (0x40)	226	#define OPERAND_SIGNED (0x40)
228		227
229	/* this operand must be shifted left by 3 */	228	/* this operand must be shifted left by 3 */
230	#define OPERAND_SHIFT (0x80)	229	#define OPERAND_SHIFT (0x80)
231		230
232	/* flag register */	231	/* flag register */
233	#define OPERAND_FLAG (0x100)	232	#define OPERAND_FLAG (0x100)
234		233
235	/* control register */	234	/* control register */
236	#define OPERAND_CONTROL (0x200)	235	#define OPERAND_CONTROL (0x200)
237		236
238	/* accumulator */	237	/* accumulator */
239	#define OPERAND_ACC (0x400)	238	#define OPERAND_ACC (0x400)
240		239
241	/* @ */	240	/* @ */
242	#define OPERAND_ATSIGN (0x800)	241	#define OPERAND_ATSIGN (0x800)
243		242
244	/* @( */	243	/* @( */
245	#define OPERAND_ATPAR (0x1000)	244	#define OPERAND_ATPAR (0x1000)
246		245
247	/* predecrement mode '@-sp' */	246	/* predecrement mode '@-sp' */
248	#define OPERAND_ATMINUS (0x2000)	247	#define OPERAND_ATMINUS (0x2000)
249		248
250	/* this operand changes the instruction name */	249	/* this operand changes the instruction name */
251	/* for example, CPMcc, CMPUcc */	250	/* for example, CPMcc, CMPUcc */
252	#define OPERAND_NAME (0x4000)	251	#define OPERAND_NAME (0x4000)
253		252
254	/* fake operand for mvtsys and mvfsys */	253	/* fake operand for mvtsys and mvfsys */
255	#define OPERAND_SPECIAL (0x8000)	254	#define OPERAND_SPECIAL (0x8000)
256		255
257	/* let the optimizer know that two registers are affected */	256	/* let the optimizer know that two registers are affected */
258	#define OPERAND_2REG (0x10000)	257	#define OPERAND_2REG (0x10000)
259		258
260	/* This operand is pc-relative. Note that repeati can have two immediate	259	/* This operand is pc-relative. Note that repeati can have two immediate
261	operands, one of which is pcrel, the other (the IMM6U one) is not. */	260	operands, one of which is pcrel, the other (the IMM6U one) is not. */
262	#define OPERAND_PCREL (0x20000)	261	#define OPERAND_PCREL (0x20000)
263		262
264	/* The format table is an array of struct d30v_format. */	263	/* The format table is an array of struct d30v_format. */
265	struct d30v_format	264	struct d30v_format
266	{	265	{
267	int form; /* SHORT_A, LONG, etc */	266	int form; /* SHORT_A, LONG, etc */
268	int modifier; /* two bit modifier following opcode */	267	int modifier; /* two bit modifier following opcode */
269	unsigned char operands[5];	268	unsigned char operands[5];
270	};	269	};
271	extern const struct d30v_format d30v_format_table[];	270	extern const struct d30v_format d30v_format_table[];
272		271
273		272
274	/* an instruction is defined by an opcode and a format */	273	/* an instruction is defined by an opcode and a format */
275	/* for example, "add" has one opcode, but three different */	274	/* for example, "add" has one opcode, but three different */
276	/* formats, 2 SHORT_A forms and a LONG form. */	275	/* formats, 2 SHORT_A forms and a LONG form. */
277	struct d30v_insn	276	struct d30v_insn
278	{	277	{
279	struct d30v_opcode op; / pointer to an entry in the opcode table */	278	struct d30v_opcode op; / pointer to an entry in the opcode table */
280	struct d30v_format form; / pointer to an entry in the format table */	279	struct d30v_format form; / pointer to an entry in the format table */
281	int ecc; /* execution condition code */	280	int ecc; /* execution condition code */
282	};	281	};
283		282
284	/* an expressionS only has one register type, so we fake it */	283	/* an expressionS only has one register type, so we fake it */
285	/* by setting high bits to indicate type */	284	/* by setting high bits to indicate type */
286	#define REGISTER_MASK 0xFF	285	#define REGISTER_MASK 0xFF
287		286
288	#endif /* D30V_H */	287	#endif /* D30V_H */
289	#define>	288	#define>
290	#define>	289	#define>
291	#define>	290	#define>
292	#define>	291	#define>
293	#define>	292	#define>
294	#define>	293	#define>
295	#define>	294	#define>
296	#define>	295	#define>

Subversion Repositories Kolibri OS

(root)/contrib/toolchain/binutils/include/opcode/d30v.h – Rev 5191 → 6324