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/* AArch64 assembler/disassembler support.
 
   Copyright (C) 2009-2015 Free Software Foundation, Inc.
   Contributed by ARM Ltd.
 
   This file is part of GNU Binutils.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the license, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see .  */
 
#ifndef OPCODE_AARCH64_H
#define OPCODE_AARCH64_H
 
#include "bfd.h"
#include "bfd_stdint.h"
#include 
#include 
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* The offset for pc-relative addressing is currently defined to be 0.  */
#define AARCH64_PCREL_OFFSET		0
 
typedef uint32_t aarch64_insn;
 
/* The following bitmasks control CPU features.  */
#define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
#define AARCH64_FEATURE_V8_2	0x00000020      /* ARMv8.2 processors.  */
#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */
#define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
#define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
#define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */
#define AARCH64_FEATURE_LSE	0x00100000	/* LSE instructions.  */
#define AARCH64_FEATURE_PAN	0x00200000	/* PAN instructions.  */
#define AARCH64_FEATURE_LOR	0x00400000	/* LOR instructions.  */
#define AARCH64_FEATURE_RDMA	0x00800000	/* v8.1 SIMD instructions.  */
#define AARCH64_FEATURE_V8_1	0x01000000	/* v8.1 features.  */
#define AARCH64_FEATURE_F16	0x02000000	/* v8.2 FP16 instructions.  */
#define AARCH64_FEATURE_RAS	0x04000000	/* RAS Extensions.  */
#define AARCH64_FEATURE_PROFILE	0x08000000	/* Statistical Profiling.  */
 
/* Architectures are the sum of the base and extensions.  */
#define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
						 AARCH64_FEATURE_FP  \
						 | AARCH64_FEATURE_SIMD)
#define AARCH64_ARCH_V8_1	AARCH64_FEATURE (AARCH64_FEATURE_V8, \
						 AARCH64_FEATURE_FP  \
						 | AARCH64_FEATURE_SIMD	\
						 | AARCH64_FEATURE_CRC	\
						 | AARCH64_FEATURE_V8_1 \
						 | AARCH64_FEATURE_LSE	\
						 | AARCH64_FEATURE_PAN	\
						 | AARCH64_FEATURE_LOR	\
						 | AARCH64_FEATURE_RDMA)
#define AARCH64_ARCH_V8_2	AARCH64_FEATURE (AARCH64_FEATURE_V8,	\
						 AARCH64_FEATURE_V8_2	\
						 | AARCH64_FEATURE_F16	\
						 | AARCH64_FEATURE_RAS	\
						 | AARCH64_FEATURE_FP	\
						 | AARCH64_FEATURE_SIMD	\
						 | AARCH64_FEATURE_CRC	\
						 | AARCH64_FEATURE_V8_1 \
						 | AARCH64_FEATURE_LSE	\
						 | AARCH64_FEATURE_PAN	\
						 | AARCH64_FEATURE_LOR	\
						 | AARCH64_FEATURE_RDMA)
 
#define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
#define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
 
/* CPU-specific features.  */
typedef unsigned long aarch64_feature_set;
 
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)	\
  (((CPU) & (FEAT)) != 0)
 
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)	\
  do						\
    {						\
      (TARG) = (F1) | (F2);			\
    }						\
  while (0)
 
#define AARCH64_CLEAR_FEATURE(TARG,F1,F2)	\
  do						\
    { 						\
      (TARG) = (F1) &~ (F2);			\
    }						\
  while (0)
 
#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 
#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)	\
  (((OPC) & (FEAT)) != 0)
 
enum aarch64_operand_class
{
  AARCH64_OPND_CLASS_NIL,
  AARCH64_OPND_CLASS_INT_REG,
  AARCH64_OPND_CLASS_MODIFIED_REG,
  AARCH64_OPND_CLASS_FP_REG,
  AARCH64_OPND_CLASS_SIMD_REG,
  AARCH64_OPND_CLASS_SIMD_ELEMENT,
  AARCH64_OPND_CLASS_SISD_REG,
  AARCH64_OPND_CLASS_SIMD_REGLIST,
  AARCH64_OPND_CLASS_CP_REG,
  AARCH64_OPND_CLASS_ADDRESS,
  AARCH64_OPND_CLASS_IMMEDIATE,
  AARCH64_OPND_CLASS_SYSTEM,
  AARCH64_OPND_CLASS_COND,
};
 
/* Operand code that helps both parsing and coding.
   Keep AARCH64_OPERANDS synced.  */
 
enum aarch64_opnd
{
  AARCH64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
 
  AARCH64_OPND_Rd,	/* Integer register as destination.  */
  AARCH64_OPND_Rn,	/* Integer register as source.  */
  AARCH64_OPND_Rm,	/* Integer register as source.  */
  AARCH64_OPND_Rt,	/* Integer register used in ld/st instructions.  */
  AARCH64_OPND_Rt2,	/* Integer register used in ld/st pair instructions.  */
  AARCH64_OPND_Rs,	/* Integer register used in ld/st exclusive.  */
  AARCH64_OPND_Ra,	/* Integer register used in ddp_3src instructions.  */
  AARCH64_OPND_Rt_SYS,	/* Integer register used in system instructions.  */
 
  AARCH64_OPND_Rd_SP,	/* Integer Rd or SP.  */
  AARCH64_OPND_Rn_SP,	/* Integer Rn or SP.  */
  AARCH64_OPND_PAIRREG,	/* Paired register operand.  */
  AARCH64_OPND_Rm_EXT,	/* Integer Rm extended.  */
  AARCH64_OPND_Rm_SFT,	/* Integer Rm shifted.  */
 
  AARCH64_OPND_Fd,	/* Floating-point Fd.  */
  AARCH64_OPND_Fn,	/* Floating-point Fn.  */
  AARCH64_OPND_Fm,	/* Floating-point Fm.  */
  AARCH64_OPND_Fa,	/* Floating-point Fa.  */
  AARCH64_OPND_Ft,	/* Floating-point Ft.  */
  AARCH64_OPND_Ft2,	/* Floating-point Ft2.  */
 
  AARCH64_OPND_Sd,	/* AdvSIMD Scalar Sd.  */
  AARCH64_OPND_Sn,	/* AdvSIMD Scalar Sn.  */
  AARCH64_OPND_Sm,	/* AdvSIMD Scalar Sm.  */
 
  AARCH64_OPND_Vd,	/* AdvSIMD Vector Vd.  */
  AARCH64_OPND_Vn,	/* AdvSIMD Vector Vn.  */
  AARCH64_OPND_Vm,	/* AdvSIMD Vector Vm.  */
  AARCH64_OPND_VdD1,	/* AdvSIMD .D[1]; for FMOV only.  */
  AARCH64_OPND_VnD1,	/* AdvSIMD .D[1]; for FMOV only.  */
  AARCH64_OPND_Ed,	/* AdvSIMD Vector Element Vd.  */
  AARCH64_OPND_En,	/* AdvSIMD Vector Element Vn.  */
  AARCH64_OPND_Em,	/* AdvSIMD Vector Element Vm.  */
  AARCH64_OPND_LVn,	/* AdvSIMD Vector register list used in e.g. TBL.  */
  AARCH64_OPND_LVt,	/* AdvSIMD Vector register list used in ld/st.  */
  AARCH64_OPND_LVt_AL,	/* AdvSIMD Vector register list for loading single
			   structure to all lanes.  */
  AARCH64_OPND_LEt,	/* AdvSIMD Vector Element list.  */
 
  AARCH64_OPND_Cn,	/* Co-processor register in CRn field.  */
  AARCH64_OPND_Cm,	/* Co-processor register in CRm field.  */
 
  AARCH64_OPND_IDX,	/* AdvSIMD EXT index operand.  */
  AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
  AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
  AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
  AARCH64_OPND_SIMD_IMM_SFT,	/* AdvSIMD modified immediate with shift.  */
  AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
  AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
			   (no encoding).  */
  AARCH64_OPND_IMM0,	/* Immediate for #0.  */
  AARCH64_OPND_FPIMM0,	/* Immediate for #0.0.  */
  AARCH64_OPND_FPIMM,	/* Floating-point Immediate.  */
  AARCH64_OPND_IMMR,	/* Immediate # in e.g. BFM.  */
  AARCH64_OPND_IMMS,	/* Immediate # in e.g. BFM.  */
  AARCH64_OPND_WIDTH,	/* Immediate # in e.g. BFI.  */
  AARCH64_OPND_IMM,	/* Immediate.  */
  AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
  AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
  AARCH64_OPND_UIMM4,	/* Unsigned 4-bit immediate in the CRm field.  */
  AARCH64_OPND_UIMM7,	/* Unsigned 7-bit immediate in the CRm:op2 fields.  */
  AARCH64_OPND_BIT_NUM,	/* Immediate.  */
  AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
  AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
  AARCH64_OPND_NZCV,	/* Flag bit specifier giving an alternative value for
			   each condition flag.  */
 
  AARCH64_OPND_LIMM,	/* Logical Immediate.  */
  AARCH64_OPND_AIMM,	/* Arithmetic immediate.  */
  AARCH64_OPND_HALF,	/* #{, LSL #} operand in move wide.  */
  AARCH64_OPND_FBITS,	/* FP # operand in e.g. SCVTF */
  AARCH64_OPND_IMM_MOV,	/* Immediate operand for the MOV alias.  */
 
  AARCH64_OPND_COND,	/* Standard condition as the last operand.  */
  AARCH64_OPND_COND1,	/* Same as the above, but excluding AL and NV.  */
 
  AARCH64_OPND_ADDR_ADRP,	/* Memory address for ADRP */
  AARCH64_OPND_ADDR_PCREL14,	/* 14-bit PC-relative address for e.g. TBZ.  */
  AARCH64_OPND_ADDR_PCREL19,	/* 19-bit PC-relative address for e.g. LDR.  */
  AARCH64_OPND_ADDR_PCREL21,	/* 21-bit PC-relative address for e.g. ADR.  */
  AARCH64_OPND_ADDR_PCREL26,	/* 26-bit PC-relative address for e.g. BL.  */
 
  AARCH64_OPND_ADDR_SIMPLE,	/* Address of ld/st exclusive.  */
  AARCH64_OPND_ADDR_REGOFF,	/* Address of register offset.  */
  AARCH64_OPND_ADDR_SIMM7,	/* Address of signed 7-bit immediate.  */
  AARCH64_OPND_ADDR_SIMM9,	/* Address of signed 9-bit immediate.  */
  AARCH64_OPND_ADDR_SIMM9_2,	/* Same as the above, but the immediate is
				   negative or unaligned and there is
				   no writeback allowed.  This operand code
				   is only used to support the programmer-
				   friendly feature of using LDR/STR as the
				   the mnemonic name for LDUR/STUR instructions
				   wherever there is no ambiguity.  */
  AARCH64_OPND_ADDR_UIMM12,	/* Address of unsigned 12-bit immediate.  */
  AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
  AARCH64_OPND_SIMD_ADDR_POST,	/* Address of ld/st multiple post-indexed.  */
 
  AARCH64_OPND_SYSREG,		/* System register operand.  */
  AARCH64_OPND_PSTATEFIELD,	/* PSTATE field name operand.  */
  AARCH64_OPND_SYSREG_AT,	/* System register  operand.  */
  AARCH64_OPND_SYSREG_DC,	/* System register  operand.  */
  AARCH64_OPND_SYSREG_IC,	/* System register  operand.  */
  AARCH64_OPND_SYSREG_TLBI,	/* System register  operand.  */
  AARCH64_OPND_BARRIER,		/* Barrier operand.  */
  AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
  AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
  AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
};
 
/* Qualifier constrains an operand.  It either specifies a variant of an
   operand type or limits values available to an operand type.
 
   N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 
enum aarch64_opnd_qualifier
{
  /* Indicating no further qualification on an operand.  */
  AARCH64_OPND_QLF_NIL,
 
  /* Qualifying an operand which is a general purpose (integer) register;
     indicating the operand data size or a specific register.  */
  AARCH64_OPND_QLF_W,	/* Wn, WZR or WSP.  */
  AARCH64_OPND_QLF_X,	/* Xn, XZR or XSP.  */
  AARCH64_OPND_QLF_WSP,	/* WSP.  */
  AARCH64_OPND_QLF_SP,	/* SP.  */
 
  /* Qualifying an operand which is a floating-point register, a SIMD
     vector element or a SIMD vector element list; indicating operand data
     size or the size of each SIMD vector element in the case of a SIMD
     vector element list.
     These qualifiers are also used to qualify an address operand to
     indicate the size of data element a load/store instruction is
     accessing.
     They are also used for the immediate shift operand in e.g. SSHR.  Such
     a use is only for the ease of operand encoding/decoding and qualifier
     sequence matching; such a use should not be applied widely; use the value
     constraint qualifiers for immediate operands wherever possible.  */
  AARCH64_OPND_QLF_S_B,
  AARCH64_OPND_QLF_S_H,
  AARCH64_OPND_QLF_S_S,
  AARCH64_OPND_QLF_S_D,
  AARCH64_OPND_QLF_S_Q,
 
  /* Qualifying an operand which is a SIMD vector register or a SIMD vector
     register list; indicating register shape.
     They are also used for the immediate shift operand in e.g. SSHR.  Such
     a use is only for the ease of operand encoding/decoding and qualifier
     sequence matching; such a use should not be applied widely; use the value
     constraint qualifiers for immediate operands wherever possible.  */
  AARCH64_OPND_QLF_V_8B,
  AARCH64_OPND_QLF_V_16B,
  AARCH64_OPND_QLF_V_2H,
  AARCH64_OPND_QLF_V_4H,
  AARCH64_OPND_QLF_V_8H,
  AARCH64_OPND_QLF_V_2S,
  AARCH64_OPND_QLF_V_4S,
  AARCH64_OPND_QLF_V_1D,
  AARCH64_OPND_QLF_V_2D,
  AARCH64_OPND_QLF_V_1Q,
 
  /* Constraint on value.  */
  AARCH64_OPND_QLF_imm_0_7,
  AARCH64_OPND_QLF_imm_0_15,
  AARCH64_OPND_QLF_imm_0_31,
  AARCH64_OPND_QLF_imm_0_63,
  AARCH64_OPND_QLF_imm_1_32,
  AARCH64_OPND_QLF_imm_1_64,
 
  /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
     or shift-ones.  */
  AARCH64_OPND_QLF_LSL,
  AARCH64_OPND_QLF_MSL,
 
  /* Special qualifier helping retrieve qualifier information during the
     decoding time (currently not in use).  */
  AARCH64_OPND_QLF_RETRIEVE,
};

/* Instruction class.  */
 
enum aarch64_insn_class
{
  addsub_carry,
  addsub_ext,
  addsub_imm,
  addsub_shift,
  asimdall,
  asimddiff,
  asimdelem,
  asimdext,
  asimdimm,
  asimdins,
  asimdmisc,
  asimdperm,
  asimdsame,
  asimdshf,
  asimdtbl,
  asisddiff,
  asisdelem,
  asisdlse,
  asisdlsep,
  asisdlso,
  asisdlsop,
  asisdmisc,
  asisdone,
  asisdpair,
  asisdsame,
  asisdshf,
  bitfield,
  branch_imm,
  branch_reg,
  compbranch,
  condbranch,
  condcmp_imm,
  condcmp_reg,
  condsel,
  cryptoaes,
  cryptosha2,
  cryptosha3,
  dp_1src,
  dp_2src,
  dp_3src,
  exception,
  extract,
  float2fix,
  float2int,
  floatccmp,
  floatcmp,
  floatdp1,
  floatdp2,
  floatdp3,
  floatimm,
  floatsel,
  ldst_immpost,
  ldst_immpre,
  ldst_imm9,	/* immpost or immpre */
  ldst_pos,
  ldst_regoff,
  ldst_unpriv,
  ldst_unscaled,
  ldstexcl,
  ldstnapair_offs,
  ldstpair_off,
  ldstpair_indexed,
  loadlit,
  log_imm,
  log_shift,
  lse_atomic,
  movewide,
  pcreladdr,
  ic_system,
  testbranch,
};
 
/* Opcode enumerators.  */
 
enum aarch64_op
{
  OP_NIL,
  OP_STRB_POS,
  OP_LDRB_POS,
  OP_LDRSB_POS,
  OP_STRH_POS,
  OP_LDRH_POS,
  OP_LDRSH_POS,
  OP_STR_POS,
  OP_LDR_POS,
  OP_STRF_POS,
  OP_LDRF_POS,
  OP_LDRSW_POS,
  OP_PRFM_POS,
 
  OP_STURB,
  OP_LDURB,
  OP_LDURSB,
  OP_STURH,
  OP_LDURH,
  OP_LDURSH,
  OP_STUR,
  OP_LDUR,
  OP_STURV,
  OP_LDURV,
  OP_LDURSW,
  OP_PRFUM,
 
  OP_LDR_LIT,
  OP_LDRV_LIT,
  OP_LDRSW_LIT,
  OP_PRFM_LIT,
 
  OP_ADD,
  OP_B,
  OP_BL,
 
  OP_MOVN,
  OP_MOVZ,
  OP_MOVK,
 
  OP_MOV_IMM_LOG,	/* MOV alias for moving bitmask immediate.  */
  OP_MOV_IMM_WIDE,	/* MOV alias for moving wide immediate.  */
  OP_MOV_IMM_WIDEN,	/* MOV alias for moving wide immediate (negated).  */
 
  OP_MOV_V,		/* MOV alias for moving vector register.  */
 
  OP_ASR_IMM,
  OP_LSR_IMM,
  OP_LSL_IMM,
 
  OP_BIC,
 
  OP_UBFX,
  OP_BFXIL,
  OP_SBFX,
  OP_SBFIZ,
  OP_BFI,
  OP_BFC,		/* ARMv8.2.  */
  OP_UBFIZ,
  OP_UXTB,
  OP_UXTH,
  OP_UXTW,
 
  OP_CINC,
  OP_CINV,
  OP_CNEG,
  OP_CSET,
  OP_CSETM,
 
  OP_FCVT,
  OP_FCVTN,
  OP_FCVTN2,
  OP_FCVTL,
  OP_FCVTL2,
  OP_FCVTXN_S,		/* Scalar version.  */
 
  OP_ROR_IMM,
 
  OP_SXTL,
  OP_SXTL2,
  OP_UXTL,
  OP_UXTL2,
 
  OP_TOTAL_NUM,		/* Pseudo.  */
};
 
/* Maximum number of operands an instruction can have.  */
#define AARCH64_MAX_OPND_NUM 6
/* Maximum number of qualifier sequences an instruction can have.  */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size.  */
typedef unsigned char aarch64_opnd_qualifier_t;
/* Operand qualifier sequence typedef.  */
typedef aarch64_opnd_qualifier_t	\
	  aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 
/* FIXME: improve the efficiency.  */
static inline bfd_boolean
empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
{
  int i;
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
    if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
      return FALSE;
  return TRUE;
}
 
/* This structure holds information for a particular opcode.  */
 
struct aarch64_opcode
{
  /* The name of the mnemonic.  */
  const char *name;
 
  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  aarch64_insn opcode;
 
  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  aarch64_insn mask;
 
  /* Instruction class.  */
  enum aarch64_insn_class iclass;
 
  /* Enumerator identifier.  */
  enum aarch64_op op;
 
  /* Which architecture variant provides this instruction.  */
  const aarch64_feature_set *avariant;
 
  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 
  /* A list of operand qualifier code sequence.  Each operand qualifier
     code qualifies the corresponding operand code.  Each operand
     qualifier sequence specifies a valid opcode variant and related
     constraint on operands.  */
  aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 
  /* Flags providing information about this instruction */
  uint32_t flags;
};
 
typedef struct aarch64_opcode aarch64_opcode;
 
/* Table describing all the AArch64 opcodes.  */
extern aarch64_opcode aarch64_opcode_table[];
 
/* Opcode flags.  */
#define F_ALIAS (1 << 0)
#define F_HAS_ALIAS (1 << 1)
/* Disassembly preference priority 1-3 (the larger the higher).  If nothing
   is specified, it is the priority 0 by default, i.e. the lowest priority.  */
#define F_P1 (1 << 2)
#define F_P2 (2 << 2)
#define F_P3 (3 << 2)
/* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
#define F_COND (1 << 4)
/* Instruction has the field of 'sf'.  */
#define F_SF (1 << 5)
/* Instruction has the field of 'size:Q'.  */
#define F_SIZEQ (1 << 6)
/* Floating-point instruction has the field of 'type'.  */
#define F_FPTYPE (1 << 7)
/* AdvSIMD scalar instruction has the field of 'size'.  */
#define F_SSIZE (1 << 8)
/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
#define F_T (1 << 9)
/* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
#define F_GPRSIZE_IN_Q (1 << 10)
/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
#define F_LDS_SIZE (1 << 11)
/* Optional operand; assume maximum of 1 operand can be optional.  */
#define F_OPD0_OPT (1 << 12)
#define F_OPD1_OPT (2 << 12)
#define F_OPD2_OPT (3 << 12)
#define F_OPD3_OPT (4 << 12)
#define F_OPD4_OPT (5 << 12)
/* Default value for the optional operand when omitted from the assembly.  */
#define F_DEFAULT(X) (((X) & 0x1f) << 15)
/* Instruction that is an alias of another instruction needs to be
   encoded/decoded by converting it to/from the real form, followed by
   the encoding/decoding according to the rules of the real opcode.
   This compares to the direct coding using the alias's information.
   N.B. this flag requires F_ALIAS to be used together.  */
#define F_CONV (1 << 20)
/* Use together with F_ALIAS to indicate an alias opcode is a programmer
   friendly pseudo instruction available only in the assembly code (thus will
   not show up in the disassembly).  */
#define F_PSEUDO (1 << 21)
/* Instruction has miscellaneous encoding/decoding rules.  */
#define F_MISC (1 << 22)
/* Instruction has the field of 'N'; used in conjunction with F_SF.  */
#define F_N (1 << 23)
/* Opcode dependent field.  */
#define F_OD(X) (((X) & 0x7) << 24)
/* Instruction has the field of 'sz'.  */
#define F_LSE_SZ (1 << 27)
/* Next bit is 28.  */
 
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
{
  return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
}
 
static inline bfd_boolean
opcode_has_alias (const aarch64_opcode *opcode)
{
  return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
}
 
/* Priority for disassembling preference.  */
static inline int
opcode_priority (const aarch64_opcode *opcode)
{
  return (opcode->flags >> 2) & 0x3;
}
 
static inline bfd_boolean
pseudo_opcode_p (const aarch64_opcode *opcode)
{
  return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
}
 
static inline bfd_boolean
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
  return (((opcode->flags >> 12) & 0x7) == idx + 1)
    ? TRUE : FALSE;
}
 
static inline aarch64_insn
get_optional_operand_default_value (const aarch64_opcode *opcode)
{
  return (opcode->flags >> 15) & 0x1f;
}
 
static inline unsigned int
get_opcode_dependent_value (const aarch64_opcode *opcode)
{
  return (opcode->flags >> 24) & 0x7;
}
 
static inline bfd_boolean
opcode_has_special_coder (const aarch64_opcode *opcode)
{
  return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
	  | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
    : FALSE;
}

struct aarch64_name_value_pair
{
  const char *  name;
  aarch64_insn	value;
};
 
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options [];
 
typedef struct
{
  const char *  name;
  aarch64_insn	value;
  uint32_t	flags;
} aarch64_sys_reg;
 
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
						const aarch64_sys_reg *);
extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
						    const aarch64_sys_reg *);
 
typedef struct
{
  const char *name;
  uint32_t value;
  uint32_t flags ;
} aarch64_sys_ins_reg;
 
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
				 const aarch64_sys_ins_reg *);
 
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 
/* Shift/extending operator kinds.
   N.B. order is important; keep aarch64_operand_modifiers synced.  */
enum aarch64_modifier_kind
{
  AARCH64_MOD_NONE,
  AARCH64_MOD_MSL,
  AARCH64_MOD_ROR,
  AARCH64_MOD_ASR,
  AARCH64_MOD_LSR,
  AARCH64_MOD_LSL,
  AARCH64_MOD_UXTB,
  AARCH64_MOD_UXTH,
  AARCH64_MOD_UXTW,
  AARCH64_MOD_UXTX,
  AARCH64_MOD_SXTB,
  AARCH64_MOD_SXTH,
  AARCH64_MOD_SXTW,
  AARCH64_MOD_SXTX,
};
 
bfd_boolean
aarch64_extend_operator_p (enum aarch64_modifier_kind);
 
enum aarch64_modifier_kind
aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
/* Condition.  */
 
typedef struct
{
  /* A list of names with the first one as the disassembly preference;
     terminated by NULL if fewer than 3.  */
  const char *names[3];
  aarch64_insn value;
} aarch64_cond;
 
extern const aarch64_cond aarch64_conds[16];
 
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);

/* Structure representing an operand.  */
 
struct aarch64_opnd_info
{
  enum aarch64_opnd type;
  aarch64_opnd_qualifier_t qualifier;
  int idx;
 
  union
    {
      struct
	{
	  unsigned regno;
	} reg;
      struct
	{
	  unsigned regno : 5;
	  unsigned index : 4;
	} reglane;
      /* e.g. LVn.  */
      struct
	{
	  unsigned first_regno : 5;
	  unsigned num_regs : 3;
	  /* 1 if it is a list of reg element.  */
	  unsigned has_index : 1;
	  /* Lane index; valid only when has_index is 1.  */
	  unsigned index : 4;
	} reglist;
      /* e.g. immediate or pc relative address offset.  */
      struct
	{
	  int64_t value;
	  unsigned is_fp : 1;
	} imm;
      /* e.g. address in STR (register offset).  */
      struct
	{
	  unsigned base_regno;
	  struct
	    {
	      union
		{
		  int imm;
		  unsigned regno;
		};
	      unsigned is_reg;
	    } offset;
	  unsigned pcrel : 1;		/* PC-relative.  */
	  unsigned writeback : 1;
	  unsigned preind : 1;		/* Pre-indexed.  */
	  unsigned postind : 1;		/* Post-indexed.  */
	} addr;
      const aarch64_cond *cond;
      /* The encoding of the system register.  */
      aarch64_insn sysreg;
      /* The encoding of the PSTATE field.  */
      aarch64_insn pstatefield;
      const aarch64_sys_ins_reg *sysins_op;
      const struct aarch64_name_value_pair *barrier;
      const struct aarch64_name_value_pair *hint_option;
      const struct aarch64_name_value_pair *prfop;
    };
 
  /* Operand shifter; in use when the operand is a register offset address,
     add/sub extended reg, etc. e.g. {,  {#}}.  */
  struct
    {
      enum aarch64_modifier_kind kind;
      int amount;
      unsigned operator_present: 1;	/* Only valid during encoding.  */
      /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
      unsigned amount_present: 1;
    } shifter;
 
  unsigned skip:1;	/* Operand is not completed if there is a fixup needed
			   to be done on it.  In some (but not all) of these
			   cases, we need to tell libopcodes to skip the
			   constraint checking and the encoding for this
			   operand, so that the libopcodes can pick up the
			   right opcode before the operand is fixed-up.  This
			   flag should only be used during the
			   assembling/encoding.  */
  unsigned present:1;	/* Whether this operand is present in the assembly
			   line; not used during the disassembly.  */
};
 
typedef struct aarch64_opnd_info aarch64_opnd_info;
 
/* Structure representing an instruction.
 
   It is used during both the assembling and disassembling.  The assembler
   fills an aarch64_inst after a successful parsing and then passes it to the
   encoding routine to do the encoding.  During the disassembling, the
   disassembler calls the decoding routine to decode a binary instruction; on a
   successful return, such a structure will be filled with information of the
   instruction; then the disassembler uses the information to print out the
   instruction.  */
 
struct aarch64_inst
{
  /* The value of the binary instruction.  */
  aarch64_insn value;
 
  /* Corresponding opcode entry.  */
  const aarch64_opcode *opcode;
 
  /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
  const aarch64_cond *cond;
 
  /* Operands information.  */
  aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
};
 
typedef struct aarch64_inst aarch64_inst;

/* Diagnosis related declaration and interface.  */
 
/* Operand error kind enumerators.
 
   AARCH64_OPDE_RECOVERABLE
     Less severe error found during the parsing, very possibly because that
     GAS has picked up a wrong instruction template for the parsing.
 
   AARCH64_OPDE_SYNTAX_ERROR
     General syntax error; it can be either a user error, or simply because
     that GAS is trying a wrong instruction template.
 
   AARCH64_OPDE_FATAL_SYNTAX_ERROR
     Definitely a user syntax error.
 
   AARCH64_OPDE_INVALID_VARIANT
     No syntax error, but the operands are not a valid combination, e.g.
     FMOV D0,S0
 
   AARCH64_OPDE_OUT_OF_RANGE
     Error about some immediate value out of a valid range.
 
   AARCH64_OPDE_UNALIGNED
     Error about some immediate value not properly aligned (i.e. not being a
     multiple times of a certain value).
 
   AARCH64_OPDE_REG_LIST
     Error about the register list operand having unexpected number of
     registers.
 
   AARCH64_OPDE_OTHER_ERROR
     Error of the highest severity and used for any severe issue that does not
     fall into any of the above categories.
 
   The enumerators are only interesting to GAS.  They are declared here (in
   libopcodes) because that some errors are detected (and then notified to GAS)
   by libopcodes (rather than by GAS solely).
 
   The first three errors are only deteced by GAS while the
   AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
   only libopcodes has the information about the valid variants of each
   instruction.
 
   The enumerators have an increasing severity.  This is helpful when there are
   multiple instruction templates available for a given mnemonic name (e.g.
   FMOV); this mechanism will help choose the most suitable template from which
   the generated diagnostics can most closely describe the issues, if any.  */
 
enum aarch64_operand_error_kind
{
  AARCH64_OPDE_NIL,
  AARCH64_OPDE_RECOVERABLE,
  AARCH64_OPDE_SYNTAX_ERROR,
  AARCH64_OPDE_FATAL_SYNTAX_ERROR,
  AARCH64_OPDE_INVALID_VARIANT,
  AARCH64_OPDE_OUT_OF_RANGE,
  AARCH64_OPDE_UNALIGNED,
  AARCH64_OPDE_REG_LIST,
  AARCH64_OPDE_OTHER_ERROR
};
 
/* N.B. GAS assumes that this structure work well with shallow copy.  */
struct aarch64_operand_error
{
  enum aarch64_operand_error_kind kind;
  int index;
  const char *error;
  int data[3];	/* Some data for extra information.  */
};
 
typedef struct aarch64_operand_error aarch64_operand_error;
 
/* Encoding entrypoint.  */
 
extern int
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
		       aarch64_insn *, aarch64_opnd_qualifier_t *,
		       aarch64_operand_error *);
 
extern const aarch64_opcode *
aarch64_replace_opcode (struct aarch64_inst *,
			const aarch64_opcode *);
 
/* Given the opcode enumerator OP, return the pointer to the corresponding
   opcode entry.  */
 
extern const aarch64_opcode *
aarch64_get_opcode (enum aarch64_op);
 
/* Generate the string representation of an operand.  */
extern void
aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
		       const aarch64_opnd_info *, int, int *, bfd_vma *);
 
/* Miscellaneous interface.  */
 
extern int
aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 
extern aarch64_opnd_qualifier_t
aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
				const aarch64_opnd_qualifier_t, int);
 
extern int
aarch64_num_of_operands (const aarch64_opcode *);
 
extern int
aarch64_stack_pointer_p (const aarch64_opnd_info *);
 
extern int
aarch64_zero_register_p (const aarch64_opnd_info *);
 
extern int
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 
/* Given an operand qualifier, return the expected data element size
   of a qualified operand.  */
extern unsigned char
aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 
extern enum aarch64_operand_class
aarch64_get_operand_class (enum aarch64_opnd);
 
extern const char *
aarch64_get_operand_name (enum aarch64_opnd);
 
extern const char *
aarch64_get_operand_desc (enum aarch64_opnd);
 
#ifdef DEBUG_AARCH64
extern int debug_dump;
 
extern void
aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 
#define DEBUG_TRACE(M, ...)					\
  {								\
    if (debug_dump)						\
      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
  }
 
#define DEBUG_TRACE_IF(C, M, ...)				\
  {								\
    if (debug_dump && (C))					\
      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
  }
#else  /* !DEBUG_AARCH64 */
#define DEBUG_TRACE(M, ...) ;
#define DEBUG_TRACE_IF(C, M, ...) ;
#endif /* DEBUG_AARCH64 */
 
#ifdef __cplusplus
}
#endif
 
#endif /* OPCODE_AARCH64_H */

Rev 5191	Rev 6324
1	/* AArch64 assembler/disassembler support.	1	/* AArch64 assembler/disassembler support.
2		2
3	Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.	3	Copyright (C) 2009-2015 Free Software Foundation, Inc.
4	Contributed by ARM Ltd.	4	Contributed by ARM Ltd.
5		5
6	This file is part of GNU Binutils.	6	This file is part of GNU Binutils.
7		7
8	This program is free software; you can redistribute it and/or modify	8	This program is free software; you can redistribute it and/or modify
9	it under the terms of the GNU General Public License as published by	9	it under the terms of the GNU General Public License as published by
10	the Free Software Foundation; either version 3 of the license, or	10	the Free Software Foundation; either version 3 of the license, or
11	(at your option) any later version.	11	(at your option) any later version.
12		12
13	This program is distributed in the hope that it will be useful,	13	This program is distributed in the hope that it will be useful,
14	but WITHOUT ANY WARRANTY; without even the implied warranty of	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	GNU General Public License for more details.	16	GNU General Public License for more details.
17		17
18	You should have received a copy of the GNU General Public License	18	You should have received a copy of the GNU General Public License
19	along with this program; see the file COPYING3. If not,	19	along with this program; see the file COPYING3. If not,
20	see . */	20	see . */
21		21
22	#ifndef OPCODE_AARCH64_H	22	#ifndef OPCODE_AARCH64_H
23	#define OPCODE_AARCH64_H	23	#define OPCODE_AARCH64_H
24		24
25	#include "bfd.h"	25	#include "bfd.h"
26	#include "bfd_stdint.h"	26	#include "bfd_stdint.h"
27	#include	27	#include
28	#include	28	#include
-		29
-		30	#ifdef __cplusplus
-		31	extern "C" {
-		32	#endif
29		33
30	/* The offset for pc-relative addressing is currently defined to be 0. */	34	/* The offset for pc-relative addressing is currently defined to be 0. */
31	#define AARCH64_PCREL_OFFSET 0	35	#define AARCH64_PCREL_OFFSET 0
32		36
33	typedef uint32_t aarch64_insn;	37	typedef uint32_t aarch64_insn;
34		38
35	/* The following bitmasks control CPU features. */	39	/* The following bitmasks control CPU features. */
36	#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */	40	#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
-		41	#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
37	#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */	42	#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
38	#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */	43	#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
39	#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */	44	#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
40	#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */	45	#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
-		46	#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
-		47	#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
-		48	#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
-		49	#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
-		50	#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
-		51	#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
-		52	#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
-		53	#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
41		54
42	/* Architectures are the sum of the base and extensions. */	55	/* Architectures are the sum of the base and extensions. */
43	#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \	56	#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
44	AARCH64_FEATURE_FP \	57	AARCH64_FEATURE_FP \
45	\| AARCH64_FEATURE_SIMD)	58	\| AARCH64_FEATURE_SIMD)
-		59	#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
-		60	AARCH64_FEATURE_FP \
-		61	\| AARCH64_FEATURE_SIMD \
-		62	\| AARCH64_FEATURE_CRC \
-		63	\| AARCH64_FEATURE_V8_1 \
-		64	\| AARCH64_FEATURE_LSE \
-		65	\| AARCH64_FEATURE_PAN \
-		66	\| AARCH64_FEATURE_LOR \
-		67	\| AARCH64_FEATURE_RDMA)
-		68	#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
-		69	AARCH64_FEATURE_V8_2 \
-		70	\| AARCH64_FEATURE_F16 \
-		71	\| AARCH64_FEATURE_RAS \
-		72	\| AARCH64_FEATURE_FP \
-		73	\| AARCH64_FEATURE_SIMD \
-		74	\| AARCH64_FEATURE_CRC \
-		75	\| AARCH64_FEATURE_V8_1 \
-		76	\| AARCH64_FEATURE_LSE \
-		77	\| AARCH64_FEATURE_PAN \
-		78	\| AARCH64_FEATURE_LOR \
-		79	\| AARCH64_FEATURE_RDMA)
-		80
46	#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)	81	#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
47	#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */	82	#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
48		83
49	/* CPU-specific features. */	84	/* CPU-specific features. */
50	typedef unsigned long aarch64_feature_set;	85	typedef unsigned long aarch64_feature_set;
51		86
52	#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \	87	#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
53	(((CPU) & (FEAT)) != 0)	88	(((CPU) & (FEAT)) != 0)
54		89
55	#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \	90	#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
56	do \	91	do \
57	{ \	92	{ \
58	(TARG) = (F1) \| (F2); \	93	(TARG) = (F1) \| (F2); \
59	} \	94	} \
60	while (0)	95	while (0)
61		96
62	#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \	97	#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
63	do \	98	do \
64	{ \	99	{ \
65	(TARG) = (F1) &~ (F2); \	100	(TARG) = (F1) &~ (F2); \
66	} \	101	} \
67	while (0)	102	while (0)
68		103
69	#define AARCH64_FEATURE(core,coproc) ((core) \| (coproc))	104	#define AARCH64_FEATURE(core,coproc) ((core) \| (coproc))
70		105
71	#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \	106	#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
72	(((OPC) & (FEAT)) != 0)	107	(((OPC) & (FEAT)) != 0)
73		108
74	enum aarch64_operand_class	109	enum aarch64_operand_class
75	{	110	{
76	AARCH64_OPND_CLASS_NIL,	111	AARCH64_OPND_CLASS_NIL,
77	AARCH64_OPND_CLASS_INT_REG,	112	AARCH64_OPND_CLASS_INT_REG,
78	AARCH64_OPND_CLASS_MODIFIED_REG,	113	AARCH64_OPND_CLASS_MODIFIED_REG,
79	AARCH64_OPND_CLASS_FP_REG,	114	AARCH64_OPND_CLASS_FP_REG,
80	AARCH64_OPND_CLASS_SIMD_REG,	115	AARCH64_OPND_CLASS_SIMD_REG,
81	AARCH64_OPND_CLASS_SIMD_ELEMENT,	116	AARCH64_OPND_CLASS_SIMD_ELEMENT,
82	AARCH64_OPND_CLASS_SISD_REG,	117	AARCH64_OPND_CLASS_SISD_REG,
83	AARCH64_OPND_CLASS_SIMD_REGLIST,	118	AARCH64_OPND_CLASS_SIMD_REGLIST,
84	AARCH64_OPND_CLASS_CP_REG,	119	AARCH64_OPND_CLASS_CP_REG,
85	AARCH64_OPND_CLASS_ADDRESS,	120	AARCH64_OPND_CLASS_ADDRESS,
86	AARCH64_OPND_CLASS_IMMEDIATE,	121	AARCH64_OPND_CLASS_IMMEDIATE,
87	AARCH64_OPND_CLASS_SYSTEM,	122	AARCH64_OPND_CLASS_SYSTEM,
88	AARCH64_OPND_CLASS_COND,	123	AARCH64_OPND_CLASS_COND,
89	};	124	};
90		125
91	/* Operand code that helps both parsing and coding.	126	/* Operand code that helps both parsing and coding.
92	Keep AARCH64_OPERANDS synced. */	127	Keep AARCH64_OPERANDS synced. */
93		128
94	enum aarch64_opnd	129	enum aarch64_opnd
95	{	130	{
96	AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/	131	AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
97		132
98	AARCH64_OPND_Rd, /* Integer register as destination. */	133	AARCH64_OPND_Rd, /* Integer register as destination. */
99	AARCH64_OPND_Rn, /* Integer register as source. */	134	AARCH64_OPND_Rn, /* Integer register as source. */
100	AARCH64_OPND_Rm, /* Integer register as source. */	135	AARCH64_OPND_Rm, /* Integer register as source. */
101	AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */	136	AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
102	AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */	137	AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
103	AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */	138	AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
104	AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */	139	AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
105	AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */	140	AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
106		141
107	AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */	142	AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
108	AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */	143	AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
-		144	AARCH64_OPND_PAIRREG, /* Paired register operand. */
109	AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */	145	AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
110	AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */	146	AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
111		147
112	AARCH64_OPND_Fd, /* Floating-point Fd. */	148	AARCH64_OPND_Fd, /* Floating-point Fd. */
113	AARCH64_OPND_Fn, /* Floating-point Fn. */	149	AARCH64_OPND_Fn, /* Floating-point Fn. */
114	AARCH64_OPND_Fm, /* Floating-point Fm. */	150	AARCH64_OPND_Fm, /* Floating-point Fm. */
115	AARCH64_OPND_Fa, /* Floating-point Fa. */	151	AARCH64_OPND_Fa, /* Floating-point Fa. */
116	AARCH64_OPND_Ft, /* Floating-point Ft. */	152	AARCH64_OPND_Ft, /* Floating-point Ft. */
117	AARCH64_OPND_Ft2, /* Floating-point Ft2. */	153	AARCH64_OPND_Ft2, /* Floating-point Ft2. */
118		154
119	AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */	155	AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
120	AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */	156	AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
121	AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */	157	AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
122		158
123	AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */	159	AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
124	AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */	160	AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
125	AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */	161	AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
126	AARCH64_OPND_VdD1, /* AdvSIMD .D[1]; for FMOV only. */	162	AARCH64_OPND_VdD1, /* AdvSIMD .D[1]; for FMOV only. */
127	AARCH64_OPND_VnD1, /* AdvSIMD .D[1]; for FMOV only. */	163	AARCH64_OPND_VnD1, /* AdvSIMD .D[1]; for FMOV only. */
128	AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */	164	AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
129	AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */	165	AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
130	AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */	166	AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
131	AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */	167	AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
132	AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */	168	AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
133	AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single	169	AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
134	structure to all lanes. */	170	structure to all lanes. */
135	AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */	171	AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
136		172
137	AARCH64_OPND_Cn, /* Co-processor register in CRn field. */	173	AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
138	AARCH64_OPND_Cm, /* Co-processor register in CRm field. */	174	AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
139		175
140	AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */	176	AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
141	AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */	177	AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
142	AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */	178	AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
143	AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */	179	AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
144	AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */	180	AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
145	AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */	181	AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
146	AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction	182	AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
147	(no encoding). */	183	(no encoding). */
148	AARCH64_OPND_IMM0, /* Immediate for #0. */	184	AARCH64_OPND_IMM0, /* Immediate for #0. */
149	AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */	185	AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
150	AARCH64_OPND_FPIMM, /* Floating-point Immediate. */	186	AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
151	AARCH64_OPND_IMMR, /* Immediate # in e.g. BFM. */	187	AARCH64_OPND_IMMR, /* Immediate # in e.g. BFM. */
152	AARCH64_OPND_IMMS, /* Immediate # in e.g. BFM. */	188	AARCH64_OPND_IMMS, /* Immediate # in e.g. BFM. */
153	AARCH64_OPND_WIDTH, /* Immediate # in e.g. BFI. */	189	AARCH64_OPND_WIDTH, /* Immediate # in e.g. BFI. */
154	AARCH64_OPND_IMM, /* Immediate. */	190	AARCH64_OPND_IMM, /* Immediate. */
155	AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */	191	AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
156	AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */	192	AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
157	AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */	193	AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
158	AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */	194	AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
159	AARCH64_OPND_BIT_NUM, /* Immediate. */	195	AARCH64_OPND_BIT_NUM, /* Immediate. */
160	AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */	196	AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
161	AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */	197	AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
162	AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for	198	AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
163	each condition flag. */	199	each condition flag. */
164		200
165	AARCH64_OPND_LIMM, /* Logical Immediate. */	201	AARCH64_OPND_LIMM, /* Logical Immediate. */
166	AARCH64_OPND_AIMM, /* Arithmetic immediate. */	202	AARCH64_OPND_AIMM, /* Arithmetic immediate. */
167	AARCH64_OPND_HALF, /* #{, LSL #} operand in move wide. */	203	AARCH64_OPND_HALF, /* #{, LSL #} operand in move wide. */
168	AARCH64_OPND_FBITS, /* FP # operand in e.g. SCVTF */	204	AARCH64_OPND_FBITS, /* FP # operand in e.g. SCVTF */
169	AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */	205	AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
170		206
171	AARCH64_OPND_COND, /* Standard condition as the last operand. */	207	AARCH64_OPND_COND, /* Standard condition as the last operand. */
172	AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */	208	AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
173		209
174	AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */	210	AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
175	AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */	211	AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
176	AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */	212	AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
177	AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */	213	AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
178	AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */	214	AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
179		215
180	AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */	216	AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
181	AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */	217	AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
182	AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */	218	AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
183	AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */	219	AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
184	AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is	220	AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
185	negative or unaligned and there is	221	negative or unaligned and there is
186	no writeback allowed. This operand code	222	no writeback allowed. This operand code
187	is only used to support the programmer-	223	is only used to support the programmer-
188	friendly feature of using LDR/STR as the	224	friendly feature of using LDR/STR as the
189	the mnemonic name for LDUR/STUR instructions	225	the mnemonic name for LDUR/STUR instructions
190	wherever there is no ambiguity. */	226	wherever there is no ambiguity. */
191	AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */	227	AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
192	AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */	228	AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
193	AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */	229	AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
194		230
195	AARCH64_OPND_SYSREG, /* System register operand. */	231	AARCH64_OPND_SYSREG, /* System register operand. */
196	AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */	232	AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
197	AARCH64_OPND_SYSREG_AT, /* System register operand. */	233	AARCH64_OPND_SYSREG_AT, /* System register operand. */
198	AARCH64_OPND_SYSREG_DC, /* System register operand. */	234	AARCH64_OPND_SYSREG_DC, /* System register operand. */
199	AARCH64_OPND_SYSREG_IC, /* System register operand. */	235	AARCH64_OPND_SYSREG_IC, /* System register operand. */
200	AARCH64_OPND_SYSREG_TLBI, /* System register operand. */	236	AARCH64_OPND_SYSREG_TLBI, /* System register operand. */
201	AARCH64_OPND_BARRIER, /* Barrier operand. */	237	AARCH64_OPND_BARRIER, /* Barrier operand. */
202	AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */	238	AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
203	AARCH64_OPND_PRFOP, /* Prefetch operation. */	239	AARCH64_OPND_PRFOP, /* Prefetch operation. */
-		240	AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
204	};	241	};
205		242
206	/* Qualifier constrains an operand. It either specifies a variant of an	243	/* Qualifier constrains an operand. It either specifies a variant of an
207	operand type or limits values available to an operand type.	244	operand type or limits values available to an operand type.
208		245
209	N.B. Order is important; keep aarch64_opnd_qualifiers synced. */	246	N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
210		247
211	enum aarch64_opnd_qualifier	248	enum aarch64_opnd_qualifier
212	{	249	{
213	/* Indicating no further qualification on an operand. */	250	/* Indicating no further qualification on an operand. */
214	AARCH64_OPND_QLF_NIL,	251	AARCH64_OPND_QLF_NIL,
215		252
216	/* Qualifying an operand which is a general purpose (integer) register;	253	/* Qualifying an operand which is a general purpose (integer) register;
217	indicating the operand data size or a specific register. */	254	indicating the operand data size or a specific register. */
218	AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */	255	AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
219	AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */	256	AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
220	AARCH64_OPND_QLF_WSP, /* WSP. */	257	AARCH64_OPND_QLF_WSP, /* WSP. */
221	AARCH64_OPND_QLF_SP, /* SP. */	258	AARCH64_OPND_QLF_SP, /* SP. */
222		259
223	/* Qualifying an operand which is a floating-point register, a SIMD	260	/* Qualifying an operand which is a floating-point register, a SIMD
224	vector element or a SIMD vector element list; indicating operand data	261	vector element or a SIMD vector element list; indicating operand data
225	size or the size of each SIMD vector element in the case of a SIMD	262	size or the size of each SIMD vector element in the case of a SIMD
226	vector element list.	263	vector element list.
227	These qualifiers are also used to qualify an address operand to	264	These qualifiers are also used to qualify an address operand to
228	indicate the size of data element a load/store instruction is	265	indicate the size of data element a load/store instruction is
229	accessing.	266	accessing.
230	They are also used for the immediate shift operand in e.g. SSHR. Such	267	They are also used for the immediate shift operand in e.g. SSHR. Such
231	a use is only for the ease of operand encoding/decoding and qualifier	268	a use is only for the ease of operand encoding/decoding and qualifier
232	sequence matching; such a use should not be applied widely; use the value	269	sequence matching; such a use should not be applied widely; use the value
233	constraint qualifiers for immediate operands wherever possible. */	270	constraint qualifiers for immediate operands wherever possible. */
234	AARCH64_OPND_QLF_S_B,	271	AARCH64_OPND_QLF_S_B,
235	AARCH64_OPND_QLF_S_H,	272	AARCH64_OPND_QLF_S_H,
236	AARCH64_OPND_QLF_S_S,	273	AARCH64_OPND_QLF_S_S,
237	AARCH64_OPND_QLF_S_D,	274	AARCH64_OPND_QLF_S_D,
238	AARCH64_OPND_QLF_S_Q,	275	AARCH64_OPND_QLF_S_Q,
239		276
240	/* Qualifying an operand which is a SIMD vector register or a SIMD vector	277	/* Qualifying an operand which is a SIMD vector register or a SIMD vector
241	register list; indicating register shape.	278	register list; indicating register shape.
242	They are also used for the immediate shift operand in e.g. SSHR. Such	279	They are also used for the immediate shift operand in e.g. SSHR. Such
243	a use is only for the ease of operand encoding/decoding and qualifier	280	a use is only for the ease of operand encoding/decoding and qualifier
244	sequence matching; such a use should not be applied widely; use the value	281	sequence matching; such a use should not be applied widely; use the value
245	constraint qualifiers for immediate operands wherever possible. */	282	constraint qualifiers for immediate operands wherever possible. */
246	AARCH64_OPND_QLF_V_8B,	283	AARCH64_OPND_QLF_V_8B,
247	AARCH64_OPND_QLF_V_16B,	284	AARCH64_OPND_QLF_V_16B,
-		285	AARCH64_OPND_QLF_V_2H,
248	AARCH64_OPND_QLF_V_4H,	286	AARCH64_OPND_QLF_V_4H,
249	AARCH64_OPND_QLF_V_8H,	287	AARCH64_OPND_QLF_V_8H,
250	AARCH64_OPND_QLF_V_2S,	288	AARCH64_OPND_QLF_V_2S,
251	AARCH64_OPND_QLF_V_4S,	289	AARCH64_OPND_QLF_V_4S,
252	AARCH64_OPND_QLF_V_1D,	290	AARCH64_OPND_QLF_V_1D,
253	AARCH64_OPND_QLF_V_2D,	291	AARCH64_OPND_QLF_V_2D,
254	AARCH64_OPND_QLF_V_1Q,	292	AARCH64_OPND_QLF_V_1Q,
255		293
256	/* Constraint on value. */	294	/* Constraint on value. */
257	AARCH64_OPND_QLF_imm_0_7,	295	AARCH64_OPND_QLF_imm_0_7,
258	AARCH64_OPND_QLF_imm_0_15,	296	AARCH64_OPND_QLF_imm_0_15,
259	AARCH64_OPND_QLF_imm_0_31,	297	AARCH64_OPND_QLF_imm_0_31,
260	AARCH64_OPND_QLF_imm_0_63,	298	AARCH64_OPND_QLF_imm_0_63,
261	AARCH64_OPND_QLF_imm_1_32,	299	AARCH64_OPND_QLF_imm_1_32,
262	AARCH64_OPND_QLF_imm_1_64,	300	AARCH64_OPND_QLF_imm_1_64,
263		301
264	/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros	302	/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
265	or shift-ones. */	303	or shift-ones. */
266	AARCH64_OPND_QLF_LSL,	304	AARCH64_OPND_QLF_LSL,
267	AARCH64_OPND_QLF_MSL,	305	AARCH64_OPND_QLF_MSL,
268		306
269	/* Special qualifier helping retrieve qualifier information during the	307	/* Special qualifier helping retrieve qualifier information during the
270	decoding time (currently not in use). */	308	decoding time (currently not in use). */
271	AARCH64_OPND_QLF_RETRIEVE,	309	AARCH64_OPND_QLF_RETRIEVE,
272	};	310	};
273		311
274	/* Instruction class. */	312	/* Instruction class. */
275		313
276	enum aarch64_insn_class	314	enum aarch64_insn_class
277	{	315	{
278	addsub_carry,	316	addsub_carry,
279	addsub_ext,	317	addsub_ext,
280	addsub_imm,	318	addsub_imm,
281	addsub_shift,	319	addsub_shift,
282	asimdall,	320	asimdall,
283	asimddiff,	321	asimddiff,
284	asimdelem,	322	asimdelem,
285	asimdext,	323	asimdext,
286	asimdimm,	324	asimdimm,
287	asimdins,	325	asimdins,
288	asimdmisc,	326	asimdmisc,
289	asimdperm,	327	asimdperm,
290	asimdsame,	328	asimdsame,
291	asimdshf,	329	asimdshf,
292	asimdtbl,	330	asimdtbl,
293	asisddiff,	331	asisddiff,
294	asisdelem,	332	asisdelem,
295	asisdlse,	333	asisdlse,
296	asisdlsep,	334	asisdlsep,
297	asisdlso,	335	asisdlso,
298	asisdlsop,	336	asisdlsop,
299	asisdmisc,	337	asisdmisc,
300	asisdone,	338	asisdone,
301	asisdpair,	339	asisdpair,
302	asisdsame,	340	asisdsame,
303	asisdshf,	341	asisdshf,
304	bitfield,	342	bitfield,
305	branch_imm,	343	branch_imm,
306	branch_reg,	344	branch_reg,
307	compbranch,	345	compbranch,
308	condbranch,	346	condbranch,
309	condcmp_imm,	347	condcmp_imm,
310	condcmp_reg,	348	condcmp_reg,
311	condsel,	349	condsel,
312	cryptoaes,	350	cryptoaes,
313	cryptosha2,	351	cryptosha2,
314	cryptosha3,	352	cryptosha3,
315	dp_1src,	353	dp_1src,
316	dp_2src,	354	dp_2src,
317	dp_3src,	355	dp_3src,
318	exception,	356	exception,
319	extract,	357	extract,
320	float2fix,	358	float2fix,
321	float2int,	359	float2int,
322	floatccmp,	360	floatccmp,
323	floatcmp,	361	floatcmp,
324	floatdp1,	362	floatdp1,
325	floatdp2,	363	floatdp2,
326	floatdp3,	364	floatdp3,
327	floatimm,	365	floatimm,
328	floatsel,	366	floatsel,
329	ldst_immpost,	367	ldst_immpost,
330	ldst_immpre,	368	ldst_immpre,
331	ldst_imm9, /* immpost or immpre */	369	ldst_imm9, /* immpost or immpre */
332	ldst_pos,	370	ldst_pos,
333	ldst_regoff,	371	ldst_regoff,
334	ldst_unpriv,	372	ldst_unpriv,
335	ldst_unscaled,	373	ldst_unscaled,
336	ldstexcl,	374	ldstexcl,
337	ldstnapair_offs,	375	ldstnapair_offs,
338	ldstpair_off,	376	ldstpair_off,
339	ldstpair_indexed,	377	ldstpair_indexed,
340	loadlit,	378	loadlit,
341	log_imm,	379	log_imm,
342	log_shift,	380	log_shift,
-		381	lse_atomic,
343	movewide,	382	movewide,
344	pcreladdr,	383	pcreladdr,
345	ic_system,	384	ic_system,
346	testbranch,	385	testbranch,
347	};	386	};
348		387
349	/* Opcode enumerators. */	388	/* Opcode enumerators. */
350		389
351	enum aarch64_op	390	enum aarch64_op
352	{	391	{
353	OP_NIL,	392	OP_NIL,
354	OP_STRB_POS,	393	OP_STRB_POS,
355	OP_LDRB_POS,	394	OP_LDRB_POS,
356	OP_LDRSB_POS,	395	OP_LDRSB_POS,
357	OP_STRH_POS,	396	OP_STRH_POS,
358	OP_LDRH_POS,	397	OP_LDRH_POS,
359	OP_LDRSH_POS,	398	OP_LDRSH_POS,
360	OP_STR_POS,	399	OP_STR_POS,
361	OP_LDR_POS,	400	OP_LDR_POS,
362	OP_STRF_POS,	401	OP_STRF_POS,
363	OP_LDRF_POS,	402	OP_LDRF_POS,
364	OP_LDRSW_POS,	403	OP_LDRSW_POS,
365	OP_PRFM_POS,	404	OP_PRFM_POS,
366		405
367	OP_STURB,	406	OP_STURB,
368	OP_LDURB,	407	OP_LDURB,
369	OP_LDURSB,	408	OP_LDURSB,
370	OP_STURH,	409	OP_STURH,
371	OP_LDURH,	410	OP_LDURH,
372	OP_LDURSH,	411	OP_LDURSH,
373	OP_STUR,	412	OP_STUR,
374	OP_LDUR,	413	OP_LDUR,
375	OP_STURV,	414	OP_STURV,
376	OP_LDURV,	415	OP_LDURV,
377	OP_LDURSW,	416	OP_LDURSW,
378	OP_PRFUM,	417	OP_PRFUM,
379		418
380	OP_LDR_LIT,	419	OP_LDR_LIT,
381	OP_LDRV_LIT,	420	OP_LDRV_LIT,
382	OP_LDRSW_LIT,	421	OP_LDRSW_LIT,
383	OP_PRFM_LIT,	422	OP_PRFM_LIT,
384		423
385	OP_ADD,	424	OP_ADD,
386	OP_B,	425	OP_B,
387	OP_BL,	426	OP_BL,
388		427
389	OP_MOVN,	428	OP_MOVN,
390	OP_MOVZ,	429	OP_MOVZ,
391	OP_MOVK,	430	OP_MOVK,
392		431
393	OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */	432	OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
394	OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */	433	OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
395	OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */	434	OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
396		435
397	OP_MOV_V, /* MOV alias for moving vector register. */	436	OP_MOV_V, /* MOV alias for moving vector register. */
398		437
399	OP_ASR_IMM,	438	OP_ASR_IMM,
400	OP_LSR_IMM,	439	OP_LSR_IMM,
401	OP_LSL_IMM,	440	OP_LSL_IMM,
402		441
403	OP_BIC,	442	OP_BIC,
404		443
405	OP_UBFX,	444	OP_UBFX,
406	OP_BFXIL,	445	OP_BFXIL,
407	OP_SBFX,	446	OP_SBFX,
408	OP_SBFIZ,	447	OP_SBFIZ,
409	OP_BFI,	448	OP_BFI,
-		449	OP_BFC, /* ARMv8.2. */
410	OP_UBFIZ,	450	OP_UBFIZ,
411	OP_UXTB,	451	OP_UXTB,
412	OP_UXTH,	452	OP_UXTH,
413	OP_UXTW,	453	OP_UXTW,
414		454
415	OP_CINC,	455	OP_CINC,
416	OP_CINV,	456	OP_CINV,
417	OP_CNEG,	457	OP_CNEG,
418	OP_CSET,	458	OP_CSET,
419	OP_CSETM,	459	OP_CSETM,
420		460
421	OP_FCVT,	461	OP_FCVT,
422	OP_FCVTN,	462	OP_FCVTN,
423	OP_FCVTN2,	463	OP_FCVTN2,
424	OP_FCVTL,	464	OP_FCVTL,
425	OP_FCVTL2,	465	OP_FCVTL2,
426	OP_FCVTXN_S, /* Scalar version. */	466	OP_FCVTXN_S, /* Scalar version. */
427		467
428	OP_ROR_IMM,	468	OP_ROR_IMM,
429		469
430	OP_SXTL,	470	OP_SXTL,
431	OP_SXTL2,	471	OP_SXTL2,
432	OP_UXTL,	472	OP_UXTL,
433	OP_UXTL2,	473	OP_UXTL2,
434		474
435	OP_TOTAL_NUM, /* Pseudo. */	475	OP_TOTAL_NUM, /* Pseudo. */
436	};	476	};
437		477
438	/* Maximum number of operands an instruction can have. */	478	/* Maximum number of operands an instruction can have. */
439	#define AARCH64_MAX_OPND_NUM 6	479	#define AARCH64_MAX_OPND_NUM 6
440	/* Maximum number of qualifier sequences an instruction can have. */	480	/* Maximum number of qualifier sequences an instruction can have. */
441	#define AARCH64_MAX_QLF_SEQ_NUM 10	481	#define AARCH64_MAX_QLF_SEQ_NUM 10
442	/* Operand qualifier typedef; optimized for the size. */	482	/* Operand qualifier typedef; optimized for the size. */
443	typedef unsigned char aarch64_opnd_qualifier_t;	483	typedef unsigned char aarch64_opnd_qualifier_t;
444	/* Operand qualifier sequence typedef. */	484	/* Operand qualifier sequence typedef. */
445	typedef aarch64_opnd_qualifier_t \	485	typedef aarch64_opnd_qualifier_t \
446	aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];	486	aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
447		487
448	/* FIXME: improve the efficiency. */	488	/* FIXME: improve the efficiency. */
449	static inline bfd_boolean	489	static inline bfd_boolean
450	empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)	490	empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
451	{	491	{
452	int i;	492	int i;
453	for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)	493	for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
454	if (qualifiers[i] != AARCH64_OPND_QLF_NIL)	494	if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
455	return FALSE;	495	return FALSE;
456	return TRUE;	496	return TRUE;
457	}	497	}
458		498
459	/* This structure holds information for a particular opcode. */	499	/* This structure holds information for a particular opcode. */
460		500

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(root)/contrib/toolchain/binutils/include/opcode/aarch64.h – Rev 5191 → 6324