WebSVN – Kolibri OS – Diff – /contrib/toolchain/binutils/include/opcode/aarch64.h

 /* AArch64 assembler/disassembler support.
-   Copyright 2009, 2010, 2011, 2012, 2013  Free Software Foundation, Inc.
+   Copyright (C) 2009-2015 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 #include "bfd.h"
 #include "bfd_stdint.h"
 #include
 #include
+#ifdef __cplusplus
+extern "C" {
+#endif
 /* The offset for pc-relative addressing is currently defined to be 0.  */
 #define AARCH64_PCREL_OFFSET		0
 typedef uint32_t aarch64_insn;
 /* The following bitmasks control CPU features.  */
-/* The following bitmasks control CPU features.  */
+#define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
-#define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
+#define AARCH64_FEATURE_V8_2	0x00000020      /* ARMv8.2 processors.  */
 #define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */
+#define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
+#define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
+#define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */
+#define AARCH64_FEATURE_LSE	0x00100000	/* LSE instructions.  */
+#define AARCH64_FEATURE_PAN	0x00200000	/* PAN instructions.  */
+#define AARCH64_FEATURE_LOR	0x00400000	/* LOR instructions.  */
+#define AARCH64_FEATURE_RDMA	0x00800000	/* v8.1 SIMD instructions.  */
+#define AARCH64_FEATURE_V8_1	0x01000000	/* v8.1 features.  */
-#define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
+#define AARCH64_FEATURE_F16	0x02000000	/* v8.2 FP16 instructions.  */
-#define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
+#define AARCH64_FEATURE_RAS	0x04000000	/* RAS Extensions.  */
-#define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */
+#define AARCH64_FEATURE_PROFILE	0x08000000	/* Statistical Profiling.  */
+/* Architectures are the sum of the base and extensions.  */
+#define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
+						 AARCH64_FEATURE_FP  \
+						 | AARCH64_FEATURE_SIMD)
+#define AARCH64_ARCH_V8_1	AARCH64_FEATURE (AARCH64_FEATURE_V8, \
+						 AARCH64_FEATURE_FP  \
+						 | AARCH64_FEATURE_SIMD	\
+						 | AARCH64_FEATURE_CRC	\
+						 | AARCH64_FEATURE_V8_1 \
+						 | AARCH64_FEATURE_LSE	\
+						 | AARCH64_FEATURE_PAN	\
+						 | AARCH64_FEATURE_LOR	\
+						 | AARCH64_FEATURE_RDMA)
+#define AARCH64_ARCH_V8_2	AARCH64_FEATURE (AARCH64_FEATURE_V8,	\
+						 AARCH64_FEATURE_V8_2	\
+						 | AARCH64_FEATURE_F16	\
+						 | AARCH64_FEATURE_RAS	\
+						 | AARCH64_FEATURE_FP	\
+						 | AARCH64_FEATURE_SIMD	\
+						 | AARCH64_FEATURE_CRC	\
+						 | AARCH64_FEATURE_V8_1 \
+						 | AARCH64_FEATURE_LSE	\
-/* Architectures are the sum of the base and extensions.  */
+						 | AARCH64_FEATURE_PAN	\
-#define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
+						 | AARCH64_FEATURE_LOR	\
-						 AARCH64_FEATURE_FP  \
+						 | AARCH64_FEATURE_RDMA)
 						 | AARCH64_FEATURE_SIMD)
   AARCH64_OPND_Ra,	/* Integer register used in ddp_3src instructions.  */
   AARCH64_OPND_Rt_SYS,	/* Integer register used in system instructions.  */
   AARCH64_OPND_Rd_SP,	/* Integer Rd or SP.  */
+  AARCH64_OPND_Rn_SP,	/* Integer Rn or SP.  */
-  AARCH64_OPND_Rn_SP,	/* Integer Rn or SP.  */
+  AARCH64_OPND_PAIRREG,	/* Paired register operand.  */
   AARCH64_OPND_Rm_EXT,	/* Integer Rm extended.  */
   AARCH64_OPND_Rm_SFT,	/* Integer Rm shifted.  */
   AARCH64_OPND_SYSREG_IC,	/* System register  operand.  */
   AARCH64_OPND_SYSREG_TLBI,	/* System register  operand.  */
   AARCH64_OPND_BARRIER,		/* Barrier operand.  */
   AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
+  AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
 };
 /* Qualifier constrains an operand.  It either specifies a variant of an
      a use is only for the ease of operand encoding/decoding and qualifier
      sequence matching; such a use should not be applied widely; use the value
      constraint qualifiers for immediate operands wherever possible.  */
   AARCH64_OPND_QLF_V_8B,
   AARCH64_OPND_QLF_V_16B,
+  AARCH64_OPND_QLF_V_2H,
   AARCH64_OPND_QLF_V_4H,
   AARCH64_OPND_QLF_V_8H,
   AARCH64_OPND_QLF_V_2S,
   AARCH64_OPND_QLF_V_4S,
   AARCH64_OPND_QLF_V_1D,
   ldstpair_off,
   ldstpair_indexed,
   loadlit,
   log_imm,
   log_shift,
+  lse_atomic,
   movewide,
   pcreladdr,
   ic_system,
   testbranch,
 };
   OP_UBFX,
   OP_BFXIL,
   OP_SBFX,
   OP_SBFIZ,
   OP_BFI,
+  OP_BFC,		/* ARMv8.2.  */
   OP_UBFIZ,
   OP_UXTB,
   OP_UXTH,
   OP_UXTW,
 #define F_MISC (1 << 22)
 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 #define F_N (1 << 23)
 /* Opcode dependent field.  */
 #define F_OD(X) (((X) & 0x7) << 24)
+/* Instruction has the field of 'sz'.  */
+#define F_LSE_SZ (1 << 27)
-/* Next bit is 27.  */
+/* Next bit is 28.  */
 static inline bfd_boolean
 alias_opcode_p (const aarch64_opcode *opcode)
+{
+}
 static inline bfd_boolean
 opcode_has_special_coder (const aarch64_opcode *opcode)
 {
-  return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
+  return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 	  | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
     : FALSE;
+}
 };
 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
+extern const struct aarch64_name_value_pair aarch64_prfops [32];
-extern const struct aarch64_name_value_pair aarch64_prfops [32];
+extern const struct aarch64_name_value_pair aarch64_hint_options [];
 typedef struct
+{
 } aarch64_sys_reg;
 extern const aarch64_sys_reg aarch64_sys_regs [];
 extern const aarch64_sys_reg aarch64_pstatefields [];
+extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
+extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
+						const aarch64_sys_reg *);
+extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
-extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
+						    const aarch64_sys_reg *);
 typedef struct
+{
-  const char *template;
+  const char *name;
   uint32_t value;
+  uint32_t flags ;
+} aarch64_sys_ins_reg;
+extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bfd_boolean
-  int has_xt;
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
-} aarch64_sys_ins_reg;
+				 const aarch64_sys_ins_reg *);
 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
       aarch64_insn sysreg;
       /* The encoding of the PSTATE field.  */
       aarch64_insn pstatefield;
       const aarch64_sys_ins_reg *sysins_op;
       const struct aarch64_name_value_pair *barrier;
+      const struct aarch64_name_value_pair *hint_option;
       const struct aarch64_name_value_pair *prfop;
     };
   /* Operand shifter; in use when the operand is a register offset address,
 aarch64_num_of_operands (const aarch64_opcode *);
 extern int
 aarch64_stack_pointer_p (const aarch64_opnd_info *);
+extern int
+aarch64_zero_register_p (const aarch64_opnd_info *);
-extern
+extern int
-int aarch64_zero_register_p (const aarch64_opnd_info *);
+aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 /* Given an operand qualifier, return the expected data element size
 #else  /* !DEBUG_AARCH64 */
 #define DEBUG_TRACE(M, ...) ;
 #define DEBUG_TRACE_IF(C, M, ...) ;
 #endif /* DEBUG_AARCH64 */
+#ifdef __cplusplus
+}
+#endif

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(root)/contrib/toolchain/binutils/include/opcode/aarch64.h – Rev 5191 → 6324