WebSVN – Kolibri OS – Diff – /contrib/sdk/sources/libdrm/intel/intel_bufmgr.c


/*
 * Copyright © 2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt 
 *
 */
 
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
//#include 
#include "intel_bufmgr.h"
#include "intel_bufmgr_priv.h"
#include "xf86drm.h"
 
/** @file intel_bufmgr.c
 *
 * Convenience functions for buffer management methods.
 */
 
drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
				 unsigned long size, unsigned int alignment)
{
	return bufmgr->bo_alloc(bufmgr, name, size, alignment);
}
 
 
drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
					    const char *name,
					    unsigned long size,
					    unsigned int alignment)
{
	return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
}
 
 
drm_intel_bo *
drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
                        int x, int y, int cpp, uint32_t *tiling_mode,
                        unsigned long *pitch, unsigned long flags)
{
	return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
				      tiling_mode, pitch, flags);
}
 
void drm_intel_bo_reference(drm_intel_bo *bo)
{
	bo->bufmgr->bo_reference(bo);
}
 
void drm_intel_bo_unreference(drm_intel_bo *bo)
{
	if (bo == NULL)
		return;
 
	bo->bufmgr->bo_unreference(bo);
}
 
int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
{
	return buf->bufmgr->bo_map(buf, write_enable);
}
 
int drm_intel_bo_unmap(drm_intel_bo *buf)
{
	return buf->bufmgr->bo_unmap(buf);
}
 
int
drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
		     unsigned long size, const void *data)
{
	return bo->bufmgr->bo_subdata(bo, offset, size, data);
}
 
int
drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
			 unsigned long size, void *data)
{
	int ret;
//	if (bo->bufmgr->bo_get_subdata)
//		return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
 
	if (size == 0 || data == NULL)
		return 0;
 
	ret = drm_intel_bo_map(bo, 0);
	if (ret)
		return ret;
	memcpy(data, (unsigned char *)bo->virtual + offset, size);
	drm_intel_bo_unmap(bo);
	return 0;
}
 
void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
{
	bo->bufmgr->bo_wait_rendering(bo);
}
 
void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
{
	bufmgr->destroy(bufmgr);
}
 
int
drm_intel_bo_exec(drm_intel_bo *bo, int used,
		  drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
{
	return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
}
 
int
drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
		drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
		unsigned int rings)
{
	if (bo->bufmgr->bo_mrb_exec)
		return bo->bufmgr->bo_mrb_exec(bo, used,
					cliprects, num_cliprects, DR4,
					rings);
 
	switch (rings) {
	case I915_EXEC_DEFAULT:
	case I915_EXEC_RENDER:
		return bo->bufmgr->bo_exec(bo, used,
					   cliprects, num_cliprects, DR4);
	default:
		return -ENODEV;
	}
}
 
void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
{
	bufmgr->debug = enable_debug;
}
 
int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
{
	return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
}
 
int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
{
	if (bo->bufmgr->bo_flink)
		return bo->bufmgr->bo_flink(bo, name);
 
	return -ENODEV;
}
 
int
drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
			drm_intel_bo *target_bo, uint32_t target_offset,
			uint32_t read_domains, uint32_t write_domain)
{
	return bo->bufmgr->bo_emit_reloc(bo, offset,
					 target_bo, target_offset,
					 read_domains, write_domain);
}
 
/* For fence registers, not GL fences */
int
drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
			      drm_intel_bo *target_bo, uint32_t target_offset,
			      uint32_t read_domains, uint32_t write_domain)
{
	return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
					       target_bo, target_offset,
					       read_domains, write_domain);
}
 
 
int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
{
	if (bo->bufmgr->bo_pin)
		return bo->bufmgr->bo_pin(bo, alignment);
 
	return -ENODEV;
}
 
int drm_intel_bo_unpin(drm_intel_bo *bo)
{
	if (bo->bufmgr->bo_unpin)
		return bo->bufmgr->bo_unpin(bo);
 
	return -ENODEV;
}
 
int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
			    uint32_t stride)
{
	if (bo->bufmgr->bo_set_tiling)
		return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
 
	*tiling_mode = I915_TILING_NONE;
	return 0;
}
 
int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
			    uint32_t * swizzle_mode)
{
	if (bo->bufmgr->bo_get_tiling)
		return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
 
	*tiling_mode = I915_TILING_NONE;
	*swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	return 0;
}
 
int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
{
	if (bo->bufmgr->bo_disable_reuse)
		return bo->bufmgr->bo_disable_reuse(bo);
	return 0;
}
 
int drm_intel_bo_is_reusable(drm_intel_bo *bo)
{
	if (bo->bufmgr->bo_is_reusable)
		return bo->bufmgr->bo_is_reusable(bo);
	return 0;
}
 
int drm_intel_bo_busy(drm_intel_bo *bo)
{
	if (bo->bufmgr->bo_busy)
		return bo->bufmgr->bo_busy(bo);
	return 0;
}
 
int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
{
	if (bo->bufmgr->bo_madvise)
		return bo->bufmgr->bo_madvise(bo, madv);
	return -1;
}
 
int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
{
	return bo->bufmgr->bo_references(bo, target_bo);
}
 
 
 
#if 0
static size_t
drm_intel_probe_agp_aperture_size(int fd)
{
	struct pci_device *pci_dev;
	size_t size = 0;
	int ret;
 
	ret = pci_system_init();
	if (ret)
		goto err;
 
	/* XXX handle multiple adaptors? */
	pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
	if (pci_dev == NULL)
		goto err;
 
	ret = pci_device_probe(pci_dev);
	if (ret)
		goto err;
 
	size = pci_dev->regions[2].size;
err:
	pci_system_cleanup ();
	return size;
}
#endif
 
int drm_intel_get_aperture_sizes(int fd,
				 size_t *mappable,
				 size_t *total)
{
 
	struct drm_i915_gem_get_aperture aperture;
	int ret;
 
	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
	if (ret)
		return ret;
 
	/* XXX add a query for the kernel value? */
    *mappable = 512 * 1024 * 1024; /* minimum possible value */
	*total = aperture.aper_size;
	return 0;
}

Rev 4363	Rev 5068
1	/*	1	/*
2	* Copyright © 2007 Intel Corporation	2	* Copyright © 2007 Intel Corporation
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice (including the next	11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the	12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.	13	* Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.	21	* IN THE SOFTWARE.
22	*	22	*
23	* Authors:	23	* Authors:
24	* Eric Anholt	24	* Eric Anholt
25	*	25	*
26	*/	26	*/
27		27
28	#ifdef HAVE_CONFIG_H	28	#ifdef HAVE_CONFIG_H
29	#include "config.h"	29	#include "config.h"
30	#endif	30	#endif
31		31
32	#include	32	#include
33	#include	33	#include
34	#include	34	#include
35	#include	35	#include
36	#include	36	#include
37	#include	37	#include
38	#include	38	#include
39	//#include	39	//#include
40	#include "intel_bufmgr.h"	40	#include "intel_bufmgr.h"
41	#include "intel_bufmgr_priv.h"	41	#include "intel_bufmgr_priv.h"
42	#include "xf86drm.h"	42	#include "xf86drm.h"
43		43
44	/** @file intel_bufmgr.c	44	/** @file intel_bufmgr.c
45	*	45	*
46	* Convenience functions for buffer management methods.	46	* Convenience functions for buffer management methods.
47	*/	47	*/
48		48
49	drm_intel_bo drm_intel_bo_alloc(drm_intel_bufmgr bufmgr, const char *name,	49	drm_intel_bo drm_intel_bo_alloc(drm_intel_bufmgr bufmgr, const char *name,
50	unsigned long size, unsigned int alignment)	50	unsigned long size, unsigned int alignment)
51	{	51	{
52	return bufmgr->bo_alloc(bufmgr, name, size, alignment);	52	return bufmgr->bo_alloc(bufmgr, name, size, alignment);
53	}	53	}
54		-
55	#if 0	54
56	drm_intel_bo drm_intel_bo_alloc_for_render(drm_intel_bufmgr bufmgr,	55	drm_intel_bo drm_intel_bo_alloc_for_render(drm_intel_bufmgr bufmgr,
57	const char *name,	56	const char *name,
58	unsigned long size,	57	unsigned long size,
59	unsigned int alignment)	58	unsigned int alignment)
60	{	59	{
61	return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);	60	return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
62	}	61	}
63	#endif	-
64		62
65	drm_intel_bo *	63	drm_intel_bo *
66	drm_intel_bo_alloc_tiled(drm_intel_bufmgr bufmgr, const char name,	64	drm_intel_bo_alloc_tiled(drm_intel_bufmgr bufmgr, const char name,
67	int x, int y, int cpp, uint32_t *tiling_mode,	65	int x, int y, int cpp, uint32_t *tiling_mode,
68	unsigned long *pitch, unsigned long flags)	66	unsigned long *pitch, unsigned long flags)
69	{	67	{
70	return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,	68	return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
71	tiling_mode, pitch, flags);	69	tiling_mode, pitch, flags);
72	}	70	}
73		71
74	void drm_intel_bo_reference(drm_intel_bo *bo)	72	void drm_intel_bo_reference(drm_intel_bo *bo)
75	{	73	{
76	bo->bufmgr->bo_reference(bo);	74	bo->bufmgr->bo_reference(bo);
77	}	75	}
78		76
79	void drm_intel_bo_unreference(drm_intel_bo *bo)	77	void drm_intel_bo_unreference(drm_intel_bo *bo)
80	{	78	{
81	if (bo == NULL)	79	if (bo == NULL)
82	return;	80	return;
83		81
84	bo->bufmgr->bo_unreference(bo);	82	bo->bufmgr->bo_unreference(bo);
85	}	83	}
86		84
87	int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)	85	int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
88	{	86	{
89	return buf->bufmgr->bo_map(buf, write_enable);	87	return buf->bufmgr->bo_map(buf, write_enable);
90	}	88	}
91		89
92	int drm_intel_bo_unmap(drm_intel_bo *buf)	90	int drm_intel_bo_unmap(drm_intel_bo *buf)
93	{	91	{
94	return buf->bufmgr->bo_unmap(buf);	92	return buf->bufmgr->bo_unmap(buf);
95	}	93	}
96		94
97	int	95	int
98	drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,	96	drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
99	unsigned long size, const void *data)	97	unsigned long size, const void *data)
100	{	98	{
101	return bo->bufmgr->bo_subdata(bo, offset, size, data);	99	return bo->bufmgr->bo_subdata(bo, offset, size, data);
102	}	100	}
103		101
104	int	102	int
105	drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,	103	drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
106	unsigned long size, void *data)	104	unsigned long size, void *data)
107	{	105	{
108	int ret;	106	int ret;
109	// if (bo->bufmgr->bo_get_subdata)	107	// if (bo->bufmgr->bo_get_subdata)
110	// return bo->bufmgr->bo_get_subdata(bo, offset, size, data);	108	// return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
111		109
112	if (size == 0 \|\| data == NULL)	110	if (size == 0 \|\| data == NULL)
113	return 0;	111	return 0;
114		112
115	ret = drm_intel_bo_map(bo, 0);	113	ret = drm_intel_bo_map(bo, 0);
116	if (ret)	114	if (ret)
117	return ret;	115	return ret;
118	memcpy(data, (unsigned char *)bo->virtual + offset, size);	116	memcpy(data, (unsigned char *)bo->virtual + offset, size);
119	drm_intel_bo_unmap(bo);	117	drm_intel_bo_unmap(bo);
120	return 0;	118	return 0;
121	}	119	}
122		120
123	void drm_intel_bo_wait_rendering(drm_intel_bo *bo)	121	void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
124	{	122	{
125	bo->bufmgr->bo_wait_rendering(bo);	123	bo->bufmgr->bo_wait_rendering(bo);
126	}	124	}
127		125
128	void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)	126	void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
129	{	127	{
130	bufmgr->destroy(bufmgr);	128	bufmgr->destroy(bufmgr);
131	}	129	}
132		130
133	int	131	int
134	drm_intel_bo_exec(drm_intel_bo *bo, int used,	132	drm_intel_bo_exec(drm_intel_bo *bo, int used,
135	drm_clip_rect_t * cliprects, int num_cliprects, int DR4)	133	drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
136	{	134	{
137	return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);	135	return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
138	}	136	}
139		137
140	int	138	int
141	drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,	139	drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
142	drm_clip_rect_t *cliprects, int num_cliprects, int DR4,	140	drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
143	unsigned int rings)	141	unsigned int rings)
144	{	142	{
145	if (bo->bufmgr->bo_mrb_exec)	143	if (bo->bufmgr->bo_mrb_exec)
146	return bo->bufmgr->bo_mrb_exec(bo, used,	144	return bo->bufmgr->bo_mrb_exec(bo, used,
147	cliprects, num_cliprects, DR4,	145	cliprects, num_cliprects, DR4,
148	rings);	146	rings);
149		147
150	switch (rings) {	148	switch (rings) {
151	case I915_EXEC_DEFAULT:	149	case I915_EXEC_DEFAULT:
152	case I915_EXEC_RENDER:	150	case I915_EXEC_RENDER:
153	return bo->bufmgr->bo_exec(bo, used,	151	return bo->bufmgr->bo_exec(bo, used,
154	cliprects, num_cliprects, DR4);	152	cliprects, num_cliprects, DR4);
155	default:	153	default:
156	return -ENODEV;	154	return -ENODEV;
157	}	155	}
158	}	156	}
159		157
160	void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)	158	void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
161	{	159	{
162	bufmgr->debug = enable_debug;	160	bufmgr->debug = enable_debug;
163	}	161	}
164		162
165	int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)	163	int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
166	{	164	{
167	return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);	165	return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
168	}	166	}
169		167
170	int drm_intel_bo_flink(drm_intel_bo bo, uint32_t name)	168	int drm_intel_bo_flink(drm_intel_bo bo, uint32_t name)
171	{	169	{
172	if (bo->bufmgr->bo_flink)	170	if (bo->bufmgr->bo_flink)
173	return bo->bufmgr->bo_flink(bo, name);	171	return bo->bufmgr->bo_flink(bo, name);
174		172
175	return -ENODEV;	173	return -ENODEV;
176	}	174	}
177		175
178	int	176	int
179	drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,	177	drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
180	drm_intel_bo *target_bo, uint32_t target_offset,	178	drm_intel_bo *target_bo, uint32_t target_offset,
181	uint32_t read_domains, uint32_t write_domain)	179	uint32_t read_domains, uint32_t write_domain)
182	{	180	{
183	return bo->bufmgr->bo_emit_reloc(bo, offset,	181	return bo->bufmgr->bo_emit_reloc(bo, offset,
184	target_bo, target_offset,	182	target_bo, target_offset,
185	read_domains, write_domain);	183	read_domains, write_domain);
186	}	184	}
187		185
188	/* For fence registers, not GL fences */	186	/* For fence registers, not GL fences */
189	int	187	int
190	drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,	188	drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
191	drm_intel_bo *target_bo, uint32_t target_offset,	189	drm_intel_bo *target_bo, uint32_t target_offset,
192	uint32_t read_domains, uint32_t write_domain)	190	uint32_t read_domains, uint32_t write_domain)
193	{	191	{
194	return bo->bufmgr->bo_emit_reloc_fence(bo, offset,	192	return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
195	target_bo, target_offset,	193	target_bo, target_offset,
196	read_domains, write_domain);	194	read_domains, write_domain);
197	}	195	}
198		196
199		197
200	int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)	198	int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
201	{	199	{
202	if (bo->bufmgr->bo_pin)	200	if (bo->bufmgr->bo_pin)
203	return bo->bufmgr->bo_pin(bo, alignment);	201	return bo->bufmgr->bo_pin(bo, alignment);
204		202
205	return -ENODEV;	203	return -ENODEV;
206	}	204	}
207		205
208	int drm_intel_bo_unpin(drm_intel_bo *bo)	206	int drm_intel_bo_unpin(drm_intel_bo *bo)
209	{	207	{
210	if (bo->bufmgr->bo_unpin)	208	if (bo->bufmgr->bo_unpin)
211	return bo->bufmgr->bo_unpin(bo);	209	return bo->bufmgr->bo_unpin(bo);
212		210
213	return -ENODEV;	211	return -ENODEV;
214	}	212	}
215		213
216	int drm_intel_bo_set_tiling(drm_intel_bo bo, uint32_t tiling_mode,	214	int drm_intel_bo_set_tiling(drm_intel_bo bo, uint32_t tiling_mode,
217	uint32_t stride)	215	uint32_t stride)
218	{	216	{
219	if (bo->bufmgr->bo_set_tiling)	217	if (bo->bufmgr->bo_set_tiling)
220	return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);	218	return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
221		219
222	*tiling_mode = I915_TILING_NONE;	220	*tiling_mode = I915_TILING_NONE;
223	return 0;	221	return 0;
224	}	222	}
225		223
226	int drm_intel_bo_get_tiling(drm_intel_bo bo, uint32_t tiling_mode,	224	int drm_intel_bo_get_tiling(drm_intel_bo bo, uint32_t tiling_mode,
227	uint32_t * swizzle_mode)	225	uint32_t * swizzle_mode)
228	{	226	{
229	if (bo->bufmgr->bo_get_tiling)	227	if (bo->bufmgr->bo_get_tiling)
230	return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);	228	return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
231		229
232	*tiling_mode = I915_TILING_NONE;	230	*tiling_mode = I915_TILING_NONE;
233	*swizzle_mode = I915_BIT_6_SWIZZLE_NONE;	231	*swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
234	return 0;	232	return 0;
235	}	233	}
236		234
237	int drm_intel_bo_disable_reuse(drm_intel_bo *bo)	235	int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
238	{	236	{
239	if (bo->bufmgr->bo_disable_reuse)	237	if (bo->bufmgr->bo_disable_reuse)
240	return bo->bufmgr->bo_disable_reuse(bo);	238	return bo->bufmgr->bo_disable_reuse(bo);
241	return 0;	239	return 0;
242	}	240	}
243		241
244	int drm_intel_bo_is_reusable(drm_intel_bo *bo)	242	int drm_intel_bo_is_reusable(drm_intel_bo *bo)
245	{	243	{
246	if (bo->bufmgr->bo_is_reusable)	244	if (bo->bufmgr->bo_is_reusable)
247	return bo->bufmgr->bo_is_reusable(bo);	245	return bo->bufmgr->bo_is_reusable(bo);
248	return 0;	246	return 0;
249	}	247	}
250		248
251	int drm_intel_bo_busy(drm_intel_bo *bo)	249	int drm_intel_bo_busy(drm_intel_bo *bo)
252	{	250	{
253	if (bo->bufmgr->bo_busy)	251	if (bo->bufmgr->bo_busy)
254	return bo->bufmgr->bo_busy(bo);	252	return bo->bufmgr->bo_busy(bo);
255	return 0;	253	return 0;
256	}	254	}
257		255
258	int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)	256	int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
259	{	257	{
260	if (bo->bufmgr->bo_madvise)	258	if (bo->bufmgr->bo_madvise)
261	return bo->bufmgr->bo_madvise(bo, madv);	259	return bo->bufmgr->bo_madvise(bo, madv);
262	return -1;	260	return -1;
263	}	261	}
264		262
265	int drm_intel_bo_references(drm_intel_bo bo, drm_intel_bo target_bo)	263	int drm_intel_bo_references(drm_intel_bo bo, drm_intel_bo target_bo)
266	{	264	{
267	return bo->bufmgr->bo_references(bo, target_bo);	265	return bo->bufmgr->bo_references(bo, target_bo);
268	}	266	}
269		267
270		268
271		269
272	#if 0	270	#if 0
273	static size_t	271	static size_t
274	drm_intel_probe_agp_aperture_size(int fd)	272	drm_intel_probe_agp_aperture_size(int fd)
275	{	273	{
276	struct pci_device *pci_dev;	274	struct pci_device *pci_dev;
277	size_t size = 0;	275	size_t size = 0;
278	int ret;	276	int ret;
279		277
280	ret = pci_system_init();	278	ret = pci_system_init();
281	if (ret)	279	if (ret)
282	goto err;	280	goto err;
283		281
284	/* XXX handle multiple adaptors? */	282	/* XXX handle multiple adaptors? */
285	pci_dev = pci_device_find_by_slot(0, 0, 2, 0);	283	pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
286	if (pci_dev == NULL)	284	if (pci_dev == NULL)
287	goto err;	285	goto err;
288		286
289	ret = pci_device_probe(pci_dev);	287	ret = pci_device_probe(pci_dev);
290	if (ret)	288	if (ret)
291	goto err;	289	goto err;
292		290
293	size = pci_dev->regions[2].size;	291	size = pci_dev->regions[2].size;
294	err:	292	err:
295	pci_system_cleanup ();	293	pci_system_cleanup ();
296	return size;	294	return size;
297	}	295	}
298	#endif	296	#endif
299		297
300	int drm_intel_get_aperture_sizes(int fd,	298	int drm_intel_get_aperture_sizes(int fd,
301	size_t *mappable,	299	size_t *mappable,
302	size_t *total)	300	size_t *total)
303	{	301	{
304		302
305	struct drm_i915_gem_get_aperture aperture;	303	struct drm_i915_gem_get_aperture aperture;
306	int ret;	304	int ret;
307		305
308	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);	306	ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
309	if (ret)	307	if (ret)
310	return ret;	308	return ret;
311		309
312	/* XXX add a query for the kernel value? */	310	/* XXX add a query for the kernel value? */
313	mappable = 512 1024 * 1024; /* minimum possible value */	311	mappable = 512 1024 * 1024; /* minimum possible value */
314	*total = aperture.aper_size;	312	*total = aperture.aper_size;
315	return 0;	313	return 0;
316	}	314	}

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(root)/contrib/sdk/sources/libdrm/intel/intel_bufmgr.c – Rev 4363 → 5068