Subversion Repositories Kolibri OS

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)

enum adreno_mmu_clnt_beh {

	BEH_NEVR = 0,

	BEH_TRAN_RNG = 1,

	BEH_TRAN_FLT = 2,

};

#define REG_AXXX_MH_MMU_CONFIG					0x00000040

#define AXXX_MH_MMU_CONFIG_MMU_ENABLE				0x00000001

#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE			0x00000002

#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK		0x00000030

#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT		4

static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK		0x000000c0

#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT		6

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK		0x00000300

#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT		8

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK		0x00000c00

#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT		10

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK		0x00003000

#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT		12

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK		0x0000c000

#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT		14

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK		0x00030000

#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT		16

static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK		0x000c0000

#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT		18

static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK		0x00300000

#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT		20

static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK		0x00c00000

#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT		22

static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;

}

#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK		0x03000000

#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT		24

static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)

{

	return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;

}

#define REG_AXXX_MH_MMU_VA_RANGE				0x00000041

#define REG_AXXX_MH_MMU_PT_BASE					0x00000042

#define REG_AXXX_MH_MMU_PAGE_FAULT				0x00000043

#define REG_AXXX_MH_MMU_TRAN_ERROR				0x00000044

#define REG_AXXX_MH_MMU_INVALIDATE				0x00000045

#define REG_AXXX_MH_MMU_MPU_BASE				0x00000046

#define REG_AXXX_MH_MMU_MPU_END					0x00000047

#define REG_AXXX_CP_RB_BASE					0x000001c0

#define REG_AXXX_CP_RB_CNTL					0x000001c1

#define AXXX_CP_RB_CNTL_BUFSZ__MASK				0x0000003f

#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT				0

static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)

{

	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;

}

#define AXXX_CP_RB_CNTL_BLKSZ__MASK				0x00003f00

#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT				8

static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)

{

	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;

}

#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK				0x00030000

#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT				16

static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)

{

	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;

}

#define AXXX_CP_RB_CNTL_POLL_EN					0x00100000

#define AXXX_CP_RB_CNTL_NO_UPDATE				0x08000000

#define AXXX_CP_RB_CNTL_RPTR_WR_EN				0x80000000

#define REG_AXXX_CP_RB_RPTR_ADDR				0x000001c3

#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK				0x00000003

#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT			0

static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)

{

	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;

}

#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK				0xfffffffc

#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT			2

static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)

{

	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;

}

#define REG_AXXX_CP_RB_RPTR					0x000001c4

#define REG_AXXX_CP_RB_WPTR					0x000001c5

#define REG_AXXX_CP_RB_WPTR_DELAY				0x000001c6

#define REG_AXXX_CP_RB_RPTR_WR					0x000001c7

#define REG_AXXX_CP_RB_WPTR_BASE				0x000001c8

#define REG_AXXX_CP_QUEUE_THRESHOLDS				0x000001d5

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK		0x0000000f

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT		0

static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)

{

	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;

}

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK		0x00000f00

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT		8

static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)

{

	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;

}

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK		0x000f0000

#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT		16

static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)

{

	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;

}

#define REG_AXXX_CP_MEQ_THRESHOLDS				0x000001d6

#define REG_AXXX_CP_CSQ_AVAIL					0x000001d7

#define AXXX_CP_CSQ_AVAIL_RING__MASK				0x0000007f

#define AXXX_CP_CSQ_AVAIL_RING__SHIFT				0

static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;

}

#define AXXX_CP_CSQ_AVAIL_IB1__MASK				0x00007f00

#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT				8

static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;

}

#define AXXX_CP_CSQ_AVAIL_IB2__MASK				0x007f0000

#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT				16

static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;

}

#define REG_AXXX_CP_STQ_AVAIL					0x000001d8

#define AXXX_CP_STQ_AVAIL_ST__MASK				0x0000007f

#define AXXX_CP_STQ_AVAIL_ST__SHIFT				0

static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)

{

	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;

}

#define REG_AXXX_CP_MEQ_AVAIL					0x000001d9

#define AXXX_CP_MEQ_AVAIL_MEQ__MASK				0x0000001f

#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT				0

static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)

{

	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;

}

#define REG_AXXX_SCRATCH_UMSK					0x000001dc

#define AXXX_SCRATCH_UMSK_UMSK__MASK				0x000000ff

#define AXXX_SCRATCH_UMSK_UMSK__SHIFT				0

static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)

{

	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;

}

#define AXXX_SCRATCH_UMSK_SWAP__MASK				0x00030000

#define AXXX_SCRATCH_UMSK_SWAP__SHIFT				16

static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)

{

	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;

}

#define REG_AXXX_SCRATCH_ADDR					0x000001dd

#define REG_AXXX_CP_ME_RDADDR					0x000001ea

#define REG_AXXX_CP_STATE_DEBUG_INDEX				0x000001ec

#define REG_AXXX_CP_STATE_DEBUG_DATA				0x000001ed

#define REG_AXXX_CP_INT_CNTL					0x000001f2

#define REG_AXXX_CP_INT_STATUS					0x000001f3

#define REG_AXXX_CP_INT_ACK					0x000001f4

#define REG_AXXX_CP_ME_CNTL					0x000001f6

#define REG_AXXX_CP_ME_STATUS					0x000001f7

#define REG_AXXX_CP_ME_RAM_WADDR				0x000001f8

#define REG_AXXX_CP_ME_RAM_RADDR				0x000001f9

#define REG_AXXX_CP_ME_RAM_DATA					0x000001fa

#define REG_AXXX_CP_DEBUG					0x000001fc

#define AXXX_CP_DEBUG_PREDICATE_DISABLE				0x00800000

#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE			0x01000000

#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE			0x02000000

#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS			0x04000000

#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE			0x08000000

#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE			0x10000000

#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL			0x40000000

#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE			0x80000000

#define REG_AXXX_CP_CSQ_RB_STAT					0x000001fd

#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK				0x0000007f

#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT				0

static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;

}

#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK				0x007f0000

#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT				16

static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;

}

#define REG_AXXX_CP_CSQ_IB1_STAT				0x000001fe

#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK				0x0000007f

#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT			0

static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;

}

#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK				0x007f0000

#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT			16

static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;

}

#define REG_AXXX_CP_CSQ_IB2_STAT				0x000001ff

#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK				0x0000007f

#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT			0

static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;

}

#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK				0x007f0000

#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT			16

static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)

{

	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;

}

#define REG_AXXX_CP_SCRATCH_REG0				0x00000578

#define REG_AXXX_CP_SCRATCH_REG1				0x00000579

#define REG_AXXX_CP_SCRATCH_REG2				0x0000057a

#define REG_AXXX_CP_SCRATCH_REG3				0x0000057b

#define REG_AXXX_CP_SCRATCH_REG4				0x0000057c

#define REG_AXXX_CP_SCRATCH_REG5				0x0000057d

#define REG_AXXX_CP_SCRATCH_REG6				0x0000057e

#define REG_AXXX_CP_SCRATCH_REG7				0x0000057f

#define REG_AXXX_CP_ME_CF_EVENT_SRC				0x0000060a

#define REG_AXXX_CP_ME_CF_EVENT_ADDR				0x0000060b

#define REG_AXXX_CP_ME_CF_EVENT_DATA				0x0000060c

#define REG_AXXX_CP_ME_NRT_ADDR					0x0000060d

#define REG_AXXX_CP_ME_NRT_DATA					0x0000060e