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1 | #ifndef _PXA255_TIMR_H_ |
1 | #ifndef _PXA255_TIMR_H_ |
2 | #define _PXA255_TIMR_H_ |
2 | #define _PXA255_TIMR_H_ |
3 | 3 | ||
4 | #include "mem.h" |
4 | #include "mem.h" |
5 | #include "cpu.h" |
5 | #include "CPU.h" |
6 | #include "pxa255_IC.h" |
6 | #include "pxa255_IC.h" |
7 | 7 | ||
8 | 8 | ||
9 | /* |
9 | /* |
10 | PXA255 OS timers controller |
10 | PXA255 OS timers controller |
11 | 11 | ||
12 | PURRPOSE: timers are useful for stuff :) |
12 | PURRPOSE: timers are useful for stuff :) |
13 | 13 | ||
14 | */ |
14 | */ |
15 | 15 | ||
16 | #define PXA255_TIMR_BASE 0x40A00000UL |
16 | #define PXA255_TIMR_BASE 0x40A00000UL |
17 | #define PXA255_TIMR_SIZE 0x00010000UL |
17 | #define PXA255_TIMR_SIZE 0x00010000UL |
18 | 18 | ||
19 | 19 | ||
20 | typedef struct{ |
20 | typedef struct{ |
21 | 21 | ||
22 | Pxa255ic* ic; |
22 | Pxa255ic* ic; |
23 | 23 | ||
24 | UInt32 OSMR[4]; //Match Register 0-3 |
24 | UInt32 OSMR[4]; //Match Register 0-3 |
25 | UInt32 OIER; //Interrupt Enable |
25 | UInt32 OIER; //Interrupt Enable |
26 | UInt32 OWER; //Watchdog enable |
26 | UInt32 OWER; //Watchdog enable |
27 | UInt32 OSCR; //Counter Register |
27 | UInt32 OSCR; //Counter Register |
28 | UInt32 OSSR; //Status Register |
28 | UInt32 OSSR; //Status Register |
29 | 29 | ||
30 | }Pxa255timr; |
30 | }Pxa255timr; |
31 | 31 | ||
32 | Boolean pxa255timrInit(Pxa255timr* timr, ArmMem* physMem, Pxa255ic* ic); |
32 | Boolean pxa255timrInit(Pxa255timr* timr, ArmMem* physMem, Pxa255ic* ic); |
33 | void pxa255timrTick(Pxa255timr* timr); |
33 | void pxa255timrTick(Pxa255timr* timr); |
34 | 34 | ||
35 | 35 | ||
36 | #endif |
36 | #endif |