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Rev 1428 | Rev 1430 | ||
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Line 53... | Line 53... | ||
53 | 53 | ||
54 | void rv515_ring_start(struct radeon_device *rdev) |
54 | void rv515_ring_start(struct radeon_device *rdev) |
55 | { |
55 | { |
Line 56... | Line -... | ||
56 | int r; |
- | |
57 | - | ||
58 | ENTER(); |
56 | int r; |
59 | 57 | ||
60 | r = radeon_ring_lock(rdev, 64); |
58 | r = radeon_ring_lock(rdev, 64); |
61 | if (r) { |
59 | if (r) { |
62 | return; |
60 | return; |
Line 117... | Line 115... | ||
117 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
115 | radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); |
118 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
116 | radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
119 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
117 | radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
120 | radeon_ring_write(rdev, 0); |
118 | radeon_ring_write(rdev, 0); |
121 | radeon_ring_unlock_commit(rdev); |
119 | radeon_ring_unlock_commit(rdev); |
122 | - | ||
123 | LEAVE(); |
- | |
124 | - | ||
125 | } |
120 | } |
Line 126... | Line 121... | ||
126 | 121 | ||
127 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
122 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
128 | { |
123 | { |
Line 181... | Line 176... | ||
181 | { |
176 | { |
182 | uint32_t tmp; |
177 | uint32_t tmp; |
183 | bool reinit_cp; |
178 | bool reinit_cp; |
184 | int i; |
179 | int i; |
Line 185... | Line -... | ||
185 | - | ||
186 | ENTER(); |
- | |
187 | 180 | ||
188 | reinit_cp = rdev->cp.ready; |
181 | reinit_cp = rdev->cp.ready; |
189 | rdev->cp.ready = false; |
182 | rdev->cp.ready = false; |
190 | for (i = 0; i < rdev->usec_timeout; i++) { |
183 | for (i = 0; i < rdev->usec_timeout; i++) { |
191 | WREG32(CP_CSQ_MODE, 0); |
184 | WREG32(CP_CSQ_MODE, 0); |
Line 235... | Line 228... | ||
235 | 228 | ||
236 | int rv515_gpu_reset(struct radeon_device *rdev) |
229 | int rv515_gpu_reset(struct radeon_device *rdev) |
237 | { |
230 | { |
Line 238... | Line -... | ||
238 | uint32_t status; |
- | |
239 | - | ||
240 | ENTER(); |
231 | uint32_t status; |
241 | 232 | ||
242 | /* reset order likely matter */ |
233 | /* reset order likely matter */ |
243 | status = RREG32(RBBM_STATUS); |
234 | status = RREG32(RBBM_STATUS); |
244 | /* reset HDP */ |
235 | /* reset HDP */ |
Line 284... | Line 275... | ||
284 | rdev->mc.vram_width = 128; |
275 | rdev->mc.vram_width = 128; |
285 | break; |
276 | break; |
286 | } |
277 | } |
287 | } |
278 | } |
Line 288... | Line 279... | ||
288 | 279 | ||
289 | void rv515_vram_info(struct radeon_device *rdev) |
280 | void rv515_mc_init(struct radeon_device *rdev) |
290 | { |
281 | { |
Line 291... | Line 282... | ||
291 | fixed20_12 a; |
282 | fixed20_12 a; |
292 | - | ||
293 | rv515_vram_get_type(rdev); |
283 | |
- | 284 | rv515_vram_get_type(rdev); |
|
- | 285 | r100_vram_init_sizes(rdev); |
|
- | 286 | radeon_vram_location(rdev, &rdev->mc, 0); |
|
294 | 287 | if (!(rdev->flags & RADEON_IS_AGP)) |
|
295 | r100_vram_init_sizes(rdev); |
288 | radeon_gtt_location(rdev, &rdev->mc); |
296 | /* FIXME: we should enforce default clock in case GPU is not in |
289 | /* FIXME: we should enforce default clock in case GPU is not in |
297 | * default setup |
290 | * default setup |
298 | */ |
291 | */ |
Line 547... | Line 540... | ||
547 | return -EINVAL; |
540 | return -EINVAL; |
548 | /* Initialize clocks */ |
541 | /* Initialize clocks */ |
549 | radeon_get_clock_info(rdev->ddev); |
542 | radeon_get_clock_info(rdev->ddev); |
550 | /* Initialize power management */ |
543 | /* Initialize power management */ |
551 | radeon_pm_init(rdev); |
544 | radeon_pm_init(rdev); |
552 | /* Get vram informations */ |
545 | /* initialize AGP */ |
553 | rv515_vram_info(rdev); |
- | |
554 | /* Initialize memory controller (also test AGP) */ |
546 | if (rdev->flags & RADEON_IS_AGP) { |
555 | r = r420_mc_init(rdev); |
547 | r = radeon_agp_init(rdev); |
556 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
- | |
557 | if (r) |
548 | if (r) { |
- | 549 | radeon_agp_disable(rdev); |
|
- | 550 | } |
|
- | 551 | } |
|
- | 552 | /* initialize memory controller */ |
|
558 | return r; |
553 | rv515_mc_init(rdev); |
559 | rv515_debugfs(rdev); |
554 | rv515_debugfs(rdev); |
560 | /* Fence driver */ |
555 | /* Fence driver */ |
561 | // r = radeon_fence_driver_init(rdev); |
556 | // r = radeon_fence_driver_init(rdev); |
562 | // if (r) |
557 | // if (r) |
563 | // return r; |
558 | // return r; |