Rev 1413 | Rev 2005 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 1413 | Rev 1430 | ||
---|---|---|---|
Line 43... | Line 43... | ||
43 | #include "rs600_reg_safe.h" |
43 | #include "rs600_reg_safe.h" |
Line 44... | Line 44... | ||
44 | 44 | ||
45 | void rs600_gpu_init(struct radeon_device *rdev); |
45 | void rs600_gpu_init(struct radeon_device *rdev); |
Line 46... | Line -... | ||
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
- | |
47 | - | ||
48 | int rs600_mc_init(struct radeon_device *rdev) |
- | |
49 | { |
- | |
50 | /* read back the MC value from the hw */ |
- | |
51 | int r; |
- | |
52 | u32 tmp; |
- | |
53 | - | ||
54 | /* Setup GPU memory space */ |
- | |
55 | tmp = RREG32_MC(R_000004_MC_FB_LOCATION); |
- | |
56 | rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; |
- | |
57 | rdev->mc.gtt_location = 0xffffffffUL; |
- | |
58 | r = radeon_mc_setup(rdev); |
- | |
59 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
- | |
60 | if (r) |
- | |
61 | return r; |
- | |
62 | return 0; |
- | |
63 | } |
46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
64 | 47 | ||
65 | /* hpd for digital panel detect/disconnect */ |
48 | /* hpd for digital panel detect/disconnect */ |
66 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
49 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
67 | { |
50 | { |
Line 211... | Line 194... | ||
211 | return -EINVAL; |
194 | return -EINVAL; |
212 | } |
195 | } |
213 | r = radeon_gart_table_vram_pin(rdev); |
196 | r = radeon_gart_table_vram_pin(rdev); |
214 | if (r) |
197 | if (r) |
215 | return r; |
198 | return r; |
- | 199 | radeon_gart_restore(rdev); |
|
216 | /* Enable bus master */ |
200 | /* Enable bus master */ |
217 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
201 | tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
218 | WREG32(R_00004C_BUS_CNTL, tmp); |
202 | WREG32(R_00004C_BUS_CNTL, tmp); |
219 | /* FIXME: setup default page */ |
203 | /* FIXME: setup default page */ |
220 | WREG32_MC(R_000100_MC_PT0_CNTL, |
204 | WREG32_MC(R_000100_MC_PT0_CNTL, |
Line 421... | Line 405... | ||
421 | /* Wait for mc idle */ |
405 | /* Wait for mc idle */ |
422 | if (rs600_mc_wait_for_idle(rdev)) |
406 | if (rs600_mc_wait_for_idle(rdev)) |
423 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
407 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
424 | } |
408 | } |
Line 425... | Line 409... | ||
425 | 409 | ||
426 | void rs600_vram_info(struct radeon_device *rdev) |
410 | void rs600_mc_init(struct radeon_device *rdev) |
- | 411 | { |
|
- | 412 | u64 base; |
|
- | 413 | ||
- | 414 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
|
427 | { |
415 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
428 | rdev->mc.vram_is_ddr = true; |
416 | rdev->mc.vram_is_ddr = true; |
429 | rdev->mc.vram_width = 128; |
- | |
430 | 417 | rdev->mc.vram_width = 128; |
|
431 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
418 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
432 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
- | |
433 | 419 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
|
434 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
420 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
435 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
- | |
436 | 421 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
|
437 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
422 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
438 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
- | |
439 | 423 | base = G_000004_MC_FB_START(base) << 16; |
|
440 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
424 | radeon_vram_location(rdev, &rdev->mc, base); |
441 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
425 | radeon_gtt_location(rdev, &rdev->mc); |
Line 442... | Line 426... | ||
442 | } |
426 | } |
443 | 427 | ||
444 | void rs600_bandwidth_update(struct radeon_device *rdev) |
428 | void rs600_bandwidth_update(struct radeon_device *rdev) |
Line 569... | Line 553... | ||
569 | 553 | ||
570 | /* Initialize clocks */ |
554 | /* Initialize clocks */ |
571 | radeon_get_clock_info(rdev->ddev); |
555 | radeon_get_clock_info(rdev->ddev); |
572 | /* Initialize power management */ |
556 | /* Initialize power management */ |
573 | radeon_pm_init(rdev); |
- | |
574 | /* Get vram informations */ |
- | |
575 | rs600_vram_info(rdev); |
557 | radeon_pm_init(rdev); |
576 | /* Initialize memory controller (also test AGP) */ |
558 | /* initialize memory controller */ |
577 | r = rs600_mc_init(rdev); |
- | |
578 | if (r) |
- | |
579 | return r; |
559 | rs600_mc_init(rdev); |
580 | rs600_debugfs(rdev); |
560 | rs600_debugfs(rdev); |
581 | /* Fence driver */ |
561 | /* Fence driver */ |
582 | // r = radeon_fence_driver_init(rdev); |
562 | // r = radeon_fence_driver_init(rdev); |
583 | // if (r) |
563 | // if (r) |