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Rev 1128 | Rev 1179 | ||
---|---|---|---|
Line 101... | Line 101... | ||
101 | } |
101 | } |
Line 102... | Line 102... | ||
102 | 102 | ||
103 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
103 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
104 | uint32_t supported_device, |
104 | uint32_t supported_device, |
105 | int *connector_type, |
105 | int *connector_type, |
- | 106 | struct radeon_i2c_bus_rec *i2c_bus, |
|
106 | struct radeon_i2c_bus_rec *i2c_bus) |
107 | uint16_t *line_mux) |
Line 107... | Line 108... | ||
107 | { |
108 | { |
108 | 109 | ||
109 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
110 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
Line 125... | Line 126... | ||
125 | 126 | ||
126 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
127 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
127 | if ((dev->pdev->device == 0x5653) && |
128 | if ((dev->pdev->device == 0x5653) && |
128 | (dev->pdev->subsystem_vendor == 0x1462) && |
129 | (dev->pdev->subsystem_vendor == 0x1462) && |
129 | (dev->pdev->subsystem_device == 0x0291)) { |
130 | (dev->pdev->subsystem_device == 0x0291)) { |
130 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) |
131 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
- | 132 | i2c_bus->valid = false; |
|
- | 133 | *line_mux = 53; |
|
131 | i2c_bus->valid = false; |
134 | } |
Line 132... | Line 135... | ||
132 | } |
135 | } |
133 | 136 | ||
134 | /* Funky macbooks */ |
137 | /* Funky macbooks */ |
Line 138... | Line 141... | ||
138 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
141 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
139 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
142 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
140 | return false; |
143 | return false; |
141 | } |
144 | } |
Line 142... | Line -... | ||
142 | - | ||
143 | /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ |
- | |
144 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || |
- | |
145 | (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { |
- | |
146 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
- | |
147 | return false; |
- | |
148 | } |
- | |
149 | } |
- | |
150 | 145 | ||
151 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
146 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
152 | if ((dev->pdev->device == 0x9598) && |
147 | if ((dev->pdev->device == 0x9598) && |
153 | (dev->pdev->subsystem_vendor == 0x1043) && |
148 | (dev->pdev->subsystem_vendor == 0x1043) && |
154 | (dev->pdev->subsystem_device == 0x01da)) { |
149 | (dev->pdev->subsystem_device == 0x01da)) { |
- | 150 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
|
- | 151 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
|
- | 152 | } |
|
- | 153 | } |
|
- | 154 | ||
- | 155 | /* ASUS HD 3450 board lists the DVI port as HDMI */ |
|
- | 156 | if ((dev->pdev->device == 0x95C5) && |
|
- | 157 | (dev->pdev->subsystem_vendor == 0x1043) && |
|
- | 158 | (dev->pdev->subsystem_device == 0x01e2)) { |
|
155 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { |
159 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
- | 160 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
|
- | 161 | } |
|
- | 162 | } |
|
- | 163 | ||
- | 164 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
|
- | 165 | * HDMI + VGA reporting as HDMI |
|
- | 166 | */ |
|
- | 167 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
|
- | 168 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
|
- | 169 | *connector_type = DRM_MODE_CONNECTOR_VGA; |
|
156 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
170 | *line_mux = 0; |
157 | } |
171 | } |
Line 158... | Line 172... | ||
158 | } |
172 | } |
159 | 173 | ||
Line 187... | Line 201... | ||
187 | DRM_MODE_CONNECTOR_DVID, |
201 | DRM_MODE_CONNECTOR_DVID, |
188 | DRM_MODE_CONNECTOR_VGA, |
202 | DRM_MODE_CONNECTOR_VGA, |
189 | DRM_MODE_CONNECTOR_Composite, |
203 | DRM_MODE_CONNECTOR_Composite, |
190 | DRM_MODE_CONNECTOR_SVIDEO, |
204 | DRM_MODE_CONNECTOR_SVIDEO, |
191 | DRM_MODE_CONNECTOR_Unknown, |
205 | DRM_MODE_CONNECTOR_Unknown, |
- | 206 | DRM_MODE_CONNECTOR_Unknown, |
|
192 | DRM_MODE_CONNECTOR_9PinDIN, |
207 | DRM_MODE_CONNECTOR_9PinDIN, |
193 | DRM_MODE_CONNECTOR_Unknown, |
208 | DRM_MODE_CONNECTOR_Unknown, |
194 | DRM_MODE_CONNECTOR_HDMIA, |
209 | DRM_MODE_CONNECTOR_HDMIA, |
195 | DRM_MODE_CONNECTOR_HDMIB, |
210 | DRM_MODE_CONNECTOR_HDMIB, |
196 | DRM_MODE_CONNECTOR_HDMIB, |
- | |
197 | DRM_MODE_CONNECTOR_LVDS, |
211 | DRM_MODE_CONNECTOR_LVDS, |
198 | DRM_MODE_CONNECTOR_9PinDIN, |
212 | DRM_MODE_CONNECTOR_9PinDIN, |
199 | DRM_MODE_CONNECTOR_Unknown, |
213 | DRM_MODE_CONNECTOR_Unknown, |
200 | DRM_MODE_CONNECTOR_Unknown, |
214 | DRM_MODE_CONNECTOR_Unknown, |
201 | DRM_MODE_CONNECTOR_Unknown, |
215 | DRM_MODE_CONNECTOR_Unknown, |
Line 213... | Line 227... | ||
213 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
227 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
214 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
228 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
215 | ATOM_OBJECT_HEADER *obj_header; |
229 | ATOM_OBJECT_HEADER *obj_header; |
216 | int i, j, path_size, device_support; |
230 | int i, j, path_size, device_support; |
217 | int connector_type; |
231 | int connector_type; |
218 | uint16_t igp_lane_info; |
232 | uint16_t igp_lane_info, conn_id; |
219 | bool linkb; |
233 | bool linkb; |
220 | struct radeon_i2c_bus_rec ddc_bus; |
234 | struct radeon_i2c_bus_rec ddc_bus; |
Line 221... | Line 235... | ||
221 | 235 | ||
Line 365... | Line 379... | ||
365 | 379 | ||
366 | while (record->ucRecordType > 0 |
380 | while (record->ucRecordType > 0 |
367 | && record-> |
381 | && record-> |
368 | ucRecordType <= |
382 | ucRecordType <= |
369 | ATOM_MAX_OBJECT_RECORD_NUMBER) { |
- | |
370 | DRM_ERROR |
- | |
371 | ("record type %d\n", |
- | |
372 | record-> |
- | |
373 | ucRecordType); |
383 | ATOM_MAX_OBJECT_RECORD_NUMBER) { |
374 | switch (record-> |
384 | switch (record-> |
375 | ucRecordType) { |
385 | ucRecordType) { |
376 | case ATOM_I2C_RECORD_TYPE: |
386 | case ATOM_I2C_RECORD_TYPE: |
377 | i2c_record = |
387 | i2c_record = |
Line 404... | Line 414... | ||
404 | ATOM_DEVICE_CV_SUPPORT)) |
414 | ATOM_DEVICE_CV_SUPPORT)) |
405 | ddc_bus.valid = false; |
415 | ddc_bus.valid = false; |
406 | else |
416 | else |
407 | ddc_bus = radeon_lookup_gpio(dev, line_mux); |
417 | ddc_bus = radeon_lookup_gpio(dev, line_mux); |
Line -... | Line 418... | ||
- | 418 | ||
- | 419 | conn_id = le16_to_cpu(path->usConnObjectId); |
|
- | 420 | ||
- | 421 | if (!radeon_atom_apply_quirks |
|
- | 422 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, |
|
- | 423 | &ddc_bus, &conn_id)) |
|
- | 424 | continue; |
|
408 | 425 | ||
409 | radeon_add_atom_connector(dev, |
- | |
410 | le16_to_cpu(path-> |
426 | radeon_add_atom_connector(dev, |
411 | usConnObjectId), |
427 | conn_id, |
412 | le16_to_cpu(path-> |
428 | le16_to_cpu(path-> |
413 | usDeviceTag), |
429 | usDeviceTag), |
414 | connector_type, &ddc_bus, |
430 | connector_type, &ddc_bus, |
Line 422... | Line 438... | ||
422 | return true; |
438 | return true; |
423 | } |
439 | } |
Line 424... | Line 440... | ||
424 | 440 | ||
425 | struct bios_connector { |
441 | struct bios_connector { |
426 | bool valid; |
442 | bool valid; |
427 | uint8_t line_mux; |
443 | uint16_t line_mux; |
428 | uint16_t devices; |
444 | uint16_t devices; |
429 | int connector_type; |
445 | int connector_type; |
430 | struct radeon_i2c_bus_rec ddc_bus; |
446 | struct radeon_i2c_bus_rec ddc_bus; |
Line 466... | Line 482... | ||
466 | if (i == ATOM_DEVICE_CV_INDEX) { |
482 | if (i == ATOM_DEVICE_CV_INDEX) { |
467 | DRM_DEBUG("Skipping Component Video\n"); |
483 | DRM_DEBUG("Skipping Component Video\n"); |
468 | continue; |
484 | continue; |
469 | } |
485 | } |
Line 470... | Line -... | ||
470 | - | ||
471 | if (i == ATOM_DEVICE_TV1_INDEX) { |
- | |
472 | DRM_DEBUG("Skipping TV Out\n"); |
- | |
473 | continue; |
- | |
474 | } |
- | |
475 | 486 | ||
476 | bios_connectors[i].connector_type = |
487 | bios_connectors[i].connector_type = |
477 | supported_devices_connector_convert[ci.sucConnectorInfo. |
488 | supported_devices_connector_convert[ci.sucConnectorInfo. |
478 | sbfAccess. |
489 | sbfAccess. |
Line 524... | Line 535... | ||
524 | bios_connectors[i].connector_type = |
535 | bios_connectors[i].connector_type = |
525 | DRM_MODE_CONNECTOR_VGA; |
536 | DRM_MODE_CONNECTOR_VGA; |
Line 526... | Line 537... | ||
526 | 537 | ||
527 | if (!radeon_atom_apply_quirks |
538 | if (!radeon_atom_apply_quirks |
528 | (dev, (1 << i), &bios_connectors[i].connector_type, |
539 | (dev, (1 << i), &bios_connectors[i].connector_type, |
529 | &bios_connectors[i].ddc_bus)) |
540 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux)) |
Line 530... | Line 541... | ||
530 | continue; |
541 | continue; |
531 | 542 | ||
Line 706... | Line 717... | ||
706 | return true; |
717 | return true; |
707 | } |
718 | } |
708 | return false; |
719 | return false; |
709 | } |
720 | } |
Line 710... | Line 721... | ||
710 | 721 | ||
711 | struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct |
722 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
712 | radeon_encoder |
- | |
713 | *encoder) |
723 | struct radeon_encoder_int_tmds *tmds) |
714 | { |
724 | { |
715 | struct drm_device *dev = encoder->base.dev; |
725 | struct drm_device *dev = encoder->base.dev; |
716 | struct radeon_device *rdev = dev->dev_private; |
726 | struct radeon_device *rdev = dev->dev_private; |
717 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
727 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
718 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
728 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
719 | uint16_t data_offset; |
729 | uint16_t data_offset; |
720 | struct _ATOM_TMDS_INFO *tmds_info; |
730 | struct _ATOM_TMDS_INFO *tmds_info; |
721 | uint8_t frev, crev; |
731 | uint8_t frev, crev; |
722 | uint16_t maxfreq; |
732 | uint16_t maxfreq; |
723 | int i; |
- | |
Line 724... | Line 733... | ||
724 | struct radeon_encoder_int_tmds *tmds = NULL; |
733 | int i; |
725 | 734 | ||
Line 726... | Line 735... | ||
726 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
735 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
727 | &crev, &data_offset); |
736 | &crev, &data_offset); |
728 | 737 | ||
Line 729... | Line 738... | ||
729 | tmds_info = |
738 | tmds_info = |
730 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
- | |
731 | data_offset); |
- | |
732 | - | ||
733 | if (tmds_info) { |
- | |
734 | tmds = |
- | |
735 | kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
- | |
736 | 739 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
|
737 | if (!tmds) |
740 | data_offset); |
738 | return NULL; |
741 | |
739 | 742 | if (tmds_info) { |
|
740 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
743 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
Line 760... | Line 763... | ||
760 | if (maxfreq == tmds->tmds_pll[i].freq) { |
763 | if (maxfreq == tmds->tmds_pll[i].freq) { |
761 | tmds->tmds_pll[i].freq = 0xffffffff; |
764 | tmds->tmds_pll[i].freq = 0xffffffff; |
762 | break; |
765 | break; |
763 | } |
766 | } |
764 | } |
767 | } |
- | 768 | return true; |
|
765 | } |
769 | } |
766 | return tmds; |
770 | return false; |
767 | } |
771 | } |
Line 768... | Line 772... | ||
768 | 772 | ||
769 | union lvds_info { |
773 | union lvds_info { |
770 | struct _ATOM_LVDS_INFO info; |
774 | struct _ATOM_LVDS_INFO info; |
Line 853... | Line 857... | ||
853 | 857 | ||
854 | } |
858 | } |
855 | return p_dac; |
859 | return p_dac; |
Line -... | Line 860... | ||
- | 860 | } |
|
- | 861 | ||
- | 862 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
|
- | 863 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
|
- | 864 | int32_t *pixel_clock) |
|
- | 865 | { |
|
- | 866 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
|
- | 867 | ATOM_ANALOG_TV_INFO *tv_info; |
|
- | 868 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
|
- | 869 | ATOM_DTD_FORMAT *dtd_timings; |
|
- | 870 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
|
- | 871 | u8 frev, crev; |
|
- | 872 | uint16_t data_offset; |
|
- | 873 | ||
- | 874 | atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); |
|
- | 875 | ||
- | 876 | switch (crev) { |
|
- | 877 | case 1: |
|
- | 878 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
|
- | 879 | if (index > MAX_SUPPORTED_TV_TIMING) |
|
- | 880 | return false; |
|
- | 881 | ||
- | 882 | crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
|
- | 883 | crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
|
- | 884 | crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
|
- | 885 | crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
|
- | 886 | ||
- | 887 | crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
|
- | 888 | crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
|
- | 889 | crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
|
- | 890 | crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
|
- | 891 | ||
- | 892 | crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; |
|
- | 893 | ||
- | 894 | crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); |
|
- | 895 | crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); |
|
- | 896 | crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); |
|
- | 897 | crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); |
|
- | 898 | *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
|
- | 899 | ||
- | 900 | if (index == 1) { |
|
- | 901 | /* PAL timings appear to have wrong values for totals */ |
|
- | 902 | crtc_timing->usH_Total -= 1; |
|
- | 903 | crtc_timing->usV_Total -= 1; |
|
- | 904 | } |
|
- | 905 | break; |
|
- | 906 | case 2: |
|
- | 907 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
|
- | 908 | if (index > MAX_SUPPORTED_TV_TIMING_V1_2) |
|
- | 909 | return false; |
|
- | 910 | ||
- | 911 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
|
- | 912 | crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); |
|
- | 913 | crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); |
|
- | 914 | crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); |
|
- | 915 | crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); |
|
- | 916 | crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); |
|
- | 917 | crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); |
|
- | 918 | crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); |
|
- | 919 | crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); |
|
- | 920 | ||
- | 921 | crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); |
|
- | 922 | *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; |
|
- | 923 | break; |
|
- | 924 | } |
|
- | 925 | return true; |
|
856 | } |
926 | } |
857 | 927 | ||
858 | struct radeon_encoder_tv_dac * |
928 | struct radeon_encoder_tv_dac * |
859 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
929 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
860 | { |
930 | { |
Line 943... | Line 1013... | ||
943 | { |
1013 | { |
944 | struct radeon_device *rdev = dev->dev_private; |
1014 | struct radeon_device *rdev = dev->dev_private; |
945 | uint32_t bios_2_scratch, bios_6_scratch; |
1015 | uint32_t bios_2_scratch, bios_6_scratch; |
Line 946... | Line 1016... | ||
946 | 1016 | ||
947 | if (rdev->family >= CHIP_R600) { |
1017 | if (rdev->family >= CHIP_R600) { |
948 | bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); |
1018 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
949 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
1019 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
950 | } else { |
1020 | } else { |
951 | bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
1021 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
952 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
1022 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
Line 953... | Line 1023... | ||
953 | } |
1023 | } |
954 | 1024 | ||
Line 966... | Line 1036... | ||
966 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
1036 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
967 | } |
1037 | } |
Line 968... | Line 1038... | ||
968 | 1038 | ||
Line -... | Line 1039... | ||
- | 1039 | } |
|
- | 1040 | ||
- | 1041 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
|
- | 1042 | { |
|
- | 1043 | uint32_t scratch_reg; |
|
- | 1044 | int i; |
|
- | 1045 | ||
- | 1046 | if (rdev->family >= CHIP_R600) |
|
- | 1047 | scratch_reg = R600_BIOS_0_SCRATCH; |
|
- | 1048 | else |
|
- | 1049 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
|
- | 1050 | ||
- | 1051 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
|
- | 1052 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); |
|
- | 1053 | } |
|
- | 1054 | ||
- | 1055 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) |
|
- | 1056 | { |
|
- | 1057 | uint32_t scratch_reg; |
|
- | 1058 | int i; |
|
- | 1059 | ||
- | 1060 | if (rdev->family >= CHIP_R600) |
|
- | 1061 | scratch_reg = R600_BIOS_0_SCRATCH; |
|
- | 1062 | else |
|
- | 1063 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
|
- | 1064 | ||
- | 1065 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
|
- | 1066 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); |
|
969 | } |
1067 | } |
970 | 1068 | ||
971 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
1069 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
972 | { |
1070 | { |
973 | struct drm_device *dev = encoder->dev; |
1071 | struct drm_device *dev = encoder->dev; |