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Rev 3764 | Rev 5078 | ||
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Line 124... | Line 124... | ||
124 | } |
124 | } |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; |
126 | rdev->mc_rreg = &rs780_mc_rreg; |
127 | rdev->mc_wreg = &rs780_mc_wreg; |
127 | rdev->mc_wreg = &rs780_mc_wreg; |
128 | } |
128 | } |
- | 129 | ||
- | 130 | if (rdev->family >= CHIP_BONAIRE) { |
|
- | 131 | rdev->pciep_rreg = &cik_pciep_rreg; |
|
- | 132 | rdev->pciep_wreg = &cik_pciep_wreg; |
|
129 | if (rdev->family >= CHIP_R600) { |
133 | } else if (rdev->family >= CHIP_R600) { |
130 | rdev->pciep_rreg = &r600_pciep_rreg; |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
131 | rdev->pciep_wreg = &r600_pciep_wreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; |
132 | } |
136 | } |
133 | } |
137 | } |
Line 166... | Line 170... | ||
166 | } |
170 | } |
Line 167... | Line 171... | ||
167 | 171 | ||
168 | /* |
172 | /* |
169 | * ASIC |
173 | * ASIC |
- | 174 | */ |
|
- | 175 | ||
- | 176 | static struct radeon_asic_ring r100_gfx_ring = { |
|
- | 177 | .ib_execute = &r100_ring_ib_execute, |
|
- | 178 | .emit_fence = &r100_fence_ring_emit, |
|
- | 179 | .emit_semaphore = &r100_semaphore_ring_emit, |
|
- | 180 | .cs_parse = &r100_cs_parse, |
|
- | 181 | .ring_start = &r100_ring_start, |
|
- | 182 | .ring_test = &r100_ring_test, |
|
- | 183 | .ib_test = &r100_ib_test, |
|
- | 184 | .is_lockup = &r100_gpu_is_lockup, |
|
- | 185 | .get_rptr = &r100_gfx_get_rptr, |
|
- | 186 | .get_wptr = &r100_gfx_get_wptr, |
|
- | 187 | .set_wptr = &r100_gfx_set_wptr, |
|
- | 188 | .hdp_flush = &r100_ring_hdp_flush, |
|
- | 189 | }; |
|
170 | */ |
190 | |
171 | static struct radeon_asic r100_asic = { |
191 | static struct radeon_asic r100_asic = { |
172 | .init = &r100_init, |
192 | .init = &r100_init, |
173 | // .fini = &r100_fini, |
193 | // .fini = &r100_fini, |
174 | // .suspend = &r100_suspend, |
194 | // .suspend = &r100_suspend, |
175 | // .resume = &r100_resume, |
195 | // .resume = &r100_resume, |
176 | // .vga_set_state = &r100_vga_set_state, |
196 | // .vga_set_state = &r100_vga_set_state, |
177 | .asic_reset = &r100_asic_reset, |
197 | .asic_reset = &r100_asic_reset, |
178 | .ioctl_wait_idle = NULL, |
198 | .mmio_hdp_flush = NULL, |
179 | .gui_idle = &r100_gui_idle, |
199 | .gui_idle = &r100_gui_idle, |
180 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
200 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
181 | .gart = { |
201 | .gart = { |
182 | .tlb_flush = &r100_pci_gart_tlb_flush, |
202 | .tlb_flush = &r100_pci_gart_tlb_flush, |
183 | .set_page = &r100_pci_gart_set_page, |
203 | .set_page = &r100_pci_gart_set_page, |
184 | }, |
204 | }, |
185 | .ring = { |
205 | .ring = { |
186 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
187 | .ib_execute = &r100_ring_ib_execute, |
- | |
188 | .emit_fence = &r100_fence_ring_emit, |
- | |
189 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
190 | // .cs_parse = &r100_cs_parse, |
- | |
191 | .ring_start = &r100_ring_start, |
- | |
192 | .ring_test = &r100_ring_test, |
- | |
193 | .ib_test = &r100_ib_test, |
- | |
194 | .is_lockup = &r100_gpu_is_lockup, |
- | |
195 | } |
206 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
196 | }, |
207 | }, |
197 | .irq = { |
208 | .irq = { |
198 | .set = &r100_irq_set, |
209 | .set = &r100_irq_set, |
199 | .process = &r100_irq_process, |
210 | .process = &r100_irq_process, |
200 | }, |
211 | }, |
201 | .display = { |
212 | .display = { |
202 | .bandwidth_update = &r100_bandwidth_update, |
213 | .bandwidth_update = &r100_bandwidth_update, |
203 | .get_vblank_counter = &r100_get_vblank_counter, |
214 | .get_vblank_counter = &r100_get_vblank_counter, |
204 | .wait_for_vblank = &r100_wait_for_vblank, |
215 | .wait_for_vblank = &r100_wait_for_vblank, |
205 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
216 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
206 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
217 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
207 | }, |
218 | }, |
208 | .copy = { |
219 | .copy = { |
209 | .blit = &r100_copy_blit, |
220 | .blit = &r100_copy_blit, |
210 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
221 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 216... | Line 227... | ||
216 | .surface = { |
227 | .surface = { |
217 | .set_reg = r100_set_surface_reg, |
228 | .set_reg = r100_set_surface_reg, |
218 | .clear_reg = r100_clear_surface_reg, |
229 | .clear_reg = r100_clear_surface_reg, |
219 | }, |
230 | }, |
220 | .hpd = { |
231 | .hpd = { |
221 | // .init = &r100_hpd_init, |
232 | .init = &r100_hpd_init, |
222 | // .fini = &r100_hpd_fini, |
233 | .fini = &r100_hpd_fini, |
223 | // .sense = &r100_hpd_sense, |
234 | .sense = &r100_hpd_sense, |
224 | // .set_polarity = &r100_hpd_set_polarity, |
235 | .set_polarity = &r100_hpd_set_polarity, |
225 | }, |
236 | }, |
226 | .pm = { |
237 | .pm = { |
227 | // .misc = &r100_pm_misc, |
238 | .misc = &r100_pm_misc, |
228 | // .prepare = &r100_pm_prepare, |
239 | .prepare = &r100_pm_prepare, |
229 | // .finish = &r100_pm_finish, |
240 | .finish = &r100_pm_finish, |
230 | // .init_profile = &r100_pm_init_profile, |
241 | .init_profile = &r100_pm_init_profile, |
231 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
242 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
232 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
243 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
233 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
244 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
234 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
245 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
235 | .set_memory_clock = NULL, |
246 | .set_memory_clock = NULL, |
236 | .get_pcie_lanes = NULL, |
247 | .get_pcie_lanes = NULL, |
237 | .set_pcie_lanes = NULL, |
248 | .set_pcie_lanes = NULL, |
238 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
249 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
239 | }, |
250 | }, |
240 | .pflip = { |
251 | .pflip = { |
241 | // .pre_page_flip = &r100_pre_page_flip, |
252 | // .pre_page_flip = &r100_pre_page_flip, |
242 | // .page_flip = &r100_page_flip, |
253 | // .page_flip = &r100_page_flip, |
243 | // .post_page_flip = &r100_post_page_flip, |
- | |
244 | }, |
254 | }, |
245 | }; |
255 | }; |
Line 246... | Line 256... | ||
246 | 256 | ||
247 | static struct radeon_asic r200_asic = { |
257 | static struct radeon_asic r200_asic = { |
248 | .init = &r100_init, |
258 | .init = &r100_init, |
249 | // .fini = &r100_fini, |
259 | // .fini = &r100_fini, |
250 | // .suspend = &r100_suspend, |
260 | // .suspend = &r100_suspend, |
251 | // .resume = &r100_resume, |
261 | // .resume = &r100_resume, |
252 | // .vga_set_state = &r100_vga_set_state, |
262 | // .vga_set_state = &r100_vga_set_state, |
253 | .asic_reset = &r100_asic_reset, |
263 | .asic_reset = &r100_asic_reset, |
254 | .ioctl_wait_idle = NULL, |
264 | .mmio_hdp_flush = NULL, |
255 | .gui_idle = &r100_gui_idle, |
265 | .gui_idle = &r100_gui_idle, |
256 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
266 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
257 | .gart = { |
267 | .gart = { |
258 | .tlb_flush = &r100_pci_gart_tlb_flush, |
268 | .tlb_flush = &r100_pci_gart_tlb_flush, |
259 | .set_page = &r100_pci_gart_set_page, |
269 | .set_page = &r100_pci_gart_set_page, |
260 | }, |
270 | }, |
261 | .ring = { |
271 | .ring = { |
262 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
263 | .ib_execute = &r100_ring_ib_execute, |
- | |
264 | .emit_fence = &r100_fence_ring_emit, |
- | |
265 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
266 | // .cs_parse = &r100_cs_parse, |
- | |
267 | .ring_start = &r100_ring_start, |
- | |
268 | .ring_test = &r100_ring_test, |
- | |
269 | .ib_test = &r100_ib_test, |
- | |
270 | .is_lockup = &r100_gpu_is_lockup, |
- | |
271 | } |
272 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
272 | }, |
273 | }, |
273 | .irq = { |
274 | .irq = { |
274 | .set = &r100_irq_set, |
275 | .set = &r100_irq_set, |
275 | .process = &r100_irq_process, |
276 | .process = &r100_irq_process, |
276 | }, |
277 | }, |
277 | .display = { |
278 | .display = { |
278 | .bandwidth_update = &r100_bandwidth_update, |
279 | .bandwidth_update = &r100_bandwidth_update, |
279 | .get_vblank_counter = &r100_get_vblank_counter, |
280 | .get_vblank_counter = &r100_get_vblank_counter, |
280 | .wait_for_vblank = &r100_wait_for_vblank, |
281 | .wait_for_vblank = &r100_wait_for_vblank, |
281 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
282 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
282 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
283 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
283 | }, |
284 | }, |
284 | .copy = { |
285 | .copy = { |
285 | .blit = &r100_copy_blit, |
286 | .blit = &r100_copy_blit, |
286 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
287 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 292... | Line 293... | ||
292 | .surface = { |
293 | .surface = { |
293 | .set_reg = r100_set_surface_reg, |
294 | .set_reg = r100_set_surface_reg, |
294 | .clear_reg = r100_clear_surface_reg, |
295 | .clear_reg = r100_clear_surface_reg, |
295 | }, |
296 | }, |
296 | .hpd = { |
297 | .hpd = { |
297 | // .init = &r100_hpd_init, |
298 | .init = &r100_hpd_init, |
298 | // .fini = &r100_hpd_fini, |
299 | .fini = &r100_hpd_fini, |
299 | // .sense = &r100_hpd_sense, |
300 | .sense = &r100_hpd_sense, |
300 | // .set_polarity = &r100_hpd_set_polarity, |
301 | .set_polarity = &r100_hpd_set_polarity, |
301 | }, |
302 | }, |
302 | .pm = { |
303 | .pm = { |
303 | // .misc = &r100_pm_misc, |
304 | .misc = &r100_pm_misc, |
304 | // .prepare = &r100_pm_prepare, |
305 | .prepare = &r100_pm_prepare, |
305 | // .finish = &r100_pm_finish, |
306 | .finish = &r100_pm_finish, |
306 | // .init_profile = &r100_pm_init_profile, |
307 | .init_profile = &r100_pm_init_profile, |
307 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
308 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
308 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
309 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
309 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
310 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
310 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
311 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
311 | .set_memory_clock = NULL, |
312 | .set_memory_clock = NULL, |
312 | .get_pcie_lanes = NULL, |
313 | .get_pcie_lanes = NULL, |
313 | .set_pcie_lanes = NULL, |
314 | .set_pcie_lanes = NULL, |
314 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
315 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
315 | }, |
316 | }, |
316 | .pflip = { |
317 | .pflip = { |
317 | // .pre_page_flip = &r100_pre_page_flip, |
318 | // .pre_page_flip = &r100_pre_page_flip, |
318 | // .page_flip = &r100_page_flip, |
319 | // .page_flip = &r100_page_flip, |
319 | // .post_page_flip = &r100_post_page_flip, |
- | |
320 | }, |
320 | }, |
321 | }; |
321 | }; |
Line -... | Line 322... | ||
- | 322 | ||
- | 323 | static struct radeon_asic_ring r300_gfx_ring = { |
|
- | 324 | .ib_execute = &r100_ring_ib_execute, |
|
- | 325 | .emit_fence = &r300_fence_ring_emit, |
|
- | 326 | .emit_semaphore = &r100_semaphore_ring_emit, |
|
- | 327 | .cs_parse = &r300_cs_parse, |
|
- | 328 | .ring_start = &r300_ring_start, |
|
- | 329 | .ring_test = &r100_ring_test, |
|
- | 330 | .ib_test = &r100_ib_test, |
|
- | 331 | .is_lockup = &r100_gpu_is_lockup, |
|
- | 332 | .get_rptr = &r100_gfx_get_rptr, |
|
- | 333 | .get_wptr = &r100_gfx_get_wptr, |
|
- | 334 | .set_wptr = &r100_gfx_set_wptr, |
|
- | 335 | .hdp_flush = &r100_ring_hdp_flush, |
|
- | 336 | }; |
|
322 | 337 | ||
323 | static struct radeon_asic r300_asic = { |
338 | static struct radeon_asic r300_asic = { |
324 | .init = &r300_init, |
339 | .init = &r300_init, |
325 | // .fini = &r300_fini, |
340 | // .fini = &r300_fini, |
326 | // .suspend = &r300_suspend, |
341 | // .suspend = &r300_suspend, |
327 | // .resume = &r300_resume, |
342 | // .resume = &r300_resume, |
328 | // .vga_set_state = &r100_vga_set_state, |
343 | // .vga_set_state = &r100_vga_set_state, |
329 | .asic_reset = &r300_asic_reset, |
344 | .asic_reset = &r300_asic_reset, |
330 | .ioctl_wait_idle = NULL, |
345 | .mmio_hdp_flush = NULL, |
331 | .gui_idle = &r100_gui_idle, |
346 | .gui_idle = &r100_gui_idle, |
332 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
347 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
333 | .gart = { |
348 | .gart = { |
334 | .tlb_flush = &r100_pci_gart_tlb_flush, |
349 | .tlb_flush = &r100_pci_gart_tlb_flush, |
335 | .set_page = &r100_pci_gart_set_page, |
350 | .set_page = &r100_pci_gart_set_page, |
336 | }, |
351 | }, |
337 | .ring = { |
352 | .ring = { |
338 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
339 | .ib_execute = &r100_ring_ib_execute, |
- | |
340 | .emit_fence = &r300_fence_ring_emit, |
- | |
341 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
342 | // .cs_parse = &r300_cs_parse, |
- | |
343 | .ring_start = &r300_ring_start, |
- | |
344 | .ring_test = &r100_ring_test, |
- | |
345 | .ib_test = &r100_ib_test, |
- | |
346 | .is_lockup = &r100_gpu_is_lockup, |
- | |
347 | } |
353 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
348 | }, |
354 | }, |
349 | .irq = { |
355 | .irq = { |
350 | .set = &r100_irq_set, |
356 | .set = &r100_irq_set, |
351 | .process = &r100_irq_process, |
357 | .process = &r100_irq_process, |
352 | }, |
358 | }, |
353 | .display = { |
359 | .display = { |
354 | .bandwidth_update = &r100_bandwidth_update, |
360 | .bandwidth_update = &r100_bandwidth_update, |
355 | .get_vblank_counter = &r100_get_vblank_counter, |
361 | .get_vblank_counter = &r100_get_vblank_counter, |
356 | .wait_for_vblank = &r100_wait_for_vblank, |
362 | .wait_for_vblank = &r100_wait_for_vblank, |
357 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
363 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
358 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
364 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
359 | }, |
365 | }, |
360 | .copy = { |
366 | .copy = { |
361 | .blit = &r100_copy_blit, |
367 | .blit = &r100_copy_blit, |
362 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
368 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 368... | Line 374... | ||
368 | .surface = { |
374 | .surface = { |
369 | .set_reg = r100_set_surface_reg, |
375 | .set_reg = r100_set_surface_reg, |
370 | .clear_reg = r100_clear_surface_reg, |
376 | .clear_reg = r100_clear_surface_reg, |
371 | }, |
377 | }, |
372 | .hpd = { |
378 | .hpd = { |
373 | // .init = &r100_hpd_init, |
379 | .init = &r100_hpd_init, |
374 | // .fini = &r100_hpd_fini, |
380 | .fini = &r100_hpd_fini, |
375 | // .sense = &r100_hpd_sense, |
381 | .sense = &r100_hpd_sense, |
376 | // .set_polarity = &r100_hpd_set_polarity, |
382 | .set_polarity = &r100_hpd_set_polarity, |
377 | }, |
383 | }, |
378 | .pm = { |
384 | .pm = { |
379 | // .misc = &r100_pm_misc, |
385 | .misc = &r100_pm_misc, |
380 | // .prepare = &r100_pm_prepare, |
386 | .prepare = &r100_pm_prepare, |
381 | // .finish = &r100_pm_finish, |
387 | .finish = &r100_pm_finish, |
382 | // .init_profile = &r100_pm_init_profile, |
388 | .init_profile = &r100_pm_init_profile, |
383 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
389 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
384 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
390 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
385 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
391 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
386 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
392 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
387 | // .set_memory_clock = NULL, |
393 | .set_memory_clock = NULL, |
388 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
394 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
389 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
395 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
390 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
396 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
391 | }, |
397 | }, |
392 | .pflip = { |
398 | .pflip = { |
393 | // .pre_page_flip = &r100_pre_page_flip, |
399 | // .pre_page_flip = &r100_pre_page_flip, |
394 | // .page_flip = &r100_page_flip, |
400 | // .page_flip = &r100_page_flip, |
395 | // .post_page_flip = &r100_post_page_flip, |
- | |
396 | }, |
401 | }, |
397 | }; |
402 | }; |
Line 398... | Line 403... | ||
398 | 403 | ||
399 | static struct radeon_asic r300_asic_pcie = { |
404 | static struct radeon_asic r300_asic_pcie = { |
400 | .init = &r300_init, |
405 | .init = &r300_init, |
401 | // .fini = &r300_fini, |
406 | // .fini = &r300_fini, |
402 | // .suspend = &r300_suspend, |
407 | // .suspend = &r300_suspend, |
403 | // .resume = &r300_resume, |
408 | // .resume = &r300_resume, |
404 | // .vga_set_state = &r100_vga_set_state, |
409 | // .vga_set_state = &r100_vga_set_state, |
405 | .asic_reset = &r300_asic_reset, |
410 | .asic_reset = &r300_asic_reset, |
406 | .ioctl_wait_idle = NULL, |
411 | .mmio_hdp_flush = NULL, |
407 | .gui_idle = &r100_gui_idle, |
412 | .gui_idle = &r100_gui_idle, |
408 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
413 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
409 | .gart = { |
414 | .gart = { |
410 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
415 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
411 | .set_page = &rv370_pcie_gart_set_page, |
416 | .set_page = &rv370_pcie_gart_set_page, |
412 | }, |
417 | }, |
413 | .ring = { |
418 | .ring = { |
414 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
415 | .ib_execute = &r100_ring_ib_execute, |
- | |
416 | .emit_fence = &r300_fence_ring_emit, |
- | |
417 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
418 | // .cs_parse = &r300_cs_parse, |
- | |
419 | .ring_start = &r300_ring_start, |
- | |
420 | .ring_test = &r100_ring_test, |
- | |
421 | .ib_test = &r100_ib_test, |
- | |
422 | .is_lockup = &r100_gpu_is_lockup, |
- | |
423 | } |
419 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
424 | }, |
420 | }, |
425 | .irq = { |
421 | .irq = { |
426 | .set = &r100_irq_set, |
422 | .set = &r100_irq_set, |
427 | .process = &r100_irq_process, |
423 | .process = &r100_irq_process, |
428 | }, |
424 | }, |
429 | .display = { |
425 | .display = { |
430 | .bandwidth_update = &r100_bandwidth_update, |
426 | .bandwidth_update = &r100_bandwidth_update, |
431 | .get_vblank_counter = &r100_get_vblank_counter, |
427 | .get_vblank_counter = &r100_get_vblank_counter, |
432 | .wait_for_vblank = &r100_wait_for_vblank, |
428 | .wait_for_vblank = &r100_wait_for_vblank, |
433 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
429 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
434 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
430 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
435 | }, |
431 | }, |
436 | .copy = { |
432 | .copy = { |
437 | .blit = &r100_copy_blit, |
433 | .blit = &r100_copy_blit, |
438 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
434 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 450... | Line 446... | ||
450 | .fini = &r100_hpd_fini, |
446 | .fini = &r100_hpd_fini, |
451 | .sense = &r100_hpd_sense, |
447 | .sense = &r100_hpd_sense, |
452 | .set_polarity = &r100_hpd_set_polarity, |
448 | .set_polarity = &r100_hpd_set_polarity, |
453 | }, |
449 | }, |
454 | .pm = { |
450 | .pm = { |
455 | // .misc = &r100_pm_misc, |
451 | .misc = &r100_pm_misc, |
456 | // .prepare = &r100_pm_prepare, |
452 | .prepare = &r100_pm_prepare, |
457 | // .finish = &r100_pm_finish, |
453 | .finish = &r100_pm_finish, |
458 | // .init_profile = &r100_pm_init_profile, |
454 | .init_profile = &r100_pm_init_profile, |
459 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
455 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
460 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
456 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
461 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
457 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
462 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
458 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
463 | // .set_memory_clock = NULL, |
459 | .set_memory_clock = NULL, |
464 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
460 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
465 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
461 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
466 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
462 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
467 | }, |
463 | }, |
468 | .pflip = { |
464 | .pflip = { |
469 | // .pre_page_flip = &r100_pre_page_flip, |
465 | // .pre_page_flip = &r100_pre_page_flip, |
470 | // .page_flip = &r100_page_flip, |
466 | // .page_flip = &r100_page_flip, |
471 | // .post_page_flip = &r100_post_page_flip, |
- | |
472 | }, |
467 | }, |
473 | }; |
468 | }; |
Line 474... | Line 469... | ||
474 | 469 | ||
475 | static struct radeon_asic r420_asic = { |
470 | static struct radeon_asic r420_asic = { |
476 | .init = &r420_init, |
471 | .init = &r420_init, |
477 | // .fini = &r420_fini, |
472 | // .fini = &r420_fini, |
478 | // .suspend = &r420_suspend, |
473 | // .suspend = &r420_suspend, |
479 | // .resume = &r420_resume, |
474 | // .resume = &r420_resume, |
480 | // .vga_set_state = &r100_vga_set_state, |
475 | // .vga_set_state = &r100_vga_set_state, |
481 | .asic_reset = &r300_asic_reset, |
476 | .asic_reset = &r300_asic_reset, |
482 | .ioctl_wait_idle = NULL, |
477 | .mmio_hdp_flush = NULL, |
483 | .gui_idle = &r100_gui_idle, |
478 | .gui_idle = &r100_gui_idle, |
484 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
479 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
485 | .gart = { |
480 | .gart = { |
486 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
481 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
487 | .set_page = &rv370_pcie_gart_set_page, |
482 | .set_page = &rv370_pcie_gart_set_page, |
488 | }, |
483 | }, |
489 | .ring = { |
484 | .ring = { |
490 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
491 | .ib_execute = &r100_ring_ib_execute, |
- | |
492 | .emit_fence = &r300_fence_ring_emit, |
- | |
493 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
494 | // .cs_parse = &r300_cs_parse, |
- | |
495 | .ring_start = &r300_ring_start, |
- | |
496 | .ring_test = &r100_ring_test, |
- | |
497 | .ib_test = &r100_ib_test, |
- | |
498 | .is_lockup = &r100_gpu_is_lockup, |
- | |
499 | } |
485 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
500 | }, |
486 | }, |
501 | .irq = { |
487 | .irq = { |
502 | .set = &r100_irq_set, |
488 | .set = &r100_irq_set, |
503 | .process = &r100_irq_process, |
489 | .process = &r100_irq_process, |
504 | }, |
490 | }, |
505 | .display = { |
491 | .display = { |
506 | .bandwidth_update = &r100_bandwidth_update, |
492 | .bandwidth_update = &r100_bandwidth_update, |
507 | .get_vblank_counter = &r100_get_vblank_counter, |
493 | .get_vblank_counter = &r100_get_vblank_counter, |
508 | .wait_for_vblank = &r100_wait_for_vblank, |
494 | .wait_for_vblank = &r100_wait_for_vblank, |
509 | // .set_backlight_level = &atombios_set_backlight_level, |
495 | .set_backlight_level = &atombios_set_backlight_level, |
510 | // .get_backlight_level = &atombios_get_backlight_level, |
496 | .get_backlight_level = &atombios_get_backlight_level, |
511 | }, |
497 | }, |
512 | .copy = { |
498 | .copy = { |
513 | .blit = &r100_copy_blit, |
499 | .blit = &r100_copy_blit, |
514 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
500 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 520... | Line 506... | ||
520 | .surface = { |
506 | .surface = { |
521 | .set_reg = r100_set_surface_reg, |
507 | .set_reg = r100_set_surface_reg, |
522 | .clear_reg = r100_clear_surface_reg, |
508 | .clear_reg = r100_clear_surface_reg, |
523 | }, |
509 | }, |
524 | .hpd = { |
510 | .hpd = { |
525 | // .init = &r100_hpd_init, |
511 | .init = &r100_hpd_init, |
526 | // .fini = &r100_hpd_fini, |
512 | .fini = &r100_hpd_fini, |
527 | // .sense = &r100_hpd_sense, |
513 | .sense = &r100_hpd_sense, |
528 | // .set_polarity = &r100_hpd_set_polarity, |
514 | .set_polarity = &r100_hpd_set_polarity, |
529 | }, |
515 | }, |
530 | .pm = { |
516 | .pm = { |
531 | // .misc = &r100_pm_misc, |
517 | .misc = &r100_pm_misc, |
532 | // .prepare = &r100_pm_prepare, |
518 | .prepare = &r100_pm_prepare, |
533 | // .finish = &r100_pm_finish, |
519 | .finish = &r100_pm_finish, |
534 | // .init_profile = &r420_pm_init_profile, |
520 | .init_profile = &r420_pm_init_profile, |
535 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
521 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
536 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
522 | .get_engine_clock = &radeon_atom_get_engine_clock, |
537 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
523 | .set_engine_clock = &radeon_atom_set_engine_clock, |
538 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
524 | .get_memory_clock = &radeon_atom_get_memory_clock, |
539 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
525 | .set_memory_clock = &radeon_atom_set_memory_clock, |
540 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
526 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
541 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
527 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
542 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
528 | .set_clock_gating = &radeon_atom_set_clock_gating, |
543 | }, |
529 | }, |
544 | .pflip = { |
530 | .pflip = { |
545 | // .pre_page_flip = &r100_pre_page_flip, |
531 | // .pre_page_flip = &r100_pre_page_flip, |
546 | // .page_flip = &r100_page_flip, |
532 | // .page_flip = &r100_page_flip, |
547 | // .post_page_flip = &r100_post_page_flip, |
- | |
548 | }, |
533 | }, |
549 | }; |
534 | }; |
Line 550... | Line 535... | ||
550 | 535 | ||
551 | static struct radeon_asic rs400_asic = { |
536 | static struct radeon_asic rs400_asic = { |
552 | .init = &rs400_init, |
537 | .init = &rs400_init, |
553 | // .fini = &rs400_fini, |
538 | // .fini = &rs400_fini, |
554 | // .suspend = &rs400_suspend, |
539 | // .suspend = &rs400_suspend, |
555 | // .resume = &rs400_resume, |
540 | // .resume = &rs400_resume, |
556 | // .vga_set_state = &r100_vga_set_state, |
541 | // .vga_set_state = &r100_vga_set_state, |
557 | .asic_reset = &r300_asic_reset, |
542 | .asic_reset = &r300_asic_reset, |
558 | .ioctl_wait_idle = NULL, |
543 | .mmio_hdp_flush = NULL, |
559 | .gui_idle = &r100_gui_idle, |
544 | .gui_idle = &r100_gui_idle, |
560 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
545 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
561 | .gart = { |
546 | .gart = { |
562 | .tlb_flush = &rs400_gart_tlb_flush, |
547 | .tlb_flush = &rs400_gart_tlb_flush, |
563 | .set_page = &rs400_gart_set_page, |
548 | .set_page = &rs400_gart_set_page, |
564 | }, |
549 | }, |
565 | .ring = { |
550 | .ring = { |
566 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
567 | .ib_execute = &r100_ring_ib_execute, |
- | |
568 | .emit_fence = &r300_fence_ring_emit, |
- | |
569 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
570 | // .cs_parse = &r300_cs_parse, |
- | |
571 | .ring_start = &r300_ring_start, |
- | |
572 | .ring_test = &r100_ring_test, |
- | |
573 | .ib_test = &r100_ib_test, |
- | |
574 | .is_lockup = &r100_gpu_is_lockup, |
- | |
575 | } |
551 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
576 | }, |
552 | }, |
577 | .irq = { |
553 | .irq = { |
578 | .set = &r100_irq_set, |
554 | .set = &r100_irq_set, |
579 | .process = &r100_irq_process, |
555 | .process = &r100_irq_process, |
580 | }, |
556 | }, |
581 | .display = { |
557 | .display = { |
582 | .bandwidth_update = &r100_bandwidth_update, |
558 | .bandwidth_update = &r100_bandwidth_update, |
583 | .get_vblank_counter = &r100_get_vblank_counter, |
559 | .get_vblank_counter = &r100_get_vblank_counter, |
584 | .wait_for_vblank = &r100_wait_for_vblank, |
560 | .wait_for_vblank = &r100_wait_for_vblank, |
585 | // .set_backlight_level = &radeon_legacy_set_backlight_level, |
561 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
586 | // .get_backlight_level = &radeon_legacy_get_backlight_level, |
562 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
587 | }, |
563 | }, |
588 | .copy = { |
564 | .copy = { |
589 | .blit = &r100_copy_blit, |
565 | .blit = &r100_copy_blit, |
590 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
566 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 596... | Line 572... | ||
596 | .surface = { |
572 | .surface = { |
597 | .set_reg = r100_set_surface_reg, |
573 | .set_reg = r100_set_surface_reg, |
598 | .clear_reg = r100_clear_surface_reg, |
574 | .clear_reg = r100_clear_surface_reg, |
599 | }, |
575 | }, |
600 | .hpd = { |
576 | .hpd = { |
601 | // .init = &r100_hpd_init, |
577 | .init = &r100_hpd_init, |
602 | // .fini = &r100_hpd_fini, |
578 | .fini = &r100_hpd_fini, |
603 | // .sense = &r100_hpd_sense, |
579 | .sense = &r100_hpd_sense, |
604 | // .set_polarity = &r100_hpd_set_polarity, |
580 | .set_polarity = &r100_hpd_set_polarity, |
605 | }, |
581 | }, |
606 | .pm = { |
582 | .pm = { |
607 | // .misc = &r100_pm_misc, |
583 | .misc = &r100_pm_misc, |
608 | // .prepare = &r100_pm_prepare, |
584 | .prepare = &r100_pm_prepare, |
609 | // .finish = &r100_pm_finish, |
585 | .finish = &r100_pm_finish, |
610 | // .init_profile = &r100_pm_init_profile, |
586 | .init_profile = &r100_pm_init_profile, |
611 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
587 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
612 | // .get_engine_clock = &radeon_legacy_get_engine_clock, |
588 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
613 | // .set_engine_clock = &radeon_legacy_set_engine_clock, |
589 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
614 | // .get_memory_clock = &radeon_legacy_get_memory_clock, |
590 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
615 | // .set_memory_clock = NULL, |
591 | .set_memory_clock = NULL, |
616 | // .get_pcie_lanes = NULL, |
592 | .get_pcie_lanes = NULL, |
617 | // .set_pcie_lanes = NULL, |
593 | .set_pcie_lanes = NULL, |
618 | // .set_clock_gating = &radeon_legacy_set_clock_gating, |
594 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
619 | }, |
595 | }, |
620 | .pflip = { |
596 | .pflip = { |
621 | // .pre_page_flip = &r100_pre_page_flip, |
597 | // .pre_page_flip = &r100_pre_page_flip, |
622 | // .page_flip = &r100_page_flip, |
598 | // .page_flip = &r100_page_flip, |
623 | // .post_page_flip = &r100_post_page_flip, |
- | |
624 | }, |
599 | }, |
625 | }; |
600 | }; |
Line 626... | Line 601... | ||
626 | 601 | ||
627 | static struct radeon_asic rs600_asic = { |
602 | static struct radeon_asic rs600_asic = { |
628 | .init = &rs600_init, |
603 | .init = &rs600_init, |
629 | // .fini = &rs600_fini, |
604 | // .fini = &rs600_fini, |
630 | // .suspend = &rs600_suspend, |
605 | // .suspend = &rs600_suspend, |
631 | // .resume = &rs600_resume, |
606 | // .resume = &rs600_resume, |
632 | // .vga_set_state = &r100_vga_set_state, |
607 | // .vga_set_state = &r100_vga_set_state, |
633 | .asic_reset = &rs600_asic_reset, |
608 | .asic_reset = &rs600_asic_reset, |
634 | .ioctl_wait_idle = NULL, |
609 | .mmio_hdp_flush = NULL, |
635 | .gui_idle = &r100_gui_idle, |
610 | .gui_idle = &r100_gui_idle, |
636 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
611 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
637 | .gart = { |
612 | .gart = { |
638 | .tlb_flush = &rs600_gart_tlb_flush, |
613 | .tlb_flush = &rs600_gart_tlb_flush, |
639 | .set_page = &rs600_gart_set_page, |
614 | .set_page = &rs600_gart_set_page, |
640 | }, |
615 | }, |
641 | .ring = { |
616 | .ring = { |
642 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
643 | .ib_execute = &r100_ring_ib_execute, |
- | |
644 | .emit_fence = &r300_fence_ring_emit, |
- | |
645 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
646 | // .cs_parse = &r300_cs_parse, |
- | |
647 | .ring_start = &r300_ring_start, |
- | |
648 | .ring_test = &r100_ring_test, |
- | |
649 | .ib_test = &r100_ib_test, |
- | |
650 | .is_lockup = &r100_gpu_is_lockup, |
- | |
651 | } |
617 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
652 | }, |
618 | }, |
653 | .irq = { |
619 | .irq = { |
654 | .set = &rs600_irq_set, |
620 | .set = &rs600_irq_set, |
655 | .process = &rs600_irq_process, |
621 | .process = &rs600_irq_process, |
656 | }, |
622 | }, |
657 | .display = { |
623 | .display = { |
658 | .bandwidth_update = &rs600_bandwidth_update, |
624 | .bandwidth_update = &rs600_bandwidth_update, |
659 | .get_vblank_counter = &rs600_get_vblank_counter, |
625 | .get_vblank_counter = &rs600_get_vblank_counter, |
660 | .wait_for_vblank = &avivo_wait_for_vblank, |
626 | .wait_for_vblank = &avivo_wait_for_vblank, |
661 | // .set_backlight_level = &atombios_set_backlight_level, |
627 | .set_backlight_level = &atombios_set_backlight_level, |
- | 628 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 629 | .hdmi_enable = &r600_hdmi_enable, |
|
662 | // .get_backlight_level = &atombios_get_backlight_level, |
630 | .hdmi_setmode = &r600_hdmi_setmode, |
663 | }, |
631 | }, |
664 | .copy = { |
632 | .copy = { |
665 | .blit = &r100_copy_blit, |
633 | .blit = &r100_copy_blit, |
666 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
634 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 672... | Line 640... | ||
672 | .surface = { |
640 | .surface = { |
673 | .set_reg = r100_set_surface_reg, |
641 | .set_reg = r100_set_surface_reg, |
674 | .clear_reg = r100_clear_surface_reg, |
642 | .clear_reg = r100_clear_surface_reg, |
675 | }, |
643 | }, |
676 | .hpd = { |
644 | .hpd = { |
677 | // .init = &rs600_hpd_init, |
645 | .init = &rs600_hpd_init, |
678 | // .fini = &rs600_hpd_fini, |
646 | .fini = &rs600_hpd_fini, |
679 | // .sense = &rs600_hpd_sense, |
647 | .sense = &rs600_hpd_sense, |
680 | // .set_polarity = &rs600_hpd_set_polarity, |
648 | .set_polarity = &rs600_hpd_set_polarity, |
681 | }, |
649 | }, |
682 | .pm = { |
650 | .pm = { |
683 | // .misc = &rs600_pm_misc, |
651 | .misc = &rs600_pm_misc, |
684 | // .prepare = &rs600_pm_prepare, |
652 | .prepare = &rs600_pm_prepare, |
685 | // .finish = &rs600_pm_finish, |
653 | .finish = &rs600_pm_finish, |
686 | // .init_profile = &r420_pm_init_profile, |
654 | .init_profile = &r420_pm_init_profile, |
687 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
655 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
688 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
656 | .get_engine_clock = &radeon_atom_get_engine_clock, |
689 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
657 | .set_engine_clock = &radeon_atom_set_engine_clock, |
690 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
658 | .get_memory_clock = &radeon_atom_get_memory_clock, |
691 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
659 | .set_memory_clock = &radeon_atom_set_memory_clock, |
692 | .get_pcie_lanes = NULL, |
660 | .get_pcie_lanes = NULL, |
693 | .set_pcie_lanes = NULL, |
661 | .set_pcie_lanes = NULL, |
694 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
662 | .set_clock_gating = &radeon_atom_set_clock_gating, |
695 | }, |
663 | }, |
696 | .pflip = { |
664 | .pflip = { |
697 | // .pre_page_flip = &rs600_pre_page_flip, |
665 | // .pre_page_flip = &rs600_pre_page_flip, |
698 | // .page_flip = &rs600_page_flip, |
666 | // .page_flip = &rs600_page_flip, |
699 | // .post_page_flip = &rs600_post_page_flip, |
- | |
700 | }, |
667 | }, |
701 | }; |
668 | }; |
Line 702... | Line 669... | ||
702 | 669 | ||
703 | static struct radeon_asic rs690_asic = { |
670 | static struct radeon_asic rs690_asic = { |
704 | .init = &rs690_init, |
671 | .init = &rs690_init, |
705 | // .fini = &rs690_fini, |
672 | // .fini = &rs690_fini, |
706 | // .suspend = &rs690_suspend, |
673 | // .suspend = &rs690_suspend, |
707 | // .resume = &rs690_resume, |
674 | // .resume = &rs690_resume, |
708 | // .vga_set_state = &r100_vga_set_state, |
675 | // .vga_set_state = &r100_vga_set_state, |
709 | .asic_reset = &rs600_asic_reset, |
676 | .asic_reset = &rs600_asic_reset, |
710 | .ioctl_wait_idle = NULL, |
677 | .mmio_hdp_flush = NULL, |
711 | .gui_idle = &r100_gui_idle, |
678 | .gui_idle = &r100_gui_idle, |
712 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
679 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
713 | .gart = { |
680 | .gart = { |
714 | .tlb_flush = &rs400_gart_tlb_flush, |
681 | .tlb_flush = &rs400_gart_tlb_flush, |
715 | .set_page = &rs400_gart_set_page, |
682 | .set_page = &rs400_gart_set_page, |
716 | }, |
683 | }, |
717 | .ring = { |
684 | .ring = { |
718 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
719 | .ib_execute = &r100_ring_ib_execute, |
- | |
720 | .emit_fence = &r300_fence_ring_emit, |
- | |
721 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
722 | // .cs_parse = &r300_cs_parse, |
- | |
723 | .ring_start = &r300_ring_start, |
- | |
724 | .ring_test = &r100_ring_test, |
- | |
725 | .ib_test = &r100_ib_test, |
- | |
726 | .is_lockup = &r100_gpu_is_lockup, |
- | |
727 | } |
685 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
728 | }, |
686 | }, |
729 | .irq = { |
687 | .irq = { |
730 | .set = &rs600_irq_set, |
688 | .set = &rs600_irq_set, |
731 | .process = &rs600_irq_process, |
689 | .process = &rs600_irq_process, |
732 | }, |
690 | }, |
733 | .display = { |
691 | .display = { |
734 | .get_vblank_counter = &rs600_get_vblank_counter, |
692 | .get_vblank_counter = &rs600_get_vblank_counter, |
735 | .bandwidth_update = &rs690_bandwidth_update, |
693 | .bandwidth_update = &rs690_bandwidth_update, |
736 | .wait_for_vblank = &avivo_wait_for_vblank, |
694 | .wait_for_vblank = &avivo_wait_for_vblank, |
737 | // .set_backlight_level = &atombios_set_backlight_level, |
695 | .set_backlight_level = &atombios_set_backlight_level, |
- | 696 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 697 | .hdmi_enable = &r600_hdmi_enable, |
|
738 | // .get_backlight_level = &atombios_get_backlight_level, |
698 | .hdmi_setmode = &r600_hdmi_setmode, |
739 | }, |
699 | }, |
740 | .copy = { |
700 | .copy = { |
741 | .blit = &r100_copy_blit, |
701 | .blit = &r100_copy_blit, |
742 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
702 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 748... | Line 708... | ||
748 | .surface = { |
708 | .surface = { |
749 | .set_reg = r100_set_surface_reg, |
709 | .set_reg = r100_set_surface_reg, |
750 | .clear_reg = r100_clear_surface_reg, |
710 | .clear_reg = r100_clear_surface_reg, |
751 | }, |
711 | }, |
752 | .hpd = { |
712 | .hpd = { |
753 | // .init = &rs600_hpd_init, |
713 | .init = &rs600_hpd_init, |
754 | // .fini = &rs600_hpd_fini, |
714 | .fini = &rs600_hpd_fini, |
755 | .sense = &rs600_hpd_sense, |
715 | .sense = &rs600_hpd_sense, |
756 | .set_polarity = &rs600_hpd_set_polarity, |
716 | .set_polarity = &rs600_hpd_set_polarity, |
757 | }, |
717 | }, |
758 | .pm = { |
718 | .pm = { |
759 | // .misc = &rs600_pm_misc, |
719 | .misc = &rs600_pm_misc, |
760 | // .prepare = &rs600_pm_prepare, |
720 | .prepare = &rs600_pm_prepare, |
761 | // .finish = &rs600_pm_finish, |
721 | .finish = &rs600_pm_finish, |
762 | // .init_profile = &r420_pm_init_profile, |
722 | .init_profile = &r420_pm_init_profile, |
763 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
723 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
764 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
724 | .get_engine_clock = &radeon_atom_get_engine_clock, |
765 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
725 | .set_engine_clock = &radeon_atom_set_engine_clock, |
766 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
726 | .get_memory_clock = &radeon_atom_get_memory_clock, |
767 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
727 | .set_memory_clock = &radeon_atom_set_memory_clock, |
768 | .get_pcie_lanes = NULL, |
728 | .get_pcie_lanes = NULL, |
769 | .set_pcie_lanes = NULL, |
729 | .set_pcie_lanes = NULL, |
770 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
730 | .set_clock_gating = &radeon_atom_set_clock_gating, |
771 | }, |
731 | }, |
772 | .pflip = { |
732 | .pflip = { |
773 | // .pre_page_flip = &rs600_pre_page_flip, |
733 | // .pre_page_flip = &rs600_pre_page_flip, |
774 | // .page_flip = &rs600_page_flip, |
734 | // .page_flip = &rs600_page_flip, |
775 | // .post_page_flip = &rs600_post_page_flip, |
- | |
776 | }, |
735 | }, |
777 | }; |
736 | }; |
Line 778... | Line 737... | ||
778 | 737 | ||
779 | static struct radeon_asic rv515_asic = { |
738 | static struct radeon_asic rv515_asic = { |
780 | .init = &rv515_init, |
739 | .init = &rv515_init, |
781 | // .fini = &rv515_fini, |
740 | // .fini = &rv515_fini, |
782 | // .suspend = &rv515_suspend, |
741 | // .suspend = &rv515_suspend, |
783 | // .resume = &rv515_resume, |
742 | // .resume = &rv515_resume, |
784 | // .vga_set_state = &r100_vga_set_state, |
743 | // .vga_set_state = &r100_vga_set_state, |
785 | .asic_reset = &rs600_asic_reset, |
744 | .asic_reset = &rs600_asic_reset, |
786 | .ioctl_wait_idle = NULL, |
745 | .mmio_hdp_flush = NULL, |
787 | .gui_idle = &r100_gui_idle, |
746 | .gui_idle = &r100_gui_idle, |
788 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
747 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
789 | .gart = { |
748 | .gart = { |
790 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
749 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
791 | .set_page = &rv370_pcie_gart_set_page, |
750 | .set_page = &rv370_pcie_gart_set_page, |
792 | }, |
751 | }, |
793 | .ring = { |
752 | .ring = { |
794 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
795 | .ib_execute = &r100_ring_ib_execute, |
- | |
796 | .emit_fence = &r300_fence_ring_emit, |
- | |
797 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
798 | // .cs_parse = &r300_cs_parse, |
- | |
799 | .ring_start = &rv515_ring_start, |
- | |
800 | .ring_test = &r100_ring_test, |
- | |
801 | .ib_test = &r100_ib_test, |
- | |
802 | .is_lockup = &r100_gpu_is_lockup, |
- | |
803 | } |
753 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
804 | }, |
754 | }, |
805 | .irq = { |
755 | .irq = { |
806 | .set = &rs600_irq_set, |
756 | .set = &rs600_irq_set, |
807 | .process = &rs600_irq_process, |
757 | .process = &rs600_irq_process, |
808 | }, |
758 | }, |
809 | .display = { |
759 | .display = { |
810 | .get_vblank_counter = &rs600_get_vblank_counter, |
760 | .get_vblank_counter = &rs600_get_vblank_counter, |
811 | .bandwidth_update = &rv515_bandwidth_update, |
761 | .bandwidth_update = &rv515_bandwidth_update, |
812 | .wait_for_vblank = &avivo_wait_for_vblank, |
762 | .wait_for_vblank = &avivo_wait_for_vblank, |
813 | // .set_backlight_level = &atombios_set_backlight_level, |
763 | .set_backlight_level = &atombios_set_backlight_level, |
814 | // .get_backlight_level = &atombios_get_backlight_level, |
764 | .get_backlight_level = &atombios_get_backlight_level, |
815 | }, |
765 | }, |
816 | .copy = { |
766 | .copy = { |
817 | .blit = &r100_copy_blit, |
767 | .blit = &r100_copy_blit, |
818 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
768 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 824... | Line 774... | ||
824 | .surface = { |
774 | .surface = { |
825 | .set_reg = r100_set_surface_reg, |
775 | .set_reg = r100_set_surface_reg, |
826 | .clear_reg = r100_clear_surface_reg, |
776 | .clear_reg = r100_clear_surface_reg, |
827 | }, |
777 | }, |
828 | .hpd = { |
778 | .hpd = { |
829 | // .init = &rs600_hpd_init, |
779 | .init = &rs600_hpd_init, |
830 | // .fini = &rs600_hpd_fini, |
780 | .fini = &rs600_hpd_fini, |
831 | // .sense = &rs600_hpd_sense, |
781 | .sense = &rs600_hpd_sense, |
832 | // .set_polarity = &rs600_hpd_set_polarity, |
782 | .set_polarity = &rs600_hpd_set_polarity, |
833 | }, |
783 | }, |
834 | .pm = { |
784 | .pm = { |
835 | // .misc = &rs600_pm_misc, |
785 | .misc = &rs600_pm_misc, |
836 | // .prepare = &rs600_pm_prepare, |
786 | .prepare = &rs600_pm_prepare, |
837 | // .finish = &rs600_pm_finish, |
787 | .finish = &rs600_pm_finish, |
838 | // .init_profile = &r420_pm_init_profile, |
788 | .init_profile = &r420_pm_init_profile, |
839 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
789 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
840 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
790 | .get_engine_clock = &radeon_atom_get_engine_clock, |
841 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
791 | .set_engine_clock = &radeon_atom_set_engine_clock, |
842 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
792 | .get_memory_clock = &radeon_atom_get_memory_clock, |
843 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
793 | .set_memory_clock = &radeon_atom_set_memory_clock, |
844 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
794 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
845 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
795 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
846 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
796 | .set_clock_gating = &radeon_atom_set_clock_gating, |
847 | }, |
797 | }, |
848 | .pflip = { |
798 | .pflip = { |
849 | // .pre_page_flip = &rs600_pre_page_flip, |
799 | // .pre_page_flip = &rs600_pre_page_flip, |
850 | // .page_flip = &rs600_page_flip, |
800 | // .page_flip = &rs600_page_flip, |
851 | // .post_page_flip = &rs600_post_page_flip, |
- | |
852 | }, |
801 | }, |
853 | }; |
802 | }; |
Line 854... | Line 803... | ||
854 | 803 | ||
855 | static struct radeon_asic r520_asic = { |
804 | static struct radeon_asic r520_asic = { |
856 | .init = &r520_init, |
805 | .init = &r520_init, |
857 | // .fini = &rv515_fini, |
806 | // .fini = &rv515_fini, |
858 | // .suspend = &rv515_suspend, |
807 | // .suspend = &rv515_suspend, |
859 | // .resume = &r520_resume, |
808 | // .resume = &r520_resume, |
860 | // .vga_set_state = &r100_vga_set_state, |
809 | // .vga_set_state = &r100_vga_set_state, |
861 | .asic_reset = &rs600_asic_reset, |
810 | .asic_reset = &rs600_asic_reset, |
862 | .ioctl_wait_idle = NULL, |
811 | .mmio_hdp_flush = NULL, |
863 | .gui_idle = &r100_gui_idle, |
812 | .gui_idle = &r100_gui_idle, |
864 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
813 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
865 | .gart = { |
814 | .gart = { |
866 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
815 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
867 | .set_page = &rv370_pcie_gart_set_page, |
816 | .set_page = &rv370_pcie_gart_set_page, |
868 | }, |
817 | }, |
869 | .ring = { |
818 | .ring = { |
870 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
871 | .ib_execute = &r100_ring_ib_execute, |
- | |
872 | .emit_fence = &r300_fence_ring_emit, |
- | |
873 | .emit_semaphore = &r100_semaphore_ring_emit, |
- | |
874 | // .cs_parse = &r300_cs_parse, |
- | |
875 | .ring_start = &rv515_ring_start, |
- | |
876 | .ring_test = &r100_ring_test, |
- | |
877 | .ib_test = &r100_ib_test, |
- | |
878 | .is_lockup = &r100_gpu_is_lockup, |
- | |
879 | } |
819 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
880 | }, |
820 | }, |
881 | .irq = { |
821 | .irq = { |
882 | .set = &rs600_irq_set, |
822 | .set = &rs600_irq_set, |
883 | .process = &rs600_irq_process, |
823 | .process = &rs600_irq_process, |
884 | }, |
824 | }, |
885 | .display = { |
825 | .display = { |
886 | .bandwidth_update = &rv515_bandwidth_update, |
826 | .bandwidth_update = &rv515_bandwidth_update, |
887 | .get_vblank_counter = &rs600_get_vblank_counter, |
827 | .get_vblank_counter = &rs600_get_vblank_counter, |
888 | .wait_for_vblank = &avivo_wait_for_vblank, |
828 | .wait_for_vblank = &avivo_wait_for_vblank, |
889 | // .set_backlight_level = &atombios_set_backlight_level, |
829 | .set_backlight_level = &atombios_set_backlight_level, |
890 | // .get_backlight_level = &atombios_get_backlight_level, |
830 | .get_backlight_level = &atombios_get_backlight_level, |
891 | }, |
831 | }, |
892 | .copy = { |
832 | .copy = { |
893 | .blit = &r100_copy_blit, |
833 | .blit = &r100_copy_blit, |
894 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
834 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
Line 900... | Line 840... | ||
900 | .surface = { |
840 | .surface = { |
901 | .set_reg = r100_set_surface_reg, |
841 | .set_reg = r100_set_surface_reg, |
902 | .clear_reg = r100_clear_surface_reg, |
842 | .clear_reg = r100_clear_surface_reg, |
903 | }, |
843 | }, |
904 | .hpd = { |
844 | .hpd = { |
905 | // .init = &rs600_hpd_init, |
845 | .init = &rs600_hpd_init, |
906 | // .fini = &rs600_hpd_fini, |
846 | .fini = &rs600_hpd_fini, |
907 | // .sense = &rs600_hpd_sense, |
847 | .sense = &rs600_hpd_sense, |
908 | // .set_polarity = &rs600_hpd_set_polarity, |
848 | .set_polarity = &rs600_hpd_set_polarity, |
909 | }, |
849 | }, |
910 | .pm = { |
850 | .pm = { |
911 | // .misc = &rs600_pm_misc, |
851 | .misc = &rs600_pm_misc, |
912 | // .prepare = &rs600_pm_prepare, |
852 | .prepare = &rs600_pm_prepare, |
913 | // .finish = &rs600_pm_finish, |
853 | .finish = &rs600_pm_finish, |
914 | // .init_profile = &r420_pm_init_profile, |
854 | .init_profile = &r420_pm_init_profile, |
915 | // .get_dynpm_state = &r100_pm_get_dynpm_state, |
855 | .get_dynpm_state = &r100_pm_get_dynpm_state, |
916 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
856 | .get_engine_clock = &radeon_atom_get_engine_clock, |
917 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
857 | .set_engine_clock = &radeon_atom_set_engine_clock, |
918 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
858 | .get_memory_clock = &radeon_atom_get_memory_clock, |
919 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
859 | .set_memory_clock = &radeon_atom_set_memory_clock, |
920 | // .get_pcie_lanes = &rv370_get_pcie_lanes, |
860 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
921 | // .set_pcie_lanes = &rv370_set_pcie_lanes, |
861 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
922 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
862 | .set_clock_gating = &radeon_atom_set_clock_gating, |
923 | }, |
863 | }, |
924 | .pflip = { |
864 | .pflip = { |
925 | // .pre_page_flip = &rs600_pre_page_flip, |
865 | // .pre_page_flip = &rs600_pre_page_flip, |
926 | // .page_flip = &rs600_page_flip, |
866 | // .page_flip = &rs600_page_flip, |
927 | // .post_page_flip = &rs600_post_page_flip, |
- | |
928 | }, |
867 | }, |
929 | }; |
868 | }; |
Line -... | Line 869... | ||
- | 869 | ||
- | 870 | static struct radeon_asic_ring r600_gfx_ring = { |
|
- | 871 | .ib_execute = &r600_ring_ib_execute, |
|
- | 872 | .emit_fence = &r600_fence_ring_emit, |
|
- | 873 | .emit_semaphore = &r600_semaphore_ring_emit, |
|
- | 874 | .cs_parse = &r600_cs_parse, |
|
- | 875 | .ring_test = &r600_ring_test, |
|
- | 876 | .ib_test = &r600_ib_test, |
|
- | 877 | .is_lockup = &r600_gfx_is_lockup, |
|
- | 878 | .get_rptr = &r600_gfx_get_rptr, |
|
- | 879 | .get_wptr = &r600_gfx_get_wptr, |
|
- | 880 | .set_wptr = &r600_gfx_set_wptr, |
|
- | 881 | }; |
|
- | 882 | ||
- | 883 | static struct radeon_asic_ring r600_dma_ring = { |
|
- | 884 | .ib_execute = &r600_dma_ring_ib_execute, |
|
- | 885 | .emit_fence = &r600_dma_fence_ring_emit, |
|
- | 886 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
- | 887 | .cs_parse = &r600_dma_cs_parse, |
|
- | 888 | .ring_test = &r600_dma_ring_test, |
|
- | 889 | .ib_test = &r600_dma_ib_test, |
|
- | 890 | .is_lockup = &r600_dma_is_lockup, |
|
- | 891 | .get_rptr = &r600_dma_get_rptr, |
|
- | 892 | .get_wptr = &r600_dma_get_wptr, |
|
- | 893 | .set_wptr = &r600_dma_set_wptr, |
|
- | 894 | }; |
|
930 | 895 | ||
931 | static struct radeon_asic r600_asic = { |
896 | static struct radeon_asic r600_asic = { |
932 | .init = &r600_init, |
897 | .init = &r600_init, |
933 | // .fini = &r600_fini, |
898 | // .fini = &r600_fini, |
934 | // .suspend = &r600_suspend, |
899 | // .suspend = &r600_suspend, |
935 | // .resume = &r600_resume, |
900 | // .resume = &r600_resume, |
936 | // .vga_set_state = &r600_vga_set_state, |
901 | // .vga_set_state = &r600_vga_set_state, |
937 | .asic_reset = &r600_asic_reset, |
902 | .asic_reset = &r600_asic_reset, |
938 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
903 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
939 | .gui_idle = &r600_gui_idle, |
904 | .gui_idle = &r600_gui_idle, |
940 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
905 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
941 | .get_xclk = &r600_get_xclk, |
906 | .get_xclk = &r600_get_xclk, |
942 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
907 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
943 | .gart = { |
908 | .gart = { |
944 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
909 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
945 | .set_page = &rs600_gart_set_page, |
910 | .set_page = &rs600_gart_set_page, |
946 | }, |
911 | }, |
947 | .ring = { |
912 | .ring = { |
948 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
949 | .ib_execute = &r600_ring_ib_execute, |
- | |
950 | .emit_fence = &r600_fence_ring_emit, |
913 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
951 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
952 | // .cs_parse = &r600_cs_parse, |
- | |
953 | .ring_test = &r600_ring_test, |
- | |
954 | .ib_test = &r600_ib_test, |
- | |
955 | .is_lockup = &r600_gfx_is_lockup, |
914 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
- | 915 | }, |
|
- | 916 | .irq = { |
|
- | 917 | .set = &r600_irq_set, |
|
- | 918 | .process = &r600_irq_process, |
|
- | 919 | }, |
|
- | 920 | .display = { |
|
- | 921 | .bandwidth_update = &rv515_bandwidth_update, |
|
- | 922 | .get_vblank_counter = &rs600_get_vblank_counter, |
|
- | 923 | .wait_for_vblank = &avivo_wait_for_vblank, |
|
- | 924 | .set_backlight_level = &atombios_set_backlight_level, |
|
- | 925 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 926 | .hdmi_enable = &r600_hdmi_enable, |
|
- | 927 | .hdmi_setmode = &r600_hdmi_setmode, |
|
- | 928 | }, |
|
- | 929 | .copy = { |
|
- | 930 | .blit = &r600_copy_cpdma, |
|
- | 931 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
|
956 | }, |
932 | .dma = &r600_copy_dma, |
- | 933 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
|
- | 934 | .copy = &r600_copy_cpdma, |
|
- | 935 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
|
- | 936 | }, |
|
- | 937 | .surface = { |
|
- | 938 | .set_reg = r600_set_surface_reg, |
|
- | 939 | .clear_reg = r600_clear_surface_reg, |
|
- | 940 | }, |
|
957 | [R600_RING_TYPE_DMA_INDEX] = { |
941 | .hpd = { |
- | 942 | .init = &r600_hpd_init, |
|
958 | .ib_execute = &r600_dma_ring_ib_execute, |
943 | .fini = &r600_hpd_fini, |
959 | .emit_fence = &r600_dma_fence_ring_emit, |
944 | .sense = &r600_hpd_sense, |
- | 945 | .set_polarity = &r600_hpd_set_polarity, |
|
- | 946 | }, |
|
- | 947 | .pm = { |
|
960 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
948 | .misc = &r600_pm_misc, |
961 | // .cs_parse = &r600_dma_cs_parse, |
949 | .prepare = &rs600_pm_prepare, |
- | 950 | .finish = &rs600_pm_finish, |
|
- | 951 | .init_profile = &r600_pm_init_profile, |
|
- | 952 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
|
- | 953 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
- | 954 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
- | 955 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
- | 956 | .set_memory_clock = &radeon_atom_set_memory_clock, |
|
- | 957 | .get_pcie_lanes = &r600_get_pcie_lanes, |
|
- | 958 | .set_pcie_lanes = &r600_set_pcie_lanes, |
|
- | 959 | .set_clock_gating = NULL, |
|
- | 960 | .get_temperature = &rv6xx_get_temp, |
|
- | 961 | }, |
|
- | 962 | .pflip = { |
|
- | 963 | // .pre_page_flip = &rs600_pre_page_flip, |
|
- | 964 | // .page_flip = &rs600_page_flip, |
|
- | 965 | }, |
|
- | 966 | }; |
|
- | 967 | ||
- | 968 | static struct radeon_asic rv6xx_asic = { |
|
- | 969 | .init = &r600_init, |
|
- | 970 | // .fini = &r600_fini, |
|
- | 971 | // .suspend = &r600_suspend, |
|
- | 972 | // .resume = &r600_resume, |
|
962 | .ring_test = &r600_dma_ring_test, |
973 | // .vga_set_state = &r600_vga_set_state, |
- | 974 | .asic_reset = &r600_asic_reset, |
|
- | 975 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
|
- | 976 | .gui_idle = &r600_gui_idle, |
|
- | 977 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
|
- | 978 | .get_xclk = &r600_get_xclk, |
|
- | 979 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
|
- | 980 | .gart = { |
|
963 | .ib_test = &r600_dma_ib_test, |
981 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
964 | .is_lockup = &r600_dma_is_lockup, |
982 | .set_page = &rs600_gart_set_page, |
- | 983 | }, |
|
- | 984 | .ring = { |
|
- | 985 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
|
965 | } |
986 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
966 | }, |
987 | }, |
967 | .irq = { |
988 | .irq = { |
968 | .set = &r600_irq_set, |
989 | .set = &r600_irq_set, |
969 | .process = &r600_irq_process, |
990 | .process = &r600_irq_process, |
970 | }, |
991 | }, |
971 | .display = { |
992 | .display = { |
972 | .bandwidth_update = &rv515_bandwidth_update, |
993 | .bandwidth_update = &rv515_bandwidth_update, |
973 | .get_vblank_counter = &rs600_get_vblank_counter, |
994 | .get_vblank_counter = &rs600_get_vblank_counter, |
974 | .wait_for_vblank = &avivo_wait_for_vblank, |
995 | .wait_for_vblank = &avivo_wait_for_vblank, |
975 | // .set_backlight_level = &atombios_set_backlight_level, |
996 | .set_backlight_level = &atombios_set_backlight_level, |
- | 997 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 998 | .hdmi_enable = &r600_hdmi_enable, |
|
976 | // .get_backlight_level = &atombios_get_backlight_level, |
999 | .hdmi_setmode = &r600_hdmi_setmode, |
977 | }, |
1000 | }, |
978 | .copy = { |
1001 | .copy = { |
979 | .blit = &r600_copy_blit, |
1002 | .blit = &r600_copy_cpdma, |
980 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1003 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
981 | .dma = &r600_copy_dma, |
1004 | .dma = &r600_copy_dma, |
982 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1005 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
983 | .copy = &r600_copy_dma, |
1006 | .copy = &r600_copy_cpdma, |
984 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1007 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
985 | }, |
1008 | }, |
986 | .surface = { |
1009 | .surface = { |
987 | .set_reg = r600_set_surface_reg, |
1010 | .set_reg = r600_set_surface_reg, |
988 | .clear_reg = r600_clear_surface_reg, |
1011 | .clear_reg = r600_clear_surface_reg, |
989 | }, |
1012 | }, |
990 | .hpd = { |
1013 | .hpd = { |
991 | // .init = &r600_hpd_init, |
1014 | .init = &r600_hpd_init, |
992 | // .fini = &r600_hpd_fini, |
1015 | .fini = &r600_hpd_fini, |
993 | // .sense = &r600_hpd_sense, |
1016 | .sense = &r600_hpd_sense, |
994 | // .set_polarity = &r600_hpd_set_polarity, |
1017 | .set_polarity = &r600_hpd_set_polarity, |
995 | }, |
1018 | }, |
996 | .pm = { |
1019 | .pm = { |
997 | // .misc = &r600_pm_misc, |
1020 | .misc = &r600_pm_misc, |
998 | // .prepare = &rs600_pm_prepare, |
1021 | .prepare = &rs600_pm_prepare, |
999 | // .finish = &rs600_pm_finish, |
1022 | .finish = &rs600_pm_finish, |
1000 | // .init_profile = &r600_pm_init_profile, |
1023 | .init_profile = &r600_pm_init_profile, |
1001 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1024 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1002 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1025 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1003 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1026 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1004 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1027 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1005 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1028 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1006 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
1029 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1007 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
1030 | .set_pcie_lanes = &r600_set_pcie_lanes, |
- | 1031 | .set_clock_gating = NULL, |
|
- | 1032 | .get_temperature = &rv6xx_get_temp, |
|
- | 1033 | .set_uvd_clocks = &r600_set_uvd_clocks, |
|
- | 1034 | }, |
|
- | 1035 | .dpm = { |
|
- | 1036 | .init = &rv6xx_dpm_init, |
|
- | 1037 | .setup_asic = &rv6xx_setup_asic, |
|
- | 1038 | .enable = &rv6xx_dpm_enable, |
|
- | 1039 | .late_enable = &r600_dpm_late_enable, |
|
- | 1040 | .disable = &rv6xx_dpm_disable, |
|
- | 1041 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
|
- | 1042 | .set_power_state = &rv6xx_dpm_set_power_state, |
|
- | 1043 | .post_set_power_state = &r600_dpm_post_set_power_state, |
|
- | 1044 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, |
|
- | 1045 | .fini = &rv6xx_dpm_fini, |
|
- | 1046 | .get_sclk = &rv6xx_dpm_get_sclk, |
|
- | 1047 | .get_mclk = &rv6xx_dpm_get_mclk, |
|
- | 1048 | .print_power_state = &rv6xx_dpm_print_power_state, |
|
- | 1049 | .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, |
|
1008 | .set_clock_gating = NULL, |
1050 | .force_performance_level = &rv6xx_dpm_force_performance_level, |
1009 | }, |
1051 | }, |
1010 | .pflip = { |
1052 | .pflip = { |
1011 | // .pre_page_flip = &rs600_pre_page_flip, |
1053 | // .pre_page_flip = &rs600_pre_page_flip, |
1012 | // .page_flip = &rs600_page_flip, |
- | |
1013 | // .post_page_flip = &rs600_post_page_flip, |
1054 | // .page_flip = &rs600_page_flip, |
1014 | }, |
1055 | }, |
Line 1015... | Line 1056... | ||
1015 | }; |
1056 | }; |
1016 | 1057 | ||
1017 | static struct radeon_asic rs780_asic = { |
1058 | static struct radeon_asic rs780_asic = { |
1018 | .init = &r600_init, |
1059 | .init = &r600_init, |
1019 | // .fini = &r600_fini, |
1060 | // .fini = &r600_fini, |
1020 | // .suspend = &r600_suspend, |
1061 | // .suspend = &r600_suspend, |
1021 | // .resume = &r600_resume, |
1062 | // .resume = &r600_resume, |
1022 | // .vga_set_state = &r600_vga_set_state, |
1063 | // .vga_set_state = &r600_vga_set_state, |
1023 | .asic_reset = &r600_asic_reset, |
1064 | .asic_reset = &r600_asic_reset, |
1024 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1065 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1025 | .gui_idle = &r600_gui_idle, |
1066 | .gui_idle = &r600_gui_idle, |
1026 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1067 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1027 | .get_xclk = &r600_get_xclk, |
1068 | .get_xclk = &r600_get_xclk, |
1028 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1069 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1029 | .gart = { |
1070 | .gart = { |
1030 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1071 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1031 | .set_page = &rs600_gart_set_page, |
1072 | .set_page = &rs600_gart_set_page, |
1032 | }, |
1073 | }, |
1033 | .ring = { |
- | |
1034 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
1035 | .ib_execute = &r600_ring_ib_execute, |
- | |
1036 | .emit_fence = &r600_fence_ring_emit, |
- | |
1037 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1038 | // .cs_parse = &r600_cs_parse, |
- | |
1039 | .ring_test = &r600_ring_test, |
- | |
1040 | .ib_test = &r600_ib_test, |
- | |
1041 | .is_lockup = &r600_gfx_is_lockup, |
1074 | .ring = { |
1042 | }, |
- | |
1043 | [R600_RING_TYPE_DMA_INDEX] = { |
- | |
1044 | .ib_execute = &r600_dma_ring_ib_execute, |
- | |
1045 | .emit_fence = &r600_dma_fence_ring_emit, |
- | |
1046 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1047 | // .cs_parse = &r600_dma_cs_parse, |
- | |
1048 | .ring_test = &r600_dma_ring_test, |
- | |
1049 | .ib_test = &r600_dma_ib_test, |
- | |
1050 | .is_lockup = &r600_dma_is_lockup, |
1075 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1051 | } |
1076 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
1052 | }, |
1077 | }, |
1053 | .irq = { |
1078 | .irq = { |
1054 | .set = &r600_irq_set, |
1079 | .set = &r600_irq_set, |
1055 | .process = &r600_irq_process, |
1080 | .process = &r600_irq_process, |
1056 | }, |
1081 | }, |
1057 | .display = { |
1082 | .display = { |
1058 | .bandwidth_update = &rs690_bandwidth_update, |
1083 | .bandwidth_update = &rs690_bandwidth_update, |
1059 | .get_vblank_counter = &rs600_get_vblank_counter, |
1084 | .get_vblank_counter = &rs600_get_vblank_counter, |
1060 | .wait_for_vblank = &avivo_wait_for_vblank, |
1085 | .wait_for_vblank = &avivo_wait_for_vblank, |
- | 1086 | .set_backlight_level = &atombios_set_backlight_level, |
|
- | 1087 | .get_backlight_level = &atombios_get_backlight_level, |
|
1061 | // .set_backlight_level = &atombios_set_backlight_level, |
1088 | .hdmi_enable = &r600_hdmi_enable, |
1062 | // .get_backlight_level = &atombios_get_backlight_level, |
1089 | .hdmi_setmode = &r600_hdmi_setmode, |
1063 | }, |
1090 | }, |
1064 | .copy = { |
1091 | .copy = { |
1065 | .blit = &r600_copy_blit, |
1092 | .blit = &r600_copy_cpdma, |
1066 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1093 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1067 | .dma = &r600_copy_dma, |
1094 | .dma = &r600_copy_dma, |
1068 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1095 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1069 | .copy = &r600_copy_dma, |
1096 | .copy = &r600_copy_cpdma, |
1070 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1097 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1071 | }, |
1098 | }, |
1072 | .surface = { |
1099 | .surface = { |
1073 | .set_reg = r600_set_surface_reg, |
1100 | .set_reg = r600_set_surface_reg, |
1074 | .clear_reg = r600_clear_surface_reg, |
1101 | .clear_reg = r600_clear_surface_reg, |
1075 | }, |
1102 | }, |
1076 | .hpd = { |
1103 | .hpd = { |
1077 | // .init = &r600_hpd_init, |
1104 | .init = &r600_hpd_init, |
1078 | // .fini = &r600_hpd_fini, |
1105 | .fini = &r600_hpd_fini, |
1079 | // .sense = &r600_hpd_sense, |
1106 | .sense = &r600_hpd_sense, |
1080 | // .set_polarity = &r600_hpd_set_polarity, |
1107 | .set_polarity = &r600_hpd_set_polarity, |
1081 | }, |
1108 | }, |
1082 | .pm = { |
1109 | .pm = { |
1083 | // .misc = &r600_pm_misc, |
1110 | .misc = &r600_pm_misc, |
1084 | // .prepare = &rs600_pm_prepare, |
1111 | .prepare = &rs600_pm_prepare, |
1085 | // .finish = &rs600_pm_finish, |
1112 | .finish = &rs600_pm_finish, |
1086 | // .init_profile = &rs780_pm_init_profile, |
1113 | .init_profile = &rs780_pm_init_profile, |
1087 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1114 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1088 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1115 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1089 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1116 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1090 | .get_memory_clock = NULL, |
1117 | .get_memory_clock = NULL, |
1091 | .set_memory_clock = NULL, |
1118 | .set_memory_clock = NULL, |
1092 | .get_pcie_lanes = NULL, |
1119 | .get_pcie_lanes = NULL, |
- | 1120 | .set_pcie_lanes = NULL, |
|
- | 1121 | .set_clock_gating = NULL, |
|
- | 1122 | .get_temperature = &rv6xx_get_temp, |
|
- | 1123 | .set_uvd_clocks = &r600_set_uvd_clocks, |
|
- | 1124 | }, |
|
- | 1125 | .dpm = { |
|
- | 1126 | .init = &rs780_dpm_init, |
|
- | 1127 | .setup_asic = &rs780_dpm_setup_asic, |
|
- | 1128 | .enable = &rs780_dpm_enable, |
|
- | 1129 | .late_enable = &r600_dpm_late_enable, |
|
- | 1130 | .disable = &rs780_dpm_disable, |
|
- | 1131 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
|
- | 1132 | .set_power_state = &rs780_dpm_set_power_state, |
|
- | 1133 | .post_set_power_state = &r600_dpm_post_set_power_state, |
|
- | 1134 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, |
|
- | 1135 | .fini = &rs780_dpm_fini, |
|
- | 1136 | .get_sclk = &rs780_dpm_get_sclk, |
|
- | 1137 | .get_mclk = &rs780_dpm_get_mclk, |
|
- | 1138 | .print_power_state = &rs780_dpm_print_power_state, |
|
1093 | .set_pcie_lanes = NULL, |
1139 | .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, |
1094 | .set_clock_gating = NULL, |
1140 | .force_performance_level = &rs780_dpm_force_performance_level, |
1095 | }, |
1141 | }, |
1096 | .pflip = { |
1142 | .pflip = { |
1097 | // .pre_page_flip = &rs600_pre_page_flip, |
- | |
1098 | // .page_flip = &rs600_page_flip, |
1143 | // .pre_page_flip = &rs600_pre_page_flip, |
1099 | // .post_page_flip = &rs600_post_page_flip, |
1144 | // .page_flip = &rs600_page_flip, |
Line -... | Line 1145... | ||
- | 1145 | }, |
|
- | 1146 | }; |
|
- | 1147 | ||
- | 1148 | static struct radeon_asic_ring rv770_uvd_ring = { |
|
- | 1149 | .ib_execute = &uvd_v1_0_ib_execute, |
|
- | 1150 | .emit_fence = &uvd_v2_2_fence_emit, |
|
- | 1151 | .emit_semaphore = &uvd_v1_0_semaphore_emit, |
|
- | 1152 | .cs_parse = &radeon_uvd_cs_parse, |
|
- | 1153 | .ring_test = &uvd_v1_0_ring_test, |
|
- | 1154 | .ib_test = &uvd_v1_0_ib_test, |
|
- | 1155 | .is_lockup = &radeon_ring_test_lockup, |
|
- | 1156 | .get_rptr = &uvd_v1_0_get_rptr, |
|
- | 1157 | .get_wptr = &uvd_v1_0_get_wptr, |
|
1100 | }, |
1158 | .set_wptr = &uvd_v1_0_set_wptr, |
1101 | }; |
1159 | }; |
1102 | 1160 | ||
1103 | static struct radeon_asic rv770_asic = { |
1161 | static struct radeon_asic rv770_asic = { |
1104 | .init = &rv770_init, |
1162 | .init = &rv770_init, |
1105 | // .fini = &rv770_fini, |
1163 | // .fini = &rv770_fini, |
1106 | // .suspend = &rv770_suspend, |
1164 | // .suspend = &rv770_suspend, |
1107 | // .resume = &rv770_resume, |
1165 | // .resume = &rv770_resume, |
1108 | .asic_reset = &r600_asic_reset, |
1166 | .asic_reset = &r600_asic_reset, |
1109 | // .vga_set_state = &r600_vga_set_state, |
1167 | // .vga_set_state = &r600_vga_set_state, |
1110 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1168 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1111 | .gui_idle = &r600_gui_idle, |
1169 | .gui_idle = &r600_gui_idle, |
1112 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1170 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1113 | .get_xclk = &rv770_get_xclk, |
1171 | .get_xclk = &rv770_get_xclk, |
1114 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1172 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1115 | .gart = { |
1173 | .gart = { |
1116 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1174 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1117 | .set_page = &rs600_gart_set_page, |
1175 | .set_page = &rs600_gart_set_page, |
1118 | }, |
- | |
1119 | .ring = { |
- | |
1120 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
1121 | .ib_execute = &r600_ring_ib_execute, |
- | |
1122 | .emit_fence = &r600_fence_ring_emit, |
- | |
1123 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1124 | // .cs_parse = &r600_cs_parse, |
- | |
1125 | .ring_test = &r600_ring_test, |
- | |
1126 | .ib_test = &r600_ib_test, |
1176 | }, |
1127 | .is_lockup = &r600_gfx_is_lockup, |
- | |
1128 | }, |
- | |
1129 | [R600_RING_TYPE_DMA_INDEX] = { |
- | |
1130 | .ib_execute = &r600_dma_ring_ib_execute, |
- | |
1131 | .emit_fence = &r600_dma_fence_ring_emit, |
- | |
1132 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1133 | // .cs_parse = &r600_dma_cs_parse, |
- | |
1134 | .ring_test = &r600_dma_ring_test, |
- | |
1135 | .ib_test = &r600_dma_ib_test, |
1177 | .ring = { |
1136 | .is_lockup = &r600_dma_is_lockup, |
- | |
1137 | }, |
- | |
1138 | [R600_RING_TYPE_UVD_INDEX] = { |
- | |
1139 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1140 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1141 | // .emit_semaphore = &r600_uvd_semaphore_emit, |
- | |
1142 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1143 | // .ring_test = &r600_uvd_ring_test, |
- | |
1144 | // .ib_test = &r600_uvd_ib_test, |
1178 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1145 | // .is_lockup = &radeon_ring_test_lockup, |
1179 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, |
1146 | } |
1180 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, |
1147 | }, |
1181 | }, |
1148 | .irq = { |
1182 | .irq = { |
1149 | .set = &r600_irq_set, |
1183 | .set = &r600_irq_set, |
1150 | .process = &r600_irq_process, |
1184 | .process = &r600_irq_process, |
1151 | }, |
1185 | }, |
1152 | .display = { |
1186 | .display = { |
1153 | .bandwidth_update = &rv515_bandwidth_update, |
1187 | .bandwidth_update = &rv515_bandwidth_update, |
1154 | .get_vblank_counter = &rs600_get_vblank_counter, |
1188 | .get_vblank_counter = &rs600_get_vblank_counter, |
- | 1189 | .wait_for_vblank = &avivo_wait_for_vblank, |
|
- | 1190 | .set_backlight_level = &atombios_set_backlight_level, |
|
1155 | .wait_for_vblank = &avivo_wait_for_vblank, |
1191 | .get_backlight_level = &atombios_get_backlight_level, |
1156 | // .set_backlight_level = &atombios_set_backlight_level, |
1192 | .hdmi_enable = &r600_hdmi_enable, |
1157 | // .get_backlight_level = &atombios_get_backlight_level, |
1193 | .hdmi_setmode = &dce3_1_hdmi_setmode, |
1158 | }, |
1194 | }, |
1159 | .copy = { |
1195 | .copy = { |
1160 | .blit = &r600_copy_blit, |
1196 | .blit = &r600_copy_cpdma, |
1161 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1197 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1162 | .dma = &rv770_copy_dma, |
1198 | .dma = &rv770_copy_dma, |
Line 1167... | Line 1203... | ||
1167 | .surface = { |
1203 | .surface = { |
1168 | .set_reg = r600_set_surface_reg, |
1204 | .set_reg = r600_set_surface_reg, |
1169 | .clear_reg = r600_clear_surface_reg, |
1205 | .clear_reg = r600_clear_surface_reg, |
1170 | }, |
1206 | }, |
1171 | .hpd = { |
1207 | .hpd = { |
1172 | // .init = &r600_hpd_init, |
1208 | .init = &r600_hpd_init, |
1173 | // .fini = &r600_hpd_fini, |
1209 | .fini = &r600_hpd_fini, |
1174 | // .sense = &r600_hpd_sense, |
1210 | .sense = &r600_hpd_sense, |
1175 | // .set_polarity = &r600_hpd_set_polarity, |
1211 | .set_polarity = &r600_hpd_set_polarity, |
1176 | }, |
1212 | }, |
1177 | .pm = { |
1213 | .pm = { |
1178 | // .misc = &rv770_pm_misc, |
1214 | .misc = &rv770_pm_misc, |
1179 | // .prepare = &rs600_pm_prepare, |
1215 | .prepare = &rs600_pm_prepare, |
1180 | // .finish = &rs600_pm_finish, |
1216 | .finish = &rs600_pm_finish, |
1181 | // .init_profile = &r600_pm_init_profile, |
1217 | .init_profile = &r600_pm_init_profile, |
1182 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1218 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1183 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1219 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1184 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1220 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1185 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1221 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1186 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1222 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1187 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
1223 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1188 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
1224 | .set_pcie_lanes = &r600_set_pcie_lanes, |
1189 | // .set_clock_gating = &radeon_atom_set_clock_gating, |
1225 | .set_clock_gating = &radeon_atom_set_clock_gating, |
1190 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
1226 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
- | 1227 | .get_temperature = &rv770_get_temp, |
|
- | 1228 | }, |
|
- | 1229 | .dpm = { |
|
- | 1230 | .init = &rv770_dpm_init, |
|
- | 1231 | .setup_asic = &rv770_dpm_setup_asic, |
|
- | 1232 | .enable = &rv770_dpm_enable, |
|
- | 1233 | .late_enable = &rv770_dpm_late_enable, |
|
- | 1234 | .disable = &rv770_dpm_disable, |
|
- | 1235 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
|
- | 1236 | .set_power_state = &rv770_dpm_set_power_state, |
|
- | 1237 | .post_set_power_state = &r600_dpm_post_set_power_state, |
|
- | 1238 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, |
|
- | 1239 | .fini = &rv770_dpm_fini, |
|
- | 1240 | .get_sclk = &rv770_dpm_get_sclk, |
|
- | 1241 | .get_mclk = &rv770_dpm_get_mclk, |
|
- | 1242 | .print_power_state = &rv770_dpm_print_power_state, |
|
- | 1243 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
|
- | 1244 | .force_performance_level = &rv770_dpm_force_performance_level, |
|
- | 1245 | .vblank_too_short = &rv770_dpm_vblank_too_short, |
|
1191 | }, |
1246 | }, |
1192 | .pflip = { |
1247 | .pflip = { |
1193 | // .pre_page_flip = &rs600_pre_page_flip, |
1248 | // .pre_page_flip = &rs600_pre_page_flip, |
1194 | // .page_flip = &rv770_page_flip, |
1249 | // .page_flip = &rv770_page_flip, |
1195 | // .post_page_flip = &rs600_post_page_flip, |
- | |
1196 | }, |
1250 | }, |
1197 | }; |
1251 | }; |
Line -... | Line 1252... | ||
- | 1252 | ||
- | 1253 | static struct radeon_asic_ring evergreen_gfx_ring = { |
|
- | 1254 | .ib_execute = &evergreen_ring_ib_execute, |
|
- | 1255 | .emit_fence = &r600_fence_ring_emit, |
|
- | 1256 | .emit_semaphore = &r600_semaphore_ring_emit, |
|
- | 1257 | .cs_parse = &evergreen_cs_parse, |
|
- | 1258 | .ring_test = &r600_ring_test, |
|
- | 1259 | .ib_test = &r600_ib_test, |
|
- | 1260 | .is_lockup = &evergreen_gfx_is_lockup, |
|
- | 1261 | .get_rptr = &r600_gfx_get_rptr, |
|
- | 1262 | .get_wptr = &r600_gfx_get_wptr, |
|
- | 1263 | .set_wptr = &r600_gfx_set_wptr, |
|
- | 1264 | }; |
|
- | 1265 | ||
- | 1266 | static struct radeon_asic_ring evergreen_dma_ring = { |
|
- | 1267 | .ib_execute = &evergreen_dma_ring_ib_execute, |
|
- | 1268 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
- | 1269 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
- | 1270 | .cs_parse = &evergreen_dma_cs_parse, |
|
- | 1271 | .ring_test = &r600_dma_ring_test, |
|
- | 1272 | .ib_test = &r600_dma_ib_test, |
|
- | 1273 | .is_lockup = &evergreen_dma_is_lockup, |
|
- | 1274 | .get_rptr = &r600_dma_get_rptr, |
|
- | 1275 | .get_wptr = &r600_dma_get_wptr, |
|
- | 1276 | .set_wptr = &r600_dma_set_wptr, |
|
- | 1277 | }; |
|
1198 | 1278 | ||
1199 | static struct radeon_asic evergreen_asic = { |
1279 | static struct radeon_asic evergreen_asic = { |
1200 | .init = &evergreen_init, |
1280 | .init = &evergreen_init, |
1201 | // .fini = &evergreen_fini, |
1281 | // .fini = &evergreen_fini, |
1202 | // .suspend = &evergreen_suspend, |
1282 | // .suspend = &evergreen_suspend, |
1203 | // .resume = &evergreen_resume, |
1283 | // .resume = &evergreen_resume, |
1204 | .asic_reset = &evergreen_asic_reset, |
1284 | .asic_reset = &evergreen_asic_reset, |
1205 | // .vga_set_state = &r600_vga_set_state, |
1285 | // .vga_set_state = &r600_vga_set_state, |
1206 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1286 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1207 | .gui_idle = &r600_gui_idle, |
1287 | .gui_idle = &r600_gui_idle, |
1208 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1288 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1209 | .get_xclk = &rv770_get_xclk, |
1289 | .get_xclk = &rv770_get_xclk, |
1210 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1290 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1211 | .gart = { |
1291 | .gart = { |
1212 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1292 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1213 | .set_page = &rs600_gart_set_page, |
1293 | .set_page = &rs600_gart_set_page, |
1214 | }, |
1294 | }, |
1215 | .ring = { |
1295 | .ring = { |
1216 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
1217 | .ib_execute = &evergreen_ring_ib_execute, |
- | |
1218 | .emit_fence = &r600_fence_ring_emit, |
- | |
1219 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1220 | // .cs_parse = &evergreen_cs_parse, |
- | |
1221 | .ring_test = &r600_ring_test, |
- | |
1222 | .ib_test = &r600_ib_test, |
- | |
1223 | .is_lockup = &evergreen_gfx_is_lockup, |
- | |
1224 | }, |
1296 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1225 | [R600_RING_TYPE_DMA_INDEX] = { |
- | |
1226 | .ib_execute = &evergreen_dma_ring_ib_execute, |
- | |
1227 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1228 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1229 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1230 | .ring_test = &r600_dma_ring_test, |
- | |
1231 | .ib_test = &r600_dma_ib_test, |
- | |
1232 | .is_lockup = &evergreen_dma_is_lockup, |
- | |
1233 | }, |
1297 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, |
1234 | [R600_RING_TYPE_UVD_INDEX] = { |
- | |
1235 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1236 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1237 | // .emit_semaphore = &r600_uvd_semaphore_emit, |
- | |
1238 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1239 | // .ring_test = &r600_uvd_ring_test, |
- | |
1240 | // .ib_test = &r600_uvd_ib_test, |
- | |
1241 | // .is_lockup = &radeon_ring_test_lockup, |
- | |
1242 | } |
1298 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, |
1243 | }, |
1299 | }, |
1244 | .irq = { |
1300 | .irq = { |
1245 | .set = &evergreen_irq_set, |
1301 | .set = &evergreen_irq_set, |
1246 | .process = &evergreen_irq_process, |
1302 | .process = &evergreen_irq_process, |
1247 | }, |
1303 | }, |
1248 | .display = { |
1304 | .display = { |
1249 | .bandwidth_update = &evergreen_bandwidth_update, |
1305 | .bandwidth_update = &evergreen_bandwidth_update, |
1250 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1306 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1251 | .wait_for_vblank = &dce4_wait_for_vblank, |
1307 | .wait_for_vblank = &dce4_wait_for_vblank, |
1252 | // .set_backlight_level = &atombios_set_backlight_level, |
1308 | .set_backlight_level = &atombios_set_backlight_level, |
- | 1309 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 1310 | .hdmi_enable = &evergreen_hdmi_enable, |
|
1253 | // .get_backlight_level = &atombios_get_backlight_level, |
1311 | .hdmi_setmode = &evergreen_hdmi_setmode, |
1254 | }, |
1312 | }, |
1255 | .copy = { |
1313 | .copy = { |
1256 | .blit = &r600_copy_blit, |
1314 | .blit = &r600_copy_cpdma, |
1257 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1315 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1258 | .dma = &evergreen_copy_dma, |
1316 | .dma = &evergreen_copy_dma, |
1259 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1317 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1260 | .copy = &evergreen_copy_dma, |
1318 | .copy = &evergreen_copy_dma, |
Line 1263... | Line 1321... | ||
1263 | .surface = { |
1321 | .surface = { |
1264 | .set_reg = r600_set_surface_reg, |
1322 | .set_reg = r600_set_surface_reg, |
1265 | .clear_reg = r600_clear_surface_reg, |
1323 | .clear_reg = r600_clear_surface_reg, |
1266 | }, |
1324 | }, |
1267 | .hpd = { |
1325 | .hpd = { |
1268 | // .init = &evergreen_hpd_init, |
1326 | .init = &evergreen_hpd_init, |
1269 | // .fini = &evergreen_hpd_fini, |
1327 | .fini = &evergreen_hpd_fini, |
1270 | // .sense = &evergreen_hpd_sense, |
1328 | .sense = &evergreen_hpd_sense, |
1271 | // .set_polarity = &evergreen_hpd_set_polarity, |
1329 | .set_polarity = &evergreen_hpd_set_polarity, |
1272 | }, |
1330 | }, |
1273 | .pm = { |
1331 | .pm = { |
1274 | // .misc = &evergreen_pm_misc, |
1332 | .misc = &evergreen_pm_misc, |
1275 | // .prepare = &evergreen_pm_prepare, |
1333 | .prepare = &evergreen_pm_prepare, |
1276 | // .finish = &evergreen_pm_finish, |
1334 | .finish = &evergreen_pm_finish, |
1277 | // .init_profile = &r600_pm_init_profile, |
1335 | .init_profile = &r600_pm_init_profile, |
1278 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1336 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1279 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1337 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1280 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1338 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1281 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1339 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1282 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1340 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1283 | // .get_pcie_lanes = &r600_get_pcie_lanes, |
1341 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1284 | // .set_pcie_lanes = &r600_set_pcie_lanes, |
1342 | .set_pcie_lanes = &r600_set_pcie_lanes, |
1285 | // .set_clock_gating = NULL, |
1343 | .set_clock_gating = NULL, |
1286 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
1344 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
- | 1345 | .get_temperature = &evergreen_get_temp, |
|
- | 1346 | }, |
|
- | 1347 | .dpm = { |
|
- | 1348 | .init = &cypress_dpm_init, |
|
- | 1349 | .setup_asic = &cypress_dpm_setup_asic, |
|
- | 1350 | .enable = &cypress_dpm_enable, |
|
- | 1351 | .late_enable = &rv770_dpm_late_enable, |
|
- | 1352 | .disable = &cypress_dpm_disable, |
|
- | 1353 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
|
- | 1354 | .set_power_state = &cypress_dpm_set_power_state, |
|
- | 1355 | .post_set_power_state = &r600_dpm_post_set_power_state, |
|
- | 1356 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
|
- | 1357 | .fini = &cypress_dpm_fini, |
|
- | 1358 | .get_sclk = &rv770_dpm_get_sclk, |
|
- | 1359 | .get_mclk = &rv770_dpm_get_mclk, |
|
- | 1360 | .print_power_state = &rv770_dpm_print_power_state, |
|
- | 1361 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
|
- | 1362 | .force_performance_level = &rv770_dpm_force_performance_level, |
|
- | 1363 | .vblank_too_short = &cypress_dpm_vblank_too_short, |
|
1287 | }, |
1364 | }, |
1288 | .pflip = { |
1365 | .pflip = { |
1289 | // .pre_page_flip = &evergreen_pre_page_flip, |
- | |
1290 | // .page_flip = &evergreen_page_flip, |
- | |
1291 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1292 | }, |
1366 | }, |
1293 | }; |
1367 | }; |
Line 1294... | Line 1368... | ||
1294 | 1368 | ||
1295 | static struct radeon_asic sumo_asic = { |
1369 | static struct radeon_asic sumo_asic = { |
1296 | .init = &evergreen_init, |
1370 | .init = &evergreen_init, |
1297 | // .fini = &evergreen_fini, |
1371 | // .fini = &evergreen_fini, |
1298 | // .suspend = &evergreen_suspend, |
1372 | // .suspend = &evergreen_suspend, |
1299 | // .resume = &evergreen_resume, |
1373 | // .resume = &evergreen_resume, |
1300 | .asic_reset = &evergreen_asic_reset, |
1374 | .asic_reset = &evergreen_asic_reset, |
1301 | // .vga_set_state = &r600_vga_set_state, |
1375 | // .vga_set_state = &r600_vga_set_state, |
1302 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1376 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1303 | .gui_idle = &r600_gui_idle, |
1377 | .gui_idle = &r600_gui_idle, |
1304 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1378 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1305 | .get_xclk = &r600_get_xclk, |
1379 | .get_xclk = &r600_get_xclk, |
1306 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1380 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1307 | .gart = { |
1381 | .gart = { |
1308 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1382 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1309 | .set_page = &rs600_gart_set_page, |
1383 | .set_page = &rs600_gart_set_page, |
1310 | }, |
1384 | }, |
1311 | .ring = { |
1385 | .ring = { |
1312 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
1313 | .ib_execute = &evergreen_ring_ib_execute, |
- | |
1314 | .emit_fence = &r600_fence_ring_emit, |
- | |
1315 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1316 | // .cs_parse = &evergreen_cs_parse, |
- | |
1317 | .ring_test = &r600_ring_test, |
- | |
1318 | .ib_test = &r600_ib_test, |
- | |
1319 | .is_lockup = &evergreen_gfx_is_lockup, |
- | |
1320 | }, |
1386 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1321 | [R600_RING_TYPE_DMA_INDEX] = { |
- | |
1322 | .ib_execute = &evergreen_dma_ring_ib_execute, |
- | |
1323 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1324 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1325 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1326 | .ring_test = &r600_dma_ring_test, |
- | |
1327 | .ib_test = &r600_dma_ib_test, |
- | |
1328 | .is_lockup = &evergreen_dma_is_lockup, |
- | |
1329 | }, |
1387 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, |
1330 | [R600_RING_TYPE_UVD_INDEX] = { |
- | |
1331 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1332 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1333 | // .emit_semaphore = &r600_uvd_semaphore_emit, |
- | |
1334 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1335 | // .ring_test = &r600_uvd_ring_test, |
- | |
1336 | // .ib_test = &r600_uvd_ib_test, |
- | |
1337 | // .is_lockup = &radeon_ring_test_lockup, |
- | |
1338 | } |
1388 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, |
1339 | }, |
1389 | }, |
1340 | .irq = { |
1390 | .irq = { |
1341 | .set = &evergreen_irq_set, |
1391 | .set = &evergreen_irq_set, |
1342 | .process = &evergreen_irq_process, |
1392 | .process = &evergreen_irq_process, |
1343 | }, |
1393 | }, |
1344 | .display = { |
1394 | .display = { |
1345 | .bandwidth_update = &evergreen_bandwidth_update, |
1395 | .bandwidth_update = &evergreen_bandwidth_update, |
1346 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1396 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1347 | .wait_for_vblank = &dce4_wait_for_vblank, |
1397 | .wait_for_vblank = &dce4_wait_for_vblank, |
1348 | // .set_backlight_level = &atombios_set_backlight_level, |
1398 | .set_backlight_level = &atombios_set_backlight_level, |
- | 1399 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 1400 | .hdmi_enable = &evergreen_hdmi_enable, |
|
1349 | // .get_backlight_level = &atombios_get_backlight_level, |
1401 | .hdmi_setmode = &evergreen_hdmi_setmode, |
1350 | }, |
1402 | }, |
1351 | .copy = { |
1403 | .copy = { |
1352 | .blit = &r600_copy_blit, |
1404 | .blit = &r600_copy_cpdma, |
1353 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1405 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1354 | .dma = &evergreen_copy_dma, |
1406 | .dma = &evergreen_copy_dma, |
1355 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1407 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1356 | .copy = &evergreen_copy_dma, |
1408 | .copy = &evergreen_copy_dma, |
Line 1359... | Line 1411... | ||
1359 | .surface = { |
1411 | .surface = { |
1360 | .set_reg = r600_set_surface_reg, |
1412 | .set_reg = r600_set_surface_reg, |
1361 | .clear_reg = r600_clear_surface_reg, |
1413 | .clear_reg = r600_clear_surface_reg, |
1362 | }, |
1414 | }, |
1363 | .hpd = { |
1415 | .hpd = { |
1364 | // .init = &evergreen_hpd_init, |
1416 | .init = &evergreen_hpd_init, |
1365 | // .fini = &evergreen_hpd_fini, |
1417 | .fini = &evergreen_hpd_fini, |
1366 | // .sense = &evergreen_hpd_sense, |
1418 | .sense = &evergreen_hpd_sense, |
1367 | // .set_polarity = &evergreen_hpd_set_polarity, |
1419 | .set_polarity = &evergreen_hpd_set_polarity, |
1368 | }, |
1420 | }, |
1369 | .pm = { |
1421 | .pm = { |
1370 | // .misc = &evergreen_pm_misc, |
1422 | .misc = &evergreen_pm_misc, |
1371 | // .prepare = &evergreen_pm_prepare, |
1423 | .prepare = &evergreen_pm_prepare, |
1372 | // .finish = &evergreen_pm_finish, |
1424 | .finish = &evergreen_pm_finish, |
1373 | // .init_profile = &sumo_pm_init_profile, |
1425 | .init_profile = &sumo_pm_init_profile, |
1374 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1426 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1375 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1427 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1376 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1428 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1377 | .get_memory_clock = NULL, |
1429 | .get_memory_clock = NULL, |
1378 | .set_memory_clock = NULL, |
1430 | .set_memory_clock = NULL, |
1379 | .get_pcie_lanes = NULL, |
1431 | .get_pcie_lanes = NULL, |
1380 | .set_pcie_lanes = NULL, |
1432 | .set_pcie_lanes = NULL, |
1381 | .set_clock_gating = NULL, |
1433 | .set_clock_gating = NULL, |
1382 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
1434 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
- | 1435 | .get_temperature = &sumo_get_temp, |
|
- | 1436 | }, |
|
- | 1437 | .dpm = { |
|
- | 1438 | .init = &sumo_dpm_init, |
|
- | 1439 | .setup_asic = &sumo_dpm_setup_asic, |
|
- | 1440 | .enable = &sumo_dpm_enable, |
|
- | 1441 | .late_enable = &sumo_dpm_late_enable, |
|
- | 1442 | .disable = &sumo_dpm_disable, |
|
- | 1443 | .pre_set_power_state = &sumo_dpm_pre_set_power_state, |
|
- | 1444 | .set_power_state = &sumo_dpm_set_power_state, |
|
- | 1445 | .post_set_power_state = &sumo_dpm_post_set_power_state, |
|
- | 1446 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, |
|
- | 1447 | .fini = &sumo_dpm_fini, |
|
- | 1448 | .get_sclk = &sumo_dpm_get_sclk, |
|
- | 1449 | .get_mclk = &sumo_dpm_get_mclk, |
|
- | 1450 | .print_power_state = &sumo_dpm_print_power_state, |
|
- | 1451 | .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, |
|
- | 1452 | .force_performance_level = &sumo_dpm_force_performance_level, |
|
1383 | }, |
1453 | }, |
1384 | .pflip = { |
1454 | .pflip = { |
1385 | // .pre_page_flip = &evergreen_pre_page_flip, |
1455 | // .pre_page_flip = &evergreen_pre_page_flip, |
1386 | // .page_flip = &evergreen_page_flip, |
1456 | // .page_flip = &evergreen_page_flip, |
1387 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1388 | }, |
1457 | }, |
1389 | }; |
1458 | }; |
Line 1390... | Line 1459... | ||
1390 | 1459 | ||
1391 | static struct radeon_asic btc_asic = { |
1460 | static struct radeon_asic btc_asic = { |
1392 | .init = &evergreen_init, |
1461 | .init = &evergreen_init, |
1393 | // .fini = &evergreen_fini, |
1462 | // .fini = &evergreen_fini, |
1394 | // .suspend = &evergreen_suspend, |
1463 | // .suspend = &evergreen_suspend, |
1395 | // .resume = &evergreen_resume, |
1464 | // .resume = &evergreen_resume, |
1396 | .asic_reset = &evergreen_asic_reset, |
1465 | .asic_reset = &evergreen_asic_reset, |
1397 | // .vga_set_state = &r600_vga_set_state, |
1466 | // .vga_set_state = &r600_vga_set_state, |
1398 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1467 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1399 | .gui_idle = &r600_gui_idle, |
1468 | .gui_idle = &r600_gui_idle, |
1400 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1469 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1401 | .get_xclk = &rv770_get_xclk, |
1470 | .get_xclk = &rv770_get_xclk, |
1402 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1471 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1403 | .gart = { |
1472 | .gart = { |
1404 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1473 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1405 | .set_page = &rs600_gart_set_page, |
1474 | .set_page = &rs600_gart_set_page, |
1406 | }, |
1475 | }, |
1407 | .ring = { |
1476 | .ring = { |
1408 | [RADEON_RING_TYPE_GFX_INDEX] = { |
- | |
1409 | .ib_execute = &evergreen_ring_ib_execute, |
- | |
1410 | .emit_fence = &r600_fence_ring_emit, |
- | |
1411 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1412 | // .cs_parse = &evergreen_cs_parse, |
- | |
1413 | .ring_test = &r600_ring_test, |
- | |
1414 | .ib_test = &r600_ib_test, |
- | |
1415 | .is_lockup = &evergreen_gfx_is_lockup, |
- | |
1416 | }, |
1477 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1417 | [R600_RING_TYPE_DMA_INDEX] = { |
- | |
1418 | .ib_execute = &evergreen_dma_ring_ib_execute, |
- | |
1419 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1420 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1421 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1422 | .ring_test = &r600_dma_ring_test, |
- | |
1423 | .ib_test = &r600_dma_ib_test, |
- | |
1424 | .is_lockup = &evergreen_dma_is_lockup, |
- | |
1425 | }, |
1478 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, |
1426 | [R600_RING_TYPE_UVD_INDEX] = { |
- | |
1427 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1428 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1429 | // .emit_semaphore = &r600_uvd_semaphore_emit, |
- | |
1430 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1431 | // .ring_test = &r600_uvd_ring_test, |
- | |
1432 | // .ib_test = &r600_uvd_ib_test, |
- | |
1433 | // .is_lockup = &radeon_ring_test_lockup, |
- | |
1434 | } |
1479 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, |
1435 | }, |
1480 | }, |
1436 | .irq = { |
1481 | .irq = { |
1437 | .set = &evergreen_irq_set, |
1482 | .set = &evergreen_irq_set, |
1438 | .process = &evergreen_irq_process, |
1483 | .process = &evergreen_irq_process, |
1439 | }, |
1484 | }, |
1440 | .display = { |
1485 | .display = { |
1441 | .bandwidth_update = &evergreen_bandwidth_update, |
1486 | .bandwidth_update = &evergreen_bandwidth_update, |
1442 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1487 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1443 | .wait_for_vblank = &dce4_wait_for_vblank, |
1488 | .wait_for_vblank = &dce4_wait_for_vblank, |
1444 | // .set_backlight_level = &atombios_set_backlight_level, |
1489 | .set_backlight_level = &atombios_set_backlight_level, |
- | 1490 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 1491 | .hdmi_enable = &evergreen_hdmi_enable, |
|
1445 | // .get_backlight_level = &atombios_get_backlight_level, |
1492 | .hdmi_setmode = &evergreen_hdmi_setmode, |
1446 | }, |
1493 | }, |
1447 | .copy = { |
1494 | .copy = { |
1448 | .blit = &r600_copy_blit, |
1495 | .blit = &r600_copy_cpdma, |
1449 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1496 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1450 | .dma = &evergreen_copy_dma, |
1497 | .dma = &evergreen_copy_dma, |
1451 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1498 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1452 | .copy = &evergreen_copy_dma, |
1499 | .copy = &evergreen_copy_dma, |
Line 1455... | Line 1502... | ||
1455 | .surface = { |
1502 | .surface = { |
1456 | .set_reg = r600_set_surface_reg, |
1503 | .set_reg = r600_set_surface_reg, |
1457 | .clear_reg = r600_clear_surface_reg, |
1504 | .clear_reg = r600_clear_surface_reg, |
1458 | }, |
1505 | }, |
1459 | .hpd = { |
1506 | .hpd = { |
1460 | // .init = &evergreen_hpd_init, |
1507 | .init = &evergreen_hpd_init, |
1461 | // .fini = &evergreen_hpd_fini, |
1508 | .fini = &evergreen_hpd_fini, |
1462 | // .sense = &evergreen_hpd_sense, |
1509 | .sense = &evergreen_hpd_sense, |
1463 | // .set_polarity = &evergreen_hpd_set_polarity, |
1510 | .set_polarity = &evergreen_hpd_set_polarity, |
1464 | }, |
1511 | }, |
1465 | .pm = { |
1512 | .pm = { |
1466 | // .misc = &evergreen_pm_misc, |
1513 | .misc = &evergreen_pm_misc, |
1467 | // .prepare = &evergreen_pm_prepare, |
1514 | .prepare = &evergreen_pm_prepare, |
1468 | // .finish = &evergreen_pm_finish, |
1515 | .finish = &evergreen_pm_finish, |
1469 | // .init_profile = &btc_pm_init_profile, |
1516 | .init_profile = &btc_pm_init_profile, |
1470 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1517 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1471 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1518 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1472 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1519 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1473 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1520 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1474 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1521 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1475 | .get_pcie_lanes = NULL, |
1522 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1476 | .set_pcie_lanes = NULL, |
1523 | .set_pcie_lanes = &r600_set_pcie_lanes, |
1477 | .set_clock_gating = NULL, |
1524 | .set_clock_gating = NULL, |
1478 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
1525 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
- | 1526 | .get_temperature = &evergreen_get_temp, |
|
- | 1527 | }, |
|
- | 1528 | .dpm = { |
|
- | 1529 | .init = &btc_dpm_init, |
|
- | 1530 | .setup_asic = &btc_dpm_setup_asic, |
|
- | 1531 | .enable = &btc_dpm_enable, |
|
- | 1532 | .late_enable = &rv770_dpm_late_enable, |
|
- | 1533 | .disable = &btc_dpm_disable, |
|
- | 1534 | .pre_set_power_state = &btc_dpm_pre_set_power_state, |
|
- | 1535 | .set_power_state = &btc_dpm_set_power_state, |
|
- | 1536 | .post_set_power_state = &btc_dpm_post_set_power_state, |
|
- | 1537 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
|
- | 1538 | .fini = &btc_dpm_fini, |
|
- | 1539 | .get_sclk = &btc_dpm_get_sclk, |
|
- | 1540 | .get_mclk = &btc_dpm_get_mclk, |
|
- | 1541 | .print_power_state = &rv770_dpm_print_power_state, |
|
- | 1542 | .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, |
|
- | 1543 | .force_performance_level = &rv770_dpm_force_performance_level, |
|
- | 1544 | .vblank_too_short = &btc_dpm_vblank_too_short, |
|
1479 | }, |
1545 | }, |
1480 | .pflip = { |
1546 | .pflip = { |
1481 | // .pre_page_flip = &evergreen_pre_page_flip, |
1547 | // .pre_page_flip = &evergreen_pre_page_flip, |
1482 | // .page_flip = &evergreen_page_flip, |
1548 | // .page_flip = &evergreen_page_flip, |
1483 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1484 | }, |
1549 | }, |
1485 | }; |
1550 | }; |
Line -... | Line 1551... | ||
- | 1551 | ||
- | 1552 | static struct radeon_asic_ring cayman_gfx_ring = { |
|
- | 1553 | .ib_execute = &cayman_ring_ib_execute, |
|
- | 1554 | .ib_parse = &evergreen_ib_parse, |
|
- | 1555 | .emit_fence = &cayman_fence_ring_emit, |
|
- | 1556 | .emit_semaphore = &r600_semaphore_ring_emit, |
|
- | 1557 | .cs_parse = &evergreen_cs_parse, |
|
- | 1558 | .ring_test = &r600_ring_test, |
|
- | 1559 | .ib_test = &r600_ib_test, |
|
- | 1560 | .is_lockup = &cayman_gfx_is_lockup, |
|
- | 1561 | .vm_flush = &cayman_vm_flush, |
|
- | 1562 | .get_rptr = &cayman_gfx_get_rptr, |
|
- | 1563 | .get_wptr = &cayman_gfx_get_wptr, |
|
- | 1564 | .set_wptr = &cayman_gfx_set_wptr, |
|
- | 1565 | }; |
|
- | 1566 | ||
- | 1567 | static struct radeon_asic_ring cayman_dma_ring = { |
|
- | 1568 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
- | 1569 | .ib_parse = &evergreen_dma_ib_parse, |
|
- | 1570 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
- | 1571 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
- | 1572 | .cs_parse = &evergreen_dma_cs_parse, |
|
- | 1573 | .ring_test = &r600_dma_ring_test, |
|
- | 1574 | .ib_test = &r600_dma_ib_test, |
|
- | 1575 | .is_lockup = &cayman_dma_is_lockup, |
|
- | 1576 | .vm_flush = &cayman_dma_vm_flush, |
|
- | 1577 | .get_rptr = &cayman_dma_get_rptr, |
|
- | 1578 | .get_wptr = &cayman_dma_get_wptr, |
|
- | 1579 | .set_wptr = &cayman_dma_set_wptr |
|
- | 1580 | }; |
|
- | 1581 | ||
- | 1582 | static struct radeon_asic_ring cayman_uvd_ring = { |
|
- | 1583 | .ib_execute = &uvd_v1_0_ib_execute, |
|
- | 1584 | .emit_fence = &uvd_v2_2_fence_emit, |
|
- | 1585 | .emit_semaphore = &uvd_v3_1_semaphore_emit, |
|
- | 1586 | .cs_parse = &radeon_uvd_cs_parse, |
|
- | 1587 | .ring_test = &uvd_v1_0_ring_test, |
|
- | 1588 | .ib_test = &uvd_v1_0_ib_test, |
|
- | 1589 | .is_lockup = &radeon_ring_test_lockup, |
|
- | 1590 | .get_rptr = &uvd_v1_0_get_rptr, |
|
- | 1591 | .get_wptr = &uvd_v1_0_get_wptr, |
|
- | 1592 | .set_wptr = &uvd_v1_0_set_wptr, |
|
- | 1593 | }; |
|
1486 | 1594 | ||
1487 | static struct radeon_asic cayman_asic = { |
1595 | static struct radeon_asic cayman_asic = { |
1488 | .init = &cayman_init, |
1596 | .init = &cayman_init, |
1489 | // .fini = &cayman_fini, |
1597 | // .fini = &cayman_fini, |
1490 | // .suspend = &cayman_suspend, |
1598 | // .suspend = &cayman_suspend, |
1491 | // .resume = &cayman_resume, |
1599 | // .resume = &cayman_resume, |
1492 | .asic_reset = &cayman_asic_reset, |
1600 | .asic_reset = &cayman_asic_reset, |
1493 | // .vga_set_state = &r600_vga_set_state, |
1601 | // .vga_set_state = &r600_vga_set_state, |
1494 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1602 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1495 | .gui_idle = &r600_gui_idle, |
1603 | .gui_idle = &r600_gui_idle, |
1496 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1604 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1497 | .get_xclk = &rv770_get_xclk, |
1605 | .get_xclk = &rv770_get_xclk, |
1498 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1606 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
Line 1501... | Line 1609... | ||
1501 | .set_page = &rs600_gart_set_page, |
1609 | .set_page = &rs600_gart_set_page, |
1502 | }, |
1610 | }, |
1503 | .vm = { |
1611 | .vm = { |
1504 | .init = &cayman_vm_init, |
1612 | .init = &cayman_vm_init, |
1505 | .fini = &cayman_vm_fini, |
1613 | .fini = &cayman_vm_fini, |
- | 1614 | .copy_pages = &cayman_dma_vm_copy_pages, |
|
1506 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
1615 | .write_pages = &cayman_dma_vm_write_pages, |
1507 | .set_page = &cayman_vm_set_page, |
1616 | .set_pages = &cayman_dma_vm_set_pages, |
- | 1617 | .pad_ib = &cayman_dma_vm_pad_ib, |
|
1508 | }, |
1618 | }, |
1509 | .ring = { |
1619 | .ring = { |
1510 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1620 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1511 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1512 | // .ib_parse = &evergreen_ib_parse, |
- | |
1513 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1514 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1515 | // .cs_parse = &evergreen_cs_parse, |
- | |
1516 | .ring_test = &r600_ring_test, |
- | |
1517 | .ib_test = &r600_ib_test, |
- | |
1518 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1519 | .vm_flush = &cayman_vm_flush, |
- | |
1520 | }, |
- | |
1521 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
1621 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, |
1522 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1523 | // .ib_parse = &evergreen_ib_parse, |
- | |
1524 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1525 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1526 | // .cs_parse = &evergreen_cs_parse, |
- | |
1527 | .ring_test = &r600_ring_test, |
- | |
1528 | .ib_test = &r600_ib_test, |
- | |
1529 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1530 | .vm_flush = &cayman_vm_flush, |
- | |
1531 | }, |
- | |
1532 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1622 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, |
1533 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1534 | // .ib_parse = &evergreen_ib_parse, |
- | |
1535 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1536 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1537 | // .cs_parse = &evergreen_cs_parse, |
- | |
1538 | .ring_test = &r600_ring_test, |
- | |
1539 | .ib_test = &r600_ib_test, |
- | |
1540 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1541 | .vm_flush = &cayman_vm_flush, |
- | |
1542 | }, |
- | |
1543 | [R600_RING_TYPE_DMA_INDEX] = { |
1623 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, |
1544 | .ib_execute = &cayman_dma_ring_ib_execute, |
- | |
1545 | // .ib_parse = &evergreen_dma_ib_parse, |
- | |
1546 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1547 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1548 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1549 | .ring_test = &r600_dma_ring_test, |
- | |
1550 | .ib_test = &r600_dma_ib_test, |
- | |
1551 | .is_lockup = &cayman_dma_is_lockup, |
- | |
1552 | .vm_flush = &cayman_dma_vm_flush, |
- | |
1553 | }, |
- | |
1554 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
1624 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, |
1555 | .ib_execute = &cayman_dma_ring_ib_execute, |
- | |
1556 | // .ib_parse = &evergreen_dma_ib_parse, |
- | |
1557 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1558 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1559 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1560 | .ring_test = &r600_dma_ring_test, |
- | |
1561 | .ib_test = &r600_dma_ib_test, |
- | |
1562 | .is_lockup = &cayman_dma_is_lockup, |
- | |
1563 | .vm_flush = &cayman_dma_vm_flush, |
- | |
1564 | }, |
- | |
1565 | [R600_RING_TYPE_UVD_INDEX] = { |
1625 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, |
1566 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1567 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1568 | // .emit_semaphore = &cayman_uvd_semaphore_emit, |
- | |
1569 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1570 | // .ring_test = &r600_uvd_ring_test, |
- | |
1571 | // .ib_test = &r600_uvd_ib_test, |
- | |
1572 | // .is_lockup = &radeon_ring_test_lockup, |
- | |
1573 | } |
- | |
1574 | }, |
1626 | }, |
1575 | .irq = { |
1627 | .irq = { |
1576 | .set = &evergreen_irq_set, |
1628 | .set = &evergreen_irq_set, |
1577 | .process = &evergreen_irq_process, |
1629 | .process = &evergreen_irq_process, |
1578 | }, |
1630 | }, |
1579 | .display = { |
1631 | .display = { |
1580 | .bandwidth_update = &evergreen_bandwidth_update, |
1632 | .bandwidth_update = &evergreen_bandwidth_update, |
1581 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1633 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1582 | .wait_for_vblank = &dce4_wait_for_vblank, |
1634 | .wait_for_vblank = &dce4_wait_for_vblank, |
1583 | // .set_backlight_level = &atombios_set_backlight_level, |
1635 | .set_backlight_level = &atombios_set_backlight_level, |
1584 | // .get_backlight_level = &atombios_get_backlight_level, |
1636 | .get_backlight_level = &atombios_get_backlight_level, |
- | 1637 | .hdmi_enable = &evergreen_hdmi_enable, |
|
- | 1638 | .hdmi_setmode = &evergreen_hdmi_setmode, |
|
1585 | }, |
1639 | }, |
1586 | .copy = { |
1640 | .copy = { |
1587 | .blit = &r600_copy_blit, |
1641 | .blit = &r600_copy_cpdma, |
1588 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1642 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1589 | .dma = &evergreen_copy_dma, |
1643 | .dma = &evergreen_copy_dma, |
1590 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1644 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1591 | .copy = &evergreen_copy_dma, |
1645 | .copy = &evergreen_copy_dma, |
1592 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1646 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
Line 1594... | Line 1648... | ||
1594 | .surface = { |
1648 | .surface = { |
1595 | .set_reg = r600_set_surface_reg, |
1649 | .set_reg = r600_set_surface_reg, |
1596 | .clear_reg = r600_clear_surface_reg, |
1650 | .clear_reg = r600_clear_surface_reg, |
1597 | }, |
1651 | }, |
1598 | .hpd = { |
1652 | .hpd = { |
1599 | // .init = &evergreen_hpd_init, |
1653 | .init = &evergreen_hpd_init, |
1600 | // .fini = &evergreen_hpd_fini, |
1654 | .fini = &evergreen_hpd_fini, |
1601 | // .sense = &evergreen_hpd_sense, |
1655 | .sense = &evergreen_hpd_sense, |
1602 | // .set_polarity = &evergreen_hpd_set_polarity, |
1656 | .set_polarity = &evergreen_hpd_set_polarity, |
1603 | }, |
1657 | }, |
1604 | .pm = { |
1658 | .pm = { |
1605 | // .misc = &evergreen_pm_misc, |
1659 | .misc = &evergreen_pm_misc, |
1606 | // .prepare = &evergreen_pm_prepare, |
1660 | .prepare = &evergreen_pm_prepare, |
1607 | // .finish = &evergreen_pm_finish, |
1661 | .finish = &evergreen_pm_finish, |
1608 | // .init_profile = &btc_pm_init_profile, |
1662 | .init_profile = &btc_pm_init_profile, |
1609 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1663 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1610 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1664 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1611 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1665 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1612 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
1666 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1613 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
1667 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1614 | .get_pcie_lanes = NULL, |
1668 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1615 | .set_pcie_lanes = NULL, |
1669 | .set_pcie_lanes = &r600_set_pcie_lanes, |
1616 | .set_clock_gating = NULL, |
1670 | .set_clock_gating = NULL, |
1617 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
1671 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
- | 1672 | .get_temperature = &evergreen_get_temp, |
|
- | 1673 | }, |
|
- | 1674 | .dpm = { |
|
- | 1675 | .init = &ni_dpm_init, |
|
- | 1676 | .setup_asic = &ni_dpm_setup_asic, |
|
- | 1677 | .enable = &ni_dpm_enable, |
|
- | 1678 | .late_enable = &rv770_dpm_late_enable, |
|
- | 1679 | .disable = &ni_dpm_disable, |
|
- | 1680 | .pre_set_power_state = &ni_dpm_pre_set_power_state, |
|
- | 1681 | .set_power_state = &ni_dpm_set_power_state, |
|
- | 1682 | .post_set_power_state = &ni_dpm_post_set_power_state, |
|
- | 1683 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
|
- | 1684 | .fini = &ni_dpm_fini, |
|
- | 1685 | .get_sclk = &ni_dpm_get_sclk, |
|
- | 1686 | .get_mclk = &ni_dpm_get_mclk, |
|
- | 1687 | .print_power_state = &ni_dpm_print_power_state, |
|
- | 1688 | .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, |
|
- | 1689 | .force_performance_level = &ni_dpm_force_performance_level, |
|
- | 1690 | .vblank_too_short = &ni_dpm_vblank_too_short, |
|
1618 | }, |
1691 | }, |
1619 | .pflip = { |
1692 | .pflip = { |
1620 | // .pre_page_flip = &evergreen_pre_page_flip, |
1693 | // .pre_page_flip = &evergreen_pre_page_flip, |
1621 | // .page_flip = &evergreen_page_flip, |
1694 | // .page_flip = &evergreen_page_flip, |
1622 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1623 | }, |
1695 | }, |
1624 | }; |
1696 | }; |
Line 1625... | Line 1697... | ||
1625 | 1697 | ||
1626 | static struct radeon_asic trinity_asic = { |
1698 | static struct radeon_asic trinity_asic = { |
1627 | .init = &cayman_init, |
1699 | .init = &cayman_init, |
1628 | // .fini = &cayman_fini, |
1700 | // .fini = &cayman_fini, |
1629 | // .suspend = &cayman_suspend, |
1701 | // .suspend = &cayman_suspend, |
1630 | // .resume = &cayman_resume, |
1702 | // .resume = &cayman_resume, |
1631 | .asic_reset = &cayman_asic_reset, |
1703 | .asic_reset = &cayman_asic_reset, |
1632 | // .vga_set_state = &r600_vga_set_state, |
1704 | // .vga_set_state = &r600_vga_set_state, |
1633 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1705 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1634 | .gui_idle = &r600_gui_idle, |
1706 | .gui_idle = &r600_gui_idle, |
1635 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1707 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1636 | .get_xclk = &r600_get_xclk, |
1708 | .get_xclk = &r600_get_xclk, |
1637 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
1709 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
Line 1640... | Line 1712... | ||
1640 | .set_page = &rs600_gart_set_page, |
1712 | .set_page = &rs600_gart_set_page, |
1641 | }, |
1713 | }, |
1642 | .vm = { |
1714 | .vm = { |
1643 | .init = &cayman_vm_init, |
1715 | .init = &cayman_vm_init, |
1644 | .fini = &cayman_vm_fini, |
1716 | .fini = &cayman_vm_fini, |
- | 1717 | .copy_pages = &cayman_dma_vm_copy_pages, |
|
1645 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
1718 | .write_pages = &cayman_dma_vm_write_pages, |
1646 | .set_page = &cayman_vm_set_page, |
1719 | .set_pages = &cayman_dma_vm_set_pages, |
- | 1720 | .pad_ib = &cayman_dma_vm_pad_ib, |
|
1647 | }, |
1721 | }, |
1648 | .ring = { |
1722 | .ring = { |
1649 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1723 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1650 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1651 | // .ib_parse = &evergreen_ib_parse, |
- | |
1652 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1653 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1654 | // .cs_parse = &evergreen_cs_parse, |
- | |
1655 | .ring_test = &r600_ring_test, |
- | |
1656 | .ib_test = &r600_ib_test, |
- | |
1657 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1658 | .vm_flush = &cayman_vm_flush, |
- | |
1659 | }, |
- | |
1660 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
1724 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, |
1661 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1662 | // .ib_parse = &evergreen_ib_parse, |
- | |
1663 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1664 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1665 | // .cs_parse = &evergreen_cs_parse, |
- | |
1666 | .ring_test = &r600_ring_test, |
- | |
1667 | .ib_test = &r600_ib_test, |
- | |
1668 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1669 | .vm_flush = &cayman_vm_flush, |
- | |
1670 | }, |
- | |
1671 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1725 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, |
1672 | .ib_execute = &cayman_ring_ib_execute, |
- | |
1673 | // .ib_parse = &evergreen_ib_parse, |
- | |
1674 | .emit_fence = &cayman_fence_ring_emit, |
- | |
1675 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1676 | // .cs_parse = &evergreen_cs_parse, |
- | |
1677 | .ring_test = &r600_ring_test, |
- | |
1678 | .ib_test = &r600_ib_test, |
- | |
1679 | .is_lockup = &cayman_gfx_is_lockup, |
- | |
1680 | .vm_flush = &cayman_vm_flush, |
- | |
1681 | }, |
- | |
1682 | [R600_RING_TYPE_DMA_INDEX] = { |
1726 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, |
1683 | .ib_execute = &cayman_dma_ring_ib_execute, |
- | |
1684 | // .ib_parse = &evergreen_dma_ib_parse, |
- | |
1685 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1686 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1687 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1688 | .ring_test = &r600_dma_ring_test, |
- | |
1689 | .ib_test = &r600_dma_ib_test, |
- | |
1690 | .is_lockup = &cayman_dma_is_lockup, |
- | |
1691 | .vm_flush = &cayman_dma_vm_flush, |
- | |
1692 | }, |
- | |
1693 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
1727 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, |
1694 | .ib_execute = &cayman_dma_ring_ib_execute, |
- | |
1695 | // .ib_parse = &evergreen_dma_ib_parse, |
- | |
1696 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1697 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
- | |
1698 | // .cs_parse = &evergreen_dma_cs_parse, |
- | |
1699 | .ring_test = &r600_dma_ring_test, |
- | |
1700 | .ib_test = &r600_dma_ib_test, |
- | |
1701 | .is_lockup = &cayman_dma_is_lockup, |
- | |
1702 | .vm_flush = &cayman_dma_vm_flush, |
- | |
1703 | }, |
- | |
1704 | [R600_RING_TYPE_UVD_INDEX] = { |
1728 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, |
1705 | // .ib_execute = &r600_uvd_ib_execute, |
- | |
1706 | // .emit_fence = &r600_uvd_fence_emit, |
- | |
1707 | // .emit_semaphore = &cayman_uvd_semaphore_emit, |
- | |
1708 | // .cs_parse = &radeon_uvd_cs_parse, |
- | |
1709 | // .ring_test = &r600_uvd_ring_test, |
- | |
1710 | // .ib_test = &r600_uvd_ib_test, |
- | |
1711 | // .is_lockup = &radeon_ring_test_lockup, |
- | |
1712 | } |
- | |
1713 | }, |
1729 | }, |
1714 | .irq = { |
1730 | .irq = { |
1715 | .set = &evergreen_irq_set, |
1731 | .set = &evergreen_irq_set, |
1716 | .process = &evergreen_irq_process, |
1732 | .process = &evergreen_irq_process, |
1717 | }, |
1733 | }, |
1718 | .display = { |
1734 | .display = { |
1719 | .bandwidth_update = &dce6_bandwidth_update, |
1735 | .bandwidth_update = &dce6_bandwidth_update, |
1720 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1736 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1721 | .wait_for_vblank = &dce4_wait_for_vblank, |
1737 | .wait_for_vblank = &dce4_wait_for_vblank, |
1722 | // .set_backlight_level = &atombios_set_backlight_level, |
1738 | .set_backlight_level = &atombios_set_backlight_level, |
1723 | // .get_backlight_level = &atombios_get_backlight_level, |
1739 | .get_backlight_level = &atombios_get_backlight_level, |
- | 1740 | .hdmi_enable = &evergreen_hdmi_enable, |
|
- | 1741 | .hdmi_setmode = &evergreen_hdmi_setmode, |
|
1724 | }, |
1742 | }, |
1725 | .copy = { |
1743 | .copy = { |
1726 | .blit = &r600_copy_blit, |
1744 | .blit = &r600_copy_cpdma, |
1727 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1745 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1728 | .dma = &evergreen_copy_dma, |
1746 | .dma = &evergreen_copy_dma, |
1729 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1747 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1730 | .copy = &evergreen_copy_dma, |
1748 | .copy = &evergreen_copy_dma, |
1731 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1749 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
Line 1733... | Line 1751... | ||
1733 | .surface = { |
1751 | .surface = { |
1734 | .set_reg = r600_set_surface_reg, |
1752 | .set_reg = r600_set_surface_reg, |
1735 | .clear_reg = r600_clear_surface_reg, |
1753 | .clear_reg = r600_clear_surface_reg, |
1736 | }, |
1754 | }, |
1737 | .hpd = { |
1755 | .hpd = { |
1738 | // .init = &evergreen_hpd_init, |
1756 | .init = &evergreen_hpd_init, |
1739 | // .fini = &evergreen_hpd_fini, |
1757 | .fini = &evergreen_hpd_fini, |
1740 | // .sense = &evergreen_hpd_sense, |
1758 | .sense = &evergreen_hpd_sense, |
1741 | // .set_polarity = &evergreen_hpd_set_polarity, |
1759 | .set_polarity = &evergreen_hpd_set_polarity, |
1742 | }, |
1760 | }, |
1743 | .pm = { |
1761 | .pm = { |
1744 | // .misc = &evergreen_pm_misc, |
1762 | .misc = &evergreen_pm_misc, |
1745 | // .prepare = &evergreen_pm_prepare, |
1763 | .prepare = &evergreen_pm_prepare, |
1746 | // .finish = &evergreen_pm_finish, |
1764 | .finish = &evergreen_pm_finish, |
1747 | // .init_profile = &sumo_pm_init_profile, |
1765 | .init_profile = &sumo_pm_init_profile, |
1748 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
1766 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1749 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
1767 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1750 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
1768 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1751 | .get_memory_clock = NULL, |
1769 | .get_memory_clock = NULL, |
1752 | .set_memory_clock = NULL, |
1770 | .set_memory_clock = NULL, |
1753 | .get_pcie_lanes = NULL, |
1771 | .get_pcie_lanes = NULL, |
1754 | .set_pcie_lanes = NULL, |
1772 | .set_pcie_lanes = NULL, |
1755 | .set_clock_gating = NULL, |
1773 | .set_clock_gating = NULL, |
1756 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
1774 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
- | 1775 | .get_temperature = &tn_get_temp, |
|
- | 1776 | }, |
|
- | 1777 | .dpm = { |
|
- | 1778 | .init = &trinity_dpm_init, |
|
- | 1779 | .setup_asic = &trinity_dpm_setup_asic, |
|
- | 1780 | .enable = &trinity_dpm_enable, |
|
- | 1781 | .late_enable = &trinity_dpm_late_enable, |
|
- | 1782 | .disable = &trinity_dpm_disable, |
|
- | 1783 | .pre_set_power_state = &trinity_dpm_pre_set_power_state, |
|
- | 1784 | .set_power_state = &trinity_dpm_set_power_state, |
|
- | 1785 | .post_set_power_state = &trinity_dpm_post_set_power_state, |
|
- | 1786 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, |
|
- | 1787 | .fini = &trinity_dpm_fini, |
|
- | 1788 | .get_sclk = &trinity_dpm_get_sclk, |
|
- | 1789 | .get_mclk = &trinity_dpm_get_mclk, |
|
- | 1790 | .print_power_state = &trinity_dpm_print_power_state, |
|
- | 1791 | .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, |
|
- | 1792 | .force_performance_level = &trinity_dpm_force_performance_level, |
|
- | 1793 | .enable_bapm = &trinity_dpm_enable_bapm, |
|
1757 | }, |
1794 | }, |
1758 | .pflip = { |
1795 | .pflip = { |
1759 | // .pre_page_flip = &evergreen_pre_page_flip, |
1796 | // .pre_page_flip = &evergreen_pre_page_flip, |
1760 | // .page_flip = &evergreen_page_flip, |
1797 | // .page_flip = &evergreen_page_flip, |
1761 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1762 | }, |
1798 | }, |
1763 | }; |
1799 | }; |
Line -... | Line 1800... | ||
- | 1800 | ||
- | 1801 | static struct radeon_asic_ring si_gfx_ring = { |
|
- | 1802 | .ib_execute = &si_ring_ib_execute, |
|
- | 1803 | .ib_parse = &si_ib_parse, |
|
- | 1804 | .emit_fence = &si_fence_ring_emit, |
|
- | 1805 | .emit_semaphore = &r600_semaphore_ring_emit, |
|
- | 1806 | .cs_parse = NULL, |
|
- | 1807 | .ring_test = &r600_ring_test, |
|
- | 1808 | .ib_test = &r600_ib_test, |
|
- | 1809 | .is_lockup = &si_gfx_is_lockup, |
|
- | 1810 | .vm_flush = &si_vm_flush, |
|
- | 1811 | .get_rptr = &cayman_gfx_get_rptr, |
|
- | 1812 | .get_wptr = &cayman_gfx_get_wptr, |
|
- | 1813 | .set_wptr = &cayman_gfx_set_wptr, |
|
- | 1814 | }; |
|
- | 1815 | ||
- | 1816 | static struct radeon_asic_ring si_dma_ring = { |
|
- | 1817 | .ib_execute = &cayman_dma_ring_ib_execute, |
|
- | 1818 | .ib_parse = &evergreen_dma_ib_parse, |
|
- | 1819 | .emit_fence = &evergreen_dma_fence_ring_emit, |
|
- | 1820 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
|
- | 1821 | .cs_parse = NULL, |
|
- | 1822 | .ring_test = &r600_dma_ring_test, |
|
- | 1823 | .ib_test = &r600_dma_ib_test, |
|
- | 1824 | .is_lockup = &si_dma_is_lockup, |
|
- | 1825 | .vm_flush = &si_dma_vm_flush, |
|
- | 1826 | .get_rptr = &cayman_dma_get_rptr, |
|
- | 1827 | .get_wptr = &cayman_dma_get_wptr, |
|
- | 1828 | .set_wptr = &cayman_dma_set_wptr, |
|
- | 1829 | }; |
|
1764 | 1830 | ||
1765 | static struct radeon_asic si_asic = { |
1831 | static struct radeon_asic si_asic = { |
1766 | .init = &si_init, |
1832 | .init = &si_init, |
1767 | // .fini = &si_fini, |
1833 | // .fini = &si_fini, |
1768 | // .suspend = &si_suspend, |
1834 | // .suspend = &si_suspend, |
1769 | // .resume = &si_resume, |
1835 | // .resume = &si_resume, |
1770 | .asic_reset = &si_asic_reset, |
1836 | .asic_reset = &si_asic_reset, |
1771 | // .vga_set_state = &r600_vga_set_state, |
1837 | // .vga_set_state = &r600_vga_set_state, |
1772 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
1838 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
1773 | .gui_idle = &r600_gui_idle, |
1839 | .gui_idle = &r600_gui_idle, |
1774 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1840 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1775 | .get_xclk = &si_get_xclk, |
1841 | .get_xclk = &si_get_xclk, |
1776 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
1842 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
Line 1779... | Line 1845... | ||
1779 | .set_page = &rs600_gart_set_page, |
1845 | .set_page = &rs600_gart_set_page, |
1780 | }, |
1846 | }, |
1781 | .vm = { |
1847 | .vm = { |
1782 | .init = &si_vm_init, |
1848 | .init = &si_vm_init, |
1783 | .fini = &si_vm_fini, |
1849 | .fini = &si_vm_fini, |
- | 1850 | .copy_pages = &si_dma_vm_copy_pages, |
|
1784 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
1851 | .write_pages = &si_dma_vm_write_pages, |
1785 | .set_page = &si_vm_set_page, |
1852 | .set_pages = &si_dma_vm_set_pages, |
- | 1853 | .pad_ib = &cayman_dma_vm_pad_ib, |
|
1786 | }, |
1854 | }, |
1787 | .ring = { |
1855 | .ring = { |
1788 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1856 | [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, |
1789 | .ib_execute = &si_ring_ib_execute, |
1857 | [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, |
1790 | // .ib_parse = &si_ib_parse, |
1858 | [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, |
1791 | .emit_fence = &si_fence_ring_emit, |
1859 | [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, |
1792 | .emit_semaphore = &r600_semaphore_ring_emit, |
1860 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, |
1793 | .cs_parse = NULL, |
- | |
1794 | .ring_test = &r600_ring_test, |
1861 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, |
1795 | .ib_test = &r600_ib_test, |
- | |
1796 | .is_lockup = &si_gfx_is_lockup, |
- | |
1797 | .vm_flush = &si_vm_flush, |
- | |
1798 | }, |
1862 | }, |
1799 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
- | |
1800 | .ib_execute = &si_ring_ib_execute, |
- | |
1801 | // .ib_parse = &si_ib_parse, |
- | |
1802 | .emit_fence = &si_fence_ring_emit, |
- | |
1803 | .emit_semaphore = &r600_semaphore_ring_emit, |
- | |
1804 | .cs_parse = NULL, |
1863 | .irq = { |
1805 | .ring_test = &r600_ring_test, |
- | |
1806 | .ib_test = &r600_ib_test, |
1864 | .set = &si_irq_set, |
1807 | .is_lockup = &si_gfx_is_lockup, |
1865 | .process = &si_irq_process, |
1808 | .vm_flush = &si_vm_flush, |
- | |
1809 | }, |
1866 | }, |
1810 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1867 | .display = { |
1811 | .ib_execute = &si_ring_ib_execute, |
1868 | .bandwidth_update = &dce6_bandwidth_update, |
1812 | // .ib_parse = &si_ib_parse, |
- | |
1813 | .emit_fence = &si_fence_ring_emit, |
1869 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1814 | .emit_semaphore = &r600_semaphore_ring_emit, |
1870 | .wait_for_vblank = &dce4_wait_for_vblank, |
1815 | .cs_parse = NULL, |
- | |
1816 | .ring_test = &r600_ring_test, |
1871 | .set_backlight_level = &atombios_set_backlight_level, |
1817 | .ib_test = &r600_ib_test, |
1872 | .get_backlight_level = &atombios_get_backlight_level, |
1818 | .is_lockup = &si_gfx_is_lockup, |
1873 | .hdmi_enable = &evergreen_hdmi_enable, |
1819 | .vm_flush = &si_vm_flush, |
1874 | .hdmi_setmode = &evergreen_hdmi_setmode, |
1820 | }, |
1875 | }, |
1821 | [R600_RING_TYPE_DMA_INDEX] = { |
1876 | .copy = { |
1822 | .ib_execute = &cayman_dma_ring_ib_execute, |
- | |
1823 | // .ib_parse = &evergreen_dma_ib_parse, |
1877 | .blit = &r600_copy_cpdma, |
1824 | .emit_fence = &evergreen_dma_fence_ring_emit, |
- | |
1825 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
1878 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1826 | .cs_parse = NULL, |
1879 | .dma = &si_copy_dma, |
1827 | .ring_test = &r600_dma_ring_test, |
1880 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1828 | .ib_test = &r600_dma_ib_test, |
- | |
1829 | .is_lockup = &si_dma_is_lockup, |
1881 | .copy = &si_copy_dma, |
1830 | .vm_flush = &si_dma_vm_flush, |
1882 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1831 | }, |
1883 | }, |
- | 1884 | .surface = { |
|
- | 1885 | .set_reg = r600_set_surface_reg, |
|
- | 1886 | .clear_reg = r600_clear_surface_reg, |
|
- | 1887 | }, |
|
- | 1888 | .hpd = { |
|
- | 1889 | .init = &evergreen_hpd_init, |
|
- | 1890 | .fini = &evergreen_hpd_fini, |
|
- | 1891 | .sense = &evergreen_hpd_sense, |
|
- | 1892 | .set_polarity = &evergreen_hpd_set_polarity, |
|
- | 1893 | }, |
|
- | 1894 | .pm = { |
|
- | 1895 | .misc = &evergreen_pm_misc, |
|
- | 1896 | .prepare = &evergreen_pm_prepare, |
|
- | 1897 | .finish = &evergreen_pm_finish, |
|
- | 1898 | .init_profile = &sumo_pm_init_profile, |
|
- | 1899 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
|
- | 1900 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
- | 1901 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
- | 1902 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
- | 1903 | .set_memory_clock = &radeon_atom_set_memory_clock, |
|
- | 1904 | .get_pcie_lanes = &r600_get_pcie_lanes, |
|
- | 1905 | .set_pcie_lanes = &r600_set_pcie_lanes, |
|
- | 1906 | .set_clock_gating = NULL, |
|
- | 1907 | .set_uvd_clocks = &si_set_uvd_clocks, |
|
- | 1908 | .get_temperature = &si_get_temp, |
|
- | 1909 | }, |
|
- | 1910 | .dpm = { |
|
- | 1911 | .init = &si_dpm_init, |
|
1832 | [CAYMAN_RING_TYPE_DMA1_INDEX] = { |
1912 | .setup_asic = &si_dpm_setup_asic, |
- | 1913 | .enable = &si_dpm_enable, |
|
- | 1914 | .late_enable = &si_dpm_late_enable, |
|
- | 1915 | .disable = &si_dpm_disable, |
|
- | 1916 | .pre_set_power_state = &si_dpm_pre_set_power_state, |
|
- | 1917 | .set_power_state = &si_dpm_set_power_state, |
|
- | 1918 | .post_set_power_state = &si_dpm_post_set_power_state, |
|
- | 1919 | .display_configuration_changed = &si_dpm_display_configuration_changed, |
|
- | 1920 | .fini = &si_dpm_fini, |
|
- | 1921 | .get_sclk = &ni_dpm_get_sclk, |
|
- | 1922 | .get_mclk = &ni_dpm_get_mclk, |
|
- | 1923 | .print_power_state = &ni_dpm_print_power_state, |
|
- | 1924 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, |
|
- | 1925 | .force_performance_level = &si_dpm_force_performance_level, |
|
- | 1926 | .vblank_too_short = &ni_dpm_vblank_too_short, |
|
- | 1927 | }, |
|
- | 1928 | .pflip = { |
|
- | 1929 | // .pre_page_flip = &evergreen_pre_page_flip, |
|
- | 1930 | // .page_flip = &evergreen_page_flip, |
|
- | 1931 | }, |
|
- | 1932 | }; |
|
- | 1933 | ||
- | 1934 | static struct radeon_asic_ring ci_gfx_ring = { |
|
1833 | .ib_execute = &cayman_dma_ring_ib_execute, |
1935 | .ib_execute = &cik_ring_ib_execute, |
1834 | // .ib_parse = &evergreen_dma_ib_parse, |
1936 | .ib_parse = &cik_ib_parse, |
1835 | .emit_fence = &evergreen_dma_fence_ring_emit, |
1937 | .emit_fence = &cik_fence_gfx_ring_emit, |
1836 | .emit_semaphore = &r600_dma_semaphore_ring_emit, |
1938 | .emit_semaphore = &cik_semaphore_ring_emit, |
1837 | .cs_parse = NULL, |
1939 | .cs_parse = NULL, |
- | 1940 | .ring_test = &cik_ring_test, |
|
- | 1941 | .ib_test = &cik_ib_test, |
|
- | 1942 | .is_lockup = &cik_gfx_is_lockup, |
|
- | 1943 | .vm_flush = &cik_vm_flush, |
|
- | 1944 | .get_rptr = &cik_gfx_get_rptr, |
|
- | 1945 | .get_wptr = &cik_gfx_get_wptr, |
|
- | 1946 | .set_wptr = &cik_gfx_set_wptr, |
|
- | 1947 | }; |
|
- | 1948 | ||
- | 1949 | static struct radeon_asic_ring ci_cp_ring = { |
|
- | 1950 | .ib_execute = &cik_ring_ib_execute, |
|
- | 1951 | .ib_parse = &cik_ib_parse, |
|
- | 1952 | .emit_fence = &cik_fence_compute_ring_emit, |
|
- | 1953 | .emit_semaphore = &cik_semaphore_ring_emit, |
|
- | 1954 | .cs_parse = NULL, |
|
- | 1955 | .ring_test = &cik_ring_test, |
|
- | 1956 | .ib_test = &cik_ib_test, |
|
- | 1957 | .is_lockup = &cik_gfx_is_lockup, |
|
- | 1958 | .vm_flush = &cik_vm_flush, |
|
- | 1959 | .get_rptr = &cik_compute_get_rptr, |
|
- | 1960 | .get_wptr = &cik_compute_get_wptr, |
|
- | 1961 | .set_wptr = &cik_compute_set_wptr, |
|
- | 1962 | }; |
|
- | 1963 | ||
- | 1964 | static struct radeon_asic_ring ci_dma_ring = { |
|
- | 1965 | .ib_execute = &cik_sdma_ring_ib_execute, |
|
- | 1966 | .ib_parse = &cik_ib_parse, |
|
- | 1967 | .emit_fence = &cik_sdma_fence_ring_emit, |
|
- | 1968 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, |
|
- | 1969 | .cs_parse = NULL, |
|
1838 | .ring_test = &r600_dma_ring_test, |
1970 | .ring_test = &cik_sdma_ring_test, |
1839 | .ib_test = &r600_dma_ib_test, |
1971 | .ib_test = &cik_sdma_ib_test, |
1840 | .is_lockup = &si_dma_is_lockup, |
1972 | .is_lockup = &cik_sdma_is_lockup, |
1841 | .vm_flush = &si_dma_vm_flush, |
1973 | .vm_flush = &cik_dma_vm_flush, |
- | 1974 | .get_rptr = &cik_sdma_get_rptr, |
|
- | 1975 | .get_wptr = &cik_sdma_get_wptr, |
|
- | 1976 | .set_wptr = &cik_sdma_set_wptr, |
|
- | 1977 | }; |
|
- | 1978 | ||
- | 1979 | static struct radeon_asic_ring ci_vce_ring = { |
|
- | 1980 | .ib_execute = &radeon_vce_ib_execute, |
|
- | 1981 | .emit_fence = &radeon_vce_fence_emit, |
|
- | 1982 | .emit_semaphore = &radeon_vce_semaphore_emit, |
|
- | 1983 | .cs_parse = &radeon_vce_cs_parse, |
|
- | 1984 | .ring_test = &radeon_vce_ring_test, |
|
- | 1985 | .ib_test = &radeon_vce_ib_test, |
|
- | 1986 | .is_lockup = &radeon_ring_test_lockup, |
|
- | 1987 | .get_rptr = &vce_v1_0_get_rptr, |
|
- | 1988 | .get_wptr = &vce_v1_0_get_wptr, |
|
- | 1989 | .set_wptr = &vce_v1_0_set_wptr, |
|
- | 1990 | }; |
|
- | 1991 | ||
- | 1992 | static struct radeon_asic ci_asic = { |
|
- | 1993 | .init = &cik_init, |
|
- | 1994 | // .fini = &si_fini, |
|
- | 1995 | // .suspend = &si_suspend, |
|
- | 1996 | // .resume = &si_resume, |
|
- | 1997 | .asic_reset = &cik_asic_reset, |
|
- | 1998 | // .vga_set_state = &r600_vga_set_state, |
|
- | 1999 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
|
- | 2000 | .gui_idle = &r600_gui_idle, |
|
- | 2001 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
|
- | 2002 | .get_xclk = &cik_get_xclk, |
|
- | 2003 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, |
|
- | 2004 | .gart = { |
|
- | 2005 | .tlb_flush = &cik_pcie_gart_tlb_flush, |
|
- | 2006 | .set_page = &rs600_gart_set_page, |
|
1842 | }, |
2007 | }, |
1843 | [R600_RING_TYPE_UVD_INDEX] = { |
2008 | .vm = { |
1844 | // .ib_execute = &r600_uvd_ib_execute, |
2009 | .init = &cik_vm_init, |
1845 | // .emit_fence = &r600_uvd_fence_emit, |
2010 | .fini = &cik_vm_fini, |
1846 | // .emit_semaphore = &cayman_uvd_semaphore_emit, |
- | |
1847 | // .cs_parse = &radeon_uvd_cs_parse, |
2011 | .copy_pages = &cik_sdma_vm_copy_pages, |
1848 | // .ring_test = &r600_uvd_ring_test, |
2012 | .write_pages = &cik_sdma_vm_write_pages, |
1849 | // .ib_test = &r600_uvd_ib_test, |
2013 | .set_pages = &cik_sdma_vm_set_pages, |
1850 | // .is_lockup = &radeon_ring_test_lockup, |
2014 | .pad_ib = &cik_sdma_vm_pad_ib, |
1851 | } |
2015 | }, |
- | 2016 | .ring = { |
|
- | 2017 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
|
- | 2018 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, |
|
- | 2019 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, |
|
- | 2020 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, |
|
- | 2021 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, |
|
- | 2022 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, |
|
- | 2023 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
|
- | 2024 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, |
|
1852 | }, |
2025 | }, |
1853 | .irq = { |
2026 | .irq = { |
1854 | .set = &si_irq_set, |
2027 | .set = &cik_irq_set, |
1855 | .process = &si_irq_process, |
2028 | .process = &cik_irq_process, |
1856 | }, |
2029 | }, |
1857 | .display = { |
2030 | .display = { |
1858 | .bandwidth_update = &dce6_bandwidth_update, |
2031 | .bandwidth_update = &dce8_bandwidth_update, |
1859 | .get_vblank_counter = &evergreen_get_vblank_counter, |
2032 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1860 | .wait_for_vblank = &dce4_wait_for_vblank, |
2033 | .wait_for_vblank = &dce4_wait_for_vblank, |
1861 | // .set_backlight_level = &atombios_set_backlight_level, |
2034 | .set_backlight_level = &atombios_set_backlight_level, |
1862 | // .get_backlight_level = &atombios_get_backlight_level, |
2035 | .get_backlight_level = &atombios_get_backlight_level, |
- | 2036 | .hdmi_enable = &evergreen_hdmi_enable, |
|
- | 2037 | .hdmi_setmode = &evergreen_hdmi_setmode, |
|
1863 | }, |
2038 | }, |
1864 | .copy = { |
2039 | .copy = { |
1865 | .blit = NULL, |
2040 | .blit = &cik_copy_cpdma, |
1866 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2041 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1867 | .dma = &si_copy_dma, |
2042 | .dma = &cik_copy_dma, |
1868 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
2043 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
1869 | .copy = &si_copy_dma, |
2044 | .copy = &cik_copy_dma, |
1870 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
2045 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
1871 | }, |
2046 | }, |
1872 | .surface = { |
2047 | .surface = { |
1873 | .set_reg = r600_set_surface_reg, |
2048 | .set_reg = r600_set_surface_reg, |
1874 | .clear_reg = r600_clear_surface_reg, |
2049 | .clear_reg = r600_clear_surface_reg, |
Line 1878... | Line 2053... | ||
1878 | .fini = &evergreen_hpd_fini, |
2053 | .fini = &evergreen_hpd_fini, |
1879 | .sense = &evergreen_hpd_sense, |
2054 | .sense = &evergreen_hpd_sense, |
1880 | .set_polarity = &evergreen_hpd_set_polarity, |
2055 | .set_polarity = &evergreen_hpd_set_polarity, |
1881 | }, |
2056 | }, |
1882 | .pm = { |
2057 | .pm = { |
1883 | // .misc = &evergreen_pm_misc, |
2058 | .misc = &evergreen_pm_misc, |
1884 | // .prepare = &evergreen_pm_prepare, |
2059 | .prepare = &evergreen_pm_prepare, |
1885 | // .finish = &evergreen_pm_finish, |
2060 | .finish = &evergreen_pm_finish, |
1886 | // .init_profile = &sumo_pm_init_profile, |
2061 | .init_profile = &sumo_pm_init_profile, |
1887 | // .get_dynpm_state = &r600_pm_get_dynpm_state, |
2062 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
1888 | // .get_engine_clock = &radeon_atom_get_engine_clock, |
2063 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1889 | // .set_engine_clock = &radeon_atom_set_engine_clock, |
2064 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1890 | // .get_memory_clock = &radeon_atom_get_memory_clock, |
2065 | .get_memory_clock = &radeon_atom_get_memory_clock, |
1891 | // .set_memory_clock = &radeon_atom_set_memory_clock, |
2066 | .set_memory_clock = &radeon_atom_set_memory_clock, |
1892 | .get_pcie_lanes = NULL, |
2067 | .get_pcie_lanes = NULL, |
1893 | .set_pcie_lanes = NULL, |
2068 | .set_pcie_lanes = NULL, |
1894 | .set_clock_gating = NULL, |
2069 | .set_clock_gating = NULL, |
- | 2070 | .set_uvd_clocks = &cik_set_uvd_clocks, |
|
- | 2071 | .set_vce_clocks = &cik_set_vce_clocks, |
|
- | 2072 | .get_temperature = &ci_get_temp, |
|
- | 2073 | }, |
|
- | 2074 | .dpm = { |
|
- | 2075 | .init = &ci_dpm_init, |
|
- | 2076 | .setup_asic = &ci_dpm_setup_asic, |
|
- | 2077 | .enable = &ci_dpm_enable, |
|
- | 2078 | .late_enable = &ci_dpm_late_enable, |
|
- | 2079 | .disable = &ci_dpm_disable, |
|
- | 2080 | .pre_set_power_state = &ci_dpm_pre_set_power_state, |
|
- | 2081 | .set_power_state = &ci_dpm_set_power_state, |
|
- | 2082 | .post_set_power_state = &ci_dpm_post_set_power_state, |
|
- | 2083 | .display_configuration_changed = &ci_dpm_display_configuration_changed, |
|
- | 2084 | .fini = &ci_dpm_fini, |
|
- | 2085 | .get_sclk = &ci_dpm_get_sclk, |
|
- | 2086 | .get_mclk = &ci_dpm_get_mclk, |
|
- | 2087 | .print_power_state = &ci_dpm_print_power_state, |
|
- | 2088 | .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, |
|
- | 2089 | .force_performance_level = &ci_dpm_force_performance_level, |
|
- | 2090 | .vblank_too_short = &ci_dpm_vblank_too_short, |
|
- | 2091 | .powergate_uvd = &ci_dpm_powergate_uvd, |
|
- | 2092 | }, |
|
- | 2093 | .pflip = { |
|
- | 2094 | // .pre_page_flip = &evergreen_pre_page_flip, |
|
- | 2095 | // .page_flip = &evergreen_page_flip, |
|
- | 2096 | }, |
|
- | 2097 | }; |
|
- | 2098 | ||
- | 2099 | static struct radeon_asic kv_asic = { |
|
- | 2100 | .init = &cik_init, |
|
- | 2101 | // .fini = &si_fini, |
|
- | 2102 | // .suspend = &si_suspend, |
|
- | 2103 | // .resume = &si_resume, |
|
- | 2104 | .asic_reset = &cik_asic_reset, |
|
- | 2105 | // .vga_set_state = &r600_vga_set_state, |
|
- | 2106 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
|
- | 2107 | .gui_idle = &r600_gui_idle, |
|
- | 2108 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
|
- | 2109 | .get_xclk = &cik_get_xclk, |
|
- | 2110 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, |
|
- | 2111 | .gart = { |
|
- | 2112 | .tlb_flush = &cik_pcie_gart_tlb_flush, |
|
- | 2113 | .set_page = &rs600_gart_set_page, |
|
- | 2114 | }, |
|
- | 2115 | .vm = { |
|
- | 2116 | .init = &cik_vm_init, |
|
- | 2117 | .fini = &cik_vm_fini, |
|
- | 2118 | .copy_pages = &cik_sdma_vm_copy_pages, |
|
- | 2119 | .write_pages = &cik_sdma_vm_write_pages, |
|
- | 2120 | .set_pages = &cik_sdma_vm_set_pages, |
|
- | 2121 | .pad_ib = &cik_sdma_vm_pad_ib, |
|
- | 2122 | }, |
|
- | 2123 | .ring = { |
|
- | 2124 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
|
- | 2125 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, |
|
- | 2126 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, |
|
- | 2127 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, |
|
- | 2128 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, |
|
- | 2129 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, |
|
- | 2130 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
|
- | 2131 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, |
|
- | 2132 | }, |
|
- | 2133 | .irq = { |
|
- | 2134 | .set = &cik_irq_set, |
|
- | 2135 | .process = &cik_irq_process, |
|
- | 2136 | }, |
|
- | 2137 | .display = { |
|
- | 2138 | .bandwidth_update = &dce8_bandwidth_update, |
|
- | 2139 | .get_vblank_counter = &evergreen_get_vblank_counter, |
|
- | 2140 | .wait_for_vblank = &dce4_wait_for_vblank, |
|
- | 2141 | .set_backlight_level = &atombios_set_backlight_level, |
|
- | 2142 | .get_backlight_level = &atombios_get_backlight_level, |
|
- | 2143 | .hdmi_enable = &evergreen_hdmi_enable, |
|
- | 2144 | .hdmi_setmode = &evergreen_hdmi_setmode, |
|
- | 2145 | }, |
|
- | 2146 | .copy = { |
|
- | 2147 | .blit = &cik_copy_cpdma, |
|
- | 2148 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
|
- | 2149 | .dma = &cik_copy_dma, |
|
- | 2150 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
|
- | 2151 | .copy = &cik_copy_dma, |
|
- | 2152 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
|
- | 2153 | }, |
|
- | 2154 | .surface = { |
|
- | 2155 | .set_reg = r600_set_surface_reg, |
|
- | 2156 | .clear_reg = r600_clear_surface_reg, |
|
- | 2157 | }, |
|
- | 2158 | .hpd = { |
|
- | 2159 | .init = &evergreen_hpd_init, |
|
- | 2160 | .fini = &evergreen_hpd_fini, |
|
- | 2161 | .sense = &evergreen_hpd_sense, |
|
- | 2162 | .set_polarity = &evergreen_hpd_set_polarity, |
|
- | 2163 | }, |
|
- | 2164 | .pm = { |
|
- | 2165 | .misc = &evergreen_pm_misc, |
|
- | 2166 | .prepare = &evergreen_pm_prepare, |
|
- | 2167 | .finish = &evergreen_pm_finish, |
|
- | 2168 | .init_profile = &sumo_pm_init_profile, |
|
- | 2169 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
|
- | 2170 | .get_engine_clock = &radeon_atom_get_engine_clock, |
|
- | 2171 | .set_engine_clock = &radeon_atom_set_engine_clock, |
|
- | 2172 | .get_memory_clock = &radeon_atom_get_memory_clock, |
|
- | 2173 | .set_memory_clock = &radeon_atom_set_memory_clock, |
|
- | 2174 | .get_pcie_lanes = NULL, |
|
- | 2175 | .set_pcie_lanes = NULL, |
|
- | 2176 | .set_clock_gating = NULL, |
|
1895 | // .set_uvd_clocks = &si_set_uvd_clocks, |
2177 | .set_uvd_clocks = &cik_set_uvd_clocks, |
- | 2178 | .set_vce_clocks = &cik_set_vce_clocks, |
|
- | 2179 | .get_temperature = &kv_get_temp, |
|
- | 2180 | }, |
|
- | 2181 | .dpm = { |
|
- | 2182 | .init = &kv_dpm_init, |
|
- | 2183 | .setup_asic = &kv_dpm_setup_asic, |
|
- | 2184 | .enable = &kv_dpm_enable, |
|
- | 2185 | .late_enable = &kv_dpm_late_enable, |
|
- | 2186 | .disable = &kv_dpm_disable, |
|
- | 2187 | .pre_set_power_state = &kv_dpm_pre_set_power_state, |
|
- | 2188 | .set_power_state = &kv_dpm_set_power_state, |
|
- | 2189 | .post_set_power_state = &kv_dpm_post_set_power_state, |
|
- | 2190 | .display_configuration_changed = &kv_dpm_display_configuration_changed, |
|
- | 2191 | .fini = &kv_dpm_fini, |
|
- | 2192 | .get_sclk = &kv_dpm_get_sclk, |
|
- | 2193 | .get_mclk = &kv_dpm_get_mclk, |
|
- | 2194 | .print_power_state = &kv_dpm_print_power_state, |
|
- | 2195 | .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, |
|
- | 2196 | .force_performance_level = &kv_dpm_force_performance_level, |
|
- | 2197 | .powergate_uvd = &kv_dpm_powergate_uvd, |
|
- | 2198 | .enable_bapm = &kv_dpm_enable_bapm, |
|
1896 | }, |
2199 | }, |
1897 | .pflip = { |
2200 | .pflip = { |
1898 | // .pre_page_flip = &evergreen_pre_page_flip, |
2201 | // .pre_page_flip = &evergreen_pre_page_flip, |
1899 | // .page_flip = &evergreen_page_flip, |
2202 | // .page_flip = &evergreen_page_flip, |
1900 | // .post_page_flip = &evergreen_post_page_flip, |
- | |
1901 | }, |
2203 | }, |
1902 | }; |
2204 | }; |
Line 1903... | Line 2205... | ||
1903 | 2205 | ||
1904 | /** |
2206 | /** |
Line 1979... | Line 2281... | ||
1979 | case CHIP_RV570: |
2281 | case CHIP_RV570: |
1980 | case CHIP_R580: |
2282 | case CHIP_R580: |
1981 | rdev->asic = &r520_asic; |
2283 | rdev->asic = &r520_asic; |
1982 | break; |
2284 | break; |
1983 | case CHIP_R600: |
2285 | case CHIP_R600: |
- | 2286 | rdev->asic = &r600_asic; |
|
- | 2287 | break; |
|
1984 | case CHIP_RV610: |
2288 | case CHIP_RV610: |
1985 | case CHIP_RV630: |
2289 | case CHIP_RV630: |
1986 | case CHIP_RV620: |
2290 | case CHIP_RV620: |
1987 | case CHIP_RV635: |
2291 | case CHIP_RV635: |
1988 | case CHIP_RV670: |
2292 | case CHIP_RV670: |
1989 | rdev->asic = &r600_asic; |
2293 | rdev->asic = &rv6xx_asic; |
1990 | if (rdev->family == CHIP_R600) |
- | |
1991 | rdev->has_uvd = false; |
- | |
1992 | else |
- | |
1993 | rdev->has_uvd = true; |
2294 | rdev->has_uvd = true; |
1994 | break; |
2295 | break; |
1995 | case CHIP_RS780: |
2296 | case CHIP_RS780: |
1996 | case CHIP_RS880: |
2297 | case CHIP_RS880: |
1997 | rdev->asic = &rs780_asic; |
2298 | rdev->asic = &rs780_asic; |
Line 2061... | Line 2362... | ||
2061 | rdev->num_crtc = 6; |
2362 | rdev->num_crtc = 6; |
2062 | if (rdev->family == CHIP_HAINAN) |
2363 | if (rdev->family == CHIP_HAINAN) |
2063 | rdev->has_uvd = false; |
2364 | rdev->has_uvd = false; |
2064 | else |
2365 | else |
2065 | rdev->has_uvd = true; |
2366 | rdev->has_uvd = true; |
- | 2367 | switch (rdev->family) { |
|
- | 2368 | case CHIP_TAHITI: |
|
- | 2369 | rdev->cg_flags = |
|
- | 2370 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2371 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2372 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2373 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2374 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2375 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2376 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2377 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2378 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2379 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2380 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2381 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2382 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2383 | rdev->pg_flags = 0; |
|
- | 2384 | break; |
|
- | 2385 | case CHIP_PITCAIRN: |
|
- | 2386 | rdev->cg_flags = |
|
- | 2387 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2388 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2389 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2390 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2391 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2392 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2393 | RADEON_CG_SUPPORT_GFX_RLC_LS | |
|
- | 2394 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2395 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2396 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2397 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2398 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2399 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2400 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2401 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2402 | rdev->pg_flags = 0; |
|
- | 2403 | break; |
|
- | 2404 | case CHIP_VERDE: |
|
- | 2405 | rdev->cg_flags = |
|
- | 2406 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2407 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2408 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2409 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2410 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2411 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2412 | RADEON_CG_SUPPORT_GFX_RLC_LS | |
|
- | 2413 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2414 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2415 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2416 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2417 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2418 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2419 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2420 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2421 | rdev->pg_flags = 0 | |
|
- | 2422 | /*RADEON_PG_SUPPORT_GFX_PG | */ |
|
- | 2423 | RADEON_PG_SUPPORT_SDMA; |
|
- | 2424 | break; |
|
- | 2425 | case CHIP_OLAND: |
|
- | 2426 | rdev->cg_flags = |
|
- | 2427 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2428 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2429 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2430 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2431 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2432 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2433 | RADEON_CG_SUPPORT_GFX_RLC_LS | |
|
- | 2434 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2435 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2436 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2437 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2438 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2439 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2440 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2441 | rdev->pg_flags = 0; |
|
- | 2442 | break; |
|
- | 2443 | case CHIP_HAINAN: |
|
- | 2444 | rdev->cg_flags = |
|
- | 2445 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2446 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2447 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2448 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2449 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2450 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2451 | RADEON_CG_SUPPORT_GFX_RLC_LS | |
|
- | 2452 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2453 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2454 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2455 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2456 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2457 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2458 | rdev->pg_flags = 0; |
|
- | 2459 | break; |
|
- | 2460 | default: |
|
- | 2461 | rdev->cg_flags = 0; |
|
- | 2462 | rdev->pg_flags = 0; |
|
- | 2463 | break; |
|
- | 2464 | } |
|
- | 2465 | break; |
|
- | 2466 | case CHIP_BONAIRE: |
|
- | 2467 | case CHIP_HAWAII: |
|
- | 2468 | rdev->asic = &ci_asic; |
|
- | 2469 | rdev->num_crtc = 6; |
|
- | 2470 | rdev->has_uvd = true; |
|
- | 2471 | if (rdev->family == CHIP_BONAIRE) { |
|
- | 2472 | rdev->cg_flags = |
|
- | 2473 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2474 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2475 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2476 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2477 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2478 | RADEON_CG_SUPPORT_GFX_CGTS_LS | |
|
- | 2479 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2480 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2481 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2482 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2483 | RADEON_CG_SUPPORT_SDMA_LS | |
|
- | 2484 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2485 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2486 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2487 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2488 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2489 | rdev->pg_flags = 0; |
|
- | 2490 | } else { |
|
- | 2491 | rdev->cg_flags = |
|
- | 2492 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2493 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2494 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2495 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2496 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2497 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2498 | RADEON_CG_SUPPORT_MC_LS | |
|
- | 2499 | RADEON_CG_SUPPORT_MC_MGCG | |
|
- | 2500 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2501 | RADEON_CG_SUPPORT_SDMA_LS | |
|
- | 2502 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2503 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2504 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2505 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2506 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2507 | rdev->pg_flags = 0; |
|
- | 2508 | } |
|
- | 2509 | break; |
|
- | 2510 | case CHIP_KAVERI: |
|
- | 2511 | case CHIP_KABINI: |
|
- | 2512 | case CHIP_MULLINS: |
|
- | 2513 | rdev->asic = &kv_asic; |
|
- | 2514 | /* set num crtcs */ |
|
- | 2515 | if (rdev->family == CHIP_KAVERI) { |
|
- | 2516 | rdev->num_crtc = 4; |
|
- | 2517 | rdev->cg_flags = |
|
- | 2518 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2519 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2520 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2521 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2522 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2523 | RADEON_CG_SUPPORT_GFX_CGTS_LS | |
|
- | 2524 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2525 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2526 | RADEON_CG_SUPPORT_SDMA_LS | |
|
- | 2527 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2528 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2529 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2530 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2531 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2532 | rdev->pg_flags = 0; |
|
- | 2533 | /*RADEON_PG_SUPPORT_GFX_PG | |
|
- | 2534 | RADEON_PG_SUPPORT_GFX_SMG | |
|
- | 2535 | RADEON_PG_SUPPORT_GFX_DMG | |
|
- | 2536 | RADEON_PG_SUPPORT_UVD | |
|
- | 2537 | RADEON_PG_SUPPORT_VCE | |
|
- | 2538 | RADEON_PG_SUPPORT_CP | |
|
- | 2539 | RADEON_PG_SUPPORT_GDS | |
|
- | 2540 | RADEON_PG_SUPPORT_RLC_SMU_HS | |
|
- | 2541 | RADEON_PG_SUPPORT_ACP | |
|
- | 2542 | RADEON_PG_SUPPORT_SAMU;*/ |
|
- | 2543 | } else { |
|
- | 2544 | rdev->num_crtc = 2; |
|
- | 2545 | rdev->cg_flags = |
|
- | 2546 | RADEON_CG_SUPPORT_GFX_MGCG | |
|
- | 2547 | RADEON_CG_SUPPORT_GFX_MGLS | |
|
- | 2548 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
|
- | 2549 | RADEON_CG_SUPPORT_GFX_CGLS | |
|
- | 2550 | RADEON_CG_SUPPORT_GFX_CGTS | |
|
- | 2551 | RADEON_CG_SUPPORT_GFX_CGTS_LS | |
|
- | 2552 | RADEON_CG_SUPPORT_GFX_CP_LS | |
|
- | 2553 | RADEON_CG_SUPPORT_SDMA_MGCG | |
|
- | 2554 | RADEON_CG_SUPPORT_SDMA_LS | |
|
- | 2555 | RADEON_CG_SUPPORT_BIF_LS | |
|
- | 2556 | RADEON_CG_SUPPORT_VCE_MGCG | |
|
- | 2557 | RADEON_CG_SUPPORT_UVD_MGCG | |
|
- | 2558 | RADEON_CG_SUPPORT_HDP_LS | |
|
- | 2559 | RADEON_CG_SUPPORT_HDP_MGCG; |
|
- | 2560 | rdev->pg_flags = 0; |
|
- | 2561 | /*RADEON_PG_SUPPORT_GFX_PG | |
|
- | 2562 | RADEON_PG_SUPPORT_GFX_SMG | |
|
- | 2563 | RADEON_PG_SUPPORT_UVD | |
|
- | 2564 | RADEON_PG_SUPPORT_VCE | |
|
- | 2565 | RADEON_PG_SUPPORT_CP | |
|
- | 2566 | RADEON_PG_SUPPORT_GDS | |
|
- | 2567 | RADEON_PG_SUPPORT_RLC_SMU_HS | |
|
- | 2568 | RADEON_PG_SUPPORT_SAMU;*/ |
|
- | 2569 | } |
|
- | 2570 | rdev->has_uvd = true; |
|
2066 | break; |
2571 | break; |
2067 | default: |
2572 | default: |
2068 | /* FIXME: not supported yet */ |
2573 | /* FIXME: not supported yet */ |
2069 | return -EINVAL; |
2574 | return -EINVAL; |
2070 | } |
2575 | } |