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Rev 5078 | Rev 6104 | ||
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Line 44... | Line 44... | ||
44 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
44 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
45 | #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 |
45 | #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 |
Line 46... | Line 46... | ||
46 | 46 | ||
Line -... | Line 47... | ||
- | 47 | #define DMIF_ADDR_CONFIG 0xBD4 |
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- | 48 | ||
- | 49 | /* fusion vce clocks */ |
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- | 50 | #define CG_ECLK_CNTL 0x620 |
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- | 51 | # define ECLK_DIVIDER_MASK 0x7f |
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- | 52 | # define ECLK_DIR_CNTL_EN (1 << 8) |
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- | 53 | #define CG_ECLK_STATUS 0x624 |
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47 | #define DMIF_ADDR_CONFIG 0xBD4 |
54 | # define ECLK_STATUS (1 << 0) |
48 | 55 | ||
Line 49... | Line 56... | ||
49 | /* DCE6 only */ |
56 | /* DCE6 only */ |
50 | #define DMIF_ADDR_CALC 0xC00 |
57 | #define DMIF_ADDR_CALC 0xC00 |
Line 80... | Line 87... | ||
80 | #define SOFT_RESET_DMA (1 << 20) |
87 | #define SOFT_RESET_DMA (1 << 20) |
81 | #define SOFT_RESET_TST (1 << 21) |
88 | #define SOFT_RESET_TST (1 << 21) |
82 | #define SOFT_RESET_REGBB (1 << 22) |
89 | #define SOFT_RESET_REGBB (1 << 22) |
83 | #define SOFT_RESET_ORB (1 << 23) |
90 | #define SOFT_RESET_ORB (1 << 23) |
Line -... | Line 91... | ||
- | 91 | ||
- | 92 | #define SRBM_READ_ERROR 0xE98 |
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- | 93 | #define SRBM_INT_CNTL 0xEA0 |
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- | 94 | #define SRBM_INT_ACK 0xEA8 |
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84 | 95 | ||
85 | #define SRBM_STATUS2 0x0EC4 |
96 | #define SRBM_STATUS2 0x0EC4 |
86 | #define DMA_BUSY (1 << 5) |
97 | #define DMA_BUSY (1 << 5) |
Line 87... | Line 98... | ||
87 | #define DMA1_BUSY (1 << 6) |
98 | #define DMA1_BUSY (1 << 6) |
Line 810... | Line 821... | ||
810 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c |
821 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c |
Line 811... | Line 822... | ||
811 | 822 | ||
812 | #define MC_PMG_CMD_MRS2 0x2b5c |
823 | #define MC_PMG_CMD_MRS2 0x2b5c |
Line -... | Line 824... | ||
- | 824 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 |
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- | 825 | ||
- | 826 | #define AUX_CONTROL 0x6200 |
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- | 827 | #define AUX_EN (1 << 0) |
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- | 828 | #define AUX_LS_READ_EN (1 << 8) |
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- | 829 | #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) |
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- | 830 | #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) |
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- | 831 | #define AUX_DET_EN (1 << 18) |
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- | 832 | #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) |
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- | 833 | #define AUX_IMPCAL_REQ_EN (1 << 24) |
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- | 834 | #define AUX_TEST_MODE (1 << 28) |
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- | 835 | #define AUX_DEGLITCH_EN (1 << 29) |
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- | 836 | #define AUX_SW_CONTROL 0x6204 |
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- | 837 | #define AUX_SW_GO (1 << 0) |
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- | 838 | #define AUX_LS_READ_TRIG (1 << 2) |
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- | 839 | #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) |
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- | 840 | #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) |
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- | 841 | ||
- | 842 | #define AUX_SW_INTERRUPT_CONTROL 0x620c |
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- | 843 | #define AUX_SW_DONE_INT (1 << 0) |
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- | 844 | #define AUX_SW_DONE_ACK (1 << 1) |
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- | 845 | #define AUX_SW_DONE_MASK (1 << 2) |
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- | 846 | #define AUX_SW_LS_DONE_INT (1 << 4) |
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- | 847 | #define AUX_SW_LS_DONE_MASK (1 << 6) |
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- | 848 | #define AUX_SW_STATUS 0x6210 |
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- | 849 | #define AUX_SW_DONE (1 << 0) |
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- | 850 | #define AUX_SW_REQ (1 << 1) |
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- | 851 | #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) |
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- | 852 | #define AUX_SW_RX_TIMEOUT (1 << 7) |
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- | 853 | #define AUX_SW_RX_OVERFLOW (1 << 8) |
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- | 854 | #define AUX_SW_RX_HPD_DISCON (1 << 9) |
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- | 855 | #define AUX_SW_RX_PARTIAL_BYTE (1 << 10) |
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- | 856 | #define AUX_SW_NON_AUX_MODE (1 << 11) |
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- | 857 | #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12) |
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- | 858 | #define AUX_SW_RX_INVALID_STOP (1 << 14) |
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- | 859 | #define AUX_SW_RX_SYNC_INVALID_L (1 << 17) |
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- | 860 | #define AUX_SW_RX_SYNC_INVALID_H (1 << 18) |
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- | 861 | #define AUX_SW_RX_INVALID_START (1 << 19) |
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- | 862 | #define AUX_SW_RX_RECV_NO_DET (1 << 20) |
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- | 863 | #define AUX_SW_RX_RECV_INVALID_H (1 << 22) |
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- | 864 | #define AUX_SW_RX_RECV_INVALID_V (1 << 23) |
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- | 865 | ||
- | 866 | #define AUX_SW_DATA 0x6218 |
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- | 867 | #define AUX_SW_DATA_RW (1 << 0) |
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- | 868 | #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) |
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- | 869 | #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) |
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813 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 |
870 | #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) |
814 | 871 | ||
815 | #define LB_SYNC_RESET_SEL 0x6b28 |
872 | #define LB_SYNC_RESET_SEL 0x6b28 |
Line 816... | Line 873... | ||
816 | #define LB_SYNC_RESET_SEL_MASK (3 << 0) |
873 | #define LB_SYNC_RESET_SEL_MASK (3 << 0) |
Line 1080... | Line 1137... | ||
1080 | #define UVD_UDEC_ADDR_CONFIG 0xEF4C |
1137 | #define UVD_UDEC_ADDR_CONFIG 0xEF4C |
1081 | #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 |
1138 | #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 |
1082 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 |
1139 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 |
1083 | #define UVD_RBC_RB_RPTR 0xF690 |
1140 | #define UVD_RBC_RB_RPTR 0xF690 |
1084 | #define UVD_RBC_RB_WPTR 0xF694 |
1141 | #define UVD_RBC_RB_WPTR 0xF694 |
- | 1142 | #define UVD_STATUS 0xf6bc |
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Line 1085... | Line 1143... | ||
1085 | 1143 | ||
1086 | /* |
1144 | /* |
1087 | * PM4 |
1145 | * PM4 |
1088 | */ |
1146 | */ |
Line 1131... | Line 1189... | ||
1131 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
1189 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
1132 | #define PACKET3_WRITE_DATA 0x37 |
1190 | #define PACKET3_WRITE_DATA 0x37 |
1133 | #define PACKET3_MEM_SEMAPHORE 0x39 |
1191 | #define PACKET3_MEM_SEMAPHORE 0x39 |
1134 | #define PACKET3_MPEG_INDEX 0x3A |
1192 | #define PACKET3_MPEG_INDEX 0x3A |
1135 | #define PACKET3_WAIT_REG_MEM 0x3C |
1193 | #define PACKET3_WAIT_REG_MEM 0x3C |
- | 1194 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
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- | 1195 | /* 0 - always |
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- | 1196 | * 1 - < |
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- | 1197 | * 2 - <= |
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- | 1198 | * 3 - == |
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- | 1199 | * 4 - != |
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- | 1200 | * 5 - >= |
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- | 1201 | * 6 - > |
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- | 1202 | */ |
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- | 1203 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
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- | 1204 | /* 0 - reg |
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- | 1205 | * 1 - mem |
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- | 1206 | */ |
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- | 1207 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
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- | 1208 | /* 0 - me |
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- | 1209 | * 1 - pfp |
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- | 1210 | */ |
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1136 | #define PACKET3_MEM_WRITE 0x3D |
1211 | #define PACKET3_MEM_WRITE 0x3D |
1137 | #define PACKET3_PFP_SYNC_ME 0x42 |
1212 | #define PACKET3_PFP_SYNC_ME 0x42 |
1138 | #define PACKET3_SURFACE_SYNC 0x43 |
1213 | #define PACKET3_SURFACE_SYNC 0x43 |
1139 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
1214 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
1140 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
1215 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
Line 1270... | Line 1345... | ||
1270 | #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ |
1345 | #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ |
1271 | (1 << 26) | \ |
1346 | (1 << 26) | \ |
1272 | (1 << 21) | \ |
1347 | (1 << 21) | \ |
1273 | (((n) & 0xFFFFF) << 0)) |
1348 | (((n) & 0xFFFFF) << 0)) |
Line -... | Line 1349... | ||
- | 1349 | ||
- | 1350 | #define DMA_SRBM_POLL_PACKET ((9 << 28) | \ |
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- | 1351 | (1 << 27) | \ |
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- | 1352 | (1 << 26)) |
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- | 1353 | ||
- | 1354 | #define DMA_SRBM_READ_PACKET ((9 << 28) | \ |
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- | 1355 | (1 << 27)) |
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1274 | 1356 | ||
1275 | /* async DMA Packet types */ |
1357 | /* async DMA Packet types */ |
1276 | #define DMA_PACKET_WRITE 0x2 |
1358 | #define DMA_PACKET_WRITE 0x2 |
1277 | #define DMA_PACKET_COPY 0x3 |
1359 | #define DMA_PACKET_COPY 0x3 |
1278 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 |
1360 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 |