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| Rev 3480 | Rev 3746 | ||
|---|---|---|---|
| Line 24... | Line 24... | ||
| 24 | * Eric Anholt |
24 | * Eric Anholt |
| 25 | * Zou Nan hai |
25 | * Zou Nan hai |
| 26 | * Xiang Hai hao |
26 | * Xiang Hai hao |
| 27 | * |
27 | * |
| 28 | */ |
28 | */ |
| 29 | #define iowrite32(v, addr) writel((v), (addr)) |
- | |
| 30 | #define ioread32(addr) readl(addr) |
- | |
| Line 31... | Line 29... | ||
| 31 | 29 | ||
| 32 | #include |
30 | #include |
| 33 | #include "i915_drv.h" |
31 | #include "i915_drv.h" |
| 34 | #include |
32 | #include |
| Line 504... | Line 502... | ||
| 504 | { |
502 | { |
| 505 | struct drm_device *dev = ring->dev; |
503 | struct drm_device *dev = ring->dev; |
| 506 | struct drm_i915_private *dev_priv = dev->dev_private; |
504 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 507 | int ret = init_ring_common(ring); |
505 | int ret = init_ring_common(ring); |
| Line -... | Line 506... | ||
| - | 506 | ||
| - | 507 | ENTER(); |
|
| 508 | 508 | ||
| 509 | if (INTEL_INFO(dev)->gen > 3) |
509 | if (INTEL_INFO(dev)->gen > 3) |
| Line 510... | Line 510... | ||
| 510 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
510 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
| 511 | 511 | ||
| Line 553... | Line 553... | ||
| 553 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
553 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
| Line 554... | Line 554... | ||
| 554 | 554 | ||
| 555 | if (HAS_L3_GPU_CACHE(dev)) |
555 | if (HAS_L3_GPU_CACHE(dev)) |
| Line -... | Line 556... | ||
| - | 556 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
|
| - | 557 | ||
| 556 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
558 | LEAVE(); |
| 557 | 559 | ||
| Line 558... | Line 560... | ||
| 558 | return ret; |
560 | return ret; |
| 559 | } |
561 | } |
| Line 877... | Line 879... | ||
| 877 | { |
879 | { |
| 878 | struct drm_device *dev = ring->dev; |
880 | struct drm_device *dev = ring->dev; |
| 879 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 880 | u32 mmio = 0; |
882 | u32 mmio = 0; |
| Line -... | Line 883... | ||
| - | 883 | ||
| - | 884 | ENTER(); |
|
| 881 | 885 | ||
| 882 | /* The ring status page addresses are no longer next to the rest of |
886 | /* The ring status page addresses are no longer next to the rest of |
| 883 | * the ring registers as of gen7. |
887 | * the ring registers as of gen7. |
| 884 | */ |
888 | */ |
| 885 | if (IS_GEN7(dev)) { |
889 | if (IS_GEN7(dev)) { |
| Line 900... | Line 904... | ||
| 900 | mmio = RING_HWS_PGA(ring->mmio_base); |
904 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 901 | } |
905 | } |
| Line 902... | Line 906... | ||
| 902 | 906 | ||
| 903 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
907 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| - | 908 | POSTING_READ(mmio); |
|
| - | 909 | LEAVE(); |
|
| 904 | POSTING_READ(mmio); |
910 | |
| Line 905... | Line 911... | ||
| 905 | } |
911 | } |
| 906 | 912 | ||
| 907 | static int |
913 | static int |