Rev 3243 | Rev 3482 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 3243 | Rev 3480 | ||
---|---|---|---|
Line 146... | Line 146... | ||
146 | break; |
146 | break; |
147 | } |
147 | } |
148 | return max_link_bw; |
148 | return max_link_bw; |
149 | } |
149 | } |
Line 150... | Line -... | ||
150 | - | ||
151 | static int |
- | |
152 | intel_dp_link_clock(uint8_t link_bw) |
- | |
153 | { |
- | |
154 | if (link_bw == DP_LINK_BW_2_7) |
- | |
155 | return 270000; |
- | |
156 | else |
- | |
157 | return 162000; |
- | |
158 | } |
- | |
159 | 150 | ||
160 | /* |
151 | /* |
161 | * The units on the numbers in the next two are... bizarre. Examples will |
152 | * The units on the numbers in the next two are... bizarre. Examples will |
162 | * make it clearer; this one parallels an example in the eDP spec. |
153 | * make it clearer; this one parallels an example in the eDP spec. |
163 | * |
154 | * |
Line 189... | Line 180... | ||
189 | static bool |
180 | static bool |
190 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
181 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
191 | struct drm_display_mode *mode, |
182 | struct drm_display_mode *mode, |
192 | bool adjust_mode) |
183 | bool adjust_mode) |
193 | { |
184 | { |
- | 185 | int max_link_clock = |
|
194 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
186 | drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
195 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
187 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
196 | int max_rate, mode_rate; |
188 | int max_rate, mode_rate; |
Line 197... | Line 189... | ||
197 | 189 | ||
198 | mode_rate = intel_dp_link_required(mode->clock, 24); |
190 | mode_rate = intel_dp_link_required(mode->clock, 24); |
Line 328... | Line 320... | ||
328 | I915_READ(PCH_PP_STATUS), |
320 | I915_READ(PCH_PP_STATUS), |
329 | I915_READ(PCH_PP_CONTROL)); |
321 | I915_READ(PCH_PP_CONTROL)); |
330 | } |
322 | } |
331 | } |
323 | } |
Line -... | Line 324... | ||
- | 324 | ||
- | 325 | static uint32_t |
|
- | 326 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
|
- | 327 | { |
|
- | 328 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 329 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 330 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 331 | uint32_t ch_ctl = intel_dp->output_reg + 0x10; |
|
- | 332 | uint32_t status; |
|
- | 333 | bool done; |
|
- | 334 | ||
- | 335 | if (IS_HASWELL(dev)) { |
|
- | 336 | switch (intel_dig_port->port) { |
|
- | 337 | case PORT_A: |
|
- | 338 | ch_ctl = DPA_AUX_CH_CTL; |
|
- | 339 | break; |
|
- | 340 | case PORT_B: |
|
- | 341 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
|
- | 342 | break; |
|
- | 343 | case PORT_C: |
|
- | 344 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
|
- | 345 | break; |
|
- | 346 | case PORT_D: |
|
- | 347 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
|
- | 348 | break; |
|
- | 349 | default: |
|
- | 350 | BUG(); |
|
- | 351 | } |
|
- | 352 | } |
|
- | 353 | ||
- | 354 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
|
- | 355 | if (has_aux_irq) |
|
- | 356 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
|
- | 357 | msecs_to_jiffies(10)); |
|
- | 358 | else |
|
- | 359 | done = wait_for_atomic(C, 10) == 0; |
|
- | 360 | if (!done) |
|
- | 361 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
|
- | 362 | has_aux_irq); |
|
- | 363 | #undef C |
|
- | 364 | ||
- | 365 | return status; |
|
- | 366 | } |
|
332 | 367 | ||
333 | static int |
368 | static int |
334 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
369 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
335 | uint8_t *send, int send_bytes, |
370 | uint8_t *send, int send_bytes, |
336 | uint8_t *recv, int recv_size) |
371 | uint8_t *recv, int recv_size) |
Line 339... | Line 374... | ||
339 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
340 | struct drm_device *dev = intel_dig_port->base.base.dev; |
375 | struct drm_device *dev = intel_dig_port->base.base.dev; |
341 | struct drm_i915_private *dev_priv = dev->dev_private; |
376 | struct drm_i915_private *dev_priv = dev->dev_private; |
342 | uint32_t ch_ctl = output_reg + 0x10; |
377 | uint32_t ch_ctl = output_reg + 0x10; |
343 | uint32_t ch_data = ch_ctl + 4; |
378 | uint32_t ch_data = ch_ctl + 4; |
344 | int i; |
- | |
345 | int recv_bytes; |
379 | int i, ret, recv_bytes; |
346 | uint32_t status; |
380 | uint32_t status; |
347 | uint32_t aux_clock_divider; |
381 | uint32_t aux_clock_divider; |
348 | int try, precharge; |
382 | int try, precharge; |
- | 383 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
|
- | 384 | ||
- | 385 | /* dp aux is extremely sensitive to irq latency, hence request the |
|
- | 386 | * lowest possible wakeup latency and so prevent the cpu from going into |
|
- | 387 | * deep sleep states. |
|
- | 388 | */ |
|
- | 389 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
|
Line 349... | Line 390... | ||
349 | 390 | ||
350 | if (IS_HASWELL(dev)) { |
391 | if (IS_HASWELL(dev)) { |
351 | switch (intel_dig_port->port) { |
392 | switch (intel_dig_port->port) { |
352 | case PORT_A: |
393 | case PORT_A: |
Line 377... | Line 418... | ||
377 | * |
418 | * |
378 | * Note that PCH attached eDP panels should use a 125MHz input |
419 | * Note that PCH attached eDP panels should use a 125MHz input |
379 | * clock divider. |
420 | * clock divider. |
380 | */ |
421 | */ |
381 | if (is_cpu_edp(intel_dp)) { |
422 | if (is_cpu_edp(intel_dp)) { |
382 | if (IS_HASWELL(dev)) |
423 | if (HAS_DDI(dev)) |
383 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
424 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
384 | else if (IS_VALLEYVIEW(dev)) |
425 | else if (IS_VALLEYVIEW(dev)) |
385 | aux_clock_divider = 100; |
426 | aux_clock_divider = 100; |
386 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
427 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
387 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
428 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
Line 397... | Line 438... | ||
397 | else |
438 | else |
398 | precharge = 5; |
439 | precharge = 5; |
Line 399... | Line 440... | ||
399 | 440 | ||
400 | /* Try to wait for any previous AUX channel activity */ |
441 | /* Try to wait for any previous AUX channel activity */ |
401 | for (try = 0; try < 3; try++) { |
442 | for (try = 0; try < 3; try++) { |
402 | status = I915_READ(ch_ctl); |
443 | status = I915_READ_NOTRACE(ch_ctl); |
403 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
444 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
404 | break; |
445 | break; |
405 | msleep(1); |
446 | msleep(1); |
Line 406... | Line 447... | ||
406 | } |
447 | } |
407 | 448 | ||
408 | if (try == 3) { |
449 | if (try == 3) { |
409 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
450 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
- | 451 | I915_READ(ch_ctl)); |
|
410 | I915_READ(ch_ctl)); |
452 | ret = -EBUSY; |
Line 411... | Line 453... | ||
411 | return -EBUSY; |
453 | goto out; |
412 | } |
454 | } |
413 | 455 | ||
Line 419... | Line 461... | ||
419 | pack_aux(send + i, send_bytes - i)); |
461 | pack_aux(send + i, send_bytes - i)); |
Line 420... | Line 462... | ||
420 | 462 | ||
421 | /* Send the command and wait for it to complete */ |
463 | /* Send the command and wait for it to complete */ |
422 | I915_WRITE(ch_ctl, |
464 | I915_WRITE(ch_ctl, |
- | 465 | DP_AUX_CH_CTL_SEND_BUSY | |
|
423 | DP_AUX_CH_CTL_SEND_BUSY | |
466 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
424 | DP_AUX_CH_CTL_TIME_OUT_400us | |
467 | DP_AUX_CH_CTL_TIME_OUT_400us | |
425 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
468 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
426 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
469 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
427 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
470 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
428 | DP_AUX_CH_CTL_DONE | |
471 | DP_AUX_CH_CTL_DONE | |
429 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
472 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
430 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
473 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
431 | for (;;) { |
- | |
432 | status = I915_READ(ch_ctl); |
474 | |
433 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
- | |
434 | break; |
- | |
435 | udelay(100); |
- | |
Line 436... | Line 475... | ||
436 | } |
475 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
437 | 476 | ||
438 | /* Clear done status and any errors */ |
477 | /* Clear done status and any errors */ |
439 | I915_WRITE(ch_ctl, |
478 | I915_WRITE(ch_ctl, |
Line 449... | Line 488... | ||
449 | break; |
488 | break; |
450 | } |
489 | } |
Line 451... | Line 490... | ||
451 | 490 | ||
452 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
491 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
453 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
492 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
- | 493 | ret = -EBUSY; |
|
454 | return -EBUSY; |
494 | goto out; |
Line 455... | Line 495... | ||
455 | } |
495 | } |
456 | 496 | ||
457 | /* Check for timeout or receive error. |
497 | /* Check for timeout or receive error. |
458 | * Timeouts occur when the sink is not connected |
498 | * Timeouts occur when the sink is not connected |
459 | */ |
499 | */ |
460 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
500 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
- | 501 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
|
461 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
502 | ret = -EIO; |
Line 462... | Line 503... | ||
462 | return -EIO; |
503 | goto out; |
463 | } |
504 | } |
464 | 505 | ||
465 | /* Timeouts occur when the device isn't connected, so they're |
506 | /* Timeouts occur when the device isn't connected, so they're |
466 | * "normal" -- don't fill the kernel log with these */ |
507 | * "normal" -- don't fill the kernel log with these */ |
- | 508 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
|
467 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
509 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Line 468... | Line 510... | ||
468 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
510 | ret = -ETIMEDOUT; |
469 | return -ETIMEDOUT; |
511 | goto out; |
470 | } |
512 | } |
Line 477... | Line 519... | ||
477 | 519 | ||
478 | for (i = 0; i < recv_bytes; i += 4) |
520 | for (i = 0; i < recv_bytes; i += 4) |
479 | unpack_aux(I915_READ(ch_data + i), |
521 | unpack_aux(I915_READ(ch_data + i), |
Line 480... | Line 522... | ||
480 | recv + i, recv_bytes - i); |
522 | recv + i, recv_bytes - i); |
- | 523 | ||
- | 524 | ret = recv_bytes; |
|
- | 525 | out: |
|
- | 526 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
|
481 | 527 | ||
Line 482... | Line 528... | ||
482 | return recv_bytes; |
528 | return ret; |
483 | } |
529 | } |
484 | 530 | ||
Line 716... | Line 762... | ||
716 | 762 | ||
717 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
763 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
Line 718... | Line 764... | ||
718 | return false; |
764 | return false; |
- | 765 | ||
- | 766 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
|
- | 767 | ||
- | 768 | if (intel_dp->color_range_auto) { |
|
- | 769 | /* |
|
- | 770 | * See: |
|
- | 771 | * CEA-861-E - 5.1 Default Encoding Parameters |
|
- | 772 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
|
- | 773 | */ |
|
- | 774 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
|
- | 775 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
|
- | 776 | else |
|
- | 777 | intel_dp->color_range = 0; |
|
- | 778 | } |
|
- | 779 | ||
- | 780 | if (intel_dp->color_range) |
|
719 | 781 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; |
|
Line 720... | Line 782... | ||
720 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
782 | |
721 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
783 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
- | 784 | ||
- | 785 | for (clock = 0; clock <= max_clock; clock++) { |
|
722 | 786 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
|
- | 787 | int link_bw_clock = |
|
Line 723... | Line 788... | ||
723 | for (clock = 0; clock <= max_clock; clock++) { |
788 | drm_dp_bw_code_to_link_rate(bws[clock]); |
724 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
789 | int link_avail = intel_dp_max_data_rate(link_bw_clock, |
725 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
790 | lane_count); |
726 | 791 | ||
727 | if (mode_rate <= link_avail) { |
792 | if (mode_rate <= link_avail) { |
728 | intel_dp->link_bw = bws[clock]; |
793 | intel_dp->link_bw = bws[clock]; |
729 | intel_dp->lane_count = lane_count; |
794 | intel_dp->lane_count = lane_count; |
730 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
795 | adjusted_mode->clock = link_bw_clock; |
731 | DRM_DEBUG_KMS("DP link bw %02x lane " |
796 | DRM_DEBUG_KMS("DP link bw %02x lane " |
Line 740... | Line 805... | ||
740 | } |
805 | } |
Line 741... | Line 806... | ||
741 | 806 | ||
742 | return false; |
807 | return false; |
Line 743... | Line -... | ||
743 | } |
- | |
744 | - | ||
745 | struct intel_dp_m_n { |
- | |
746 | uint32_t tu; |
- | |
747 | uint32_t gmch_m; |
- | |
748 | uint32_t gmch_n; |
- | |
749 | uint32_t link_m; |
- | |
750 | uint32_t link_n; |
- | |
751 | }; |
- | |
752 | - | ||
753 | static void |
- | |
754 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
- | |
755 | { |
- | |
756 | while (*num > 0xffffff || *den > 0xffffff) { |
- | |
757 | *num >>= 1; |
- | |
758 | *den >>= 1; |
- | |
759 | } |
- | |
760 | } |
- | |
761 | - | ||
762 | static void |
- | |
763 | intel_dp_compute_m_n(int bpp, |
- | |
764 | int nlanes, |
- | |
765 | int pixel_clock, |
- | |
766 | int link_clock, |
- | |
767 | struct intel_dp_m_n *m_n) |
- | |
768 | { |
- | |
769 | m_n->tu = 64; |
- | |
770 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
- | |
771 | m_n->gmch_n = link_clock * nlanes; |
- | |
772 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
- | |
773 | m_n->link_m = pixel_clock; |
- | |
774 | m_n->link_n = link_clock; |
- | |
775 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
- | |
776 | } |
808 | } |
777 | 809 | ||
778 | void |
810 | void |
779 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
811 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
780 | struct drm_display_mode *adjusted_mode) |
812 | struct drm_display_mode *adjusted_mode) |
781 | { |
813 | { |
782 | struct drm_device *dev = crtc->dev; |
814 | struct drm_device *dev = crtc->dev; |
783 | struct intel_encoder *intel_encoder; |
815 | struct intel_encoder *intel_encoder; |
784 | struct intel_dp *intel_dp; |
816 | struct intel_dp *intel_dp; |
785 | struct drm_i915_private *dev_priv = dev->dev_private; |
817 | struct drm_i915_private *dev_priv = dev->dev_private; |
786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
787 | int lane_count = 4; |
819 | int lane_count = 4; |
788 | struct intel_dp_m_n m_n; |
820 | struct intel_link_m_n m_n; |
- | 821 | int pipe = intel_crtc->pipe; |
|
Line 789... | Line 822... | ||
789 | int pipe = intel_crtc->pipe; |
822 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
790 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
823 | int target_clock; |
791 | 824 | ||
792 | /* |
825 | /* |
Line 801... | Line 834... | ||
801 | lane_count = intel_dp->lane_count; |
834 | lane_count = intel_dp->lane_count; |
802 | break; |
835 | break; |
803 | } |
836 | } |
804 | } |
837 | } |
Line -... | Line 838... | ||
- | 838 | ||
- | 839 | target_clock = mode->clock; |
|
- | 840 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
|
- | 841 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
|
- | 842 | target_clock = intel_edp_target_clock(intel_encoder, |
|
- | 843 | mode); |
|
- | 844 | break; |
|
- | 845 | } |
|
- | 846 | } |
|
805 | 847 | ||
806 | /* |
848 | /* |
807 | * Compute the GMCH and Link ratios. The '3' here is |
849 | * Compute the GMCH and Link ratios. The '3' here is |
808 | * the number of bytes_per_pixel post-LUT, which we always |
850 | * the number of bytes_per_pixel post-LUT, which we always |
809 | * set up for 8-bits of R/G/B, or 3 bytes total. |
851 | * set up for 8-bits of R/G/B, or 3 bytes total. |
810 | */ |
852 | */ |
811 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
853 | intel_link_compute_m_n(intel_crtc->bpp, lane_count, |
Line 812... | Line 854... | ||
812 | mode->clock, adjusted_mode->clock, &m_n); |
854 | target_clock, adjusted_mode->clock, &m_n); |
813 | 855 | ||
814 | if (IS_HASWELL(dev)) { |
856 | if (IS_HASWELL(dev)) { |
815 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
857 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
Line 849... | Line 891... | ||
849 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
891 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
850 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
892 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
851 | } |
893 | } |
852 | } |
894 | } |
Line -... | Line 895... | ||
- | 895 | ||
- | 896 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
|
- | 897 | { |
|
- | 898 | struct drm_device *dev = crtc->dev; |
|
- | 899 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 900 | u32 dpa_ctl; |
|
- | 901 | ||
- | 902 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
|
- | 903 | dpa_ctl = I915_READ(DP_A); |
|
- | 904 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
|
- | 905 | ||
- | 906 | if (clock < 200000) { |
|
- | 907 | /* For a long time we've carried around a ILK-DevA w/a for the |
|
- | 908 | * 160MHz clock. If we're really unlucky, it's still required. |
|
- | 909 | */ |
|
- | 910 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
|
- | 911 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
|
- | 912 | } else { |
|
- | 913 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
|
- | 914 | } |
|
- | 915 | ||
- | 916 | I915_WRITE(DP_A, dpa_ctl); |
|
- | 917 | ||
- | 918 | POSTING_READ(DP_A); |
|
- | 919 | udelay(500); |
|
- | 920 | } |
|
853 | 921 | ||
854 | static void |
922 | static void |
855 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
923 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
856 | struct drm_display_mode *adjusted_mode) |
924 | struct drm_display_mode *adjusted_mode) |
857 | { |
925 | { |
Line 924... | Line 992... | ||
924 | if (adjusted_mode->clock < 200000) |
992 | if (adjusted_mode->clock < 200000) |
925 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
993 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
926 | else |
994 | else |
927 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
995 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
928 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
996 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
- | 997 | if (!HAS_PCH_SPLIT(dev)) |
|
929 | intel_dp->DP |= intel_dp->color_range; |
998 | intel_dp->DP |= intel_dp->color_range; |
Line 930... | Line 999... | ||
930 | 999 | ||
931 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1000 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
932 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1001 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
Line 948... | Line 1017... | ||
948 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
1017 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
949 | } |
1018 | } |
950 | } else { |
1019 | } else { |
951 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1020 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
952 | } |
1021 | } |
- | 1022 | ||
- | 1023 | if (is_cpu_edp(intel_dp)) |
|
- | 1024 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
|
953 | } |
1025 | } |
Line 954... | Line 1026... | ||
954 | 1026 | ||
955 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1027 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
Line 1055... | Line 1127... | ||
1055 | { |
1127 | { |
1056 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1128 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1057 | struct drm_i915_private *dev_priv = dev->dev_private; |
1129 | struct drm_i915_private *dev_priv = dev->dev_private; |
1058 | u32 pp; |
1130 | u32 pp; |
Line -... | Line 1131... | ||
- | 1131 | ||
- | 1132 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
|
1059 | 1133 | ||
1060 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1134 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1061 | pp = ironlake_get_pp_control(dev_priv); |
1135 | pp = ironlake_get_pp_control(dev_priv); |
1062 | pp &= ~EDP_FORCE_VDD; |
1136 | pp &= ~EDP_FORCE_VDD; |
1063 | I915_WRITE(PCH_PP_CONTROL, pp); |
1137 | I915_WRITE(PCH_PP_CONTROL, pp); |
Line 1541... | Line 1615... | ||
1541 | for (lane = 0; lane < 4; lane++) |
1615 | for (lane = 0; lane < 4; lane++) |
1542 | intel_dp->train_set[lane] = v | p; |
1616 | intel_dp->train_set[lane] = v | p; |
1543 | } |
1617 | } |
Line 1544... | Line 1618... | ||
1544 | 1618 | ||
1545 | static uint32_t |
1619 | static uint32_t |
1546 | intel_dp_signal_levels(uint8_t train_set) |
1620 | intel_gen4_signal_levels(uint8_t train_set) |
1547 | { |
1621 | { |
Line 1548... | Line 1622... | ||
1548 | uint32_t signal_levels = 0; |
1622 | uint32_t signal_levels = 0; |
1549 | 1623 | ||
Line 1639... | Line 1713... | ||
1639 | } |
1713 | } |
1640 | } |
1714 | } |
Line 1641... | Line 1715... | ||
1641 | 1715 | ||
1642 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1716 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1643 | static uint32_t |
1717 | static uint32_t |
1644 | intel_dp_signal_levels_hsw(uint8_t train_set) |
1718 | intel_hsw_signal_levels(uint8_t train_set) |
1645 | { |
1719 | { |
1646 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1720 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1647 | DP_TRAIN_PRE_EMPHASIS_MASK); |
1721 | DP_TRAIN_PRE_EMPHASIS_MASK); |
1648 | switch (signal_levels) { |
1722 | switch (signal_levels) { |
Line 1671... | Line 1745... | ||
1671 | "0x%x\n", signal_levels); |
1745 | "0x%x\n", signal_levels); |
1672 | return DDI_BUF_EMP_400MV_0DB_HSW; |
1746 | return DDI_BUF_EMP_400MV_0DB_HSW; |
1673 | } |
1747 | } |
1674 | } |
1748 | } |
Line -... | Line 1749... | ||
- | 1749 | ||
- | 1750 | /* Properly updates "DP" with the correct signal levels. */ |
|
- | 1751 | static void |
|
- | 1752 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
|
- | 1753 | { |
|
- | 1754 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
|
- | 1755 | struct drm_device *dev = intel_dig_port->base.base.dev; |
|
- | 1756 | uint32_t signal_levels, mask; |
|
- | 1757 | uint8_t train_set = intel_dp->train_set[0]; |
|
- | 1758 | ||
- | 1759 | if (IS_HASWELL(dev)) { |
|
- | 1760 | signal_levels = intel_hsw_signal_levels(train_set); |
|
- | 1761 | mask = DDI_BUF_EMP_MASK; |
|
- | 1762 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
|
- | 1763 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
|
- | 1764 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
|
- | 1765 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
|
- | 1766 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
|
- | 1767 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
|
- | 1768 | } else { |
|
- | 1769 | signal_levels = intel_gen4_signal_levels(train_set); |
|
- | 1770 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
|
- | 1771 | } |
|
- | 1772 | ||
- | 1773 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
|
- | 1774 | ||
- | 1775 | *DP = (*DP & ~mask) | signal_levels; |
|
- | 1776 | } |
|
1675 | 1777 | ||
1676 | static bool |
1778 | static bool |
1677 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
1779 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
1678 | uint32_t dp_reg_value, |
1780 | uint32_t dp_reg_value, |
1679 | uint8_t dp_train_pat) |
1781 | uint8_t dp_train_pat) |
Line 1694... | Line 1796... | ||
1694 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
1796 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
Line 1695... | Line 1797... | ||
1695 | 1797 | ||
1696 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
1798 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
1697 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
1799 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
- | 1800 | case DP_TRAINING_PATTERN_DISABLE: |
|
- | 1801 | ||
1698 | case DP_TRAINING_PATTERN_DISABLE: |
1802 | if (port != PORT_A) { |
1699 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
1803 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
Line 1700... | Line 1804... | ||
1700 | I915_WRITE(DP_TP_CTL(port), temp); |
1804 | I915_WRITE(DP_TP_CTL(port), temp); |
1701 | 1805 | ||
1702 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & |
1806 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & |
Line 1703... | Line 1807... | ||
1703 | DP_TP_STATUS_IDLE_DONE), 1)) |
1807 | DP_TP_STATUS_IDLE_DONE), 1)) |
- | 1808 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
|
- | 1809 | ||
1704 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
1810 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
Line 1705... | Line 1811... | ||
1705 | 1811 | } |
|
1706 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
1812 | |
1707 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
1813 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
Line 1789... | Line 1895... | ||
1789 | uint8_t voltage; |
1895 | uint8_t voltage; |
1790 | bool clock_recovery = false; |
1896 | bool clock_recovery = false; |
1791 | int voltage_tries, loop_tries; |
1897 | int voltage_tries, loop_tries; |
1792 | uint32_t DP = intel_dp->DP; |
1898 | uint32_t DP = intel_dp->DP; |
Line 1793... | Line 1899... | ||
1793 | 1899 | ||
1794 | if (IS_HASWELL(dev)) |
1900 | if (HAS_DDI(dev)) |
Line 1795... | Line 1901... | ||
1795 | intel_ddi_prepare_link_retrain(encoder); |
1901 | intel_ddi_prepare_link_retrain(encoder); |
1796 | 1902 | ||
1797 | /* Write the link configuration data */ |
1903 | /* Write the link configuration data */ |
Line 1807... | Line 1913... | ||
1807 | loop_tries = 0; |
1913 | loop_tries = 0; |
1808 | clock_recovery = false; |
1914 | clock_recovery = false; |
1809 | for (;;) { |
1915 | for (;;) { |
1810 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
1916 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
1811 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1917 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1812 | uint32_t signal_levels; |
- | |
Line 1813... | Line -... | ||
1813 | - | ||
1814 | if (IS_HASWELL(dev)) { |
- | |
1815 | signal_levels = intel_dp_signal_levels_hsw( |
- | |
1816 | intel_dp->train_set[0]); |
- | |
1817 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
- | |
1818 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
- | |
1819 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
- | |
1820 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
- | |
1821 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
- | |
1822 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
- | |
1823 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
- | |
1824 | } else { |
1918 | |
1825 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
- | |
1826 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
- | |
1827 | } |
- | |
1828 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", |
- | |
Line 1829... | Line 1919... | ||
1829 | signal_levels); |
1919 | intel_dp_set_signal_levels(intel_dp, &DP); |
1830 | 1920 | ||
1831 | /* Set training pattern 1 */ |
1921 | /* Set training pattern 1 */ |
1832 | if (!intel_dp_set_link_train(intel_dp, DP, |
1922 | if (!intel_dp_set_link_train(intel_dp, DP, |
Line 1848... | Line 1938... | ||
1848 | 1938 | ||
1849 | /* Check to see if we've tried the max voltage */ |
1939 | /* Check to see if we've tried the max voltage */ |
1850 | for (i = 0; i < intel_dp->lane_count; i++) |
1940 | for (i = 0; i < intel_dp->lane_count; i++) |
1851 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
1941 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
1852 | break; |
1942 | break; |
1853 | if (i == intel_dp->lane_count && voltage_tries == 5) { |
1943 | if (i == intel_dp->lane_count) { |
1854 | ++loop_tries; |
1944 | ++loop_tries; |
1855 | if (loop_tries == 5) { |
1945 | if (loop_tries == 5) { |
1856 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
1946 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
1857 | break; |
1947 | break; |
Line 1880... | Line 1970... | ||
1880 | } |
1970 | } |
Line 1881... | Line 1971... | ||
1881 | 1971 | ||
1882 | void |
1972 | void |
1883 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1973 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1884 | { |
- | |
1885 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1974 | { |
1886 | bool channel_eq = false; |
1975 | bool channel_eq = false; |
1887 | int tries, cr_tries; |
1976 | int tries, cr_tries; |
Line 1888... | Line 1977... | ||
1888 | uint32_t DP = intel_dp->DP; |
1977 | uint32_t DP = intel_dp->DP; |
1889 | 1978 | ||
1890 | /* channel equalization */ |
1979 | /* channel equalization */ |
1891 | tries = 0; |
1980 | tries = 0; |
1892 | cr_tries = 0; |
1981 | cr_tries = 0; |
1893 | channel_eq = false; |
- | |
1894 | for (;;) { |
- | |
1895 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
1982 | channel_eq = false; |
Line 1896... | Line 1983... | ||
1896 | uint32_t signal_levels; |
1983 | for (;;) { |
1897 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1984 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1898 | 1985 | ||
1899 | if (cr_tries > 5) { |
1986 | if (cr_tries > 5) { |
1900 | DRM_ERROR("failed to train DP, aborting\n"); |
1987 | DRM_ERROR("failed to train DP, aborting\n"); |
Line 1901... | Line -... | ||
1901 | intel_dp_link_down(intel_dp); |
- | |
1902 | break; |
- | |
1903 | } |
- | |
1904 | - | ||
1905 | if (IS_HASWELL(dev)) { |
- | |
1906 | signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); |
- | |
1907 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
- | |
1908 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
- | |
1909 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
- | |
1910 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
- | |
1911 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
1988 | intel_dp_link_down(intel_dp); |
1912 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
- | |
1913 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
- | |
Line 1914... | Line 1989... | ||
1914 | } else { |
1989 | break; |
1915 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1990 | } |
1916 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1991 | |
1917 | } |
1992 | intel_dp_set_signal_levels(intel_dp, &DP); |
Line 1962... | Line 2037... | ||
1962 | intel_dp_link_down(struct intel_dp *intel_dp) |
2037 | intel_dp_link_down(struct intel_dp *intel_dp) |
1963 | { |
2038 | { |
1964 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2039 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1965 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2040 | struct drm_device *dev = intel_dig_port->base.base.dev; |
1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
2041 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 2042 | struct intel_crtc *intel_crtc = |
|
- | 2043 | to_intel_crtc(intel_dig_port->base.base.crtc); |
|
1967 | uint32_t DP = intel_dp->DP; |
2044 | uint32_t DP = intel_dp->DP; |
Line 1968... | Line 2045... | ||
1968 | 2045 | ||
1969 | /* |
2046 | /* |
1970 | * DDI code has a strict mode set sequence and we should try to respect |
2047 | * DDI code has a strict mode set sequence and we should try to respect |
Line 1979... | Line 2056... | ||
1979 | * called us. We don't need to disable the whole port on this case, so |
2056 | * called us. We don't need to disable the whole port on this case, so |
1980 | * when someone turns the monitor on again, |
2057 | * when someone turns the monitor on again, |
1981 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
2058 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
1982 | * train. |
2059 | * train. |
1983 | */ |
2060 | */ |
1984 | if (IS_HASWELL(dev)) |
2061 | if (HAS_DDI(dev)) |
1985 | return; |
2062 | return; |
Line 1986... | Line 2063... | ||
1986 | 2063 | ||
1987 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2064 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Line 1996... | Line 2073... | ||
1996 | DP &= ~DP_LINK_TRAIN_MASK; |
2073 | DP &= ~DP_LINK_TRAIN_MASK; |
1997 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
2074 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
1998 | } |
2075 | } |
1999 | POSTING_READ(intel_dp->output_reg); |
2076 | POSTING_READ(intel_dp->output_reg); |
Line -... | Line 2077... | ||
- | 2077 | ||
2000 | 2078 | /* We don't really know why we're doing this */ |
|
Line 2001... | Line 2079... | ||
2001 | msleep(17); |
2079 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2002 | 2080 | ||
2003 | if (HAS_PCH_IBX(dev) && |
2081 | if (HAS_PCH_IBX(dev) && |
Line 2016... | Line 2094... | ||
2016 | I915_WRITE(intel_dp->output_reg, DP); |
2094 | I915_WRITE(intel_dp->output_reg, DP); |
Line 2017... | Line 2095... | ||
2017 | 2095 | ||
2018 | /* Changes to enable or select take place the vblank |
2096 | /* Changes to enable or select take place the vblank |
2019 | * after being written. |
2097 | * after being written. |
2020 | */ |
2098 | */ |
2021 | if (crtc == NULL) { |
2099 | if (WARN_ON(crtc == NULL)) { |
2022 | /* We can arrive here never having been attached |
2100 | /* We should never try to disable a port without a crtc |
2023 | * to a CRTC, for instance, due to inheriting |
- | |
2024 | * random state from the BIOS. |
- | |
2025 | * |
- | |
2026 | * If the pipe is not running, play safe and |
- | |
2027 | * wait for the clocks to stabilise before |
2101 | * attached. For paranoia keep the code around for a |
2028 | * continuing. |
- | |
2029 | */ |
2102 | * bit. */ |
2030 | POSTING_READ(intel_dp->output_reg); |
2103 | POSTING_READ(intel_dp->output_reg); |
2031 | msleep(50); |
2104 | msleep(50); |
2032 | } else |
2105 | } else |
2033 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
2106 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Line 2034... | Line 2107... | ||
2034 | } |
2107 | } |
2035 | 2108 | ||
2036 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
2109 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
Line 2040... | Line 2113... | ||
2040 | } |
2113 | } |
Line 2041... | Line 2114... | ||
2041 | 2114 | ||
2042 | static bool |
2115 | static bool |
2043 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
2116 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
- | 2117 | { |
|
- | 2118 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
|
2044 | { |
2119 | |
2045 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
2120 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
2046 | sizeof(intel_dp->dpcd)) == 0) |
2121 | sizeof(intel_dp->dpcd)) == 0) |
Line -... | Line 2122... | ||
- | 2122 | return false; /* aux transfer failed */ |
|
- | 2123 | ||
- | 2124 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
|
- | 2125 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
|
2047 | return false; /* aux transfer failed */ |
2126 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
2048 | 2127 | ||
Line 2049... | Line 2128... | ||
2049 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2128 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2050 | return false; /* DPCD not present */ |
2129 | return false; /* DPCD not present */ |
Line 2204... | Line 2283... | ||
2204 | 2283 | ||
2205 | static enum drm_connector_status |
2284 | static enum drm_connector_status |
2206 | ironlake_dp_detect(struct intel_dp *intel_dp) |
2285 | ironlake_dp_detect(struct intel_dp *intel_dp) |
2207 | { |
2286 | { |
- | 2287 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
|
- | 2288 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
2208 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Line 2209... | Line 2290... | ||
2209 | enum drm_connector_status status; |
2290 | enum drm_connector_status status; |
2210 | 2291 | ||
2211 | /* Can't disconnect eDP, but you can close the lid... */ |
2292 | /* Can't disconnect eDP, but you can close the lid... */ |
2212 | if (is_edp(intel_dp)) { |
2293 | if (is_edp(intel_dp)) { |
2213 | status = intel_panel_detect(dev); |
2294 | status = intel_panel_detect(dev); |
2214 | if (status == connector_status_unknown) |
2295 | if (status == connector_status_unknown) |
2215 | status = connector_status_connected; |
2296 | status = connector_status_connected; |
Line -... | Line 2297... | ||
- | 2297 | return status; |
|
- | 2298 | } |
|
- | 2299 | ||
2216 | return status; |
2300 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
2217 | } |
2301 | return connector_status_disconnected; |
Line 2218... | Line 2302... | ||
2218 | 2302 | ||
2219 | return intel_dp_detect_dpcd(intel_dp); |
2303 | return intel_dp_detect_dpcd(intel_dp); |
2220 | } |
2304 | } |
2221 | 2305 | ||
2222 | static enum drm_connector_status |
2306 | static enum drm_connector_status |
- | 2307 | g4x_dp_detect(struct intel_dp *intel_dp) |
|
2223 | g4x_dp_detect(struct intel_dp *intel_dp) |
2308 | { |
Line 2224... | Line 2309... | ||
2224 | { |
2309 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2225 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
2226 | struct drm_i915_private *dev_priv = dev->dev_private; |
2311 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2227 | uint32_t bit; |
2312 | uint32_t bit; |
2228 | 2313 | ||
2229 | switch (intel_dp->output_reg) { |
2314 | switch (intel_dig_port->port) { |
2230 | case DP_B: |
2315 | case PORT_B: |
2231 | bit = DPB_HOTPLUG_LIVE_STATUS; |
2316 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
2232 | break; |
2317 | break; |
2233 | case DP_C: |
2318 | case PORT_C: |
2234 | bit = DPC_HOTPLUG_LIVE_STATUS; |
2319 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
2235 | break; |
2320 | break; |
2236 | case DP_D: |
2321 | case PORT_D: |
Line 2288... | Line 2373... | ||
2288 | } |
2373 | } |
Line 2289... | Line 2374... | ||
2289 | 2374 | ||
2290 | return intel_ddc_get_modes(connector, adapter); |
2375 | return intel_ddc_get_modes(connector, adapter); |
Line 2291... | Line -... | ||
2291 | } |
- | |
2292 | - | ||
2293 | - | ||
2294 | /** |
- | |
2295 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
- | |
2296 | * |
- | |
2297 | * \return true if DP port is connected. |
- | |
2298 | * \return false if DP port is disconnected. |
2376 | } |
2299 | */ |
2377 | |
2300 | static enum drm_connector_status |
2378 | static enum drm_connector_status |
2301 | intel_dp_detect(struct drm_connector *connector, bool force) |
2379 | intel_dp_detect(struct drm_connector *connector, bool force) |
2302 | { |
2380 | { |
2303 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2381 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2304 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2382 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2305 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2383 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2306 | struct drm_device *dev = connector->dev; |
2384 | struct drm_device *dev = connector->dev; |
2307 | enum drm_connector_status status; |
- | |
Line 2308... | Line 2385... | ||
2308 | struct edid *edid = NULL; |
2385 | enum drm_connector_status status; |
Line 2309... | Line 2386... | ||
2309 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2386 | struct edid *edid = NULL; |
2310 | 2387 | ||
2311 | intel_dp->has_audio = false; |
2388 | intel_dp->has_audio = false; |
2312 | 2389 | ||
Line 2313... | Line -... | ||
2313 | if (HAS_PCH_SPLIT(dev)) |
- | |
2314 | status = ironlake_dp_detect(intel_dp); |
- | |
2315 | else |
- | |
2316 | status = g4x_dp_detect(intel_dp); |
- | |
2317 | 2390 | if (HAS_PCH_SPLIT(dev)) |
|
2318 | // hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2391 | status = ironlake_dp_detect(intel_dp); |
Line 2319... | Line 2392... | ||
2319 | // 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
2392 | else |
Line 2394... | Line 2467... | ||
2394 | int ret; |
2467 | int ret; |
Line 2395... | Line 2468... | ||
2395 | 2468 | ||
2396 | ret = drm_object_property_set_value(&connector->base, property, val); |
2469 | ret = drm_object_property_set_value(&connector->base, property, val); |
2397 | if (ret) |
2470 | if (ret) |
2398 | return ret; |
2471 | return ret; |
2399 | #if 0 |
2472 | |
2400 | if (property == dev_priv->force_audio_property) { |
2473 | if (property == dev_priv->force_audio_property) { |
2401 | int i = val; |
2474 | int i = val; |
Line 2402... | Line 2475... | ||
2402 | bool has_audio; |
2475 | bool has_audio; |
Line 2417... | Line 2490... | ||
2417 | intel_dp->has_audio = has_audio; |
2490 | intel_dp->has_audio = has_audio; |
2418 | goto done; |
2491 | goto done; |
2419 | } |
2492 | } |
Line 2420... | Line 2493... | ||
2420 | 2493 | ||
- | 2494 | if (property == dev_priv->broadcast_rgb_property) { |
|
- | 2495 | switch (val) { |
|
2421 | if (property == dev_priv->broadcast_rgb_property) { |
2496 | case INTEL_BROADCAST_RGB_AUTO: |
2422 | if (val == !!intel_dp->color_range) |
2497 | intel_dp->color_range_auto = true; |
- | 2498 | break; |
|
- | 2499 | case INTEL_BROADCAST_RGB_FULL: |
|
- | 2500 | intel_dp->color_range_auto = false; |
|
2423 | return 0; |
2501 | intel_dp->color_range = 0; |
- | 2502 | break; |
|
- | 2503 | case INTEL_BROADCAST_RGB_LIMITED: |
|
2424 | 2504 | intel_dp->color_range_auto = false; |
|
- | 2505 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
|
- | 2506 | break; |
|
- | 2507 | default: |
|
- | 2508 | return -EINVAL; |
|
2425 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
2509 | } |
2426 | goto done; |
2510 | goto done; |
2427 | } |
- | |
Line 2428... | Line 2511... | ||
2428 | #endif |
2511 | } |
2429 | 2512 | ||
2430 | if (is_edp(intel_dp) && |
2513 | if (is_edp(intel_dp) && |
2431 | property == connector->dev->mode_config.scaling_mode_property) { |
2514 | property == connector->dev->mode_config.scaling_mode_property) { |
Line 2444... | Line 2527... | ||
2444 | } |
2527 | } |
Line 2445... | Line 2528... | ||
2445 | 2528 | ||
Line 2446... | Line 2529... | ||
2446 | return -EINVAL; |
2529 | return -EINVAL; |
2447 | 2530 | ||
2448 | done: |
2531 | done: |
2449 | if (intel_encoder->base.crtc) { |
- | |
2450 | struct drm_crtc *crtc = intel_encoder->base.crtc; |
- | |
2451 | intel_set_mode(crtc, &crtc->mode, |
- | |
Line 2452... | Line 2532... | ||
2452 | crtc->x, crtc->y, crtc->fb); |
2532 | if (intel_encoder->base.crtc) |
2453 | } |
2533 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Line 2454... | Line 2534... | ||
2454 | 2534 | ||
Line 2477... | Line 2557... | ||
2477 | 2557 | ||
2478 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2558 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2479 | { |
2559 | { |
2480 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2560 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
- | 2561 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
|
Line 2481... | Line 2562... | ||
2481 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
2562 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2482 | 2563 | ||
2483 | i2c_del_adapter(&intel_dp->adapter); |
2564 | i2c_del_adapter(&intel_dp->adapter); |
2484 | drm_encoder_cleanup(encoder); |
2565 | drm_encoder_cleanup(encoder); |
- | 2566 | if (is_edp(intel_dp)) { |
|
2485 | if (is_edp(intel_dp)) { |
2567 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
- | 2568 | mutex_lock(&dev->mode_config.mutex); |
|
2486 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
2569 | ironlake_panel_vdd_off_sync(intel_dp); |
2487 | ironlake_panel_vdd_off_sync(intel_dp); |
2570 | mutex_unlock(&dev->mode_config.mutex); |
2488 | } |
2571 | } |
Line 2489... | Line 2572... | ||
2489 | kfree(intel_dig_port); |
2572 | kfree(intel_dig_port); |
2490 | } |
2573 | } |
2491 | 2574 | ||
2492 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
- | |
2493 | .mode_fixup = intel_dp_mode_fixup, |
2575 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
Line 2494... | Line 2576... | ||
2494 | .mode_set = intel_dp_mode_set, |
2576 | .mode_fixup = intel_dp_mode_fixup, |
2495 | .disable = intel_encoder_noop, |
2577 | .mode_set = intel_dp_mode_set, |
2496 | }; |
2578 | }; |
Line 2565... | Line 2647... | ||
2565 | { |
2647 | { |
2566 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2648 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Line 2567... | Line 2649... | ||
2567 | 2649 | ||
2568 | intel_attach_force_audio_property(connector); |
2650 | intel_attach_force_audio_property(connector); |
- | 2651 | intel_attach_broadcast_rgb_property(connector); |
|
Line 2569... | Line 2652... | ||
2569 | intel_attach_broadcast_rgb_property(connector); |
2652 | intel_dp->color_range_auto = true; |
2570 | 2653 | ||
2571 | if (is_edp(intel_dp)) { |
2654 | if (is_edp(intel_dp)) { |
2572 | drm_mode_create_scaling_mode_property(connector->dev); |
2655 | drm_mode_create_scaling_mode_property(connector->dev); |
Line 2754... | Line 2837... | ||
2754 | ironlake_panel_vdd_work); |
2837 | ironlake_panel_vdd_work); |
Line 2755... | Line 2838... | ||
2755 | 2838 | ||
2756 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
2839 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Line 2757... | Line 2840... | ||
2757 | drm_sysfs_connector_add(connector); |
2840 | drm_sysfs_connector_add(connector); |
2758 | 2841 | ||
2759 | if (IS_HASWELL(dev)) |
2842 | if (HAS_DDI(dev)) |
2760 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2843 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
Line 2766... | Line 2849... | ||
2766 | switch (port) { |
2849 | switch (port) { |
2767 | case PORT_A: |
2850 | case PORT_A: |
2768 | name = "DPDDC-A"; |
2851 | name = "DPDDC-A"; |
2769 | break; |
2852 | break; |
2770 | case PORT_B: |
2853 | case PORT_B: |
2771 | dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; |
2854 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
2772 | name = "DPDDC-B"; |
2855 | name = "DPDDC-B"; |
2773 | break; |
2856 | break; |
2774 | case PORT_C: |
2857 | case PORT_C: |
2775 | dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; |
2858 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
2776 | name = "DPDDC-C"; |
2859 | name = "DPDDC-C"; |
2777 | break; |
2860 | break; |
2778 | case PORT_D: |
2861 | case PORT_D: |
2779 | dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; |
2862 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
2780 | name = "DPDDC-D"; |
2863 | name = "DPDDC-D"; |
2781 | break; |
2864 | break; |
2782 | default: |
2865 | default: |
2783 | WARN(1, "Invalid port %c\n", port_name(port)); |
2866 | WARN(1, "Invalid port %c\n", port_name(port)); |
2784 | break; |
2867 | break; |