Rev 6937 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 6937 | Rev 7144 | ||
---|---|---|---|
Line 83... | Line 83... | ||
83 | /* Cursor formats */ |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { |
84 | static const uint32_t intel_cursor_formats[] = { |
85 | DRM_FORMAT_ARGB8888, |
85 | DRM_FORMAT_ARGB8888, |
86 | }; |
86 | }; |
Line 87... | Line -... | ||
87 | - | ||
88 | void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
- | |
89 | 87 | ||
90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
91 | struct intel_crtc_state *pipe_config); |
89 | struct intel_crtc_state *pipe_config); |
92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
Line 1150... | Line 1148... | ||
1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
1151 | WARN(1, "pipe_off wait timed out\n"); |
1149 | WARN(1, "pipe_off wait timed out\n"); |
1152 | } |
1150 | } |
1153 | } |
1151 | } |
Line 1154... | Line -... | ||
1154 | - | ||
1155 | static const char *state_string(bool enabled) |
- | |
1156 | { |
- | |
1157 | return enabled ? "on" : "off"; |
- | |
1158 | } |
- | |
1159 | 1152 | ||
1160 | /* Only for pre-ILK configs */ |
1153 | /* Only for pre-ILK configs */ |
1161 | void assert_pll(struct drm_i915_private *dev_priv, |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1162 | enum pipe pipe, bool state) |
1155 | enum pipe pipe, bool state) |
1163 | { |
1156 | { |
Line 1166... | Line 1159... | ||
1166 | 1159 | ||
1167 | val = I915_READ(DPLL(pipe)); |
1160 | val = I915_READ(DPLL(pipe)); |
1168 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
1169 | I915_STATE_WARN(cur_state != state, |
1162 | I915_STATE_WARN(cur_state != state, |
1170 | "PLL state assertion failure (expected %s, current %s)\n", |
1163 | "PLL state assertion failure (expected %s, current %s)\n", |
1171 | state_string(state), state_string(cur_state)); |
1164 | onoff(state), onoff(cur_state)); |
Line 1172... | Line 1165... | ||
1172 | } |
1165 | } |
1173 | 1166 | ||
1174 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
Line 1182... | Line 1175... | ||
1182 | mutex_unlock(&dev_priv->sb_lock); |
1175 | mutex_unlock(&dev_priv->sb_lock); |
Line 1183... | Line 1176... | ||
1183 | 1176 | ||
1184 | cur_state = val & DSI_PLL_VCO_EN; |
1177 | cur_state = val & DSI_PLL_VCO_EN; |
1185 | I915_STATE_WARN(cur_state != state, |
1178 | I915_STATE_WARN(cur_state != state, |
1186 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1187 | state_string(state), state_string(cur_state)); |
1180 | onoff(state), onoff(cur_state)); |
1188 | } |
1181 | } |
1189 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
Line 1190... | Line 1183... | ||
1190 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
Line 1206... | Line 1199... | ||
1206 | bool state) |
1199 | bool state) |
1207 | { |
1200 | { |
1208 | bool cur_state; |
1201 | bool cur_state; |
1209 | struct intel_dpll_hw_state hw_state; |
1202 | struct intel_dpll_hw_state hw_state; |
Line 1210... | Line -... | ||
1210 | - | ||
1211 | if (WARN (!pll, |
1203 | |
1212 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
Line 1213... | Line 1205... | ||
1213 | return; |
1205 | return; |
1214 | 1206 | ||
1215 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
1216 | I915_STATE_WARN(cur_state != state, |
1208 | I915_STATE_WARN(cur_state != state, |
1217 | "%s assertion failure (expected %s, current %s)\n", |
1209 | "%s assertion failure (expected %s, current %s)\n", |
Line 1218... | Line 1210... | ||
1218 | pll->name, state_string(state), state_string(cur_state)); |
1210 | pll->name, onoff(state), onoff(cur_state)); |
1219 | } |
1211 | } |
1220 | 1212 | ||
Line 1233... | Line 1225... | ||
1233 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
1234 | cur_state = !!(val & FDI_TX_ENABLE); |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1235 | } |
1227 | } |
1236 | I915_STATE_WARN(cur_state != state, |
1228 | I915_STATE_WARN(cur_state != state, |
1237 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1238 | state_string(state), state_string(cur_state)); |
1230 | onoff(state), onoff(cur_state)); |
1239 | } |
1231 | } |
1240 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
1241 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
Line 1242... | Line 1234... | ||
1242 | 1234 | ||
Line 1248... | Line 1240... | ||
1248 | 1240 | ||
1249 | val = I915_READ(FDI_RX_CTL(pipe)); |
1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
1250 | cur_state = !!(val & FDI_RX_ENABLE); |
1242 | cur_state = !!(val & FDI_RX_ENABLE); |
1251 | I915_STATE_WARN(cur_state != state, |
1243 | I915_STATE_WARN(cur_state != state, |
1252 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1253 | state_string(state), state_string(cur_state)); |
1245 | onoff(state), onoff(cur_state)); |
1254 | } |
1246 | } |
1255 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
Line 1256... | Line 1248... | ||
1256 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
Line 1280... | Line 1272... | ||
1280 | 1272 | ||
1281 | val = I915_READ(FDI_RX_CTL(pipe)); |
1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
1282 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1283 | I915_STATE_WARN(cur_state != state, |
1275 | I915_STATE_WARN(cur_state != state, |
1284 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1285 | state_string(state), state_string(cur_state)); |
1277 | onoff(state), onoff(cur_state)); |
Line 1286... | Line 1278... | ||
1286 | } |
1278 | } |
1287 | 1279 | ||
1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
Line 1338... | Line 1330... | ||
1338 | else |
1330 | else |
1339 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Line 1340... | Line 1332... | ||
1340 | 1332 | ||
1341 | I915_STATE_WARN(cur_state != state, |
1333 | I915_STATE_WARN(cur_state != state, |
1342 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
1344 | } |
1336 | } |
1345 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
Line 1346... | Line 1338... | ||
1346 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
Line 1368... | Line 1360... | ||
1368 | cur_state = false; |
1360 | cur_state = false; |
1369 | } |
1361 | } |
Line 1370... | Line 1362... | ||
1370 | 1362 | ||
1371 | I915_STATE_WARN(cur_state != state, |
1363 | I915_STATE_WARN(cur_state != state, |
1372 | "pipe %c assertion failure (expected %s, current %s)\n", |
1364 | "pipe %c assertion failure (expected %s, current %s)\n", |
1373 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
1365 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
Line 1374... | Line 1366... | ||
1374 | } |
1366 | } |
1375 | 1367 | ||
1376 | static void assert_plane(struct drm_i915_private *dev_priv, |
1368 | static void assert_plane(struct drm_i915_private *dev_priv, |
Line 1381... | Line 1373... | ||
1381 | 1373 | ||
1382 | val = I915_READ(DSPCNTR(plane)); |
1374 | val = I915_READ(DSPCNTR(plane)); |
1383 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1375 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1384 | I915_STATE_WARN(cur_state != state, |
1376 | I915_STATE_WARN(cur_state != state, |
1385 | "plane %c assertion failure (expected %s, current %s)\n", |
1377 | "plane %c assertion failure (expected %s, current %s)\n", |
1386 | plane_name(plane), state_string(state), state_string(cur_state)); |
1378 | plane_name(plane), onoff(state), onoff(cur_state)); |
Line 1387... | Line 1379... | ||
1387 | } |
1379 | } |
1388 | 1380 | ||
Line 2154... | Line 2146... | ||
2154 | return; |
2146 | return; |
2155 | } |
2147 | } |
Line 2156... | Line 2148... | ||
2156 | 2148 | ||
2157 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
2149 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
- | 2150 | POSTING_READ(reg); |
|
- | 2151 | ||
- | 2152 | /* |
|
- | 2153 | * Until the pipe starts DSL will read as 0, which would cause |
|
- | 2154 | * an apparent vblank timestamp jump, which messes up also the |
|
- | 2155 | * frame count when it's derived from the timestamps. So let's |
|
- | 2156 | * wait for the pipe to start properly before we call |
|
- | 2157 | * drm_crtc_vblank_on() |
|
- | 2158 | */ |
|
- | 2159 | if (dev->max_vblank_count == 0 && |
|
- | 2160 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) |
|
2158 | POSTING_READ(reg); |
2161 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); |
Line 2159... | Line 2162... | ||
2159 | } |
2162 | } |
2160 | 2163 | ||
2161 | /** |
2164 | /** |
Line 2215... | Line 2218... | ||
2215 | return true; |
2218 | return true; |
2216 | #endif |
2219 | #endif |
2217 | return false; |
2220 | return false; |
2218 | } |
2221 | } |
Line 2219... | Line -... | ||
2219 | - | ||
2220 | unsigned int |
2222 | |
2221 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
- | |
2222 | uint64_t fb_format_modifier, unsigned int plane) |
2223 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2223 | { |
2224 | { |
2224 | unsigned int tile_height; |
- | |
- | 2225 | return IS_GEN2(dev_priv) ? 2048 : 4096; |
|
Line -... | Line 2226... | ||
- | 2226 | } |
|
- | 2227 | ||
- | 2228 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
|
2225 | uint32_t pixel_bytes; |
2229 | uint64_t fb_modifier, unsigned int cpp) |
2226 | 2230 | { |
|
2227 | switch (fb_format_modifier) { |
- | |
2228 | case DRM_FORMAT_MOD_NONE: |
2231 | switch (fb_modifier) { |
2229 | tile_height = 1; |
2232 | case DRM_FORMAT_MOD_NONE: |
2230 | break; |
2233 | return cpp; |
- | 2234 | case I915_FORMAT_MOD_X_TILED: |
|
2231 | case I915_FORMAT_MOD_X_TILED: |
2235 | if (IS_GEN2(dev_priv)) |
- | 2236 | return 128; |
|
2232 | tile_height = IS_GEN2(dev) ? 16 : 8; |
2237 | else |
- | 2238 | return 512; |
|
2233 | break; |
2239 | case I915_FORMAT_MOD_Y_TILED: |
2234 | case I915_FORMAT_MOD_Y_TILED: |
2240 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) |
- | 2241 | return 128; |
|
2235 | tile_height = 32; |
2242 | else |
2236 | break; |
- | |
2237 | case I915_FORMAT_MOD_Yf_TILED: |
2243 | return 512; |
2238 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
- | |
2239 | switch (pixel_bytes) { |
2244 | case I915_FORMAT_MOD_Yf_TILED: |
2240 | default: |
- | |
2241 | case 1: |
2245 | switch (cpp) { |
2242 | tile_height = 64; |
2246 | case 1: |
2243 | break; |
2247 | return 64; |
2244 | case 2: |
- | |
2245 | case 4: |
2248 | case 2: |
2246 | tile_height = 32; |
2249 | case 4: |
2247 | break; |
- | |
2248 | case 8: |
- | |
2249 | tile_height = 16; |
2250 | return 128; |
2250 | break; |
2251 | case 8: |
2251 | case 16: |
2252 | case 16: |
2252 | WARN_ONCE(1, |
2253 | return 256; |
2253 | "128-bit pixels are not supported for display!"); |
2254 | default: |
2254 | tile_height = 16; |
2255 | MISSING_CASE(cpp); |
2255 | break; |
2256 | return cpp; |
2256 | } |
2257 | } |
2257 | break; |
2258 | break; |
2258 | default: |
2259 | default: |
2259 | MISSING_CASE(fb_format_modifier); |
2260 | MISSING_CASE(fb_modifier); |
2260 | tile_height = 1; |
2261 | return cpp; |
Line -... | Line 2262... | ||
- | 2262 | } |
|
- | 2263 | } |
|
- | 2264 | ||
- | 2265 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
|
2261 | break; |
2266 | uint64_t fb_modifier, unsigned int cpp) |
- | 2267 | { |
|
- | 2268 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
|
- | 2269 | return 1; |
|
2262 | } |
2270 | else |
Line 2263... | Line 2271... | ||
2263 | 2271 | return intel_tile_size(dev_priv) / |
|
2264 | return tile_height; |
2272 | intel_tile_width(dev_priv, fb_modifier, cpp); |
2265 | } |
2273 | } |
2266 | 2274 | ||
- | 2275 | unsigned int |
|
2267 | unsigned int |
2276 | intel_fb_align_height(struct drm_device *dev, unsigned int height, |
- | 2277 | uint32_t pixel_format, uint64_t fb_modifier) |
|
2268 | intel_fb_align_height(struct drm_device *dev, unsigned int height, |
2278 | { |
2269 | uint32_t pixel_format, uint64_t fb_format_modifier) |
2279 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
Line 2270... | Line 2280... | ||
2270 | { |
2280 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); |
2271 | return ALIGN(height, intel_tile_height(dev, pixel_format, |
2281 | |
2272 | fb_format_modifier, 0)); |
2282 | return ALIGN(height, tile_height); |
2273 | } |
2283 | } |
- | 2284 | ||
2274 | 2285 | static void |
|
2275 | static void |
2286 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
Line 2276... | Line 2287... | ||
2276 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2287 | const struct drm_plane_state *plane_state) |
Line 2277... | Line 2288... | ||
2277 | const struct drm_plane_state *plane_state) |
2288 | { |
2278 | { |
2289 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
Line 2293... | Line 2304... | ||
2293 | info->pixel_format = fb->pixel_format; |
2304 | info->pixel_format = fb->pixel_format; |
2294 | info->pitch = fb->pitches[0]; |
2305 | info->pitch = fb->pitches[0]; |
2295 | info->uv_offset = fb->offsets[1]; |
2306 | info->uv_offset = fb->offsets[1]; |
2296 | info->fb_modifier = fb->modifier[0]; |
2307 | info->fb_modifier = fb->modifier[0]; |
Line 2297... | Line 2308... | ||
2297 | 2308 | ||
- | 2309 | tile_size = intel_tile_size(dev_priv); |
|
- | 2310 | ||
2298 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
2311 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2299 | fb->modifier[0], 0); |
2312 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
- | 2313 | tile_height = tile_size / tile_width; |
|
2300 | tile_pitch = PAGE_SIZE / tile_height; |
2314 | |
2301 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
2315 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); |
2302 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
2316 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
Line 2303... | Line 2317... | ||
2303 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; |
2317 | info->size = info->width_pages * info->height_pages * tile_size; |
2304 | 2318 | ||
2305 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2319 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2306 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
2320 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
- | 2321 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
|
2307 | fb->modifier[0], 1); |
2322 | tile_height = tile_size / tile_width; |
2308 | tile_pitch = PAGE_SIZE / tile_height; |
2323 | |
2309 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); |
- | |
2310 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, |
2324 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); |
2311 | tile_height); |
- | |
2312 | info->size_uv = info->width_pages_uv * info->height_pages_uv * |
2325 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
2313 | PAGE_SIZE; |
2326 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
Line 2314... | Line 2327... | ||
2314 | } |
2327 | } |
2315 | } |
2328 | } |
2316 | 2329 | ||
2317 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2330 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
2318 | { |
2331 | { |
2319 | if (INTEL_INFO(dev_priv)->gen >= 9) |
2332 | if (INTEL_INFO(dev_priv)->gen >= 9) |
Line 2325... | Line 2338... | ||
2325 | return 4 * 1024; |
2338 | return 4 * 1024; |
2326 | else |
2339 | else |
2327 | return 0; |
2340 | return 0; |
2328 | } |
2341 | } |
Line -... | Line 2342... | ||
- | 2342 | ||
- | 2343 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
|
- | 2344 | uint64_t fb_modifier) |
|
- | 2345 | { |
|
- | 2346 | switch (fb_modifier) { |
|
- | 2347 | case DRM_FORMAT_MOD_NONE: |
|
- | 2348 | return intel_linear_alignment(dev_priv); |
|
- | 2349 | case I915_FORMAT_MOD_X_TILED: |
|
- | 2350 | if (INTEL_INFO(dev_priv)->gen >= 9) |
|
- | 2351 | return 256 * 1024; |
|
- | 2352 | return 0; |
|
- | 2353 | case I915_FORMAT_MOD_Y_TILED: |
|
- | 2354 | case I915_FORMAT_MOD_Yf_TILED: |
|
- | 2355 | return 1 * 1024 * 1024; |
|
- | 2356 | default: |
|
- | 2357 | MISSING_CASE(fb_modifier); |
|
- | 2358 | return 0; |
|
- | 2359 | } |
|
- | 2360 | } |
|
2329 | 2361 | ||
2330 | int |
2362 | int |
2331 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2363 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2332 | struct drm_framebuffer *fb, |
2364 | struct drm_framebuffer *fb, |
2333 | const struct drm_plane_state *plane_state) |
2365 | const struct drm_plane_state *plane_state) |
Line 2339... | Line 2371... | ||
2339 | u32 alignment; |
2371 | u32 alignment; |
2340 | int ret; |
2372 | int ret; |
Line 2341... | Line 2373... | ||
2341 | 2373 | ||
Line 2342... | Line -... | ||
2342 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
- | |
2343 | - | ||
2344 | switch (fb->modifier[0]) { |
2374 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2345 | case DRM_FORMAT_MOD_NONE: |
- | |
2346 | alignment = intel_linear_alignment(dev_priv); |
- | |
2347 | break; |
- | |
2348 | case I915_FORMAT_MOD_X_TILED: |
- | |
2349 | if (INTEL_INFO(dev)->gen >= 9) |
- | |
2350 | alignment = 256 * 1024; |
- | |
2351 | else { |
- | |
2352 | /* pin() will align the object as required by fence */ |
- | |
2353 | alignment = 0; |
- | |
2354 | } |
- | |
2355 | break; |
- | |
2356 | case I915_FORMAT_MOD_Y_TILED: |
- | |
2357 | case I915_FORMAT_MOD_Yf_TILED: |
- | |
2358 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, |
- | |
2359 | "Y tiling bo slipped through, driver bug!\n")) |
- | |
2360 | return -EINVAL; |
- | |
2361 | alignment = 1 * 1024 * 1024; |
- | |
2362 | break; |
- | |
2363 | default: |
- | |
2364 | MISSING_CASE(fb->modifier[0]); |
- | |
Line 2365... | Line 2375... | ||
2365 | return -EINVAL; |
2375 | |
Line 2366... | Line 2376... | ||
2366 | } |
2376 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
2367 | 2377 | ||
Line 2439... | Line 2449... | ||
2439 | i915_gem_object_unpin_from_display_plane(obj, &view); |
2449 | i915_gem_object_unpin_from_display_plane(obj, &view); |
2440 | } |
2450 | } |
Line 2441... | Line 2451... | ||
2441 | 2451 | ||
2442 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2452 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2443 | * is assumed to be a power-of-two. */ |
2453 | * is assumed to be a power-of-two. */ |
2444 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2454 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2445 | int *x, int *y, |
2455 | int *x, int *y, |
2446 | unsigned int tiling_mode, |
2456 | uint64_t fb_modifier, |
2447 | unsigned int cpp, |
2457 | unsigned int cpp, |
2448 | unsigned int pitch) |
2458 | unsigned int pitch) |
2449 | { |
2459 | { |
- | 2460 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
|
2450 | if (tiling_mode != I915_TILING_NONE) { |
2461 | unsigned int tile_size, tile_width, tile_height; |
Line 2451... | Line 2462... | ||
2451 | unsigned int tile_rows, tiles; |
2462 | unsigned int tile_rows, tiles; |
- | 2463 | ||
2452 | 2464 | tile_size = intel_tile_size(dev_priv); |
|
Line 2453... | Line 2465... | ||
2453 | tile_rows = *y / 8; |
2465 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); |
2454 | *y %= 8; |
2466 | tile_height = tile_size / tile_width; |
Line -... | Line 2467... | ||
- | 2467 | ||
- | 2468 | tile_rows = *y / tile_height; |
|
- | 2469 | *y %= tile_height; |
|
2455 | 2470 | ||
2456 | tiles = *x / (512/cpp); |
2471 | tiles = *x / (tile_width/cpp); |
2457 | *x %= 512/cpp; |
2472 | *x %= tile_width/cpp; |
2458 | 2473 | ||
Line 2459... | Line 2474... | ||
2459 | return tile_rows * pitch * 8 + tiles * 4096; |
2474 | return tile_rows * pitch * tile_height + tiles * tile_size; |
Line 2537... | Line 2552... | ||
2537 | * important and we should probably use that space with FBC or other |
2552 | * important and we should probably use that space with FBC or other |
2538 | * features. */ |
2553 | * features. */ |
2539 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) |
2554 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) |
2540 | return false; |
2555 | return false; |
Line -... | Line 2556... | ||
- | 2556 | ||
- | 2557 | mutex_lock(&dev->struct_mutex); |
|
2541 | 2558 | ||
2542 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2559 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2543 | base_aligned, |
2560 | base_aligned, |
2544 | base_aligned, |
2561 | base_aligned, |
2545 | size_aligned); |
2562 | size_aligned); |
- | 2563 | if (!obj) { |
|
2546 | if (!obj) |
2564 | mutex_unlock(&dev->struct_mutex); |
- | 2565 | return false; |
|
Line 2547... | Line 2566... | ||
2547 | return false; |
2566 | } |
2548 | 2567 | ||
2549 | obj->tiling_mode = plane_config->tiling; |
2568 | obj->tiling_mode = plane_config->tiling; |
Line 2555... | Line 2574... | ||
2555 | mode_cmd.height = fb->height; |
2574 | mode_cmd.height = fb->height; |
2556 | mode_cmd.pitches[0] = fb->pitches[0]; |
2575 | mode_cmd.pitches[0] = fb->pitches[0]; |
2557 | mode_cmd.modifier[0] = fb->modifier[0]; |
2576 | mode_cmd.modifier[0] = fb->modifier[0]; |
2558 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
2577 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
Line 2559... | Line -... | ||
2559 | - | ||
2560 | mutex_lock(&dev->struct_mutex); |
2578 | |
2561 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
2579 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
2562 | &mode_cmd, obj)) { |
2580 | &mode_cmd, obj)) { |
2563 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2581 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2564 | goto out_unref_obj; |
2582 | goto out_unref_obj; |
- | 2583 | } |
|
2565 | } |
2584 | |
Line 2566... | Line 2585... | ||
2566 | mutex_unlock(&dev->struct_mutex); |
2585 | mutex_unlock(&dev->struct_mutex); |
2567 | 2586 | ||
Line 2599... | Line 2618... | ||
2599 | struct drm_i915_gem_object *obj; |
2618 | struct drm_i915_gem_object *obj; |
2600 | struct drm_plane *primary = intel_crtc->base.primary; |
2619 | struct drm_plane *primary = intel_crtc->base.primary; |
2601 | struct drm_plane_state *plane_state = primary->state; |
2620 | struct drm_plane_state *plane_state = primary->state; |
2602 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2621 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2603 | struct intel_plane *intel_plane = to_intel_plane(primary); |
2622 | struct intel_plane *intel_plane = to_intel_plane(primary); |
- | 2623 | struct intel_plane_state *intel_state = |
|
- | 2624 | to_intel_plane_state(plane_state); |
|
2604 | struct drm_framebuffer *fb; |
2625 | struct drm_framebuffer *fb; |
Line 2605... | Line 2626... | ||
2605 | 2626 | ||
2606 | if (!plane_config->fb) |
2627 | if (!plane_config->fb) |
Line 2660... | Line 2681... | ||
2660 | plane_state->crtc_x = 0; |
2681 | plane_state->crtc_x = 0; |
2661 | plane_state->crtc_y = 0; |
2682 | plane_state->crtc_y = 0; |
2662 | plane_state->crtc_w = fb->width; |
2683 | plane_state->crtc_w = fb->width; |
2663 | plane_state->crtc_h = fb->height; |
2684 | plane_state->crtc_h = fb->height; |
Line -... | Line 2685... | ||
- | 2685 | ||
- | 2686 | intel_state->src.x1 = plane_state->src_x; |
|
- | 2687 | intel_state->src.y1 = plane_state->src_y; |
|
- | 2688 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; |
|
- | 2689 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; |
|
- | 2690 | intel_state->dst.x1 = plane_state->crtc_x; |
|
- | 2691 | intel_state->dst.y1 = plane_state->crtc_y; |
|
- | 2692 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; |
|
- | 2693 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; |
|
2664 | 2694 | ||
2665 | obj = intel_fb_obj(fb); |
2695 | obj = intel_fb_obj(fb); |
2666 | if (obj->tiling_mode != I915_TILING_NONE) |
2696 | if (obj->tiling_mode != I915_TILING_NONE) |
Line 2667... | Line 2697... | ||
2667 | dev_priv->preserve_bios_swizzle = true; |
2697 | dev_priv->preserve_bios_swizzle = true; |
Line 2671... | Line 2701... | ||
2671 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
2701 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
2672 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
2702 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
2673 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
2703 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
2674 | } |
2704 | } |
Line 2675... | Line 2705... | ||
2675 | 2705 | ||
2676 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2706 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2677 | struct drm_framebuffer *fb, |
2707 | const struct intel_crtc_state *crtc_state, |
2678 | int x, int y) |
2708 | const struct intel_plane_state *plane_state) |
2679 | { |
2709 | { |
2680 | struct drm_device *dev = crtc->dev; |
2710 | struct drm_device *dev = primary->dev; |
2681 | struct drm_i915_private *dev_priv = dev->dev_private; |
2711 | struct drm_i915_private *dev_priv = dev->dev_private; |
2682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2683 | struct drm_plane *primary = crtc->primary; |
- | |
2684 | bool visible = to_intel_plane_state(primary->state)->visible; |
2713 | struct drm_framebuffer *fb = plane_state->base.fb; |
2685 | struct drm_i915_gem_object *obj; |
2714 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2686 | int plane = intel_crtc->plane; |
2715 | int plane = intel_crtc->plane; |
2687 | unsigned long linear_offset; |
2716 | u32 linear_offset; |
2688 | u32 dspcntr; |
2717 | u32 dspcntr; |
2689 | i915_reg_t reg = DSPCNTR(plane); |
- | |
2690 | int pixel_size; |
- | |
2691 | - | ||
2692 | if (!visible || !fb) { |
- | |
2693 | I915_WRITE(reg, 0); |
- | |
2694 | if (INTEL_INFO(dev)->gen >= 4) |
- | |
2695 | I915_WRITE(DSPSURF(plane), 0); |
- | |
2696 | else |
2718 | i915_reg_t reg = DSPCNTR(plane); |
2697 | I915_WRITE(DSPADDR(plane), 0); |
- | |
2698 | POSTING_READ(reg); |
- | |
2699 | return; |
- | |
2700 | } |
- | |
2701 | 2719 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
|
2702 | obj = intel_fb_obj(fb); |
- | |
2703 | if (WARN_ON(obj == NULL)) |
- | |
2704 | return; |
- | |
2705 | 2720 | int x = plane_state->src.x1 >> 16; |
|
Line 2706... | Line 2721... | ||
2706 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2721 | int y = plane_state->src.y1 >> 16; |
Line 2707... | Line 2722... | ||
2707 | 2722 | ||
Line 2715... | Line 2730... | ||
2715 | 2730 | ||
2716 | /* pipesrc and dspsize control the size that is scaled from, |
2731 | /* pipesrc and dspsize control the size that is scaled from, |
2717 | * which should always be the user's requested size. |
2732 | * which should always be the user's requested size. |
2718 | */ |
2733 | */ |
2719 | I915_WRITE(DSPSIZE(plane), |
2734 | I915_WRITE(DSPSIZE(plane), |
2720 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2735 | ((crtc_state->pipe_src_h - 1) << 16) | |
2721 | (intel_crtc->config->pipe_src_w - 1)); |
2736 | (crtc_state->pipe_src_w - 1)); |
2722 | I915_WRITE(DSPPOS(plane), 0); |
2737 | I915_WRITE(DSPPOS(plane), 0); |
2723 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2738 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2724 | I915_WRITE(PRIMSIZE(plane), |
2739 | I915_WRITE(PRIMSIZE(plane), |
2725 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2740 | ((crtc_state->pipe_src_h - 1) << 16) | |
2726 | (intel_crtc->config->pipe_src_w - 1)); |
2741 | (crtc_state->pipe_src_w - 1)); |
2727 | I915_WRITE(PRIMPOS(plane), 0); |
2742 | I915_WRITE(PRIMPOS(plane), 0); |
2728 | I915_WRITE(PRIMCNSTALPHA(plane), 0); |
2743 | I915_WRITE(PRIMCNSTALPHA(plane), 0); |
Line 2729... | Line 2744... | ||
2729 | } |
2744 | } |
Line 2759... | Line 2774... | ||
2759 | dspcntr |= DISPPLANE_TILED; |
2774 | dspcntr |= DISPPLANE_TILED; |
Line 2760... | Line 2775... | ||
2760 | 2775 | ||
2761 | if (IS_G4X(dev)) |
2776 | if (IS_G4X(dev)) |
Line 2762... | Line 2777... | ||
2762 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2777 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Line 2763... | Line 2778... | ||
2763 | 2778 | ||
2764 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
2779 | linear_offset = y * fb->pitches[0] + x * cpp; |
2765 | 2780 | ||
2766 | if (INTEL_INFO(dev)->gen >= 4) { |
- | |
2767 | intel_crtc->dspaddr_offset = |
2781 | if (INTEL_INFO(dev)->gen >= 4) { |
2768 | intel_gen4_compute_page_offset(dev_priv, |
2782 | intel_crtc->dspaddr_offset = |
2769 | &x, &y, obj->tiling_mode, |
2783 | intel_compute_tile_offset(dev_priv, &x, &y, |
2770 | pixel_size, |
2784 | fb->modifier[0], cpp, |
2771 | fb->pitches[0]); |
2785 | fb->pitches[0]); |
2772 | linear_offset -= intel_crtc->dspaddr_offset; |
2786 | linear_offset -= intel_crtc->dspaddr_offset; |
Line 2773... | Line 2787... | ||
2773 | } else { |
2787 | } else { |
2774 | intel_crtc->dspaddr_offset = linear_offset; |
2788 | intel_crtc->dspaddr_offset = linear_offset; |
Line 2775... | Line 2789... | ||
2775 | } |
2789 | } |
2776 | 2790 | ||
Line 2777... | Line 2791... | ||
2777 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
2791 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
2778 | dspcntr |= DISPPLANE_ROTATE_180; |
2792 | dspcntr |= DISPPLANE_ROTATE_180; |
2779 | 2793 | ||
2780 | x += (intel_crtc->config->pipe_src_w - 1); |
2794 | x += (crtc_state->pipe_src_w - 1); |
2781 | y += (intel_crtc->config->pipe_src_h - 1); |
2795 | y += (crtc_state->pipe_src_h - 1); |
2782 | 2796 | ||
Line 2783... | Line 2797... | ||
2783 | /* Finding the last pixel of the last line of the display |
2797 | /* Finding the last pixel of the last line of the display |
2784 | data and adding to linear_offset*/ |
2798 | data and adding to linear_offset*/ |
Line 2801... | Line 2815... | ||
2801 | } else |
2815 | } else |
2802 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2816 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
2803 | POSTING_READ(reg); |
2817 | POSTING_READ(reg); |
2804 | } |
2818 | } |
Line 2805... | Line 2819... | ||
2805 | 2819 | ||
2806 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2820 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2807 | struct drm_framebuffer *fb, |
- | |
2808 | int x, int y) |
2821 | struct drm_crtc *crtc) |
2809 | { |
2822 | { |
2810 | struct drm_device *dev = crtc->dev; |
2823 | struct drm_device *dev = crtc->dev; |
2811 | struct drm_i915_private *dev_priv = dev->dev_private; |
2824 | struct drm_i915_private *dev_priv = dev->dev_private; |
2812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
2813 | struct drm_plane *primary = crtc->primary; |
- | |
2814 | bool visible = to_intel_plane_state(primary->state)->visible; |
- | |
2815 | struct drm_i915_gem_object *obj; |
2825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2816 | int plane = intel_crtc->plane; |
- | |
2817 | unsigned long linear_offset; |
- | |
2818 | u32 dspcntr; |
- | |
2819 | i915_reg_t reg = DSPCNTR(plane); |
- | |
Line 2820... | Line 2826... | ||
2820 | int pixel_size; |
2826 | int plane = intel_crtc->plane; |
2821 | 2827 | ||
2822 | if (!visible || !fb) { |
2828 | I915_WRITE(DSPCNTR(plane), 0); |
- | 2829 | if (INTEL_INFO(dev_priv)->gen >= 4) |
|
2823 | I915_WRITE(reg, 0); |
2830 | I915_WRITE(DSPSURF(plane), 0); |
2824 | I915_WRITE(DSPSURF(plane), 0); |
2831 | else |
2825 | POSTING_READ(reg); |
2832 | I915_WRITE(DSPADDR(plane), 0); |
Line -... | Line 2833... | ||
- | 2833 | POSTING_READ(DSPCNTR(plane)); |
|
- | 2834 | } |
|
- | 2835 | ||
- | 2836 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
|
- | 2837 | const struct intel_crtc_state *crtc_state, |
|
- | 2838 | const struct intel_plane_state *plane_state) |
|
- | 2839 | { |
|
- | 2840 | struct drm_device *dev = primary->dev; |
|
2826 | return; |
2841 | struct drm_i915_private *dev_priv = dev->dev_private; |
2827 | } |
2842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
- | 2843 | struct drm_framebuffer *fb = plane_state->base.fb; |
|
2828 | 2844 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
|
2829 | obj = intel_fb_obj(fb); |
- | |
- | 2845 | int plane = intel_crtc->plane; |
|
2830 | if (WARN_ON(obj == NULL)) |
2846 | u32 linear_offset; |
- | 2847 | u32 dspcntr; |
|
- | 2848 | i915_reg_t reg = DSPCNTR(plane); |
|
Line 2831... | Line 2849... | ||
2831 | return; |
2849 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2832 | - | ||
2833 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2850 | int x = plane_state->src.x1 >> 16; |
Line 2834... | Line 2851... | ||
2834 | 2851 | int y = plane_state->src.y1 >> 16; |
|
2835 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2852 | |
Line 2866... | Line 2883... | ||
2866 | dspcntr |= DISPPLANE_TILED; |
2883 | dspcntr |= DISPPLANE_TILED; |
Line 2867... | Line 2884... | ||
2867 | 2884 | ||
2868 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
2885 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
Line 2869... | Line 2886... | ||
2869 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2886 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
2870 | 2887 | ||
2871 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
2888 | linear_offset = y * fb->pitches[0] + x * cpp; |
2872 | intel_crtc->dspaddr_offset = |
- | |
2873 | intel_gen4_compute_page_offset(dev_priv, |
2889 | intel_crtc->dspaddr_offset = |
2874 | &x, &y, obj->tiling_mode, |
2890 | intel_compute_tile_offset(dev_priv, &x, &y, |
2875 | pixel_size, |
2891 | fb->modifier[0], cpp, |
2876 | fb->pitches[0]); |
2892 | fb->pitches[0]); |
2877 | linear_offset -= intel_crtc->dspaddr_offset; |
2893 | linear_offset -= intel_crtc->dspaddr_offset; |
Line 2878... | Line 2894... | ||
2878 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
2894 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
2879 | dspcntr |= DISPPLANE_ROTATE_180; |
2895 | dspcntr |= DISPPLANE_ROTATE_180; |
2880 | 2896 | ||
Line 2881... | Line 2897... | ||
2881 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
2897 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
2882 | x += (intel_crtc->config->pipe_src_w - 1); |
2898 | x += (crtc_state->pipe_src_w - 1); |
2883 | y += (intel_crtc->config->pipe_src_h - 1); |
2899 | y += (crtc_state->pipe_src_h - 1); |
2884 | 2900 | ||
2885 | /* Finding the last pixel of the last line of the display |
2901 | /* Finding the last pixel of the last line of the display |
2886 | data and adding to linear_offset*/ |
2902 | data and adding to linear_offset*/ |
2887 | linear_offset += |
2903 | linear_offset += |
Line 2888... | Line 2904... | ||
2888 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2904 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
2889 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; |
2905 | (crtc_state->pipe_src_w - 1) * cpp; |
Line 2905... | Line 2921... | ||
2905 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2921 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
2906 | } |
2922 | } |
2907 | POSTING_READ(reg); |
2923 | POSTING_READ(reg); |
2908 | } |
2924 | } |
Line 2909... | Line 2925... | ||
2909 | 2925 | ||
2910 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2926 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2911 | uint32_t pixel_format) |
2927 | uint64_t fb_modifier, uint32_t pixel_format) |
2912 | { |
- | |
2913 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; |
- | |
2914 | - | ||
2915 | /* |
- | |
2916 | * The stride is either expressed as a multiple of 64 bytes |
- | |
2917 | * chunks for linear buffers or in number of tiles for tiled |
- | |
2918 | * buffers. |
- | |
2919 | */ |
- | |
2920 | switch (fb_modifier) { |
2928 | { |
2921 | case DRM_FORMAT_MOD_NONE: |
- | |
2922 | return 64; |
- | |
2923 | case I915_FORMAT_MOD_X_TILED: |
- | |
2924 | if (INTEL_INFO(dev)->gen == 2) |
- | |
2925 | return 128; |
- | |
2926 | return 512; |
- | |
2927 | case I915_FORMAT_MOD_Y_TILED: |
- | |
2928 | /* No need to check for old gens and Y tiling since this is |
- | |
2929 | * about the display engine and those will be blocked before |
- | |
2930 | * we get here. |
- | |
2931 | */ |
- | |
2932 | return 128; |
- | |
2933 | case I915_FORMAT_MOD_Yf_TILED: |
- | |
2934 | if (bits_per_pixel == 8) |
- | |
2935 | return 64; |
- | |
2936 | else |
- | |
2937 | return 128; |
- | |
2938 | default: |
- | |
2939 | MISSING_CASE(fb_modifier); |
2929 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
- | 2930 | return 64; |
|
- | 2931 | } else { |
|
- | 2932 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
|
- | 2933 | ||
2940 | return 64; |
2934 | return intel_tile_width(dev_priv, fb_modifier, cpp); |
2941 | } |
2935 | } |
Line 2942... | Line 2936... | ||
2942 | } |
2936 | } |
2943 | 2937 | ||
Line 2958... | Line 2952... | ||
2958 | return -1; |
2952 | return -1; |
Line 2959... | Line 2953... | ||
2959 | 2953 | ||
Line 2960... | Line 2954... | ||
2960 | offset = vma->node.start; |
2954 | offset = vma->node.start; |
2961 | 2955 | ||
2962 | if (plane == 1) { |
2956 | if (plane == 1) { |
2963 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
2957 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
Line 2964... | Line 2958... | ||
2964 | PAGE_SIZE; |
2958 | PAGE_SIZE; |
Line 3075... | Line 3069... | ||
3075 | } |
3069 | } |
Line 3076... | Line 3070... | ||
3076 | 3070 | ||
3077 | return 0; |
3071 | return 0; |
Line 3078... | Line 3072... | ||
3078 | } |
3072 | } |
3079 | 3073 | ||
3080 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
3074 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3081 | struct drm_framebuffer *fb, |
3075 | const struct intel_crtc_state *crtc_state, |
3082 | int x, int y) |
3076 | const struct intel_plane_state *plane_state) |
3083 | { |
3077 | { |
3084 | struct drm_device *dev = crtc->dev; |
3078 | struct drm_device *dev = plane->dev; |
3085 | struct drm_i915_private *dev_priv = dev->dev_private; |
3079 | struct drm_i915_private *dev_priv = dev->dev_private; |
3086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
3087 | struct drm_plane *plane = crtc->primary; |
3080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3088 | bool visible = to_intel_plane_state(plane->state)->visible; |
3081 | struct drm_framebuffer *fb = plane_state->base.fb; |
3089 | struct drm_i915_gem_object *obj; |
3082 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
3090 | int pipe = intel_crtc->pipe; |
3083 | int pipe = intel_crtc->pipe; |
3091 | u32 plane_ctl, stride_div, stride; |
3084 | u32 plane_ctl, stride_div, stride; |
3092 | u32 tile_height, plane_offset, plane_size; |
3085 | u32 tile_height, plane_offset, plane_size; |
3093 | unsigned int rotation; |
3086 | unsigned int rotation = plane_state->base.rotation; |
3094 | int x_offset, y_offset; |
3087 | int x_offset, y_offset; |
3095 | u32 surf_addr; |
3088 | u32 surf_addr; |
3096 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3089 | int scaler_id = plane_state->scaler_id; |
3097 | struct intel_plane_state *plane_state; |
3090 | int src_x = plane_state->src.x1 >> 16; |
3098 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; |
- | |
3099 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; |
- | |
3100 | int scaler_id = -1; |
3091 | int src_y = plane_state->src.y1 >> 16; |
3101 | - | ||
3102 | plane_state = to_intel_plane_state(plane->state); |
3092 | int src_w = drm_rect_width(&plane_state->src) >> 16; |
3103 | 3093 | int src_h = drm_rect_height(&plane_state->src) >> 16; |
|
3104 | if (!visible || !fb) { |
3094 | int dst_x = plane_state->dst.x1; |
3105 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3095 | int dst_y = plane_state->dst.y1; |
3106 | I915_WRITE(PLANE_SURF(pipe, 0), 0); |
- | |
3107 | POSTING_READ(PLANE_CTL(pipe, 0)); |
- | |
Line 3108... | Line 3096... | ||
3108 | return; |
3096 | int dst_w = drm_rect_width(&plane_state->dst); |
3109 | } |
3097 | int dst_h = drm_rect_height(&plane_state->dst); |
3110 | 3098 | ||
Line 3111... | Line 3099... | ||
3111 | plane_ctl = PLANE_CTL_ENABLE | |
3099 | plane_ctl = PLANE_CTL_ENABLE | |
3112 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
3100 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
3113 | PLANE_CTL_PIPE_CSC_ENABLE; |
3101 | PLANE_CTL_PIPE_CSC_ENABLE; |
3114 | - | ||
3115 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
- | |
3116 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
3102 | |
Line 3117... | Line -... | ||
3117 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
- | |
3118 | 3103 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
|
3119 | rotation = plane->state->rotation; |
3104 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
3120 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3105 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
Line 3121... | Line 3106... | ||
3121 | 3106 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
|
Line 3122... | Line -... | ||
3122 | obj = intel_fb_obj(fb); |
- | |
3123 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
- | |
3124 | fb->pixel_format); |
- | |
3125 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
- | |
3126 | - | ||
3127 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
- | |
3128 | - | ||
3129 | scaler_id = plane_state->scaler_id; |
- | |
3130 | src_x = plane_state->src.x1 >> 16; |
- | |
3131 | src_y = plane_state->src.y1 >> 16; |
- | |
3132 | src_w = drm_rect_width(&plane_state->src) >> 16; |
- | |
3133 | src_h = drm_rect_height(&plane_state->src) >> 16; |
- | |
3134 | dst_x = plane_state->dst.x1; |
3107 | |
- | 3108 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
|
- | 3109 | fb->pixel_format); |
|
3135 | dst_y = plane_state->dst.y1; |
3110 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3136 | dst_w = drm_rect_width(&plane_state->dst); |
3111 | |
3137 | dst_h = drm_rect_height(&plane_state->dst); |
- | |
3138 | 3112 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
|
3139 | WARN_ON(x != src_x || y != src_y); |
3113 | |
3140 | 3114 | if (intel_rotation_90_or_270(rotation)) { |
|
3141 | if (intel_rotation_90_or_270(rotation)) { |
3115 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3142 | /* stride = Surface height in tiles */ |
3116 | |
3143 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3117 | /* stride = Surface height in tiles */ |
3144 | fb->modifier[0], 0); |
3118 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3145 | stride = DIV_ROUND_UP(fb->height, tile_height); |
3119 | stride = DIV_ROUND_UP(fb->height, tile_height); |
3146 | x_offset = stride * tile_height - y - src_h; |
3120 | x_offset = stride * tile_height - src_y - src_h; |
3147 | y_offset = x; |
3121 | y_offset = src_x; |
3148 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3122 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
Line 3149... | Line 3123... | ||
3149 | } else { |
3123 | } else { |
Line 3180... | Line 3154... | ||
3180 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
3154 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
Line 3181... | Line 3155... | ||
3181 | 3155 | ||
3182 | POSTING_READ(PLANE_SURF(pipe, 0)); |
3156 | POSTING_READ(PLANE_SURF(pipe, 0)); |
Line 3183... | Line -... | ||
3183 | } |
- | |
3184 | - | ||
3185 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3157 | } |
3186 | static int |
3158 | |
3187 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3159 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3188 | int x, int y, enum mode_set_atomic state) |
3160 | struct drm_crtc *crtc) |
3189 | { |
3161 | { |
- | 3162 | struct drm_device *dev = crtc->dev; |
|
Line -... | Line 3163... | ||
- | 3163 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
3190 | struct drm_device *dev = crtc->dev; |
3164 | int pipe = to_intel_crtc(crtc)->pipe; |
3191 | struct drm_i915_private *dev_priv = dev->dev_private; |
3165 | |
- | 3166 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
|
Line -... | Line 3167... | ||
- | 3167 | I915_WRITE(PLANE_SURF(pipe, 0), 0); |
|
- | 3168 | POSTING_READ(PLANE_SURF(pipe, 0)); |
|
- | 3169 | } |
|
- | 3170 | ||
- | 3171 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
|
- | 3172 | static int |
|
3192 | 3173 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
|
Line 3193... | Line 3174... | ||
3193 | if (dev_priv->fbc.deactivate) |
3174 | int x, int y, enum mode_set_atomic state) |
3194 | dev_priv->fbc.deactivate(dev_priv); |
3175 | { |
Line 3195... | Line 3176... | ||
3195 | 3176 | /* Support for kgdboc is disabled, this needs a major rework. */ |
|
3196 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3177 | DRM_ERROR("legacy panic handler not supported any more.\n"); |
3197 | 3178 | ||
Line 3220... | Line 3201... | ||
3220 | struct intel_plane_state *plane_state; |
3201 | struct intel_plane_state *plane_state; |
Line 3221... | Line 3202... | ||
3221 | 3202 | ||
3222 | drm_modeset_lock_crtc(crtc, &plane->base); |
3203 | drm_modeset_lock_crtc(crtc, &plane->base); |
Line 3223... | Line 3204... | ||
3223 | plane_state = to_intel_plane_state(plane->base.state); |
3204 | plane_state = to_intel_plane_state(plane->base.state); |
3224 | 3205 | ||
- | 3206 | if (plane_state->visible) |
|
- | 3207 | plane->update_plane(&plane->base, |
|
Line 3225... | Line 3208... | ||
3225 | if (crtc->state->active && plane_state->base.fb) |
3208 | to_intel_crtc_state(crtc->state), |
3226 | plane->commit_plane(&plane->base, plane_state); |
3209 | plane_state); |
3227 | 3210 | ||
Line 4807... | Line 4790... | ||
4807 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4790 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4808 | struct intel_crtc_state *pipe_config = |
4791 | struct intel_crtc_state *pipe_config = |
4809 | to_intel_crtc_state(crtc->base.state); |
4792 | to_intel_crtc_state(crtc->base.state); |
4810 | struct drm_device *dev = crtc->base.dev; |
4793 | struct drm_device *dev = crtc->base.dev; |
Line 4811... | Line -... | ||
4811 | - | ||
4812 | if (atomic->wait_vblank) |
- | |
4813 | intel_wait_for_vblank(dev, crtc->pipe); |
- | |
4814 | 4794 | ||
Line 4815... | Line 4795... | ||
4815 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4795 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
Line 4816... | Line 4796... | ||
4816 | 4796 | ||
4817 | crtc->wm.cxsr_allowed = true; |
4797 | crtc->wm.cxsr_allowed = true; |
Line 4818... | Line 4798... | ||
4818 | 4798 | ||
4819 | if (pipe_config->update_wm_post && pipe_config->base.active) |
4799 | if (pipe_config->update_wm_post && pipe_config->base.active) |
Line 4820... | Line 4800... | ||
4820 | intel_update_watermarks(&crtc->base); |
4800 | intel_update_watermarks(&crtc->base); |
4821 | 4801 | ||
Line 4822... | Line 4802... | ||
4822 | if (atomic->update_fbc) |
4802 | if (atomic->update_fbc) |
4823 | intel_fbc_update(crtc); |
4803 | intel_fbc_post_update(crtc); |
Line 4824... | Line 4804... | ||
4824 | 4804 | ||
4825 | if (atomic->post_enable_primary) |
4805 | if (atomic->post_enable_primary) |
- | 4806 | intel_post_enable_primary(&crtc->base); |
|
4826 | intel_post_enable_primary(&crtc->base); |
4807 | |
4827 | 4808 | memset(atomic, 0, sizeof(*atomic)); |
|
4828 | memset(atomic, 0, sizeof(*atomic)); |
4809 | } |
4829 | } |
4810 | |
4830 | 4811 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
|
- | 4812 | { |
|
- | 4813 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
|
- | 4814 | struct drm_device *dev = crtc->base.dev; |
|
- | 4815 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 4816 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
|
Line 4831... | Line 4817... | ||
4831 | static void intel_pre_plane_update(struct intel_crtc *crtc) |
4817 | struct intel_crtc_state *pipe_config = |
4832 | { |
4818 | to_intel_crtc_state(crtc->base.state); |
Line 4833... | Line 4819... | ||
4833 | struct drm_device *dev = crtc->base.dev; |
4819 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
- | 4820 | struct drm_plane *primary = crtc->base.primary; |
|
- | 4821 | struct drm_plane_state *old_pri_state = |
|
- | 4822 | drm_atomic_get_existing_plane_state(old_state, primary); |
|
4834 | struct drm_i915_private *dev_priv = dev->dev_private; |
4823 | bool modeset = needs_modeset(&pipe_config->base); |
Line 4835... | Line 4824... | ||
4835 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4824 | |
- | 4825 | if (atomic->update_fbc) |
|
4836 | struct intel_crtc_state *pipe_config = |
4826 | intel_fbc_pre_update(crtc); |
- | 4827 | ||
Line 4837... | Line 4828... | ||
4837 | to_intel_crtc_state(crtc->base.state); |
4828 | if (old_pri_state) { |
4838 | 4829 | struct intel_plane_state *primary_state = |
|
- | 4830 | to_intel_plane_state(primary->state); |
|
- | 4831 | struct intel_plane_state *old_primary_state = |
|
4839 | if (atomic->disable_fbc) |
4832 | to_intel_plane_state(old_pri_state); |
4840 | intel_fbc_deactivate(crtc); |
4833 | |
Line 4841... | Line 4834... | ||
4841 | 4834 | if (old_primary_state->visible && |
|
4842 | if (crtc->atomic.disable_ips) |
4835 | (modeset || !primary_state->visible)) |
Line 4946... | Line 4939... | ||
4946 | 4939 | ||
4947 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
4940 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ |
4948 | if (intel_crtc->config->has_pch_encoder) |
4941 | if (intel_crtc->config->has_pch_encoder) |
4949 | intel_wait_for_vblank(dev, pipe); |
4942 | intel_wait_for_vblank(dev, pipe); |
4950 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
- | |
4951 | - | ||
4952 | intel_fbc_enable(intel_crtc); |
4943 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
Line 4953... | Line 4944... | ||
4953 | } |
4944 | } |
4954 | 4945 | ||
4955 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4946 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
Line 5060... | Line 5051... | ||
5060 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5051 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5061 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
5052 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { |
5062 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5053 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5063 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5054 | intel_wait_for_vblank(dev, hsw_workaround_pipe); |
5064 | } |
5055 | } |
5065 | - | ||
5066 | intel_fbc_enable(intel_crtc); |
- | |
5067 | } |
5056 | } |
Line 5068... | Line 5057... | ||
5068 | 5057 | ||
5069 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
5058 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
5070 | { |
5059 | { |
Line 5142... | Line 5131... | ||
5142 | 5131 | ||
5143 | ironlake_fdi_pll_disable(intel_crtc); |
5132 | ironlake_fdi_pll_disable(intel_crtc); |
Line 5144... | Line 5133... | ||
5144 | } |
5133 | } |
5145 | - | ||
5146 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
- | |
5147 | 5134 | ||
Line 5148... | Line 5135... | ||
5148 | intel_fbc_disable_crtc(intel_crtc); |
5135 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
5149 | } |
5136 | } |
5150 | 5137 | ||
Line 5194... | Line 5181... | ||
5194 | intel_ddi_fdi_disable(crtc); |
5181 | intel_ddi_fdi_disable(crtc); |
Line 5195... | Line 5182... | ||
5195 | 5182 | ||
5196 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5183 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5197 | true); |
5184 | true); |
5198 | } |
- | |
5199 | - | ||
5200 | intel_fbc_disable_crtc(intel_crtc); |
5185 | } |
Line 5201... | Line 5186... | ||
5201 | } |
5186 | } |
5202 | 5187 | ||
5203 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5188 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
Line 5318... | Line 5303... | ||
5318 | MISSING_CASE(intel_encoder->type); |
5303 | MISSING_CASE(intel_encoder->type); |
5319 | return POWER_DOMAIN_AUX_A; |
5304 | return POWER_DOMAIN_AUX_A; |
5320 | } |
5305 | } |
5321 | } |
5306 | } |
Line 5322... | Line 5307... | ||
5322 | 5307 | ||
- | 5308 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
|
5323 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
5309 | struct intel_crtc_state *crtc_state) |
5324 | { |
5310 | { |
5325 | struct drm_device *dev = crtc->dev; |
5311 | struct drm_device *dev = crtc->dev; |
5326 | struct intel_encoder *intel_encoder; |
5312 | struct drm_encoder *encoder; |
5327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5328 | enum pipe pipe = intel_crtc->pipe; |
5314 | enum pipe pipe = intel_crtc->pipe; |
5329 | unsigned long mask; |
5315 | unsigned long mask; |
Line 5330... | Line 5316... | ||
5330 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
5316 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
5331 | 5317 | ||
Line 5332... | Line 5318... | ||
5332 | if (!crtc->state->active) |
5318 | if (!crtc_state->base.active) |
5333 | return 0; |
5319 | return 0; |
5334 | 5320 | ||
5335 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5321 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5336 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
5322 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
Line 5337... | Line 5323... | ||
5337 | if (intel_crtc->config->pch_pfit.enabled || |
5323 | if (crtc_state->pch_pfit.enabled || |
- | 5324 | crtc_state->pch_pfit.force_thru) |
|
- | 5325 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
|
5338 | intel_crtc->config->pch_pfit.force_thru) |
5326 | |
- | 5327 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
|
Line 5339... | Line 5328... | ||
5339 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5328 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
5340 | 5329 | ||
Line -... | Line 5330... | ||
- | 5330 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
|
5341 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5331 | } |
- | 5332 | ||
5342 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
5333 | return mask; |
5343 | 5334 | } |
|
5344 | return mask; |
5335 | |
5345 | } |
5336 | static unsigned long |
5346 | 5337 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
|
Line 5347... | Line 5338... | ||
5347 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
5338 | struct intel_crtc_state *crtc_state) |
5348 | { |
5339 | { |
- | 5340 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
|
Line 5349... | Line 5341... | ||
5349 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 5350... | Line 5342... | ||
5350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5342 | enum intel_display_power_domain domain; |
5351 | enum intel_display_power_domain domain; |
5343 | unsigned long domains, new_domains, old_domains; |
Line 5369... | Line 5361... | ||
5369 | 5361 | ||
5370 | for_each_power_domain(domain, domains) |
5362 | for_each_power_domain(domain, domains) |
5371 | intel_display_power_put(dev_priv, domain); |
5363 | intel_display_power_put(dev_priv, domain); |
Line 5372... | Line -... | ||
5372 | } |
- | |
5373 | - | ||
5374 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
- | |
5375 | { |
- | |
5376 | struct drm_device *dev = state->dev; |
- | |
5377 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
5378 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
- | |
5379 | struct drm_crtc_state *crtc_state; |
- | |
5380 | struct drm_crtc *crtc; |
- | |
5381 | int i; |
- | |
5382 | - | ||
5383 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
- | |
5384 | if (needs_modeset(crtc->state)) |
- | |
5385 | put_domains[to_intel_crtc(crtc)->pipe] = |
- | |
5386 | modeset_get_crtc_power_domains(crtc); |
- | |
5387 | } |
- | |
5388 | - | ||
5389 | if (dev_priv->display.modeset_commit_cdclk) { |
- | |
5390 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; |
- | |
5391 | - | ||
5392 | if (cdclk != dev_priv->cdclk_freq && |
- | |
5393 | !WARN_ON(!state->allow_modeset)) |
- | |
5394 | dev_priv->display.modeset_commit_cdclk(state); |
- | |
5395 | } |
- | |
5396 | - | ||
5397 | for (i = 0; i < I915_MAX_PIPES; i++) |
- | |
5398 | if (put_domains[i]) |
- | |
5399 | modeset_put_power_domains(dev_priv, put_domains[i]); |
- | |
5400 | } |
5364 | } |
5401 | 5365 | ||
5402 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5366 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
Line 5403... | Line 5367... | ||
5403 | { |
5367 | { |
Line 6059... | Line 6023... | ||
6059 | return 288000; |
6023 | return 288000; |
6060 | else |
6024 | else |
6061 | return 144000; |
6025 | return 144000; |
6062 | } |
6026 | } |
Line 6063... | Line 6027... | ||
6063 | 6027 | ||
6064 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
- | |
6065 | * that's non-NULL, look at current state otherwise. */ |
6028 | /* Compute the max pixel clock for new configuration. */ |
6066 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6029 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6067 | struct drm_atomic_state *state) |
6030 | struct drm_atomic_state *state) |
- | 6031 | { |
|
- | 6032 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
|
6068 | { |
6033 | struct drm_i915_private *dev_priv = dev->dev_private; |
6069 | struct intel_crtc *intel_crtc; |
6034 | struct drm_crtc *crtc; |
6070 | struct intel_crtc_state *crtc_state; |
6035 | struct drm_crtc_state *crtc_state; |
- | 6036 | unsigned max_pixclk = 0, i; |
|
Line 6071... | Line -... | ||
6071 | int max_pixclk = 0; |
- | |
6072 | 6037 | enum pipe pipe; |
|
6073 | for_each_intel_crtc(dev, intel_crtc) { |
6038 | |
6074 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
- | |
Line 6075... | Line 6039... | ||
6075 | if (IS_ERR(crtc_state)) |
6039 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6076 | return PTR_ERR(crtc_state); |
6040 | sizeof(intel_state->min_pixclk)); |
Line 6077... | Line 6041... | ||
6077 | 6041 | ||
6078 | if (!crtc_state->base.enable) |
6042 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
- | 6043 | int pixclk = 0; |
|
- | 6044 | ||
6079 | continue; |
6045 | if (crtc_state->enable) |
Line -... | Line 6046... | ||
- | 6046 | pixclk = crtc_state->adjusted_mode.crtc_clock; |
|
- | 6047 | ||
- | 6048 | intel_state->min_pixclk[i] = pixclk; |
|
6080 | 6049 | } |
|
6081 | max_pixclk = max(max_pixclk, |
6050 | |
Line 6082... | Line 6051... | ||
6082 | crtc_state->base.adjusted_mode.crtc_clock); |
6051 | for_each_pipe(dev_priv, pipe) |
6083 | } |
6052 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); |
6084 | 6053 | ||
6085 | return max_pixclk; |
6054 | return max_pixclk; |
6086 | } |
6055 | } |
- | 6056 | ||
- | 6057 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
|
Line 6087... | Line 6058... | ||
6087 | 6058 | { |
|
6088 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
6059 | struct drm_device *dev = state->dev; |
Line 6089... | Line 6060... | ||
6089 | { |
6060 | struct drm_i915_private *dev_priv = dev->dev_private; |
6090 | struct drm_device *dev = state->dev; |
6061 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
Line -... | Line 6062... | ||
- | 6062 | struct intel_atomic_state *intel_state = |
|
- | 6063 | to_intel_atomic_state(state); |
|
- | 6064 | ||
6091 | struct drm_i915_private *dev_priv = dev->dev_private; |
6065 | if (max_pixclk < 0) |
6092 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
6066 | return max_pixclk; |
Line 6093... | Line 6067... | ||
6093 | 6067 | ||
6094 | if (max_pixclk < 0) |
6068 | intel_state->cdclk = intel_state->dev_cdclk = |
6095 | return max_pixclk; |
6069 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
6096 | 6070 | ||
6097 | to_intel_atomic_state(state)->cdclk = |
6071 | if (!intel_state->active_crtcs) |
- | 6072 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); |
|
- | 6073 | ||
Line 6098... | Line 6074... | ||
6098 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
6074 | return 0; |
6099 | 6075 | } |
|
Line 6100... | Line 6076... | ||
6100 | return 0; |
6076 | |
6101 | } |
6077 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
Line -... | Line 6078... | ||
- | 6078 | { |
|
- | 6079 | struct drm_device *dev = state->dev; |
|
- | 6080 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
6102 | 6081 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
|
6103 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6082 | struct intel_atomic_state *intel_state = |
Line 6104... | Line 6083... | ||
6104 | { |
6083 | to_intel_atomic_state(state); |
6105 | struct drm_device *dev = state->dev; |
6084 | |
Line 6152... | Line 6131... | ||
6152 | } |
6131 | } |
Line 6153... | Line 6132... | ||
6153 | 6132 | ||
6154 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
6133 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
6155 | { |
6134 | { |
6156 | struct drm_device *dev = old_state->dev; |
- | |
6157 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
6135 | struct drm_device *dev = old_state->dev; |
- | 6136 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
- | 6137 | struct intel_atomic_state *old_intel_state = |
|
- | 6138 | to_intel_atomic_state(old_state); |
|
Line 6158... | Line 6139... | ||
6158 | struct drm_i915_private *dev_priv = dev->dev_private; |
6139 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
6159 | 6140 | ||
6160 | /* |
6141 | /* |
6161 | * FIXME: We can end up here with all power domains off, yet |
6142 | * FIXME: We can end up here with all power domains off, yet |
Line 6289... | Line 6270... | ||
6289 | assert_vblank_disabled(crtc); |
6270 | assert_vblank_disabled(crtc); |
6290 | drm_crtc_vblank_on(crtc); |
6271 | drm_crtc_vblank_on(crtc); |
Line 6291... | Line 6272... | ||
6291 | 6272 | ||
6292 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6273 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6293 | encoder->enable(encoder); |
- | |
6294 | - | ||
6295 | intel_fbc_enable(intel_crtc); |
6274 | encoder->enable(encoder); |
Line 6296... | Line 6275... | ||
6296 | } |
6275 | } |
6297 | 6276 | ||
6298 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6277 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
Line 6353... | Line 6332... | ||
6353 | if (encoder->post_pll_disable) |
6332 | if (encoder->post_pll_disable) |
6354 | encoder->post_pll_disable(encoder); |
6333 | encoder->post_pll_disable(encoder); |
Line 6355... | Line 6334... | ||
6355 | 6334 | ||
6356 | if (!IS_GEN2(dev)) |
6335 | if (!IS_GEN2(dev)) |
6357 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
- | |
6358 | - | ||
6359 | intel_fbc_disable_crtc(intel_crtc); |
6336 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
Line 6360... | Line 6337... | ||
6360 | } |
6337 | } |
6361 | 6338 | ||
6362 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6339 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
Line 6378... | Line 6355... | ||
6378 | to_intel_plane_state(crtc->primary->state)->visible = false; |
6355 | to_intel_plane_state(crtc->primary->state)->visible = false; |
6379 | } |
6356 | } |
Line 6380... | Line 6357... | ||
6380 | 6357 | ||
6381 | dev_priv->display.crtc_disable(crtc); |
6358 | dev_priv->display.crtc_disable(crtc); |
- | 6359 | intel_crtc->active = false; |
|
6382 | intel_crtc->active = false; |
6360 | intel_fbc_disable(intel_crtc); |
6383 | intel_update_watermarks(crtc); |
6361 | intel_update_watermarks(crtc); |
Line 6384... | Line 6362... | ||
6384 | intel_disable_shared_dpll(intel_crtc); |
6362 | intel_disable_shared_dpll(intel_crtc); |
6385 | 6363 | ||
6386 | domains = intel_crtc->enabled_power_domains; |
6364 | domains = intel_crtc->enabled_power_domains; |
6387 | for_each_power_domain(domain, domains) |
6365 | for_each_power_domain(domain, domains) |
- | 6366 | intel_display_power_put(dev_priv, domain); |
|
- | 6367 | intel_crtc->enabled_power_domains = 0; |
|
- | 6368 | ||
6388 | intel_display_power_put(dev_priv, domain); |
6369 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); |
Line 6389... | Line 6370... | ||
6389 | intel_crtc->enabled_power_domains = 0; |
6370 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; |
6390 | } |
6371 | } |
6391 | 6372 | ||
6392 | /* |
6373 | /* |
6393 | * turn all crtc's off, but do not adjust state |
6374 | * turn all crtc's off, but do not adjust state |
6394 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
6375 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
6395 | */ |
6376 | */ |
6396 | int intel_display_suspend(struct drm_device *dev) |
- | |
6397 | { |
6377 | int intel_display_suspend(struct drm_device *dev) |
6398 | struct drm_mode_config *config = &dev->mode_config; |
- | |
6399 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; |
- | |
6400 | struct drm_atomic_state *state; |
6378 | { |
6401 | struct drm_crtc *crtc; |
- | |
6402 | unsigned crtc_mask = 0; |
- | |
6403 | int ret = 0; |
- | |
6404 | - | ||
6405 | if (WARN_ON(!ctx)) |
- | |
6406 | return 0; |
- | |
6407 | - | ||
6408 | lockdep_assert_held(&ctx->ww_ctx); |
- | |
6409 | state = drm_atomic_state_alloc(dev); |
- | |
6410 | if (WARN_ON(!state)) |
- | |
6411 | return -ENOMEM; |
- | |
6412 | - | ||
6413 | state->acquire_ctx = ctx; |
- | |
6414 | state->allow_modeset = true; |
- | |
6415 | - | ||
6416 | for_each_crtc(dev, crtc) { |
- | |
6417 | struct drm_crtc_state *crtc_state = |
- | |
6418 | drm_atomic_get_crtc_state(state, crtc); |
- | |
6419 | - | ||
6420 | ret = PTR_ERR_OR_ZERO(crtc_state); |
- | |
6421 | if (ret) |
- | |
6422 | goto free; |
- | |
6423 | - | ||
6424 | if (!crtc_state->active) |
- | |
6425 | continue; |
- | |
6426 | - | ||
6427 | crtc_state->active = false; |
- | |
6428 | crtc_mask |= 1 << drm_crtc_index(crtc); |
- | |
6429 | } |
- | |
6430 | - | ||
6431 | if (crtc_mask) { |
- | |
6432 | ret = drm_atomic_commit(state); |
- | |
6433 | - | ||
6434 | if (!ret) { |
- | |
6435 | for_each_crtc(dev, crtc) |
- | |
6436 | if (crtc_mask & (1 << drm_crtc_index(crtc))) |
- | |
6437 | crtc->state->active = true; |
- | |
6438 | - | ||
Line -... | Line 6379... | ||
- | 6379 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
6439 | return ret; |
6380 | struct drm_atomic_state *state; |
6440 | } |
6381 | int ret; |
6441 | } |
6382 | |
- | 6383 | state = drm_atomic_helper_suspend(dev); |
|
6442 | 6384 | ret = PTR_ERR_OR_ZERO(state); |
|
6443 | free: |
6385 | if (ret) |
6444 | if (ret) |
6386 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
Line 6445... | Line 6387... | ||
6445 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); |
6387 | else |
6446 | drm_atomic_state_free(state); |
6388 | dev_priv->modeset_restore_state = state; |
Line 7595... | Line 7537... | ||
7595 | * |
7537 | * |
7596 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
7538 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
7597 | * in cases where we need the PLL enabled even when @pipe is not going to |
7539 | * in cases where we need the PLL enabled even when @pipe is not going to |
7598 | * be enabled. |
7540 | * be enabled. |
7599 | */ |
7541 | */ |
7600 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7542 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7601 | const struct dpll *dpll) |
7543 | const struct dpll *dpll) |
7602 | { |
7544 | { |
7603 | struct intel_crtc *crtc = |
7545 | struct intel_crtc *crtc = |
7604 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
7546 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); |
7605 | struct intel_crtc_state pipe_config = { |
7547 | struct intel_crtc_state *pipe_config; |
- | 7548 | ||
- | 7549 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
|
- | 7550 | if (!pipe_config) |
|
- | 7551 | return -ENOMEM; |
|
- | 7552 | ||
7606 | .base.crtc = &crtc->base, |
7553 | pipe_config->base.crtc = &crtc->base; |
7607 | .pixel_multiplier = 1, |
7554 | pipe_config->pixel_multiplier = 1; |
7608 | .dpll = *dpll, |
7555 | pipe_config->dpll = *dpll; |
7609 | }; |
- | |
Line 7610... | Line 7556... | ||
7610 | 7556 | ||
7611 | if (IS_CHERRYVIEW(dev)) { |
7557 | if (IS_CHERRYVIEW(dev)) { |
7612 | chv_compute_dpll(crtc, &pipe_config); |
7558 | chv_compute_dpll(crtc, pipe_config); |
7613 | chv_prepare_pll(crtc, &pipe_config); |
7559 | chv_prepare_pll(crtc, pipe_config); |
7614 | chv_enable_pll(crtc, &pipe_config); |
7560 | chv_enable_pll(crtc, pipe_config); |
7615 | } else { |
7561 | } else { |
7616 | vlv_compute_dpll(crtc, &pipe_config); |
7562 | vlv_compute_dpll(crtc, pipe_config); |
7617 | vlv_prepare_pll(crtc, &pipe_config); |
7563 | vlv_prepare_pll(crtc, pipe_config); |
7618 | vlv_enable_pll(crtc, &pipe_config); |
7564 | vlv_enable_pll(crtc, pipe_config); |
- | 7565 | } |
|
- | 7566 | ||
- | 7567 | kfree(pipe_config); |
|
- | 7568 | ||
7619 | } |
7569 | return 0; |
Line 7620... | Line 7570... | ||
7620 | } |
7570 | } |
7621 | 7571 | ||
7622 | /** |
7572 | /** |
Line 8037... | Line 7987... | ||
8037 | return; |
7987 | return; |
8038 | } |
7988 | } |
Line 8039... | Line 7989... | ||
8039 | 7989 | ||
8040 | pipe_config->gmch_pfit.control = tmp; |
7990 | pipe_config->gmch_pfit.control = tmp; |
8041 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
- | |
8042 | if (INTEL_INFO(dev)->gen < 5) |
- | |
8043 | pipe_config->gmch_pfit.lvds_border_bits = |
- | |
8044 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
7991 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
Line 8045... | Line 7992... | ||
8045 | } |
7992 | } |
8046 | 7993 | ||
8047 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
7994 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
Line 8280... | Line 8227... | ||
8280 | 8227 | ||
8281 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
8228 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
8282 | { |
8229 | { |
8283 | struct drm_i915_private *dev_priv = dev->dev_private; |
8230 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | 8231 | struct intel_encoder *encoder; |
|
8284 | struct intel_encoder *encoder; |
8232 | int i; |
8285 | u32 val, final; |
8233 | u32 val, final; |
8286 | bool has_lvds = false; |
8234 | bool has_lvds = false; |
8287 | bool has_cpu_edp = false; |
8235 | bool has_cpu_edp = false; |
8288 | bool has_panel = false; |
8236 | bool has_panel = false; |
8289 | bool has_ck505 = false; |
8237 | bool has_ck505 = false; |
- | 8238 | bool can_ssc = false; |
|
Line 8290... | Line 8239... | ||
8290 | bool can_ssc = false; |
8239 | bool using_ssc_source = false; |
8291 | 8240 | ||
8292 | /* We need to take the global config into account */ |
8241 | /* We need to take the global config into account */ |
8293 | for_each_intel_encoder(dev, encoder) { |
8242 | for_each_intel_encoder(dev, encoder) { |
Line 8312... | Line 8261... | ||
8312 | } else { |
8261 | } else { |
8313 | has_ck505 = false; |
8262 | has_ck505 = false; |
8314 | can_ssc = true; |
8263 | can_ssc = true; |
8315 | } |
8264 | } |
Line -... | Line 8265... | ||
- | 8265 | ||
- | 8266 | /* Check if any DPLLs are using the SSC source */ |
|
- | 8267 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
|
- | 8268 | u32 temp = I915_READ(PCH_DPLL(i)); |
|
- | 8269 | ||
- | 8270 | if (!(temp & DPLL_VCO_ENABLE)) |
|
- | 8271 | continue; |
|
- | 8272 | ||
- | 8273 | if ((temp & PLL_REF_INPUT_MASK) == |
|
- | 8274 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
|
- | 8275 | using_ssc_source = true; |
|
- | 8276 | break; |
|
- | 8277 | } |
|
- | 8278 | } |
|
8316 | 8279 | ||
8317 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8280 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", |
Line 8318... | Line 8281... | ||
8318 | has_panel, has_lvds, has_ck505); |
8281 | has_panel, has_lvds, has_ck505, using_ssc_source); |
8319 | 8282 | ||
8320 | /* Ironlake: try to setup display ref clock before DPLL |
8283 | /* Ironlake: try to setup display ref clock before DPLL |
8321 | * enabling. This is only under driver's control after |
8284 | * enabling. This is only under driver's control after |
Line 8350... | Line 8313... | ||
8350 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
8313 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
8351 | else |
8314 | else |
8352 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
8315 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
8353 | } else |
8316 | } else |
8354 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8317 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8355 | } else { |
8318 | } else if (using_ssc_source) { |
8356 | final |= DREF_SSC_SOURCE_DISABLE; |
8319 | final |= DREF_SSC_SOURCE_ENABLE; |
8357 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8320 | final |= DREF_SSC1_ENABLE; |
8358 | } |
8321 | } |
Line 8359... | Line 8322... | ||
8359 | 8322 | ||
8360 | if (final == val) |
8323 | if (final == val) |
Line 8398... | Line 8361... | ||
8398 | 8361 | ||
8399 | I915_WRITE(PCH_DREF_CONTROL, val); |
8362 | I915_WRITE(PCH_DREF_CONTROL, val); |
8400 | POSTING_READ(PCH_DREF_CONTROL); |
8363 | POSTING_READ(PCH_DREF_CONTROL); |
8401 | udelay(200); |
8364 | udelay(200); |
8402 | } else { |
8365 | } else { |
Line 8403... | Line 8366... | ||
8403 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
8366 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
Line 8404... | Line 8367... | ||
8404 | 8367 | ||
8405 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8368 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Line 8406... | Line 8369... | ||
8406 | 8369 | ||
8407 | /* Turn off CPU output */ |
8370 | /* Turn off CPU output */ |
8408 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
8371 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Line -... | Line 8372... | ||
- | 8372 | ||
- | 8373 | I915_WRITE(PCH_DREF_CONTROL, val); |
|
- | 8374 | POSTING_READ(PCH_DREF_CONTROL); |
|
8409 | 8375 | udelay(200); |
|
8410 | I915_WRITE(PCH_DREF_CONTROL, val); |
8376 | |
8411 | POSTING_READ(PCH_DREF_CONTROL); |
8377 | if (!using_ssc_source) { |
Line 8412... | Line 8378... | ||
8412 | udelay(200); |
8378 | DRM_DEBUG_KMS("Disabling SSC source\n"); |
Line 8420... | Line 8386... | ||
8420 | 8386 | ||
8421 | I915_WRITE(PCH_DREF_CONTROL, val); |
8387 | I915_WRITE(PCH_DREF_CONTROL, val); |
8422 | POSTING_READ(PCH_DREF_CONTROL); |
8388 | POSTING_READ(PCH_DREF_CONTROL); |
8423 | udelay(200); |
8389 | udelay(200); |
- | 8390 | } |
|
Line 8424... | Line 8391... | ||
8424 | } |
8391 | } |
8425 | 8392 | ||
Line 8426... | Line 8393... | ||
8426 | BUG_ON(val != final); |
8393 | BUG_ON(val != final); |
Line 9257... | Line 9224... | ||
9257 | val = I915_READ(PLANE_SIZE(pipe, 0)); |
9224 | val = I915_READ(PLANE_SIZE(pipe, 0)); |
9258 | fb->height = ((val >> 16) & 0xfff) + 1; |
9225 | fb->height = ((val >> 16) & 0xfff) + 1; |
9259 | fb->width = ((val >> 0) & 0x1fff) + 1; |
9226 | fb->width = ((val >> 0) & 0x1fff) + 1; |
Line 9260... | Line 9227... | ||
9260 | 9227 | ||
9261 | val = I915_READ(PLANE_STRIDE(pipe, 0)); |
9228 | val = I915_READ(PLANE_STRIDE(pipe, 0)); |
9262 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9229 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
9263 | fb->pixel_format); |
9230 | fb->pixel_format); |
Line 9264... | Line 9231... | ||
9264 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9231 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9265 | 9232 | ||
Line 9681... | Line 9648... | ||
9681 | if (HAS_PCH_LPT_LP(dev)) { |
9648 | if (HAS_PCH_LPT_LP(dev)) { |
9682 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9649 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9683 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
9650 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
9684 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
9651 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
9685 | } |
9652 | } |
9686 | - | ||
9687 | intel_prepare_ddi(dev); |
- | |
9688 | } |
9653 | } |
Line 9689... | Line 9654... | ||
9689 | 9654 | ||
9690 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
9655 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
9691 | { |
9656 | { |
- | 9657 | struct drm_device *dev = old_state->dev; |
|
- | 9658 | struct intel_atomic_state *old_intel_state = |
|
9692 | struct drm_device *dev = old_state->dev; |
9659 | to_intel_atomic_state(old_state); |
Line 9693... | Line 9660... | ||
9693 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
9660 | unsigned int req_cdclk = old_intel_state->dev_cdclk; |
9694 | 9661 | ||
Line 9695... | Line 9662... | ||
9695 | broxton_set_cdclk(dev, req_cdclk); |
9662 | broxton_set_cdclk(dev, req_cdclk); |
9696 | } |
9663 | } |
9697 | 9664 | ||
- | 9665 | /* compute the max rate for new configuration */ |
|
- | 9666 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
|
9698 | /* compute the max rate for new configuration */ |
9667 | { |
- | 9668 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
|
9699 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
9669 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
9700 | { |
9670 | struct drm_crtc *crtc; |
- | 9671 | struct drm_crtc_state *cstate; |
|
Line 9701... | Line 9672... | ||
9701 | struct intel_crtc *intel_crtc; |
9672 | struct intel_crtc_state *crtc_state; |
9702 | struct intel_crtc_state *crtc_state; |
9673 | unsigned max_pixel_rate = 0, i; |
Line 9703... | Line 9674... | ||
9703 | int max_pixel_rate = 0; |
9674 | enum pipe pipe; |
9704 | 9675 | ||
9705 | for_each_intel_crtc(state->dev, intel_crtc) { |
- | |
Line -... | Line 9676... | ||
- | 9676 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
|
9706 | int pixel_rate; |
9677 | sizeof(intel_state->min_pixclk)); |
- | 9678 | ||
9707 | 9679 | for_each_crtc_in_state(state, crtc, cstate, i) { |
|
- | 9680 | int pixel_rate; |
|
Line 9708... | Line 9681... | ||
9708 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9681 | |
Line 9709... | Line 9682... | ||
9709 | if (IS_ERR(crtc_state)) |
9682 | crtc_state = to_intel_crtc_state(cstate); |
9710 | return PTR_ERR(crtc_state); |
9683 | if (!crtc_state->base.enable) { |
9711 | 9684 | intel_state->min_pixclk[i] = 0; |
|
Line 9712... | Line 9685... | ||
9712 | if (!crtc_state->base.enable) |
9685 | continue; |
9713 | continue; |
9686 | } |
Line -... | Line 9687... | ||
- | 9687 | ||
- | 9688 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
|
- | 9689 | ||
9714 | 9690 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
|
9715 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
9691 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
Line 9716... | Line 9692... | ||
9716 | 9692 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
|
9717 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
9693 | |
Line 9804... | Line 9780... | ||
9804 | } |
9780 | } |
Line 9805... | Line 9781... | ||
9805 | 9781 | ||
9806 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
9782 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
9807 | { |
9783 | { |
- | 9784 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
|
9808 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9785 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9809 | int max_pixclk = ilk_max_pixel_rate(state); |
9786 | int max_pixclk = ilk_max_pixel_rate(state); |
Line 9810... | Line 9787... | ||
9810 | int cdclk; |
9787 | int cdclk; |
9811 | 9788 | ||
Line 9826... | Line 9803... | ||
9826 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9803 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9827 | cdclk, dev_priv->max_cdclk_freq); |
9804 | cdclk, dev_priv->max_cdclk_freq); |
9828 | return -EINVAL; |
9805 | return -EINVAL; |
9829 | } |
9806 | } |
Line 9830... | Line 9807... | ||
9830 | 9807 | ||
- | 9808 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
|
- | 9809 | if (!intel_state->active_crtcs) |
|
Line 9831... | Line 9810... | ||
9831 | to_intel_atomic_state(state)->cdclk = cdclk; |
9810 | intel_state->dev_cdclk = 337500; |
9832 | 9811 | ||
Line 9833... | Line 9812... | ||
9833 | return 0; |
9812 | return 0; |
9834 | } |
9813 | } |
9835 | 9814 | ||
- | 9815 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
|
- | 9816 | { |
|
9836 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
9817 | struct drm_device *dev = old_state->dev; |
Line 9837... | Line 9818... | ||
9837 | { |
9818 | struct intel_atomic_state *old_intel_state = |
9838 | struct drm_device *dev = old_state->dev; |
9819 | to_intel_atomic_state(old_state); |
Line 9839... | Line 9820... | ||
9839 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
9820 | unsigned req_cdclk = old_intel_state->dev_cdclk; |
9840 | 9821 | ||
9841 | broadwell_set_cdclk(dev, req_cdclk); |
9822 | broadwell_set_cdclk(dev, req_cdclk); |
- | 9823 | } |
|
- | 9824 | ||
- | 9825 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
|
- | 9826 | struct intel_crtc_state *crtc_state) |
|
9842 | } |
9827 | { |
9843 | 9828 | struct intel_encoder *intel_encoder = |
|
- | 9829 | intel_ddi_get_crtc_new_encoder(crtc_state); |
|
Line 9844... | Line 9830... | ||
9844 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9830 | |
Line 9845... | Line 9831... | ||
9845 | struct intel_crtc_state *crtc_state) |
9831 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { |
9846 | { |
9832 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
Line 10059... | Line 10045... | ||
10059 | intel_display_power_put(dev_priv, power_domain); |
10045 | intel_display_power_put(dev_priv, power_domain); |
Line 10060... | Line 10046... | ||
10060 | 10046 | ||
10061 | return ret; |
10047 | return ret; |
Line 10062... | Line 10048... | ||
10062 | } |
10048 | } |
- | 10049 | ||
10063 | 10050 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
|
10064 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
10051 | const struct intel_plane_state *plane_state) |
10065 | { |
10052 | { |
10066 | struct drm_device *dev = crtc->dev; |
10053 | struct drm_device *dev = crtc->dev; |
10067 | struct drm_i915_private *dev_priv = dev->dev_private; |
10054 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 10068... | Line 10055... | ||
10068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10069 | uint32_t cntl = 0, size = 0; |
10056 | uint32_t cntl = 0, size = 0; |
10070 | 10057 | ||
10071 | if (on) { |
10058 | if (plane_state && plane_state->visible) { |
Line 10072... | Line 10059... | ||
10072 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10059 | unsigned int width = plane_state->base.crtc_w; |
10073 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; |
10060 | unsigned int height = plane_state->base.crtc_h; |
10074 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10061 | unsigned int stride = roundup_pow_of_two(width) * 4; |
Line 10121... | Line 10108... | ||
10121 | POSTING_READ(CURCNTR(PIPE_A)); |
10108 | POSTING_READ(CURCNTR(PIPE_A)); |
10122 | intel_crtc->cursor_cntl = cntl; |
10109 | intel_crtc->cursor_cntl = cntl; |
10123 | } |
10110 | } |
10124 | } |
10111 | } |
Line 10125... | Line 10112... | ||
10125 | 10112 | ||
- | 10113 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
|
10126 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
10114 | const struct intel_plane_state *plane_state) |
10127 | { |
10115 | { |
10128 | struct drm_device *dev = crtc->dev; |
10116 | struct drm_device *dev = crtc->dev; |
10129 | struct drm_i915_private *dev_priv = dev->dev_private; |
10117 | struct drm_i915_private *dev_priv = dev->dev_private; |
10130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10131 | int pipe = intel_crtc->pipe; |
10119 | int pipe = intel_crtc->pipe; |
Line 10132... | Line 10120... | ||
10132 | uint32_t cntl = 0; |
10120 | uint32_t cntl = 0; |
10133 | 10121 | ||
10134 | if (on) { |
10122 | if (plane_state && plane_state->visible) { |
10135 | cntl = MCURSOR_GAMMA_ENABLE; |
10123 | cntl = MCURSOR_GAMMA_ENABLE; |
10136 | switch (intel_crtc->base.cursor->state->crtc_w) { |
10124 | switch (plane_state->base.crtc_w) { |
10137 | case 64: |
10125 | case 64: |
10138 | cntl |= CURSOR_MODE_64_ARGB_AX; |
10126 | cntl |= CURSOR_MODE_64_ARGB_AX; |
10139 | break; |
10127 | break; |
10140 | case 128: |
10128 | case 128: |
10141 | cntl |= CURSOR_MODE_128_ARGB_AX; |
10129 | cntl |= CURSOR_MODE_128_ARGB_AX; |
10142 | break; |
10130 | break; |
10143 | case 256: |
10131 | case 256: |
10144 | cntl |= CURSOR_MODE_256_ARGB_AX; |
10132 | cntl |= CURSOR_MODE_256_ARGB_AX; |
10145 | break; |
10133 | break; |
10146 | default: |
10134 | default: |
10147 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
10135 | MISSING_CASE(plane_state->base.crtc_w); |
10148 | return; |
10136 | return; |
Line 10149... | Line 10137... | ||
10149 | } |
10137 | } |
10150 | cntl |= pipe << 28; /* Connect to correct pipe */ |
10138 | cntl |= pipe << 28; /* Connect to correct pipe */ |
10151 | - | ||
Line 10152... | Line 10139... | ||
10152 | if (HAS_DDI(dev)) |
10139 | |
10153 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
10140 | if (HAS_DDI(dev)) |
- | 10141 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
|
Line 10154... | Line 10142... | ||
10154 | } |
10142 | |
10155 | 10143 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
|
10156 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
10144 | cntl |= CURSOR_ROTATE_180; |
10157 | cntl |= CURSOR_ROTATE_180; |
10145 | } |
Line 10169... | Line 10157... | ||
10169 | intel_crtc->cursor_base = base; |
10157 | intel_crtc->cursor_base = base; |
10170 | } |
10158 | } |
Line 10171... | Line 10159... | ||
10171 | 10159 | ||
10172 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
10160 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
10173 | void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10161 | void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10174 | bool on) |
10162 | const struct intel_plane_state *plane_state) |
10175 | { |
10163 | { |
10176 | struct drm_device *dev = crtc->dev; |
10164 | struct drm_device *dev = crtc->dev; |
10177 | struct drm_i915_private *dev_priv = dev->dev_private; |
10165 | struct drm_i915_private *dev_priv = dev->dev_private; |
10178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10179 | int pipe = intel_crtc->pipe; |
- | |
10180 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
- | |
10181 | int x = cursor_state->crtc_x; |
- | |
10182 | int y = cursor_state->crtc_y; |
- | |
10183 | u32 base = 0, pos = 0; |
- | |
10184 | 10167 | int pipe = intel_crtc->pipe; |
|
10185 | base = intel_crtc->cursor_addr; |
- | |
10186 | - | ||
10187 | if (x >= intel_crtc->config->pipe_src_w) |
10168 | u32 base = intel_crtc->cursor_addr; |
Line -... | Line 10169... | ||
- | 10169 | u32 pos = 0; |
|
10188 | on = false; |
10170 | |
10189 | 10171 | if (plane_state) { |
|
Line 10190... | Line 10172... | ||
10190 | if (y >= intel_crtc->config->pipe_src_h) |
10172 | int x = plane_state->base.crtc_x; |
10191 | on = false; |
- | |
10192 | - | ||
10193 | if (x < 0) { |
- | |
10194 | if (x + cursor_state->crtc_w <= 0) |
10173 | int y = plane_state->base.crtc_y; |
10195 | on = false; |
10174 | |
10196 | 10175 | if (x < 0) { |
|
10197 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
10176 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
Line 10198... | Line 10177... | ||
10198 | x = -x; |
10177 | x = -x; |
10199 | } |
- | |
10200 | pos |= x << CURSOR_X_SHIFT; |
- | |
10201 | - | ||
10202 | if (y < 0) { |
10178 | } |
10203 | if (y + cursor_state->crtc_h <= 0) |
10179 | pos |= x << CURSOR_X_SHIFT; |
10204 | on = false; |
10180 | |
10205 | 10181 | if (y < 0) { |
|
Line 10206... | Line -... | ||
10206 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
- | |
10207 | y = -y; |
- | |
10208 | } |
10182 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
10209 | pos |= y << CURSOR_Y_SHIFT; |
10183 | y = -y; |
10210 | 10184 | } |
|
10211 | I915_WRITE(CURPOS(pipe), pos); |
10185 | pos |= y << CURSOR_Y_SHIFT; |
10212 | 10186 | ||
- | 10187 | /* ILK+ do this automagically */ |
|
10213 | /* ILK+ do this automagically */ |
10188 | if (HAS_GMCH_DISPLAY(dev) && |
Line -... | Line 10189... | ||
- | 10189 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
|
- | 10190 | base += (plane_state->base.crtc_h * |
|
10214 | if (HAS_GMCH_DISPLAY(dev) && |
10191 | plane_state->base.crtc_w - 1) * 4; |
10215 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
10192 | } |
10216 | base += (cursor_state->crtc_h * |
10193 | } |
10217 | cursor_state->crtc_w - 1) * 4; |
10194 | |
10218 | } |
10195 | I915_WRITE(CURPOS(pipe), pos); |
Line 10219... | Line 10196... | ||
10219 | 10196 | ||
10220 | if (IS_845G(dev) || IS_I865G(dev)) |
10197 | if (IS_845G(dev) || IS_I865G(dev)) |
10221 | i845_update_cursor(crtc, base, on); |
10198 | i845_update_cursor(crtc, base, plane_state); |
Line 10386... | Line 10363... | ||
10386 | return NULL; |
10363 | return NULL; |
Line 10387... | Line 10364... | ||
10387 | 10364 | ||
10388 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
10365 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Line -... | Line 10366... | ||
- | 10366 | return NULL; |
|
10389 | return NULL; |
10367 | |
10390 | 10368 | drm_framebuffer_reference(fb); |
|
10391 | return fb; |
10369 | return fb; |
10392 | #else |
10370 | #else |
10393 | return NULL; |
10371 | return NULL; |
Line 10441... | Line 10419... | ||
10441 | struct drm_encoder *encoder = &intel_encoder->base; |
10419 | struct drm_encoder *encoder = &intel_encoder->base; |
10442 | struct drm_crtc *crtc = NULL; |
10420 | struct drm_crtc *crtc = NULL; |
10443 | struct drm_device *dev = encoder->dev; |
10421 | struct drm_device *dev = encoder->dev; |
10444 | struct drm_framebuffer *fb; |
10422 | struct drm_framebuffer *fb; |
10445 | struct drm_mode_config *config = &dev->mode_config; |
10423 | struct drm_mode_config *config = &dev->mode_config; |
10446 | struct drm_atomic_state *state = NULL; |
10424 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
10447 | struct drm_connector_state *connector_state; |
10425 | struct drm_connector_state *connector_state; |
10448 | struct intel_crtc_state *crtc_state; |
10426 | struct intel_crtc_state *crtc_state; |
10449 | int ret, i = -1; |
10427 | int ret, i = -1; |
Line 10450... | Line 10428... | ||
10450 | 10428 | ||
10451 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
10429 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
10452 | connector->base.id, connector->name, |
10430 | connector->base.id, connector->name, |
Line -... | Line 10431... | ||
- | 10431 | encoder->base.id, encoder->name); |
|
- | 10432 | ||
10453 | encoder->base.id, encoder->name); |
10433 | old->restore_state = NULL; |
10454 | 10434 | ||
10455 | retry: |
10435 | retry: |
10456 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
10436 | ret = drm_modeset_lock(&config->connection_mutex, ctx); |
Line 10466... | Line 10446... | ||
10466 | * - try to find the first unused crtc that can drive this connector, |
10446 | * - try to find the first unused crtc that can drive this connector, |
10467 | * and use that if we find one |
10447 | * and use that if we find one |
10468 | */ |
10448 | */ |
Line 10469... | Line 10449... | ||
10469 | 10449 | ||
10470 | /* See if we already have a CRTC for this connector */ |
10450 | /* See if we already have a CRTC for this connector */ |
10471 | if (encoder->crtc) { |
10451 | if (connector->state->crtc) { |
Line 10472... | Line 10452... | ||
10472 | crtc = encoder->crtc; |
10452 | crtc = connector->state->crtc; |
10473 | 10453 | ||
10474 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10454 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10475 | if (ret) |
- | |
10476 | goto fail; |
- | |
10477 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
- | |
10478 | if (ret) |
- | |
10479 | goto fail; |
- | |
10480 | - | ||
Line 10481... | Line 10455... | ||
10481 | old->dpms_mode = connector->dpms; |
10455 | if (ret) |
10482 | old->load_detect_temp = false; |
- | |
10483 | - | ||
10484 | /* Make sure the crtc and connector are running */ |
- | |
10485 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10456 | goto fail; |
10486 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
10457 | |
Line 10487... | Line 10458... | ||
10487 | 10458 | /* Make sure the crtc and connector are running */ |
|
10488 | return true; |
10459 | goto found; |
10489 | } |
10460 | } |
10490 | 10461 | ||
10491 | /* Find an unused one (if possible) */ |
10462 | /* Find an unused one (if possible) */ |
- | 10463 | for_each_crtc(dev, possible_crtc) { |
|
- | 10464 | i++; |
|
- | 10465 | if (!(encoder->possible_crtcs & (1 << i))) |
|
- | 10466 | continue; |
|
- | 10467 | ||
10492 | for_each_crtc(dev, possible_crtc) { |
10468 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); |
- | 10469 | if (ret) |
|
10493 | i++; |
10470 | goto fail; |
- | 10471 | ||
Line 10494... | Line 10472... | ||
10494 | if (!(encoder->possible_crtcs & (1 << i))) |
10472 | if (possible_crtc->state->enable) { |
10495 | continue; |
10473 | drm_modeset_unlock(&possible_crtc->mutex); |
10496 | if (possible_crtc->state->enable) |
10474 | continue; |
Line 10506... | Line 10484... | ||
10506 | if (!crtc) { |
10484 | if (!crtc) { |
10507 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
10485 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
10508 | goto fail; |
10486 | goto fail; |
10509 | } |
10487 | } |
Line 10510... | Line -... | ||
10510 | - | ||
10511 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10488 | |
10512 | if (ret) |
10489 | found: |
- | 10490 | intel_crtc = to_intel_crtc(crtc); |
|
10513 | goto fail; |
10491 | |
10514 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10492 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10515 | if (ret) |
10493 | if (ret) |
Line 10516... | Line -... | ||
10516 | goto fail; |
- | |
10517 | - | ||
10518 | intel_crtc = to_intel_crtc(crtc); |
- | |
10519 | old->dpms_mode = connector->dpms; |
- | |
10520 | old->load_detect_temp = true; |
- | |
10521 | old->release_fb = NULL; |
10494 | goto fail; |
- | 10495 | ||
10522 | 10496 | state = drm_atomic_state_alloc(dev); |
|
- | 10497 | restore_state = drm_atomic_state_alloc(dev); |
|
10523 | state = drm_atomic_state_alloc(dev); |
10498 | if (!state || !restore_state) { |
- | 10499 | ret = -ENOMEM; |
|
Line 10524... | Line 10500... | ||
10524 | if (!state) |
10500 | goto fail; |
- | 10501 | } |
|
Line 10525... | Line 10502... | ||
10525 | return false; |
10502 | |
10526 | 10503 | state->acquire_ctx = ctx; |
|
10527 | state->acquire_ctx = ctx; |
10504 | restore_state->acquire_ctx = ctx; |
10528 | 10505 | ||
10529 | connector_state = drm_atomic_get_connector_state(state, connector); |
10506 | connector_state = drm_atomic_get_connector_state(state, connector); |
Line 10530... | Line 10507... | ||
10530 | if (IS_ERR(connector_state)) { |
10507 | if (IS_ERR(connector_state)) { |
- | 10508 | ret = PTR_ERR(connector_state); |
|
10531 | ret = PTR_ERR(connector_state); |
10509 | goto fail; |
Line 10532... | Line 10510... | ||
10532 | goto fail; |
10510 | } |
10533 | } |
10511 | |
10534 | 10512 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
|
10535 | connector_state->crtc = crtc; |
10513 | if (ret) |
Line 10555... | Line 10533... | ||
10555 | */ |
10533 | */ |
10556 | fb = mode_fits_in_fbdev(dev, mode); |
10534 | fb = mode_fits_in_fbdev(dev, mode); |
10557 | if (fb == NULL) { |
10535 | if (fb == NULL) { |
10558 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
10536 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
10559 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10537 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10560 | old->release_fb = fb; |
- | |
10561 | } else |
10538 | } else |
10562 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
10539 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
10563 | if (IS_ERR(fb)) { |
10540 | if (IS_ERR(fb)) { |
10564 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
10541 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
10565 | goto fail; |
10542 | goto fail; |
Line 10567... | Line 10544... | ||
10567 | 10544 | ||
10568 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10545 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10569 | if (ret) |
10546 | if (ret) |
Line 10570... | Line 10547... | ||
10570 | goto fail; |
10547 | goto fail; |
Line -... | Line 10548... | ||
- | 10548 | ||
- | 10549 | drm_framebuffer_unreference(fb); |
|
- | 10550 | ||
- | 10551 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); |
|
- | 10552 | if (ret) |
|
- | 10553 | goto fail; |
|
- | 10554 | ||
- | 10555 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); |
|
- | 10556 | if (!ret) |
|
- | 10557 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); |
|
- | 10558 | if (!ret) |
|
- | 10559 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); |
|
- | 10560 | if (ret) { |
|
- | 10561 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); |
|
10571 | 10562 | goto fail; |
|
- | 10563 | } |
|
10572 | drm_mode_copy(&crtc_state->base.mode, mode); |
10564 | |
10573 | - | ||
10574 | if (drm_atomic_commit(state)) { |
- | |
10575 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
10565 | ret = drm_atomic_commit(state); |
10576 | if (old->release_fb) |
10566 | if (ret) { |
- | 10567 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
|
10577 | old->release_fb->funcs->destroy(old->release_fb); |
10568 | goto fail; |
Line 10578... | Line 10569... | ||
10578 | goto fail; |
10569 | } |
10579 | } |
10570 | |
10580 | crtc->primary->crtc = crtc; |
10571 | old->restore_state = restore_state; |
Line 10581... | Line 10572... | ||
10581 | 10572 | ||
10582 | /* let the connector get through one full cycle before testing */ |
10573 | /* let the connector get through one full cycle before testing */ |
- | 10574 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
|
10583 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
10575 | return true; |
Line 10584... | Line 10576... | ||
10584 | return true; |
10576 | |
10585 | 10577 | fail: |
|
10586 | fail: |
10578 | drm_atomic_state_free(state); |
10587 | drm_atomic_state_free(state); |
10579 | drm_atomic_state_free(restore_state); |
Line 10597... | Line 10589... | ||
10597 | 10589 | ||
10598 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
10590 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
10599 | struct intel_load_detect_pipe *old, |
10591 | struct intel_load_detect_pipe *old, |
10600 | struct drm_modeset_acquire_ctx *ctx) |
10592 | struct drm_modeset_acquire_ctx *ctx) |
10601 | { |
- | |
10602 | struct drm_device *dev = connector->dev; |
10593 | { |
10603 | struct intel_encoder *intel_encoder = |
10594 | struct intel_encoder *intel_encoder = |
10604 | intel_attached_encoder(connector); |
10595 | intel_attached_encoder(connector); |
10605 | struct drm_encoder *encoder = &intel_encoder->base; |
- | |
10606 | struct drm_crtc *crtc = encoder->crtc; |
- | |
10607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
10608 | struct drm_atomic_state *state; |
10596 | struct drm_encoder *encoder = &intel_encoder->base; |
10609 | struct drm_connector_state *connector_state; |
- | |
10610 | struct intel_crtc_state *crtc_state; |
10597 | struct drm_atomic_state *state = old->restore_state; |
Line 10611... | Line 10598... | ||
10611 | int ret; |
10598 | int ret; |
10612 | 10599 | ||
10613 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
10600 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
Line 10614... | Line -... | ||
10614 | connector->base.id, connector->name, |
- | |
10615 | encoder->base.id, encoder->name); |
- | |
10616 | 10601 | connector->base.id, connector->name, |
|
10617 | if (old->load_detect_temp) { |
- | |
10618 | state = drm_atomic_state_alloc(dev); |
- | |
10619 | if (!state) |
- | |
10620 | goto fail; |
- | |
10621 | - | ||
10622 | state->acquire_ctx = ctx; |
- | |
10623 | - | ||
10624 | connector_state = drm_atomic_get_connector_state(state, connector); |
- | |
10625 | if (IS_ERR(connector_state)) |
- | |
10626 | goto fail; |
- | |
10627 | - | ||
10628 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
- | |
10629 | if (IS_ERR(crtc_state)) |
- | |
10630 | goto fail; |
- | |
10631 | - | ||
10632 | connector_state->best_encoder = NULL; |
- | |
10633 | connector_state->crtc = NULL; |
- | |
10634 | - | ||
10635 | crtc_state->base.enable = crtc_state->base.active = false; |
- | |
10636 | - | ||
10637 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
- | |
10638 | 0, 0); |
- | |
10639 | if (ret) |
- | |
10640 | goto fail; |
- | |
10641 | - | ||
10642 | ret = drm_atomic_commit(state); |
- | |
10643 | if (ret) |
- | |
10644 | goto fail; |
- | |
10645 | - | ||
10646 | if (old->release_fb) { |
- | |
10647 | drm_framebuffer_unregister_private(old->release_fb); |
- | |
10648 | drm_framebuffer_unreference(old->release_fb); |
10602 | encoder->base.id, encoder->name); |
10649 | } |
- | |
Line 10650... | Line -... | ||
10650 | - | ||
10651 | return; |
- | |
10652 | } |
10603 | |
10653 | - | ||
10654 | /* Switch crtc and encoder back off if necessary */ |
10604 | if (!state) |
10655 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
- | |
10656 | connector->funcs->dpms(connector, old->dpms_mode); |
10605 | return; |
10657 | 10606 | ||
10658 | return; |
10607 | ret = drm_atomic_commit(state); |
- | 10608 | if (ret) { |
|
Line 10659... | Line 10609... | ||
10659 | fail: |
10609 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
10660 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); |
10610 | drm_atomic_state_free(state); |
10661 | drm_atomic_state_free(state); |
10611 | } |
10662 | } |
10612 | } |
Line 10811... | Line 10761... | ||
10811 | { |
10761 | { |
10812 | struct drm_i915_private *dev_priv = dev->dev_private; |
10762 | struct drm_i915_private *dev_priv = dev->dev_private; |
10813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10814 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
10764 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
10815 | struct drm_display_mode *mode; |
10765 | struct drm_display_mode *mode; |
10816 | struct intel_crtc_state pipe_config; |
10766 | struct intel_crtc_state *pipe_config; |
10817 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10767 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10818 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
10768 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
10819 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
10769 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
10820 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
10770 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
10821 | enum pipe pipe = intel_crtc->pipe; |
10771 | enum pipe pipe = intel_crtc->pipe; |
Line 10822... | Line 10772... | ||
10822 | 10772 | ||
10823 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
10773 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
10824 | if (!mode) |
10774 | if (!mode) |
Line -... | Line 10775... | ||
- | 10775 | return NULL; |
|
- | 10776 | ||
- | 10777 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
|
- | 10778 | if (!pipe_config) { |
|
- | 10779 | kfree(mode); |
|
- | 10780 | return NULL; |
|
10825 | return NULL; |
10781 | } |
10826 | 10782 | ||
10827 | /* |
10783 | /* |
10828 | * Construct a pipe_config sufficient for getting the clock info |
10784 | * Construct a pipe_config sufficient for getting the clock info |
10829 | * back out of crtc_clock_get. |
10785 | * back out of crtc_clock_get. |
10830 | * |
10786 | * |
10831 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
10787 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
10832 | * to use a real value here instead. |
10788 | * to use a real value here instead. |
10833 | */ |
10789 | */ |
10834 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
10790 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10835 | pipe_config.pixel_multiplier = 1; |
10791 | pipe_config->pixel_multiplier = 1; |
10836 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10792 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10837 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
10793 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
Line 10838... | Line 10794... | ||
10838 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
10794 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
10839 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10795 | i9xx_crtc_clock_get(intel_crtc, pipe_config); |
10840 | 10796 | ||
10841 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
10797 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; |
10842 | mode->hdisplay = (htot & 0xffff) + 1; |
10798 | mode->hdisplay = (htot & 0xffff) + 1; |
10843 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
10799 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
Line 10848... | Line 10804... | ||
10848 | mode->vsync_start = (vsync & 0xffff) + 1; |
10804 | mode->vsync_start = (vsync & 0xffff) + 1; |
10849 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
10805 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
Line 10850... | Line 10806... | ||
10850 | 10806 | ||
Line -... | Line 10807... | ||
- | 10807 | drm_mode_set_name(mode); |
|
- | 10808 | ||
10851 | drm_mode_set_name(mode); |
10809 | kfree(pipe_config); |
10852 | 10810 | ||
Line 10853... | Line 10811... | ||
10853 | return mode; |
10811 | return mode; |
10854 | } |
10812 | } |
Line 10892... | Line 10850... | ||
10892 | work = intel_crtc->unpin_work; |
10850 | work = intel_crtc->unpin_work; |
10893 | intel_crtc->unpin_work = NULL; |
10851 | intel_crtc->unpin_work = NULL; |
10894 | spin_unlock_irq(&dev->event_lock); |
10852 | spin_unlock_irq(&dev->event_lock); |
Line 10895... | Line 10853... | ||
10895 | 10853 | ||
10896 | if (work) { |
10854 | if (work) { |
10897 | // cancel_work_sync(&work->work); |
10855 | cancel_work_sync(&work->work); |
10898 | kfree(work); |
10856 | kfree(work); |
Line 10899... | Line 10857... | ||
10899 | } |
10857 | } |
Line 10918... | Line 10876... | ||
10918 | if (work->flip_queued_req) |
10876 | if (work->flip_queued_req) |
10919 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
10877 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
10920 | mutex_unlock(&dev->struct_mutex); |
10878 | mutex_unlock(&dev->struct_mutex); |
Line 10921... | Line 10879... | ||
10921 | 10879 | ||
- | 10880 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
|
10922 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
10881 | intel_fbc_post_update(crtc); |
Line 10923... | Line 10882... | ||
10923 | drm_framebuffer_unreference(work->old_fb); |
10882 | drm_framebuffer_unreference(work->old_fb); |
10924 | 10883 | ||
Line 10999... | Line 10958... | ||
10999 | */ |
10958 | */ |
11000 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
10959 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) |
11001 | return true; |
10960 | return true; |
Line 11002... | Line 10961... | ||
11002 | 10961 | ||
- | 10962 | /* |
|
- | 10963 | * BDW signals flip done immediately if the plane |
|
- | 10964 | * is disabled, even if the plane enable is already |
|
- | 10965 | * armed to occur at the next vblank :( |
|
- | 10966 | */ |
|
- | 10967 | ||
11003 | /* |
10968 | /* |
11004 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
10969 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips |
11005 | * used the same base address. In that case the mmio flip might |
10970 | * used the same base address. In that case the mmio flip might |
11006 | * have completed, but the CS hasn't even executed the flip yet. |
10971 | * have completed, but the CS hasn't even executed the flip yet. |
11007 | * |
10972 | * |
Line 11352... | Line 11317... | ||
11352 | * The stride is either expressed as a multiple of 64 bytes chunks for |
11317 | * The stride is either expressed as a multiple of 64 bytes chunks for |
11353 | * linear buffers or in number of tiles for tiled buffers. |
11318 | * linear buffers or in number of tiles for tiled buffers. |
11354 | */ |
11319 | */ |
11355 | if (intel_rotation_90_or_270(rotation)) { |
11320 | if (intel_rotation_90_or_270(rotation)) { |
11356 | /* stride = Surface height in tiles */ |
11321 | /* stride = Surface height in tiles */ |
11357 | tile_height = intel_tile_height(dev, fb->pixel_format, |
11322 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
11358 | fb->modifier[0], 0); |
- | |
11359 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11323 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11360 | } else { |
11324 | } else { |
11361 | stride = fb->pitches[0] / |
11325 | stride = fb->pitches[0] / |
11362 | intel_fb_stride_alignment(dev, fb->modifier[0], |
11326 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11363 | fb->pixel_format); |
11327 | fb->pixel_format); |
11364 | } |
11328 | } |
Line 11365... | Line 11329... | ||
11365 | 11329 | ||
11366 | /* |
11330 | /* |
Line 11634... | Line 11598... | ||
11634 | drm_framebuffer_reference(work->old_fb); |
11598 | drm_framebuffer_reference(work->old_fb); |
11635 | drm_gem_object_reference(&obj->base); |
11599 | drm_gem_object_reference(&obj->base); |
Line 11636... | Line 11600... | ||
11636 | 11600 | ||
11637 | crtc->primary->fb = fb; |
11601 | crtc->primary->fb = fb; |
- | 11602 | update_state_fb(crtc->primary); |
|
Line 11638... | Line 11603... | ||
11638 | update_state_fb(crtc->primary); |
11603 | intel_fbc_pre_update(intel_crtc); |
Line 11639... | Line 11604... | ||
11639 | 11604 | ||
11640 | work->pending_flip_obj = obj; |
11605 | work->pending_flip_obj = obj; |
Line 11693... | Line 11658... | ||
11693 | 11658 | ||
11694 | i915_gem_request_assign(&work->flip_queued_req, |
11659 | i915_gem_request_assign(&work->flip_queued_req, |
11695 | obj->last_write_req); |
11660 | obj->last_write_req); |
11696 | } else { |
11661 | } else { |
11697 | if (!request) { |
11662 | if (!request) { |
11698 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); |
11663 | request = i915_gem_request_alloc(ring, NULL); |
- | 11664 | if (IS_ERR(request)) { |
|
11699 | if (ret) |
11665 | ret = PTR_ERR(request); |
11700 | goto cleanup_unpin; |
11666 | goto cleanup_unpin; |
- | 11667 | } |
|
Line 11701... | Line 11668... | ||
11701 | } |
11668 | } |
11702 | 11669 | ||
11703 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
11670 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
11704 | page_flip_flags); |
11671 | page_flip_flags); |
Line 11716... | Line 11683... | ||
11716 | 11683 | ||
11717 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
11684 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
11718 | to_intel_plane(primary)->frontbuffer_bit); |
11685 | to_intel_plane(primary)->frontbuffer_bit); |
Line 11719... | Line -... | ||
11719 | mutex_unlock(&dev->struct_mutex); |
- | |
11720 | 11686 | mutex_unlock(&dev->struct_mutex); |
|
11721 | intel_fbc_deactivate(intel_crtc); |
11687 | |
Line 11722... | Line 11688... | ||
11722 | intel_frontbuffer_flip_prepare(dev, |
11688 | intel_frontbuffer_flip_prepare(dev, |
Line 11723... | Line 11689... | ||
11723 | to_intel_plane(primary)->frontbuffer_bit); |
11689 | to_intel_plane(primary)->frontbuffer_bit); |
Line 11724... | Line 11690... | ||
11724 | 11690 | ||
11725 | trace_i915_flip_request(intel_crtc->plane, obj); |
11691 | trace_i915_flip_request(intel_crtc->plane, obj); |
11726 | 11692 | ||
11727 | return 0; |
11693 | return 0; |
11728 | 11694 | ||
11729 | cleanup_unpin: |
11695 | cleanup_unpin: |
11730 | intel_unpin_fb_obj(fb, crtc->primary->state); |
11696 | intel_unpin_fb_obj(fb, crtc->primary->state); |
11731 | cleanup_pending: |
11697 | cleanup_pending: |
11732 | if (request) |
11698 | if (!IS_ERR_OR_NULL(request)) |
Line 11838... | Line 11804... | ||
11838 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
11804 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
11839 | struct drm_crtc *crtc = crtc_state->crtc; |
11805 | struct drm_crtc *crtc = crtc_state->crtc; |
11840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11841 | struct drm_plane *plane = plane_state->plane; |
11807 | struct drm_plane *plane = plane_state->plane; |
11842 | struct drm_device *dev = crtc->dev; |
11808 | struct drm_device *dev = crtc->dev; |
11843 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
11844 | struct intel_plane_state *old_plane_state = |
11809 | struct intel_plane_state *old_plane_state = |
11845 | to_intel_plane_state(plane->state); |
11810 | to_intel_plane_state(plane->state); |
11846 | int idx = intel_crtc->base.base.id, ret; |
11811 | int idx = intel_crtc->base.base.id, ret; |
11847 | int i = drm_plane_index(plane); |
- | |
11848 | bool mode_changed = needs_modeset(crtc_state); |
11812 | bool mode_changed = needs_modeset(crtc_state); |
11849 | bool was_crtc_enabled = crtc->state->active; |
11813 | bool was_crtc_enabled = crtc->state->active; |
11850 | bool is_crtc_enabled = crtc_state->active; |
11814 | bool is_crtc_enabled = crtc_state->active; |
11851 | bool turn_off, turn_on, visible, was_visible; |
11815 | bool turn_off, turn_on, visible, was_visible; |
11852 | struct drm_framebuffer *fb = plane_state->fb; |
11816 | struct drm_framebuffer *fb = plane_state->fb; |
Line 11864... | Line 11828... | ||
11864 | visible = to_intel_plane_state(plane_state)->visible; |
11828 | visible = to_intel_plane_state(plane_state)->visible; |
Line 11865... | Line 11829... | ||
11865 | 11829 | ||
11866 | if (!was_crtc_enabled && WARN_ON(was_visible)) |
11830 | if (!was_crtc_enabled && WARN_ON(was_visible)) |
Line -... | Line 11831... | ||
- | 11831 | was_visible = false; |
|
11867 | was_visible = false; |
11832 | |
- | 11833 | /* |
|
- | 11834 | * Visibility is calculated as if the crtc was on, but |
|
- | 11835 | * after scaler setup everything depends on it being off |
|
11868 | 11836 | * when the crtc isn't active. |
|
- | 11837 | */ |
|
Line 11869... | Line 11838... | ||
11869 | if (!is_crtc_enabled && WARN_ON(visible)) |
11838 | if (!is_crtc_enabled) |
11870 | visible = false; |
11839 | to_intel_plane_state(plane_state)->visible = visible = false; |
Line -... | Line 11840... | ||
- | 11840 | ||
- | 11841 | if (!was_visible && !visible) |
|
- | 11842 | return 0; |
|
11871 | 11843 | ||
11872 | if (!was_visible && !visible) |
11844 | if (fb != old_plane_state->base.fb) |
Line 11873... | Line 11845... | ||
11873 | return 0; |
11845 | pipe_config->fb_changed = true; |
11874 | 11846 | ||
Line 11890... | Line 11862... | ||
11890 | pipe_config->disable_cxsr = true; |
11862 | pipe_config->disable_cxsr = true; |
11891 | } else if (turn_off) { |
11863 | } else if (turn_off) { |
11892 | pipe_config->update_wm_post = true; |
11864 | pipe_config->update_wm_post = true; |
Line 11893... | Line 11865... | ||
11893 | 11865 | ||
11894 | /* must disable cxsr around plane enable/disable */ |
11866 | /* must disable cxsr around plane enable/disable */ |
11895 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { |
- | |
11896 | if (is_crtc_enabled) |
- | |
11897 | intel_crtc->atomic.wait_vblank = true; |
11867 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
11898 | pipe_config->disable_cxsr = true; |
- | |
11899 | } |
11868 | pipe_config->disable_cxsr = true; |
11900 | } else if (intel_wm_need_update(plane, plane_state)) { |
11869 | } else if (intel_wm_need_update(plane, plane_state)) { |
11901 | /* FIXME bollocks */ |
11870 | /* FIXME bollocks */ |
11902 | pipe_config->update_wm_pre = true; |
11871 | pipe_config->update_wm_pre = true; |
11903 | pipe_config->update_wm_post = true; |
11872 | pipe_config->update_wm_post = true; |
Line 11907... | Line 11876... | ||
11907 | intel_crtc->atomic.fb_bits |= |
11876 | intel_crtc->atomic.fb_bits |= |
11908 | to_intel_plane(plane)->frontbuffer_bit; |
11877 | to_intel_plane(plane)->frontbuffer_bit; |
Line 11909... | Line 11878... | ||
11909 | 11878 | ||
11910 | switch (plane->type) { |
11879 | switch (plane->type) { |
11911 | case DRM_PLANE_TYPE_PRIMARY: |
- | |
11912 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11880 | case DRM_PLANE_TYPE_PRIMARY: |
- | 11881 | intel_crtc->atomic.post_enable_primary = turn_on; |
|
Line 11913... | Line -... | ||
11913 | intel_crtc->atomic.post_enable_primary = turn_on; |
- | |
11914 | - | ||
11915 | if (turn_off) { |
- | |
11916 | /* |
- | |
11917 | * FIXME: Actually if we will still have any other |
- | |
11918 | * plane enabled on the pipe we could let IPS enabled |
- | |
11919 | * still, but for now lets consider that when we make |
- | |
11920 | * primary invisible by setting DSPCNTR to 0 on |
- | |
11921 | * update_primary_plane function IPS needs to be |
- | |
11922 | * disable. |
- | |
11923 | */ |
- | |
11924 | intel_crtc->atomic.disable_ips = true; |
- | |
11925 | - | ||
11926 | intel_crtc->atomic.disable_fbc = true; |
- | |
11927 | } |
- | |
11928 | - | ||
11929 | /* |
- | |
11930 | * FBC does not work on some platforms for rotated |
- | |
11931 | * planes, so disable it when rotation is not 0 and |
- | |
11932 | * update it when rotation is set back to 0. |
- | |
11933 | * |
- | |
11934 | * FIXME: This is redundant with the fbc update done in |
- | |
11935 | * the primary plane enable function except that that |
- | |
11936 | * one is done too late. We eventually need to unify |
- | |
11937 | * this. |
- | |
11938 | */ |
- | |
11939 | - | ||
11940 | if (visible && |
- | |
11941 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
- | |
11942 | dev_priv->fbc.crtc == intel_crtc && |
- | |
11943 | plane_state->rotation != BIT(DRM_ROTATE_0)) |
- | |
11944 | intel_crtc->atomic.disable_fbc = true; |
- | |
11945 | - | ||
11946 | /* |
- | |
11947 | * BDW signals flip done immediately if the plane |
- | |
11948 | * is disabled, even if the plane enable is already |
- | |
11949 | * armed to occur at the next vblank :( |
- | |
11950 | */ |
- | |
11951 | if (turn_on && IS_BROADWELL(dev)) |
- | |
11952 | intel_crtc->atomic.wait_vblank = true; |
- | |
11953 | 11882 | intel_crtc->atomic.update_fbc = true; |
|
11954 | intel_crtc->atomic.update_fbc |= visible || mode_changed; |
11883 | |
11955 | break; |
11884 | break; |
11956 | case DRM_PLANE_TYPE_CURSOR: |
11885 | case DRM_PLANE_TYPE_CURSOR: |
11957 | break; |
11886 | break; |
Line 11962... | Line 11891... | ||
11962 | * cstate->update_wm was already set above, so this flag will |
11891 | * cstate->update_wm was already set above, so this flag will |
11963 | * take effect when we commit and program watermarks. |
11892 | * take effect when we commit and program watermarks. |
11964 | */ |
11893 | */ |
11965 | if (IS_IVYBRIDGE(dev) && |
11894 | if (IS_IVYBRIDGE(dev) && |
11966 | needs_scaling(to_intel_plane_state(plane_state)) && |
11895 | needs_scaling(to_intel_plane_state(plane_state)) && |
11967 | !needs_scaling(old_plane_state)) { |
11896 | !needs_scaling(old_plane_state)) |
11968 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; |
11897 | pipe_config->disable_lp_wm = true; |
11969 | } else if (turn_off && !mode_changed) { |
- | |
11970 | intel_crtc->atomic.wait_vblank = true; |
- | |
11971 | intel_crtc->atomic.update_sprite_watermarks |= |
- | |
11972 | 1 << i; |
- | |
11973 | } |
- | |
Line 11974... | Line 11898... | ||
11974 | 11898 | ||
11975 | break; |
11899 | break; |
11976 | } |
11900 | } |
11977 | return 0; |
11901 | return 0; |
Line 12570... | Line 12494... | ||
12570 | if (exact || !m || !n || !m2 || !n2) |
12494 | if (exact || !m || !n || !m2 || !n2) |
12571 | return false; |
12495 | return false; |
Line 12572... | Line 12496... | ||
12572 | 12496 | ||
Line 12573... | Line 12497... | ||
12573 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
12497 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); |
12574 | 12498 | ||
12575 | if (m > m2) { |
12499 | if (n > n2) { |
12576 | while (m > m2) { |
12500 | while (n > n2) { |
12577 | m2 <<= 1; |
12501 | m2 <<= 1; |
12578 | n2 <<= 1; |
12502 | n2 <<= 1; |
12579 | } |
12503 | } |
12580 | } else if (m < m2) { |
12504 | } else if (n < n2) { |
12581 | while (m < m2) { |
12505 | while (n < n2) { |
12582 | m <<= 1; |
12506 | m <<= 1; |
12583 | n <<= 1; |
12507 | n <<= 1; |
Line -... | Line 12508... | ||
- | 12508 | } |
|
- | 12509 | } |
|
- | 12510 | ||
12584 | } |
12511 | if (n != n2) |
12585 | } |
12512 | return false; |
Line 12586... | Line 12513... | ||
12586 | 12513 | ||
12587 | return m == m2 && n == n2; |
12514 | return intel_fuzzy_clock_check(m, m2); |
12588 | } |
12515 | } |
Line 13133... | Line 13060... | ||
13133 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
13060 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
13134 | { |
13061 | { |
13135 | struct drm_device *dev = state->dev; |
13062 | struct drm_device *dev = state->dev; |
13136 | struct drm_i915_private *dev_priv = to_i915(dev); |
13063 | struct drm_i915_private *dev_priv = to_i915(dev); |
13137 | struct intel_shared_dpll_config *shared_dpll = NULL; |
13064 | struct intel_shared_dpll_config *shared_dpll = NULL; |
13138 | struct intel_crtc *intel_crtc; |
- | |
13139 | struct intel_crtc_state *intel_crtc_state; |
- | |
13140 | struct drm_crtc *crtc; |
13065 | struct drm_crtc *crtc; |
13141 | struct drm_crtc_state *crtc_state; |
13066 | struct drm_crtc_state *crtc_state; |
13142 | int i; |
13067 | int i; |
Line 13143... | Line 13068... | ||
13143 | 13068 | ||
13144 | if (!dev_priv->display.crtc_compute_clock) |
13069 | if (!dev_priv->display.crtc_compute_clock) |
Line 13145... | Line 13070... | ||
13145 | return; |
13070 | return; |
13146 | - | ||
13147 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
- | |
13148 | int dpll; |
13071 | |
13149 | 13072 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
|
13150 | intel_crtc = to_intel_crtc(crtc); |
- | |
Line 13151... | Line 13073... | ||
13151 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
13073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13152 | dpll = intel_crtc_state->shared_dpll; |
13074 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; |
Line 13153... | Line 13075... | ||
13153 | 13075 | ||
- | 13076 | if (!needs_modeset(crtc_state)) |
|
- | 13077 | continue; |
|
- | 13078 | ||
Line 13154... | Line 13079... | ||
13154 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
13079 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13155 | continue; |
13080 | |
Line 13156... | Line 13081... | ||
13156 | 13081 | if (old_dpll == DPLL_ID_PRIVATE) |
|
13157 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
13082 | continue; |
13158 | 13083 | ||
Line 13159... | Line 13084... | ||
13159 | if (!shared_dpll) |
13084 | if (!shared_dpll) |
13160 | shared_dpll = intel_atomic_get_shared_dpll_state(state); |
13085 | shared_dpll = intel_atomic_get_shared_dpll_state(state); |
Line 13257... | Line 13182... | ||
13257 | return ret; |
13182 | return ret; |
13258 | } |
13183 | } |
Line 13259... | Line 13184... | ||
13259 | 13184 | ||
13260 | static int intel_modeset_checks(struct drm_atomic_state *state) |
13185 | static int intel_modeset_checks(struct drm_atomic_state *state) |
13261 | { |
13186 | { |
13262 | struct drm_device *dev = state->dev; |
13187 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
- | 13188 | struct drm_i915_private *dev_priv = state->dev->dev_private; |
|
- | 13189 | struct drm_crtc *crtc; |
|
13263 | struct drm_i915_private *dev_priv = dev->dev_private; |
13190 | struct drm_crtc_state *crtc_state; |
Line 13264... | Line 13191... | ||
13264 | int ret; |
13191 | int ret = 0, i; |
13265 | 13192 | ||
13266 | if (!check_digital_port_conflicts(state)) { |
13193 | if (!check_digital_port_conflicts(state)) { |
13267 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
13194 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
Line -... | Line 13195... | ||
- | 13195 | return -EINVAL; |
|
- | 13196 | } |
|
- | 13197 | ||
- | 13198 | intel_state->modeset = true; |
|
- | 13199 | intel_state->active_crtcs = dev_priv->active_crtcs; |
|
- | 13200 | ||
- | 13201 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
|
- | 13202 | if (crtc_state->active) |
|
- | 13203 | intel_state->active_crtcs |= 1 << i; |
|
- | 13204 | else |
|
13268 | return -EINVAL; |
13205 | intel_state->active_crtcs &= ~(1 << i); |
13269 | } |
13206 | } |
13270 | 13207 | ||
13271 | /* |
13208 | /* |
13272 | * See if the config requires any additional preparation, e.g. |
13209 | * See if the config requires any additional preparation, e.g. |
13273 | * to adjust global state with pipes off. We need to do this |
13210 | * to adjust global state with pipes off. We need to do this |
13274 | * here so we can get the modeset_pipe updated config for the new |
13211 | * here so we can get the modeset_pipe updated config for the new |
13275 | * mode set on this crtc. For other crtcs we need to use the |
13212 | * mode set on this crtc. For other crtcs we need to use the |
13276 | * adjusted_mode bits in the crtc directly. |
- | |
13277 | */ |
- | |
13278 | if (dev_priv->display.modeset_calc_cdclk) { |
13213 | * adjusted_mode bits in the crtc directly. |
Line 13279... | Line -... | ||
13279 | unsigned int cdclk; |
- | |
13280 | 13214 | */ |
|
13281 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13215 | if (dev_priv->display.modeset_calc_cdclk) { |
Line 13282... | Line 13216... | ||
13282 | 13216 | ret = dev_priv->display.modeset_calc_cdclk(state); |
|
13283 | cdclk = to_intel_atomic_state(state)->cdclk; |
13217 | |
- | 13218 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
|
- | 13219 | ret = intel_modeset_all_pipes(state); |
|
- | 13220 | ||
13284 | if (!ret && cdclk != dev_priv->cdclk_freq) |
13221 | if (ret < 0) |
13285 | ret = intel_modeset_all_pipes(state); |
13222 | return ret; |
Line 13286... | Line 13223... | ||
13286 | 13223 | ||
Line 13287... | Line 13224... | ||
13287 | if (ret < 0) |
13224 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", |
13288 | return ret; |
13225 | intel_state->cdclk, intel_state->dev_cdclk); |
Line 13289... | Line 13226... | ||
13289 | } else |
13226 | } else |
13290 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; |
13227 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
Line 13342... | Line 13279... | ||
13342 | * @state: state to validate |
13279 | * @state: state to validate |
13343 | */ |
13280 | */ |
13344 | static int intel_atomic_check(struct drm_device *dev, |
13281 | static int intel_atomic_check(struct drm_device *dev, |
13345 | struct drm_atomic_state *state) |
13282 | struct drm_atomic_state *state) |
13346 | { |
13283 | { |
- | 13284 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
13347 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13285 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13348 | struct drm_crtc *crtc; |
13286 | struct drm_crtc *crtc; |
13349 | struct drm_crtc_state *crtc_state; |
13287 | struct drm_crtc_state *crtc_state; |
13350 | int ret, i; |
13288 | int ret, i; |
13351 | bool any_ms = false; |
13289 | bool any_ms = false; |
Line 13384... | Line 13322... | ||
13384 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
13322 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
13385 | if (ret) |
13323 | if (ret) |
13386 | return ret; |
13324 | return ret; |
Line 13387... | Line 13325... | ||
13387 | 13325 | ||
13388 | if (i915.fastboot && |
13326 | if (i915.fastboot && |
13389 | intel_pipe_config_compare(state->dev, |
13327 | intel_pipe_config_compare(dev, |
13390 | to_intel_crtc_state(crtc->state), |
13328 | to_intel_crtc_state(crtc->state), |
13391 | pipe_config, true)) { |
13329 | pipe_config, true)) { |
13392 | crtc_state->mode_changed = false; |
13330 | crtc_state->mode_changed = false; |
13393 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
13331 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
Line 13410... | Line 13348... | ||
13410 | ret = intel_modeset_checks(state); |
13348 | ret = intel_modeset_checks(state); |
Line 13411... | Line 13349... | ||
13411 | 13349 | ||
13412 | if (ret) |
13350 | if (ret) |
13413 | return ret; |
13351 | return ret; |
13414 | } else |
13352 | } else |
Line 13415... | Line 13353... | ||
13415 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
13353 | intel_state->cdclk = dev_priv->cdclk_freq; |
13416 | 13354 | ||
13417 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13355 | ret = drm_atomic_helper_check_planes(dev, state); |
Line -... | Line 13356... | ||
- | 13356 | if (ret) |
|
13418 | if (ret) |
13357 | return ret; |
Line 13419... | Line 13358... | ||
13419 | return ret; |
13358 | |
13420 | 13359 | intel_fbc_choose_crtc(dev_priv, state); |
|
Line 13490... | Line 13429... | ||
13490 | 13429 | ||
13491 | mutex_unlock(&dev->struct_mutex); |
13430 | mutex_unlock(&dev->struct_mutex); |
13492 | return ret; |
13431 | return ret; |
Line -... | Line 13432... | ||
- | 13432 | } |
|
- | 13433 | ||
- | 13434 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
|
- | 13435 | struct drm_i915_private *dev_priv, |
|
- | 13436 | unsigned crtc_mask) |
|
- | 13437 | { |
|
- | 13438 | unsigned last_vblank_count[I915_MAX_PIPES]; |
|
- | 13439 | enum pipe pipe; |
|
- | 13440 | int ret; |
|
- | 13441 | ||
- | 13442 | if (!crtc_mask) |
|
- | 13443 | return; |
|
- | 13444 | ||
- | 13445 | for_each_pipe(dev_priv, pipe) { |
|
- | 13446 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
|
- | 13447 | ||
- | 13448 | if (!((1 << pipe) & crtc_mask)) |
|
- | 13449 | continue; |
|
- | 13450 | ||
- | 13451 | ret = drm_crtc_vblank_get(crtc); |
|
- | 13452 | if (WARN_ON(ret != 0)) { |
|
- | 13453 | crtc_mask &= ~(1 << pipe); |
|
- | 13454 | continue; |
|
- | 13455 | } |
|
- | 13456 | ||
- | 13457 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
|
- | 13458 | } |
|
- | 13459 | ||
- | 13460 | for_each_pipe(dev_priv, pipe) { |
|
- | 13461 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
|
- | 13462 | long lret; |
|
- | 13463 | ||
- | 13464 | if (!((1 << pipe) & crtc_mask)) |
|
- | 13465 | continue; |
|
- | 13466 | ||
- | 13467 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
|
- | 13468 | last_vblank_count[pipe] != |
|
- | 13469 | drm_crtc_vblank_count(crtc), |
|
- | 13470 | msecs_to_jiffies(50)); |
|
- | 13471 | ||
- | 13472 | WARN_ON(!lret); |
|
- | 13473 | ||
- | 13474 | drm_crtc_vblank_put(crtc); |
|
- | 13475 | } |
|
- | 13476 | } |
|
- | 13477 | ||
- | 13478 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
|
- | 13479 | { |
|
- | 13480 | /* fb updated, need to unpin old fb */ |
|
- | 13481 | if (crtc_state->fb_changed) |
|
- | 13482 | return true; |
|
- | 13483 | ||
- | 13484 | /* wm changes, need vblank before final wm's */ |
|
- | 13485 | if (crtc_state->update_wm_post) |
|
- | 13486 | return true; |
|
- | 13487 | ||
- | 13488 | /* |
|
- | 13489 | * cxsr is re-enabled after vblank. |
|
- | 13490 | * This is already handled by crtc_state->update_wm_post, |
|
- | 13491 | * but added for clarity. |
|
- | 13492 | */ |
|
- | 13493 | if (crtc_state->disable_cxsr) |
|
- | 13494 | return true; |
|
- | 13495 | ||
- | 13496 | return false; |
|
13493 | } |
13497 | } |
13494 | 13498 | ||
13495 | /** |
13499 | /** |
13496 | * intel_atomic_commit - commit validated state object |
13500 | * intel_atomic_commit - commit validated state object |
13497 | * @dev: DRM device |
13501 | * @dev: DRM device |
Line 13510... | Line 13514... | ||
13510 | */ |
13514 | */ |
13511 | static int intel_atomic_commit(struct drm_device *dev, |
13515 | static int intel_atomic_commit(struct drm_device *dev, |
13512 | struct drm_atomic_state *state, |
13516 | struct drm_atomic_state *state, |
13513 | bool async) |
13517 | bool async) |
13514 | { |
13518 | { |
- | 13519 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
|
13515 | struct drm_i915_private *dev_priv = dev->dev_private; |
13520 | struct drm_i915_private *dev_priv = dev->dev_private; |
13516 | struct drm_crtc_state *crtc_state; |
13521 | struct drm_crtc_state *crtc_state; |
13517 | struct drm_crtc *crtc; |
13522 | struct drm_crtc *crtc; |
13518 | int ret = 0; |
13523 | int ret = 0, i; |
13519 | int i; |
13524 | bool hw_check = intel_state->modeset; |
- | 13525 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
|
13520 | bool any_ms = false; |
13526 | unsigned crtc_vblank_mask = 0; |
Line 13521... | Line 13527... | ||
13521 | 13527 | ||
13522 | ret = intel_atomic_prepare_commit(dev, state, async); |
13528 | ret = intel_atomic_prepare_commit(dev, state, async); |
13523 | if (ret) { |
13529 | if (ret) { |
13524 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
13530 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); |
13525 | return ret; |
13531 | return ret; |
Line 13526... | Line 13532... | ||
13526 | } |
13532 | } |
13527 | 13533 | ||
Line -... | Line 13534... | ||
- | 13534 | drm_atomic_helper_swap_state(dev, state); |
|
- | 13535 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
|
- | 13536 | ||
- | 13537 | if (intel_state->modeset) { |
|
- | 13538 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, |
|
- | 13539 | sizeof(intel_state->min_pixclk)); |
|
- | 13540 | dev_priv->active_crtcs = intel_state->active_crtcs; |
|
- | 13541 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
|
- | 13542 | ||
13528 | drm_atomic_helper_swap_state(dev, state); |
13543 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
13529 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
13544 | } |
Line -... | Line 13545... | ||
- | 13545 | ||
- | 13546 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
|
- | 13547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 13548 | ||
- | 13549 | if (needs_modeset(crtc->state) || |
|
- | 13550 | to_intel_crtc_state(crtc->state)->update_pipe) { |
|
- | 13551 | hw_check = true; |
|
- | 13552 | ||
- | 13553 | put_domains[to_intel_crtc(crtc)->pipe] = |
|
13530 | 13554 | modeset_get_crtc_power_domains(crtc, |
|
13531 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13555 | to_intel_crtc_state(crtc->state)); |
Line 13532... | Line -... | ||
13532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
13533 | 13556 | } |
|
Line 13534... | Line 13557... | ||
13534 | if (!needs_modeset(crtc->state)) |
13557 | |
13535 | continue; |
13558 | if (!needs_modeset(crtc->state)) |
13536 | 13559 | continue; |
|
13537 | any_ms = true; |
13560 | |
- | 13561 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
|
13538 | intel_pre_plane_update(intel_crtc); |
13562 | |
Line 13539... | Line 13563... | ||
13539 | 13563 | if (crtc_state->active) { |
|
13540 | if (crtc_state->active) { |
13564 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
13541 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); |
13565 | dev_priv->display.crtc_disable(crtc); |
Line 13557... | Line 13581... | ||
13557 | 13581 | ||
13558 | /* Only after disabling all output pipelines that will be changed can we |
13582 | /* Only after disabling all output pipelines that will be changed can we |
13559 | * update the the output configuration. */ |
13583 | * update the the output configuration. */ |
Line 13560... | Line 13584... | ||
13560 | intel_modeset_update_crtc_state(state); |
13584 | intel_modeset_update_crtc_state(state); |
13561 | 13585 | ||
Line 13562... | Line 13586... | ||
13562 | if (any_ms) { |
13586 | if (intel_state->modeset) { |
- | 13587 | intel_shared_dpll_commit(state); |
|
- | 13588 | ||
- | 13589 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
|
13563 | intel_shared_dpll_commit(state); |
13590 | |
13564 | 13591 | if (dev_priv->display.modeset_commit_cdclk && |
|
Line 13565... | Line 13592... | ||
13565 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
13592 | intel_state->dev_cdclk != dev_priv->cdclk_freq) |
13566 | modeset_update_crtc_power_domains(state); |
13593 | dev_priv->display.modeset_commit_cdclk(state); |
13567 | } |
13594 | } |
13568 | 13595 | ||
13569 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
13596 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
13570 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13597 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
- | |
13572 | bool modeset = needs_modeset(crtc->state); |
- | |
13573 | bool update_pipe = !modeset && |
- | |
13574 | to_intel_crtc_state(crtc->state)->update_pipe; |
13598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Line 13575... | Line 13599... | ||
13575 | unsigned long put_domains = 0; |
13599 | bool modeset = needs_modeset(crtc->state); |
13576 | 13600 | struct intel_crtc_state *pipe_config = |
|
13577 | if (modeset) |
13601 | to_intel_crtc_state(crtc->state); |
13578 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
13602 | bool update_pipe = !modeset && pipe_config->update_pipe; |
Line 13579... | Line -... | ||
13579 | - | ||
13580 | if (modeset && crtc->state->active) { |
- | |
13581 | update_scanline_offset(to_intel_crtc(crtc)); |
- | |
13582 | dev_priv->display.crtc_enable(crtc); |
- | |
13583 | } |
- | |
13584 | - | ||
13585 | if (update_pipe) { |
- | |
13586 | put_domains = modeset_get_crtc_power_domains(crtc); |
13603 | |
- | 13604 | if (modeset && crtc->state->active) { |
|
- | 13605 | update_scanline_offset(to_intel_crtc(crtc)); |
|
- | 13606 | dev_priv->display.crtc_enable(crtc); |
|
13587 | 13607 | } |
|
Line 13588... | Line 13608... | ||
13588 | /* make sure intel_modeset_check_state runs */ |
13608 | |
13589 | any_ms = true; |
13609 | if (!modeset) |
13590 | } |
13610 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
Line 13591... | Line -... | ||
13591 | - | ||
13592 | if (!modeset) |
13611 | |
13593 | intel_pre_plane_update(intel_crtc); |
- | |
13594 | 13612 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
|
13595 | if (crtc->state->active && |
- | |
13596 | (crtc->state->planes_changed || update_pipe)) |
- | |
13597 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
- | |
13598 | 13613 | intel_fbc_enable(intel_crtc); |
|
Line 13599... | Line 13614... | ||
13599 | if (put_domains) |
13614 | |
Line -... | Line 13615... | ||
- | 13615 | if (crtc->state->active && |
|
13600 | modeset_put_power_domains(dev_priv, put_domains); |
13616 | (crtc->state->planes_changed || update_pipe)) |
- | 13617 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
|
- | 13618 | ||
- | 13619 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
|
- | 13620 | crtc_vblank_mask |= 1 << i; |
|
- | 13621 | } |
|
- | 13622 | ||
- | 13623 | /* FIXME: add subpixel order */ |
|
- | 13624 | ||
- | 13625 | if (!state->legacy_cursor_update) |
|
- | 13626 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); |
|
Line 13601... | Line 13627... | ||
13601 | 13627 | ||
13602 | intel_post_plane_update(intel_crtc); |
13628 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13603 | 13629 | intel_post_plane_update(to_intel_crtc(crtc)); |
|
Line 13604... | Line 13630... | ||
13604 | if (modeset) |
13630 | |
13605 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
13631 | if (put_domains[i]) |
Line 13606... | Line 13632... | ||
13606 | } |
13632 | modeset_put_power_domains(dev_priv, put_domains[i]); |
Line -... | Line 13633... | ||
- | 13633 | } |
|
- | 13634 | ||
- | 13635 | if (intel_state->modeset) |
|
- | 13636 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
|
- | 13637 | ||
- | 13638 | mutex_lock(&dev->struct_mutex); |
|
- | 13639 | drm_atomic_helper_cleanup_planes(dev, state); |
|
- | 13640 | mutex_unlock(&dev->struct_mutex); |
|
- | 13641 | ||
- | 13642 | if (hw_check) |
|
- | 13643 | intel_modeset_check_state(dev, state); |
|
- | 13644 | ||
- | 13645 | drm_atomic_state_free(state); |
|
13607 | 13646 | ||
13608 | /* FIXME: add subpixel order */ |
13647 | /* As one of the primary mmio accessors, KMS has a high likelihood |
Line 13609... | Line 13648... | ||
13609 | 13648 | * of triggering bugs in unclaimed access. After we finish |
|
13610 | drm_atomic_helper_wait_for_vblanks(dev, state); |
13649 | * modesetting, see if an error has been flagged, and if so |
Line 13895... | Line 13934... | ||
13895 | int max_scale; |
13934 | int max_scale; |
13896 | struct drm_device *dev; |
13935 | struct drm_device *dev; |
13897 | struct drm_i915_private *dev_priv; |
13936 | struct drm_i915_private *dev_priv; |
13898 | int crtc_clock, cdclk; |
13937 | int crtc_clock, cdclk; |
Line 13899... | Line 13938... | ||
13899 | 13938 | ||
13900 | if (!intel_crtc || !crtc_state) |
13939 | if (!intel_crtc || !crtc_state->base.enable) |
Line 13901... | Line 13940... | ||
13901 | return DRM_PLANE_HELPER_NO_SCALING; |
13940 | return DRM_PLANE_HELPER_NO_SCALING; |
13902 | 13941 | ||
13903 | dev = intel_crtc->base.dev; |
13942 | dev = intel_crtc->base.dev; |
Line 13944... | Line 13983... | ||
13944 | min_scale, max_scale, |
13983 | min_scale, max_scale, |
13945 | can_position, true, |
13984 | can_position, true, |
13946 | &state->visible); |
13985 | &state->visible); |
13947 | } |
13986 | } |
Line 13948... | Line -... | ||
13948 | - | ||
13949 | static void |
- | |
13950 | intel_commit_primary_plane(struct drm_plane *plane, |
- | |
13951 | struct intel_plane_state *state) |
- | |
13952 | { |
- | |
13953 | struct drm_crtc *crtc = state->base.crtc; |
- | |
13954 | struct drm_framebuffer *fb = state->base.fb; |
- | |
13955 | struct drm_device *dev = plane->dev; |
- | |
13956 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
13957 | - | ||
13958 | crtc = crtc ? crtc : plane->crtc; |
- | |
13959 | - | ||
13960 | dev_priv->display.update_primary_plane(crtc, fb, |
- | |
13961 | state->src.x1 >> 16, |
- | |
13962 | state->src.y1 >> 16); |
- | |
13963 | } |
- | |
13964 | - | ||
13965 | static void |
- | |
13966 | intel_disable_primary_plane(struct drm_plane *plane, |
- | |
13967 | struct drm_crtc *crtc) |
- | |
13968 | { |
- | |
13969 | struct drm_device *dev = plane->dev; |
- | |
13970 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
13971 | - | ||
13972 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
- | |
13973 | } |
- | |
13974 | 13987 | ||
13975 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13988 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13976 | struct drm_crtc_state *old_crtc_state) |
13989 | struct drm_crtc_state *old_crtc_state) |
13977 | { |
13990 | { |
13978 | struct drm_device *dev = crtc->dev; |
13991 | struct drm_device *dev = crtc->dev; |
Line 14054... | Line 14067... | ||
14054 | } |
14067 | } |
14055 | primary->pipe = pipe; |
14068 | primary->pipe = pipe; |
14056 | primary->plane = pipe; |
14069 | primary->plane = pipe; |
14057 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
14070 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
14058 | primary->check_plane = intel_check_primary_plane; |
14071 | primary->check_plane = intel_check_primary_plane; |
14059 | primary->commit_plane = intel_commit_primary_plane; |
- | |
14060 | primary->disable_plane = intel_disable_primary_plane; |
- | |
14061 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14072 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14062 | primary->plane = !pipe; |
14073 | primary->plane = !pipe; |
Line 14063... | Line 14074... | ||
14063 | 14074 | ||
14064 | if (INTEL_INFO(dev)->gen >= 9) { |
14075 | if (INTEL_INFO(dev)->gen >= 9) { |
14065 | intel_primary_formats = skl_primary_formats; |
14076 | intel_primary_formats = skl_primary_formats; |
- | 14077 | num_formats = ARRAY_SIZE(skl_primary_formats); |
|
- | 14078 | ||
- | 14079 | primary->update_plane = skylake_update_primary_plane; |
|
- | 14080 | primary->disable_plane = skylake_disable_primary_plane; |
|
- | 14081 | } else if (HAS_PCH_SPLIT(dev)) { |
|
- | 14082 | intel_primary_formats = i965_primary_formats; |
|
- | 14083 | num_formats = ARRAY_SIZE(i965_primary_formats); |
|
- | 14084 | ||
- | 14085 | primary->update_plane = ironlake_update_primary_plane; |
|
14066 | num_formats = ARRAY_SIZE(skl_primary_formats); |
14086 | primary->disable_plane = i9xx_disable_primary_plane; |
14067 | } else if (INTEL_INFO(dev)->gen >= 4) { |
14087 | } else if (INTEL_INFO(dev)->gen >= 4) { |
14068 | intel_primary_formats = i965_primary_formats; |
14088 | intel_primary_formats = i965_primary_formats; |
- | 14089 | num_formats = ARRAY_SIZE(i965_primary_formats); |
|
- | 14090 | ||
- | 14091 | primary->update_plane = i9xx_update_primary_plane; |
|
14069 | num_formats = ARRAY_SIZE(i965_primary_formats); |
14092 | primary->disable_plane = i9xx_disable_primary_plane; |
14070 | } else { |
14093 | } else { |
14071 | intel_primary_formats = i8xx_primary_formats; |
14094 | intel_primary_formats = i8xx_primary_formats; |
- | 14095 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
|
- | 14096 | ||
- | 14097 | primary->update_plane = i9xx_update_primary_plane; |
|
14072 | num_formats = ARRAY_SIZE(i8xx_primary_formats); |
14098 | primary->disable_plane = i9xx_disable_primary_plane; |
Line 14073... | Line 14099... | ||
14073 | } |
14099 | } |
14074 | 14100 | ||
14075 | drm_universal_plane_init(dev, &primary->base, 0, |
14101 | drm_universal_plane_init(dev, &primary->base, 0, |
Line 14166... | Line 14192... | ||
14166 | 14192 | ||
14167 | static void |
14193 | static void |
14168 | intel_disable_cursor_plane(struct drm_plane *plane, |
14194 | intel_disable_cursor_plane(struct drm_plane *plane, |
14169 | struct drm_crtc *crtc) |
14195 | struct drm_crtc *crtc) |
- | 14196 | { |
|
- | 14197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
|
- | 14198 | ||
14170 | { |
14199 | intel_crtc->cursor_addr = 0; |
14171 | intel_crtc_update_cursor(crtc, false); |
14200 | intel_crtc_update_cursor(crtc, NULL); |
Line 14172... | Line 14201... | ||
14172 | } |
14201 | } |
14173 | 14202 | ||
- | 14203 | static void |
|
14174 | static void |
14204 | intel_update_cursor_plane(struct drm_plane *plane, |
14175 | intel_commit_cursor_plane(struct drm_plane *plane, |
14205 | const struct intel_crtc_state *crtc_state, |
14176 | struct intel_plane_state *state) |
14206 | const struct intel_plane_state *state) |
- | 14207 | { |
|
14177 | { |
14208 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14178 | struct drm_crtc *crtc = state->base.crtc; |
- | |
14179 | struct drm_device *dev = plane->dev; |
14209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14180 | struct intel_crtc *intel_crtc; |
14210 | struct drm_device *dev = plane->dev; |
Line 14181... | Line -... | ||
14181 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
- | |
14182 | uint32_t addr; |
- | |
14183 | - | ||
14184 | crtc = crtc ? crtc : plane->crtc; |
14211 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
14185 | intel_crtc = to_intel_crtc(crtc); |
14212 | uint32_t addr; |
14186 | 14213 | ||
14187 | if (!obj) |
14214 | if (!obj) |
14188 | addr = 0; |
14215 | addr = 0; |
14189 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
14216 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
Line 14190... | Line 14217... | ||
14190 | addr = i915_gem_obj_ggtt_offset(obj); |
14217 | addr = i915_gem_obj_ggtt_offset(obj); |
14191 | else |
- | |
14192 | addr = obj->phys_handle->busaddr; |
- | |
14193 | 14218 | else |
|
14194 | intel_crtc->cursor_addr = addr; |
14219 | addr = obj->phys_handle->busaddr; |
Line 14195... | Line 14220... | ||
14195 | 14220 | ||
14196 | if (crtc->state->active) |
14221 | intel_crtc->cursor_addr = addr; |
14197 | intel_crtc_update_cursor(crtc, state->visible); |
14222 | intel_crtc_update_cursor(crtc, state); |
Line 14218... | Line 14243... | ||
14218 | cursor->max_downscale = 1; |
14243 | cursor->max_downscale = 1; |
14219 | cursor->pipe = pipe; |
14244 | cursor->pipe = pipe; |
14220 | cursor->plane = pipe; |
14245 | cursor->plane = pipe; |
14221 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
14246 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
14222 | cursor->check_plane = intel_check_cursor_plane; |
14247 | cursor->check_plane = intel_check_cursor_plane; |
14223 | cursor->commit_plane = intel_commit_cursor_plane; |
14248 | cursor->update_plane = intel_update_cursor_plane; |
14224 | cursor->disable_plane = intel_disable_cursor_plane; |
14249 | cursor->disable_plane = intel_disable_cursor_plane; |
Line 14225... | Line 14250... | ||
14225 | 14250 | ||
14226 | drm_universal_plane_init(dev, &cursor->base, 0, |
14251 | drm_universal_plane_init(dev, &cursor->base, 0, |
14227 | &intel_plane_funcs, |
14252 | &intel_plane_funcs, |
Line 14665... | Line 14690... | ||
14665 | uint32_t pixel_format) |
14690 | uint32_t pixel_format) |
14666 | { |
14691 | { |
14667 | u32 gen = INTEL_INFO(dev)->gen; |
14692 | u32 gen = INTEL_INFO(dev)->gen; |
Line 14668... | Line 14693... | ||
14668 | 14693 | ||
- | 14694 | if (gen >= 9) { |
|
- | 14695 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
|
14669 | if (gen >= 9) { |
14696 | |
14670 | /* "The stride in bytes must not exceed the of the size of 8K |
14697 | /* "The stride in bytes must not exceed the of the size of 8K |
14671 | * pixels and 32K bytes." |
14698 | * pixels and 32K bytes." |
14672 | */ |
14699 | */ |
14673 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); |
14700 | return min(8192 * cpp, 32768); |
14674 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
14701 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
14675 | return 32*1024; |
14702 | return 32*1024; |
14676 | } else if (gen >= 4) { |
14703 | } else if (gen >= 4) { |
14677 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
14704 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) |
Line 14692... | Line 14719... | ||
14692 | static int intel_framebuffer_init(struct drm_device *dev, |
14719 | static int intel_framebuffer_init(struct drm_device *dev, |
14693 | struct intel_framebuffer *intel_fb, |
14720 | struct intel_framebuffer *intel_fb, |
14694 | struct drm_mode_fb_cmd2 *mode_cmd, |
14721 | struct drm_mode_fb_cmd2 *mode_cmd, |
14695 | struct drm_i915_gem_object *obj) |
14722 | struct drm_i915_gem_object *obj) |
14696 | { |
14723 | { |
- | 14724 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
14697 | unsigned int aligned_height; |
14725 | unsigned int aligned_height; |
14698 | int ret; |
14726 | int ret; |
14699 | u32 pitch_limit, stride_alignment; |
14727 | u32 pitch_limit, stride_alignment; |
Line 14700... | Line 14728... | ||
14700 | 14728 | ||
Line 14733... | Line 14761... | ||
14733 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14761 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14734 | mode_cmd->modifier[0]); |
14762 | mode_cmd->modifier[0]); |
14735 | return -EINVAL; |
14763 | return -EINVAL; |
14736 | } |
14764 | } |
Line 14737... | Line 14765... | ||
14737 | 14765 | ||
- | 14766 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
|
14738 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14767 | mode_cmd->modifier[0], |
14739 | mode_cmd->pixel_format); |
14768 | mode_cmd->pixel_format); |
14740 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
14769 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { |
14741 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
14770 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", |
14742 | mode_cmd->pitches[0], stride_alignment); |
14771 | mode_cmd->pitches[0], stride_alignment); |
Line 14825... | Line 14854... | ||
14825 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
14854 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
14826 | return -EINVAL; |
14855 | return -EINVAL; |
Line 14827... | Line 14856... | ||
14827 | 14856 | ||
14828 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14857 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14829 | intel_fb->obj = obj; |
- | |
Line 14830... | Line 14858... | ||
14830 | intel_fb->obj->framebuffer_references++; |
14858 | intel_fb->obj = obj; |
14831 | 14859 | ||
14832 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14860 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14833 | if (ret) { |
14861 | if (ret) { |
14834 | DRM_ERROR("framebuffer init failed %d\n", ret); |
14862 | DRM_ERROR("framebuffer init failed %d\n", ret); |
- | 14863 | return ret; |
|
- | 14864 | } |
|
- | 14865 | ||
14835 | return ret; |
14866 | intel_fb->obj->framebuffer_references++; |
- | 14867 | ||
14836 | } |
14868 | kolibri_framebuffer_init(intel_fb); |
14837 | kolibri_framebuffer_init(intel_fb); |
14869 | |
Line 14838... | Line 14870... | ||
14838 | return 0; |
14870 | return 0; |
14839 | } |
14871 | } |
Line 14896... | Line 14928... | ||
14896 | skylake_get_initial_plane_config; |
14928 | skylake_get_initial_plane_config; |
14897 | dev_priv->display.crtc_compute_clock = |
14929 | dev_priv->display.crtc_compute_clock = |
14898 | haswell_crtc_compute_clock; |
14930 | haswell_crtc_compute_clock; |
14899 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14931 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14900 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
14932 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
14901 | dev_priv->display.update_primary_plane = |
- | |
14902 | skylake_update_primary_plane; |
- | |
14903 | } else if (HAS_DDI(dev)) { |
14933 | } else if (HAS_DDI(dev)) { |
14904 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
14934 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
14905 | dev_priv->display.get_initial_plane_config = |
14935 | dev_priv->display.get_initial_plane_config = |
14906 | ironlake_get_initial_plane_config; |
14936 | ironlake_get_initial_plane_config; |
14907 | dev_priv->display.crtc_compute_clock = |
14937 | dev_priv->display.crtc_compute_clock = |
14908 | haswell_crtc_compute_clock; |
14938 | haswell_crtc_compute_clock; |
14909 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14939 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14910 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
14940 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
14911 | dev_priv->display.update_primary_plane = |
- | |
14912 | ironlake_update_primary_plane; |
- | |
14913 | } else if (HAS_PCH_SPLIT(dev)) { |
14941 | } else if (HAS_PCH_SPLIT(dev)) { |
14914 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
14942 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
14915 | dev_priv->display.get_initial_plane_config = |
14943 | dev_priv->display.get_initial_plane_config = |
14916 | ironlake_get_initial_plane_config; |
14944 | ironlake_get_initial_plane_config; |
14917 | dev_priv->display.crtc_compute_clock = |
14945 | dev_priv->display.crtc_compute_clock = |
14918 | ironlake_crtc_compute_clock; |
14946 | ironlake_crtc_compute_clock; |
14919 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14947 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14920 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
14948 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
14921 | dev_priv->display.update_primary_plane = |
- | |
14922 | ironlake_update_primary_plane; |
- | |
14923 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
14949 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
14924 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14950 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14925 | dev_priv->display.get_initial_plane_config = |
14951 | dev_priv->display.get_initial_plane_config = |
14926 | i9xx_get_initial_plane_config; |
14952 | i9xx_get_initial_plane_config; |
14927 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14953 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14928 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14954 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14929 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
14955 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
14930 | dev_priv->display.update_primary_plane = |
- | |
14931 | i9xx_update_primary_plane; |
- | |
14932 | } else { |
14956 | } else { |
14933 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14957 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
14934 | dev_priv->display.get_initial_plane_config = |
14958 | dev_priv->display.get_initial_plane_config = |
14935 | i9xx_get_initial_plane_config; |
14959 | i9xx_get_initial_plane_config; |
14936 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14960 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
14937 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14961 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14938 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
14962 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
14939 | dev_priv->display.update_primary_plane = |
- | |
14940 | i9xx_update_primary_plane; |
- | |
14941 | } |
14963 | } |
Line 14942... | Line 14964... | ||
14942 | 14964 | ||
14943 | /* Returns the core display clock speed */ |
14965 | /* Returns the core display clock speed */ |
14944 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
14966 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
Line 15241... | Line 15263... | ||
15241 | POSTING_READ(vga_reg); |
15263 | POSTING_READ(vga_reg); |
15242 | } |
15264 | } |
Line 15243... | Line 15265... | ||
15243 | 15265 | ||
15244 | void intel_modeset_init_hw(struct drm_device *dev) |
15266 | void intel_modeset_init_hw(struct drm_device *dev) |
- | 15267 | { |
|
- | 15268 | struct drm_i915_private *dev_priv = dev->dev_private; |
|
15245 | { |
15269 | |
- | 15270 | intel_update_cdclk(dev); |
|
15246 | intel_update_cdclk(dev); |
15271 | |
- | 15272 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
|
15247 | intel_prepare_ddi(dev); |
15273 | |
15248 | intel_init_clock_gating(dev); |
15274 | intel_init_clock_gating(dev); |
15249 | intel_enable_gt_powersave(dev); |
15275 | intel_enable_gt_powersave(dev); |
Line -... | Line 15276... | ||
- | 15276 | } |
|
- | 15277 | ||
- | 15278 | /* |
|
- | 15279 | * Calculate what we think the watermarks should be for the state we've read |
|
- | 15280 | * out of the hardware and then immediately program those watermarks so that |
|
- | 15281 | * we ensure the hardware settings match our internal state. |
|
- | 15282 | * |
|
- | 15283 | * We can calculate what we think WM's should be by creating a duplicate of the |
|
- | 15284 | * current state (which was constructed during hardware readout) and running it |
|
- | 15285 | * through the atomic check code to calculate new watermark values in the |
|
- | 15286 | * state object. |
|
- | 15287 | */ |
|
- | 15288 | static void sanitize_watermarks(struct drm_device *dev) |
|
- | 15289 | { |
|
- | 15290 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
- | 15291 | struct drm_atomic_state *state; |
|
- | 15292 | struct drm_crtc *crtc; |
|
- | 15293 | struct drm_crtc_state *cstate; |
|
- | 15294 | struct drm_modeset_acquire_ctx ctx; |
|
- | 15295 | int ret; |
|
- | 15296 | int i; |
|
- | 15297 | ||
- | 15298 | /* Only supported on platforms that use atomic watermark design */ |
|
- | 15299 | if (!dev_priv->display.program_watermarks) |
|
- | 15300 | return; |
|
- | 15301 | ||
- | 15302 | /* |
|
- | 15303 | * We need to hold connection_mutex before calling duplicate_state so |
|
- | 15304 | * that the connector loop is protected. |
|
- | 15305 | */ |
|
- | 15306 | drm_modeset_acquire_init(&ctx, 0); |
|
- | 15307 | retry: |
|
- | 15308 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
|
- | 15309 | if (ret == -EDEADLK) { |
|
- | 15310 | drm_modeset_backoff(&ctx); |
|
- | 15311 | goto retry; |
|
- | 15312 | } else if (WARN_ON(ret)) { |
|
- | 15313 | goto fail; |
|
- | 15314 | } |
|
- | 15315 | ||
- | 15316 | state = drm_atomic_helper_duplicate_state(dev, &ctx); |
|
- | 15317 | if (WARN_ON(IS_ERR(state))) |
|
- | 15318 | goto fail; |
|
- | 15319 | ||
- | 15320 | ret = intel_atomic_check(dev, state); |
|
- | 15321 | if (ret) { |
|
- | 15322 | /* |
|
- | 15323 | * If we fail here, it means that the hardware appears to be |
|
- | 15324 | * programmed in a way that shouldn't be possible, given our |
|
- | 15325 | * understanding of watermark requirements. This might mean a |
|
- | 15326 | * mistake in the hardware readout code or a mistake in the |
|
- | 15327 | * watermark calculations for a given platform. Raise a WARN |
|
- | 15328 | * so that this is noticeable. |
|
- | 15329 | * |
|
- | 15330 | * If this actually happens, we'll have to just leave the |
|
- | 15331 | * BIOS-programmed watermarks untouched and hope for the best. |
|
- | 15332 | */ |
|
- | 15333 | WARN(true, "Could not determine valid watermarks for inherited state\n"); |
|
- | 15334 | goto fail; |
|
- | 15335 | } |
|
- | 15336 | ||
- | 15337 | /* Write calculated watermark values back */ |
|
- | 15338 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; |
|
- | 15339 | for_each_crtc_in_state(state, crtc, cstate, i) { |
|
- | 15340 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
|
- | 15341 | ||
- | 15342 | dev_priv->display.program_watermarks(cs); |
|
- | 15343 | } |
|
- | 15344 | ||
- | 15345 | drm_atomic_state_free(state); |
|
- | 15346 | fail: |
|
- | 15347 | drm_modeset_drop_locks(&ctx); |
|
- | 15348 | drm_modeset_acquire_fini(&ctx); |
|
15250 | } |
15349 | } |
15251 | 15350 | ||
15252 | void intel_modeset_init(struct drm_device *dev) |
15351 | void intel_modeset_init(struct drm_device *dev) |
15253 | { |
15352 | { |
15254 | struct drm_i915_private *dev_priv = dev->dev_private; |
15353 | struct drm_i915_private *dev_priv = dev->dev_private; |
Line 15363... | Line 15462... | ||
15363 | * If the fb is shared between multiple heads, we'll |
15462 | * If the fb is shared between multiple heads, we'll |
15364 | * just get the first one. |
15463 | * just get the first one. |
15365 | */ |
15464 | */ |
15366 | intel_find_initial_plane_obj(crtc, &plane_config); |
15465 | intel_find_initial_plane_obj(crtc, &plane_config); |
15367 | } |
15466 | } |
- | 15467 | ||
- | 15468 | /* |
|
- | 15469 | * Make sure hardware watermarks really match the state we read out. |
|
- | 15470 | * Note that we need to do this after reconstructing the BIOS fb's |
|
- | 15471 | * since the watermark calculation done here will use pstate->fb. |
|
- | 15472 | */ |
|
- | 15473 | sanitize_watermarks(dev); |
|
15368 | } |
15474 | } |
Line 15369... | Line 15475... | ||
15369 | 15475 | ||
15370 | static void intel_enable_pipe_a(struct drm_device *dev) |
15476 | static void intel_enable_pipe_a(struct drm_device *dev) |
15371 | { |
15477 | { |
Line 15419... | Line 15525... | ||
15419 | return true; |
15525 | return true; |
Line 15420... | Line 15526... | ||
15420 | 15526 | ||
15421 | return false; |
15527 | return false; |
Line -... | Line 15528... | ||
- | 15528 | } |
|
- | 15529 | ||
- | 15530 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
|
- | 15531 | { |
|
- | 15532 | struct drm_device *dev = encoder->base.dev; |
|
- | 15533 | struct intel_connector *connector; |
|
- | 15534 | ||
- | 15535 | for_each_connector_on_encoder(dev, &encoder->base, connector) |
|
- | 15536 | return true; |
|
- | 15537 | ||
- | 15538 | return false; |
|
15422 | } |
15539 | } |
15423 | 15540 | ||
15424 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15541 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15425 | { |
15542 | { |
15426 | struct drm_device *dev = crtc->base.dev; |
15543 | struct drm_device *dev = crtc->base.dev; |
Line 15493... | Line 15610... | ||
15493 | 15610 | ||
15494 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
15611 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
15495 | crtc->base.state->active = crtc->active; |
15612 | crtc->base.state->active = crtc->active; |
15496 | crtc->base.enabled = crtc->active; |
15613 | crtc->base.enabled = crtc->active; |
- | 15614 | crtc->base.state->connector_mask = 0; |
|
Line 15497... | Line 15615... | ||
15497 | crtc->base.state->connector_mask = 0; |
15615 | crtc->base.state->encoder_mask = 0; |
15498 | 15616 | ||
15499 | /* Because we only establish the connector -> encoder -> |
15617 | /* Because we only establish the connector -> encoder -> |
15500 | * crtc links if something is active, this means the |
15618 | * crtc links if something is active, this means the |
Line 15528... | Line 15646... | ||
15528 | 15646 | ||
15529 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
15647 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
15530 | { |
15648 | { |
15531 | struct intel_connector *connector; |
15649 | struct intel_connector *connector; |
15532 | struct drm_device *dev = encoder->base.dev; |
- | |
Line 15533... | Line 15650... | ||
15533 | bool active = false; |
15650 | struct drm_device *dev = encoder->base.dev; |
15534 | 15651 | ||
15535 | /* We need to check both for a crtc link (meaning that the |
15652 | /* We need to check both for a crtc link (meaning that the |
15536 | * encoder is active and trying to read from a pipe) and the |
15653 | * encoder is active and trying to read from a pipe) and the |
15537 | * pipe itself being active. */ |
15654 | * pipe itself being active. */ |
Line 15538... | Line -... | ||
15538 | bool has_active_crtc = encoder->base.crtc && |
- | |
15539 | to_intel_crtc(encoder->base.crtc)->active; |
- | |
15540 | - | ||
15541 | for_each_intel_connector(dev, connector) { |
- | |
15542 | if (connector->base.encoder != &encoder->base) |
- | |
15543 | continue; |
- | |
15544 | - | ||
15545 | active = true; |
- | |
15546 | break; |
15655 | bool has_active_crtc = encoder->base.crtc && |
15547 | } |
15656 | to_intel_crtc(encoder->base.crtc)->active; |
15548 | 15657 | ||
15549 | if (active && !has_active_crtc) { |
15658 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
Line 15550... | Line 15659... | ||
15550 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15659 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
Line 15637... | Line 15746... | ||
15637 | struct intel_crtc *crtc; |
15746 | struct intel_crtc *crtc; |
15638 | struct intel_encoder *encoder; |
15747 | struct intel_encoder *encoder; |
15639 | struct intel_connector *connector; |
15748 | struct intel_connector *connector; |
15640 | int i; |
15749 | int i; |
Line -... | Line 15750... | ||
- | 15750 | ||
- | 15751 | dev_priv->active_crtcs = 0; |
|
15641 | 15752 | ||
15642 | for_each_intel_crtc(dev, crtc) { |
15753 | for_each_intel_crtc(dev, crtc) { |
15643 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
- | |
15644 | memset(crtc->config, 0, sizeof(*crtc->config)); |
15754 | struct intel_crtc_state *crtc_state = crtc->config; |
Line 15645... | Line 15755... | ||
15645 | crtc->config->base.crtc = &crtc->base; |
15755 | int pixclk = 0; |
- | 15756 | ||
15646 | 15757 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
|
Line 15647... | Line 15758... | ||
15647 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
15758 | memset(crtc_state, 0, sizeof(*crtc_state)); |
- | 15759 | crtc_state->base.crtc = &crtc->base; |
|
- | 15760 | ||
15648 | crtc->config); |
15761 | crtc_state->base.active = crtc_state->base.enable = |
- | 15762 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
|
- | 15763 | ||
- | 15764 | crtc->base.enabled = crtc_state->base.enable; |
|
- | 15765 | crtc->active = crtc_state->base.active; |
|
- | 15766 | ||
- | 15767 | if (crtc_state->base.active) { |
|
- | 15768 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
|
- | 15769 | ||
- | 15770 | if (IS_BROADWELL(dev_priv)) { |
|
- | 15771 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
|
- | 15772 | ||
- | 15773 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
|
- | 15774 | if (crtc_state->ips_enabled) |
|
- | 15775 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
|
- | 15776 | } else if (IS_VALLEYVIEW(dev_priv) || |
|
- | 15777 | IS_CHERRYVIEW(dev_priv) || |
|
- | 15778 | IS_BROXTON(dev_priv)) |
|
- | 15779 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
|
- | 15780 | else |
|
- | 15781 | WARN_ON(dev_priv->display.modeset_calc_cdclk); |
|
Line 15649... | Line 15782... | ||
15649 | 15782 | } |
|
Line 15650... | Line 15783... | ||
15650 | crtc->base.state->active = crtc->active; |
15783 | |
15651 | crtc->base.enabled = crtc->active; |
15784 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
Line 15710... | Line 15843... | ||
15710 | * because anything calling .crtc_disable may |
15843 | * because anything calling .crtc_disable may |
15711 | * rely on the connector_mask being accurate. |
15844 | * rely on the connector_mask being accurate. |
15712 | */ |
15845 | */ |
15713 | encoder->base.crtc->state->connector_mask |= |
15846 | encoder->base.crtc->state->connector_mask |= |
15714 | 1 << drm_connector_index(&connector->base); |
15847 | 1 << drm_connector_index(&connector->base); |
- | 15848 | encoder->base.crtc->state->encoder_mask |= |
|
- | 15849 | 1 << drm_encoder_index(&encoder->base); |
|
15715 | } |
15850 | } |
Line 15716... | Line 15851... | ||
15716 | 15851 | ||
15717 | } else { |
15852 | } else { |
15718 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15853 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
Line 15806... | Line 15941... | ||
15806 | ilk_wm_get_hw_state(dev); |
15941 | ilk_wm_get_hw_state(dev); |
Line 15807... | Line 15942... | ||
15807 | 15942 | ||
15808 | for_each_intel_crtc(dev, crtc) { |
15943 | for_each_intel_crtc(dev, crtc) { |
Line 15809... | Line 15944... | ||
15809 | unsigned long put_domains; |
15944 | unsigned long put_domains; |
15810 | 15945 | ||
15811 | put_domains = modeset_get_crtc_power_domains(&crtc->base); |
15946 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
15812 | if (WARN_ON(put_domains)) |
15947 | if (WARN_ON(put_domains)) |
15813 | modeset_put_power_domains(dev_priv, put_domains); |
15948 | modeset_put_power_domains(dev_priv, put_domains); |
- | 15949 | } |
|
- | 15950 | intel_display_set_init_power(dev_priv, false); |
|
15814 | } |
15951 | |
Line 15815... | Line 15952... | ||
15815 | intel_display_set_init_power(dev_priv, false); |
15952 | intel_fbc_init_pipe_state(dev_priv); |
15816 | } |
15953 | } |
15817 | 15954 | ||
15818 | void intel_display_resume(struct drm_device *dev) |
15955 | void intel_display_resume(struct drm_device *dev) |
15819 | { |
- | |
15820 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); |
15956 | { |
15821 | struct intel_connector *conn; |
15957 | struct drm_i915_private *dev_priv = to_i915(dev); |
- | 15958 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; |
|
Line 15822... | Line 15959... | ||
15822 | struct intel_plane *plane; |
15959 | struct drm_modeset_acquire_ctx ctx; |
15823 | struct drm_crtc *crtc; |
- | |
Line -... | Line 15960... | ||
- | 15960 | int ret; |
|
- | 15961 | bool setup = false; |
|
- | 15962 | ||
- | 15963 | dev_priv->modeset_restore_state = NULL; |
|
- | 15964 | ||
- | 15965 | /* |
|
15824 | int ret; |
15966 | * This is a cludge because with real atomic modeset mode_config.mutex |
- | 15967 | * won't be taken. Unfortunately some probed state like |
|
Line 15825... | Line 15968... | ||
15825 | 15968 | * audio_codec_enable is still protected by mode_config.mutex, so lock |
|
15826 | if (!state) |
15969 | * it here for now. |
Line -... | Line 15970... | ||
- | 15970 | */ |
|
- | 15971 | mutex_lock(&dev->mode_config.mutex); |
|
- | 15972 | drm_modeset_acquire_init(&ctx, 0); |
|
- | 15973 | ||
15827 | return; |
15974 | retry: |
- | 15975 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
|
15828 | 15976 | ||
- | 15977 | /* |
|
15829 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
15978 | * With MST, the number of connectors can change between suspend and |
- | 15979 | * resume, which means that the state we want to restore might now be |
|
- | 15980 | * impossible to use since it'll be pointing to non-existant |
|
Line 15830... | Line -... | ||
15830 | - | ||
15831 | /* preserve complete old state, including dpll */ |
15981 | * connectors. |
15832 | intel_atomic_get_shared_dpll_state(state); |
15982 | */ |
Line 15833... | Line 15983... | ||
15833 | 15983 | if (ret == 0 && state && |
|
15834 | for_each_crtc(dev, crtc) { |
15984 | state->num_connector != dev->mode_config.num_connector) { |
15835 | struct drm_crtc_state *crtc_state = |
15985 | drm_atomic_state_free(state); |
Line 15836... | Line 15986... | ||
15836 | drm_atomic_get_crtc_state(state, crtc); |
15986 | state = NULL; |
15837 | 15987 | } |
|
- | 15988 | ||
15838 | ret = PTR_ERR_OR_ZERO(crtc_state); |
15989 | if (ret == 0 && !setup) { |
- | 15990 | setup = true; |
|
- | 15991 | ||
- | 15992 | intel_modeset_setup_hw_state(dev); |
|
- | 15993 | i915_redisable_vga(dev); |
|
- | 15994 | } |
|
- | 15995 | ||
- | 15996 | if (ret == 0 && state) { |
|
- | 15997 | struct drm_crtc_state *crtc_state; |
|
15839 | if (ret) |
15998 | struct drm_crtc *crtc; |
- | 15999 | int i; |
|
15840 | goto err; |
16000 | |
Line 15841... | Line -... | ||
15841 | - | ||
15842 | /* force a restore */ |
16001 | state->acquire_ctx = &ctx; |
15843 | crtc_state->mode_changed = true; |
- | |
15844 | } |
- | |
15845 | 16002 | ||
Line -... | Line 16003... | ||
- | 16003 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
|
15846 | for_each_intel_plane(dev, plane) { |
16004 | /* |
- | 16005 | * Force recalculation even if we restore |
|
- | 16006 | * current state. With fast modeset this may not result |
|
Line 15847... | Line 16007... | ||
15847 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); |
16007 | * in a modeset when the state is compatible. |
15848 | if (ret) |
16008 | */ |
15849 | goto err; |
16009 | crtc_state->mode_changed = true; |
15850 | } |
- | |
Line 15851... | Line 16010... | ||
15851 | 16010 | } |
|
15852 | for_each_intel_connector(dev, conn) { |
16011 | |
15853 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); |
16012 | ret = drm_atomic_commit(state); |
15854 | if (ret) |
16013 | } |
- | 16014 | ||
Line 15855... | Line 16015... | ||
15855 | goto err; |
16015 | if (ret == -EDEADLK) { |
15856 | } |
16016 | drm_modeset_backoff(&ctx); |
15857 | 16017 | goto retry; |
|
15858 | intel_modeset_setup_hw_state(dev); |
16018 | } |
15859 | 16019 | ||
Line 15860... | Line -... | ||
15860 | i915_redisable_vga(dev); |
- | |
15861 | ret = drm_atomic_commit(state); |
16020 | drm_modeset_drop_locks(&ctx); |
15862 | if (!ret) |
- | |
Line 15863... | Line 16021... | ||
15863 | return; |
16021 | drm_modeset_acquire_fini(&ctx); |
Line 15864... | Line 16022... | ||
15864 | 16022 | mutex_unlock(&dev->mode_config.mutex); |
|
Line 15941... | Line 16099... | ||
15941 | */ |
16099 | */ |
15942 | drm_kms_helper_poll_fini(dev); |
16100 | drm_kms_helper_poll_fini(dev); |
Line 15943... | Line 16101... | ||
15943 | 16101 | ||
Line 15944... | Line 16102... | ||
15944 | intel_unregister_dsm_handler(); |
16102 | intel_unregister_dsm_handler(); |
Line 15945... | Line 16103... | ||
15945 | 16103 | ||
15946 | intel_fbc_disable(dev_priv); |
16104 | intel_fbc_global_disable(dev_priv); |
Line 15947... | Line 16105... | ||
15947 | 16105 | ||
Line 15954... | Line 16112... | ||
15954 | 16112 | ||
Line 15955... | Line 16113... | ||
15955 | drm_mode_config_cleanup(dev); |
16113 | drm_mode_config_cleanup(dev); |
Line 15956... | Line -... | ||
15956 | - | ||
15957 | intel_cleanup_overlay(dev); |
16114 | |
15958 | - | ||
15959 | mutex_lock(&dev->struct_mutex); |
16115 | intel_cleanup_overlay(dev); |
15960 | intel_cleanup_gt_powersave(dev); |
16116 | |
Line 15961... | Line 16117... | ||
15961 | mutex_unlock(&dev->struct_mutex); |
16117 | intel_cleanup_gt_powersave(dev); |
15962 | #endif |
16118 | #endif |
Line 16006... | Line 16162... | ||
16006 | } |
16162 | } |
Line 16007... | Line 16163... | ||
16007 | 16163 | ||
16008 | return 0; |
16164 | return 0; |
Line 16009... | Line -... | ||
16009 | } |
- | |
16010 | - | ||
16011 | #ifdef CONFIG_DEBUG_FS |
16165 | } |
Line 16012... | Line 16166... | ||
16012 | 16166 | ||
Line 16013... | Line 16167... | ||
16013 | struct intel_display_error_state { |
16167 | struct intel_display_error_state { |
Line 16152... | Line 16306... | ||
16152 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
16306 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
16153 | error->power_well_driver); |
16307 | error->power_well_driver); |
16154 | for_each_pipe(dev_priv, i) { |
16308 | for_each_pipe(dev_priv, i) { |
16155 | err_printf(m, "Pipe [%d]:\n", i); |
16309 | err_printf(m, "Pipe [%d]:\n", i); |
16156 | err_printf(m, " Power: %s\n", |
16310 | err_printf(m, " Power: %s\n", |
16157 | error->pipe[i].power_domain_on ? "on" : "off"); |
16311 | onoff(error->pipe[i].power_domain_on)); |
16158 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
16312 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
16159 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
16313 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
Line 16160... | Line 16314... | ||
16160 | 16314 | ||
16161 | err_printf(m, "Plane [%d]:\n", i); |
16315 | err_printf(m, "Plane [%d]:\n", i); |
Line 16180... | Line 16334... | ||
16180 | 16334 | ||
16181 | for (i = 0; i < error->num_transcoders; i++) { |
16335 | for (i = 0; i < error->num_transcoders; i++) { |
16182 | err_printf(m, "CPU transcoder: %c\n", |
16336 | err_printf(m, "CPU transcoder: %c\n", |
16183 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
16337 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
16184 | err_printf(m, " Power: %s\n", |
16338 | err_printf(m, " Power: %s\n", |
16185 | error->transcoder[i].power_domain_on ? "on" : "off"); |
16339 | onoff(error->transcoder[i].power_domain_on)); |
16186 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16340 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16187 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
16341 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
16188 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
16342 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
16189 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
16343 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
16190 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
16344 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
16191 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
16345 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
16192 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
16346 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
16193 | } |
16347 | } |
16194 | } |
- | |
16195 | #endif |
- | |
16196 | - | ||
16197 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) |
- | |
16198 | { |
- | |
16199 | struct intel_crtc *crtc; |
- | |
16200 | - | ||
16201 | for_each_intel_crtc(dev, crtc) { |
- | |
16202 | struct intel_unpin_work *work; |
- | |
16203 | - | ||
16204 | spin_lock_irq(&dev->event_lock); |
- | |
16205 | - | ||
16206 | work = crtc->unpin_work; |
- | |
16207 | - | ||
16208 | if (work && work->event && |
- | |
16209 | work->event->base.file_priv == file) { |
- | |
16210 | kfree(work->event); |
- | |
16211 | work->event = NULL; |
- | |
16212 | } |
- | |
16213 | - | ||
16214 | spin_unlock_irq(&dev->event_lock); |
- | |
16215 | } |
- |