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Rev 6937 | Rev 7144 | ||
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Line 39... | Line 39... | ||
39 | #include "i915_trace.h" |
39 | #include "i915_trace.h" |
40 | #include |
40 | #include |
41 | #include |
41 | #include |
42 | #include |
42 | #include |
43 | //#include |
43 | //#include |
44 | //#include |
44 | #include |
45 | #include |
45 | #include |
46 | //#include |
46 | //#include |
47 | #include |
47 | #include |
48 | #include |
48 | #include |
Line 165... | Line 165... | ||
165 | intel_has_gpu_reset(dev); |
165 | intel_has_gpu_reset(dev); |
166 | break; |
166 | break; |
167 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
167 | case I915_PARAM_HAS_RESOURCE_STREAMER: |
168 | value = HAS_RESOURCE_STREAMER(dev); |
168 | value = HAS_RESOURCE_STREAMER(dev); |
169 | break; |
169 | break; |
- | 170 | case I915_PARAM_HAS_EXEC_SOFTPIN: |
|
- | 171 | value = 1; |
|
- | 172 | break; |
|
170 | default: |
173 | default: |
171 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
174 | DRM_DEBUG("Unknown parameter %d\n", param->param); |
172 | return -EINVAL; |
175 | return -EINVAL; |
173 | } |
176 | } |
Line 296... | Line 299... | ||
296 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
299 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
297 | * then we do not take part in VGA arbitration and the |
300 | * then we do not take part in VGA arbitration and the |
298 | * vga_client_register() fails with -ENODEV. |
301 | * vga_client_register() fails with -ENODEV. |
299 | */ |
302 | */ |
Line 300... | Line -... | ||
300 | - | ||
301 | /* Initialise stolen first so that we may reserve preallocated |
- | |
302 | * objects for the BIOS to KMS transition. |
- | |
303 | */ |
- | |
304 | ret = i915_gem_init_stolen(dev); |
- | |
305 | if (ret) |
- | |
Line 306... | Line 303... | ||
306 | goto cleanup_vga_switcheroo; |
303 | |
Line 307... | Line 304... | ||
307 | 304 | ||
Line 308... | Line 305... | ||
308 | intel_power_domains_init_hw(dev_priv, false); |
305 | intel_power_domains_init_hw(dev_priv, false); |
309 | 306 | ||
310 | intel_csr_ucode_init(dev_priv); |
307 | intel_csr_ucode_init(dev_priv); |
Line 311... | Line 308... | ||
311 | 308 | ||
Line 312... | Line 309... | ||
312 | ret = intel_irq_install(dev_priv); |
309 | ret = intel_irq_install(dev_priv); |
313 | if (ret) |
310 | if (ret) |
Line 361... | Line 358... | ||
361 | i915_gem_cleanup_ringbuffer(dev); |
358 | i915_gem_cleanup_ringbuffer(dev); |
362 | i915_gem_context_fini(dev); |
359 | i915_gem_context_fini(dev); |
363 | mutex_unlock(&dev->struct_mutex); |
360 | mutex_unlock(&dev->struct_mutex); |
364 | cleanup_irq: |
361 | cleanup_irq: |
365 | intel_guc_ucode_fini(dev); |
362 | intel_guc_ucode_fini(dev); |
366 | // drm_irq_uninstall(dev); |
- | |
367 | cleanup_gem_stolen: |
363 | cleanup_csr: |
368 | i915_gem_cleanup_stolen(dev); |
- | |
369 | cleanup_vga_switcheroo: |
- | |
370 | // vga_switcheroo_unregister_client(dev->pdev); |
- | |
371 | cleanup_vga_client: |
364 | cleanup_vga_client: |
372 | // vga_client_register(dev->pdev, NULL, NULL, NULL); |
- | |
373 | out: |
365 | out: |
374 | return ret; |
366 | return ret; |
375 | } |
367 | } |
Line 376... | Line 368... | ||
376 | 368 | ||
Line 720... | Line 712... | ||
720 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || |
712 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || |
721 | (dev_priv->pch_type == PCH_CPT && |
713 | (dev_priv->pch_type == PCH_CPT && |
722 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
714 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
723 | DRM_INFO("Display fused off, disabling\n"); |
715 | DRM_INFO("Display fused off, disabling\n"); |
724 | info->num_pipes = 0; |
716 | info->num_pipes = 0; |
- | 717 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
|
- | 718 | DRM_INFO("PipeC fused off\n"); |
|
- | 719 | info->num_pipes -= 1; |
|
- | 720 | } |
|
- | 721 | } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { |
|
- | 722 | u32 dfsm = I915_READ(SKL_DFSM); |
|
- | 723 | u8 disabled_mask = 0; |
|
- | 724 | bool invalid; |
|
- | 725 | int num_bits; |
|
- | 726 | ||
- | 727 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) |
|
- | 728 | disabled_mask |= BIT(PIPE_A); |
|
- | 729 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) |
|
- | 730 | disabled_mask |= BIT(PIPE_B); |
|
- | 731 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) |
|
- | 732 | disabled_mask |= BIT(PIPE_C); |
|
- | 733 | ||
- | 734 | num_bits = hweight8(disabled_mask); |
|
- | 735 | ||
- | 736 | switch (disabled_mask) { |
|
- | 737 | case BIT(PIPE_A): |
|
- | 738 | case BIT(PIPE_B): |
|
- | 739 | case BIT(PIPE_A) | BIT(PIPE_B): |
|
- | 740 | case BIT(PIPE_A) | BIT(PIPE_C): |
|
- | 741 | invalid = true; |
|
- | 742 | break; |
|
- | 743 | default: |
|
- | 744 | invalid = false; |
|
725 | } |
745 | } |
- | 746 | ||
- | 747 | if (num_bits > info->num_pipes || invalid) |
|
- | 748 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", |
|
- | 749 | disabled_mask); |
|
- | 750 | else |
|
- | 751 | info->num_pipes -= num_bits; |
|
726 | } |
752 | } |
Line 727... | Line 753... | ||
727 | 753 | ||
728 | /* Initialize slice/subslice/EU info */ |
754 | /* Initialize slice/subslice/EU info */ |
729 | if (IS_CHERRYVIEW(dev)) |
755 | if (IS_CHERRYVIEW(dev)) |
Line 759... | Line 785... | ||
759 | } else if (IS_VALLEYVIEW(dev_priv)) { |
785 | } else if (IS_VALLEYVIEW(dev_priv)) { |
760 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
786 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
761 | } |
787 | } |
762 | } |
788 | } |
Line -... | Line 789... | ||
- | 789 | ||
- | 790 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) |
|
- | 791 | { |
|
- | 792 | /* |
|
- | 793 | * The i915 workqueue is primarily used for batched retirement of |
|
- | 794 | * requests (and thus managing bo) once the task has been completed |
|
- | 795 | * by the GPU. i915_gem_retire_requests() is called directly when we |
|
- | 796 | * need high-priority retirement, such as waiting for an explicit |
|
- | 797 | * bo. |
|
- | 798 | * |
|
- | 799 | * It is also used for periodic low-priority events, such as |
|
- | 800 | * idle-timers and recording error state. |
|
- | 801 | * |
|
- | 802 | * All tasks on the workqueue are expected to acquire the dev mutex |
|
- | 803 | * so there is no point in running more than one instance of the |
|
- | 804 | * workqueue at any time. Use an ordered one. |
|
- | 805 | */ |
|
- | 806 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
|
- | 807 | if (dev_priv->wq == NULL) |
|
- | 808 | goto out_err; |
|
- | 809 | ||
- | 810 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
|
- | 811 | if (dev_priv->hotplug.dp_wq == NULL) |
|
- | 812 | goto out_free_wq; |
|
- | 813 | ||
- | 814 | dev_priv->gpu_error.hangcheck_wq = |
|
- | 815 | alloc_ordered_workqueue("i915-hangcheck", 0); |
|
- | 816 | if (dev_priv->gpu_error.hangcheck_wq == NULL) |
|
- | 817 | goto out_free_dp_wq; |
|
- | 818 | ||
- | 819 | system_wq = dev_priv->wq; |
|
- | 820 | ||
- | 821 | return 0; |
|
- | 822 | ||
- | 823 | out_free_dp_wq: |
|
- | 824 | out_free_wq: |
|
- | 825 | out_err: |
|
- | 826 | DRM_ERROR("Failed to allocate workqueues.\n"); |
|
- | 827 | ||
- | 828 | return -ENOMEM; |
|
- | 829 | } |
|
- | 830 | ||
- | 831 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) |
|
- | 832 | { |
|
- | 833 | } |
|
- | 834 | ||
- | 835 | static int i915_mmio_setup(struct drm_device *dev) |
|
- | 836 | { |
|
- | 837 | struct drm_i915_private *dev_priv = to_i915(dev); |
|
- | 838 | int mmio_bar; |
|
- | 839 | int mmio_size; |
|
- | 840 | ||
- | 841 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
|
- | 842 | /* |
|
- | 843 | * Before gen4, the registers and the GTT are behind different BARs. |
|
- | 844 | * However, from gen4 onwards, the registers and the GTT are shared |
|
- | 845 | * in the same BAR, so we want to restrict this ioremap from |
|
- | 846 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
|
- | 847 | * the register BAR remains the same size for all the earlier |
|
- | 848 | * generations up to Ironlake. |
|
- | 849 | */ |
|
- | 850 | if (INTEL_INFO(dev)->gen < 5) |
|
- | 851 | mmio_size = 512 * 1024; |
|
- | 852 | else |
|
- | 853 | mmio_size = 2 * 1024 * 1024; |
|
- | 854 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); |
|
- | 855 | if (dev_priv->regs == NULL) { |
|
- | 856 | DRM_ERROR("failed to map registers\n"); |
|
- | 857 | ||
- | 858 | return -EIO; |
|
- | 859 | } |
|
- | 860 | ||
- | 861 | /* Try to make sure MCHBAR is enabled before poking at it */ |
|
- | 862 | intel_setup_mchbar(dev); |
|
- | 863 | ||
- | 864 | return 0; |
|
- | 865 | } |
|
763 | 866 | ||
764 | /** |
867 | /** |
765 | * i915_driver_load - setup chip and create an initial config |
868 | * i915_driver_load - setup chip and create an initial config |
766 | * @dev: DRM device |
869 | * @dev: DRM device |
767 | * @flags: startup flags |
870 | * @flags: startup flags |
Line 774... | Line 877... | ||
774 | */ |
877 | */ |
775 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
878 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
776 | { |
879 | { |
777 | struct drm_i915_private *dev_priv; |
880 | struct drm_i915_private *dev_priv; |
778 | struct intel_device_info *info, *device_info; |
881 | struct intel_device_info *info, *device_info; |
779 | int ret = 0, mmio_bar, mmio_size; |
882 | int ret = 0; |
780 | uint32_t aperture_size; |
883 | uint32_t aperture_size; |
Line 781... | Line 884... | ||
781 | 884 | ||
Line 782... | Line 885... | ||
782 | info = (struct intel_device_info *) flags; |
885 | info = (struct intel_device_info *) flags; |
Line 801... | Line 904... | ||
801 | spin_lock_init(&dev_priv->mmio_flip_lock); |
904 | spin_lock_init(&dev_priv->mmio_flip_lock); |
802 | mutex_init(&dev_priv->sb_lock); |
905 | mutex_init(&dev_priv->sb_lock); |
803 | mutex_init(&dev_priv->modeset_restore_lock); |
906 | mutex_init(&dev_priv->modeset_restore_lock); |
804 | mutex_init(&dev_priv->av_mutex); |
907 | mutex_init(&dev_priv->av_mutex); |
Line -... | Line 908... | ||
- | 908 | ||
- | 909 | ret = i915_workqueues_init(dev_priv); |
|
- | 910 | if (ret < 0) |
|
- | 911 | goto out_free_priv; |
|
805 | 912 | ||
Line 806... | Line 913... | ||
806 | intel_pm_setup(dev); |
913 | intel_pm_setup(dev); |
Line 807... | Line 914... | ||
807 | 914 | ||
Line 819... | Line 926... | ||
819 | DRM_INFO("This is an early pre-production Haswell machine. " |
926 | DRM_INFO("This is an early pre-production Haswell machine. " |
820 | "It may not be fully functional.\n"); |
927 | "It may not be fully functional.\n"); |
Line 821... | Line 928... | ||
821 | 928 | ||
822 | if (i915_get_bridge_dev(dev)) { |
929 | if (i915_get_bridge_dev(dev)) { |
823 | ret = -EIO; |
930 | ret = -EIO; |
824 | goto free_priv; |
931 | goto out_runtime_pm_put; |
Line 825... | Line -... | ||
825 | } |
- | |
826 | - | ||
827 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
- | |
828 | /* Before gen4, the registers and the GTT are behind different BARs. |
- | |
829 | * However, from gen4 onwards, the registers and the GTT are shared |
- | |
830 | * in the same BAR, so we want to restrict this ioremap from |
- | |
831 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
932 | } |
832 | * the register BAR remains the same size for all the earlier |
- | |
833 | * generations up to Ironlake. |
933 | |
834 | */ |
- | |
835 | if (info->gen < 5) |
- | |
836 | mmio_size = 512*1024; |
- | |
837 | else |
- | |
838 | mmio_size = 2*1024*1024; |
- | |
839 | - | ||
840 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size); |
- | |
841 | if (!dev_priv->regs) { |
- | |
842 | DRM_ERROR("failed to map registers\n"); |
934 | ret = i915_mmio_setup(dev); |
843 | ret = -EIO; |
- | |
Line 844... | Line 935... | ||
844 | goto put_bridge; |
935 | if (ret < 0) |
Line 845... | Line 936... | ||
845 | } |
936 | goto put_bridge; |
846 | 937 | ||
Line 847... | Line 938... | ||
847 | set_fake_framebuffer(); |
938 | set_fake_framebuffer(); |
Line 848... | Line 939... | ||
848 | 939 | ||
849 | /* This must be called before any calls to HAS_PCH_* */ |
940 | /* This must be called before any calls to HAS_PCH_* */ |
850 | intel_detect_pch(dev); |
941 | intel_detect_pch(dev); |
Line 851... | Line 942... | ||
851 | 942 | ||
852 | intel_uncore_init(dev); |
943 | intel_uncore_init(dev); |
853 | 944 | ||
854 | ret = i915_gem_gtt_init(dev); |
945 | ret = i915_gem_gtt_init(dev); |
Line 881... | Line 972... | ||
881 | * which also needs to be handled carefully. |
972 | * which also needs to be handled carefully. |
882 | */ |
973 | */ |
Line 883... | Line 974... | ||
883 | 974 | ||
Line -... | Line 975... | ||
- | 975 | aperture_size = dev_priv->gtt.mappable_end; |
|
884 | aperture_size = dev_priv->gtt.mappable_end; |
976 | |
- | 977 | printk("aperture base %x size = %x\n",(u32)dev_priv->gtt.mappable_base,(u32)aperture_size); |
|
- | 978 | dev_priv->gtt.mappable = |
|
885 | 979 | io_mapping_create_wc(dev_priv->gtt.mappable_base, |
|
886 | dev_priv->gtt.mappable = AllocKernelSpace(8192); |
980 | aperture_size); |
887 | if (dev_priv->gtt.mappable == NULL) { |
981 | if (dev_priv->gtt.mappable == NULL) { |
888 | ret = -EIO; |
982 | ret = -EIO; |
Line 889... | Line -... | ||
889 | goto out_gtt; |
- | |
890 | } |
- | |
891 | - | ||
892 | - | ||
893 | /* The i915 workqueue is primarily used for batched retirement of |
- | |
894 | * requests (and thus managing bo) once the task has been completed |
- | |
895 | * by the GPU. i915_gem_retire_requests() is called directly when we |
- | |
896 | * need high-priority retirement, such as waiting for an explicit |
- | |
897 | * bo. |
- | |
898 | * |
- | |
899 | * It is also used for periodic low-priority events, such as |
- | |
900 | * idle-timers and recording error state. |
- | |
901 | * |
- | |
902 | * All tasks on the workqueue are expected to acquire the dev mutex |
- | |
903 | * so there is no point in running more than one instance of the |
- | |
904 | * workqueue at any time. Use an ordered one. |
- | |
905 | */ |
- | |
906 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
- | |
907 | if (dev_priv->wq == NULL) { |
- | |
908 | DRM_ERROR("Failed to create our workqueue.\n"); |
- | |
909 | ret = -ENOMEM; |
- | |
910 | goto out_mtrrfree; |
- | |
911 | } |
- | |
912 | system_wq = dev_priv->wq; |
- | |
913 | - | ||
914 | dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
- | |
915 | if (dev_priv->hotplug.dp_wq == NULL) { |
- | |
916 | DRM_ERROR("Failed to create our dp workqueue.\n"); |
- | |
917 | ret = -ENOMEM; |
983 | goto out_gtt; |
918 | goto out_freewq; |
984 | } |
Line 919... | Line -... | ||
919 | } |
- | |
920 | - | ||
921 | intel_irq_init(dev_priv); |
985 | |
Line 922... | Line 986... | ||
922 | intel_uncore_sanitize(dev); |
986 | |
Line 923... | Line 987... | ||
923 | 987 | intel_irq_init(dev_priv); |
|
924 | /* Try to make sure MCHBAR is enabled before poking at it */ |
988 | intel_uncore_sanitize(dev); |
925 | intel_setup_mchbar(dev); |
989 | |
926 | intel_opregion_setup(dev); |
990 | intel_opregion_setup(dev); |
Line 979... | Line 1043... | ||
979 | return 0; |
1043 | return 0; |
Line 980... | Line 1044... | ||
980 | 1044 | ||
981 | out_power_well: |
1045 | out_power_well: |
982 | drm_vblank_cleanup(dev); |
1046 | drm_vblank_cleanup(dev); |
983 | out_gem_unload: |
- | |
984 | - | ||
985 | out_freewq: |
- | |
986 | out_mtrrfree: |
1047 | out_gem_unload: |
987 | out_gtt: |
1048 | out_gtt: |
988 | i915_global_gtt_cleanup(dev); |
1049 | i915_global_gtt_cleanup(dev); |
989 | out_freecsr: |
1050 | out_uncore_fini: |
- | 1051 | put_bridge: |
|
- | 1052 | out_runtime_pm_put: |
|
990 | put_bridge: |
1053 | i915_workqueues_cleanup(dev_priv); |
991 | free_priv: |
1054 | out_free_priv: |
- | 1055 | kfree(dev_priv); |
|
992 | kfree(dev_priv); |
1056 | |
993 | return ret; |
1057 | return ret; |
Line 994... | Line 1058... | ||
994 | } |
1058 | } |
995 | 1059 | ||
Line 1013... | Line 1077... | ||
1013 | 1077 | ||
Line 1014... | Line 1078... | ||
1014 | intel_gpu_ips_teardown(); |
1078 | intel_gpu_ips_teardown(); |
Line 1015... | Line -... | ||
1015 | - | ||
1016 | i915_teardown_sysfs(dev); |
1079 | |
Line 1017... | Line 1080... | ||
1017 | 1080 | i915_teardown_sysfs(dev); |
|
1018 | WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier)); |
1081 | |
Line 1019... | Line 1082... | ||
1019 | unregister_shrinker(&dev_priv->mm.shrinker); |
1082 | i915_gem_shrinker_cleanup(dev_priv); |
Line 1042... | Line 1105... | ||
1042 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; |
1105 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; |
Line 1043... | Line 1106... | ||
1043 | 1106 | ||
1044 | vga_switcheroo_unregister_client(dev->pdev); |
1107 | vga_switcheroo_unregister_client(dev->pdev); |
Line -... | Line 1108... | ||
- | 1108 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
|
- | 1109 | ||
1045 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
1110 | intel_csr_ucode_fini(dev_priv); |
1046 | 1111 | ||
1047 | /* Free error state after interrupts are fully disabled. */ |
1112 | /* Free error state after interrupts are fully disabled. */ |
Line 1048... | Line 1113... | ||
1048 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
1113 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Line 1060... | Line 1125... | ||
1060 | mutex_lock(&dev->struct_mutex); |
1125 | mutex_lock(&dev->struct_mutex); |
1061 | i915_gem_cleanup_ringbuffer(dev); |
1126 | i915_gem_cleanup_ringbuffer(dev); |
1062 | i915_gem_context_fini(dev); |
1127 | i915_gem_context_fini(dev); |
1063 | mutex_unlock(&dev->struct_mutex); |
1128 | mutex_unlock(&dev->struct_mutex); |
1064 | intel_fbc_cleanup_cfb(dev_priv); |
1129 | intel_fbc_cleanup_cfb(dev_priv); |
1065 | i915_gem_cleanup_stolen(dev); |
- | |
1066 | - | ||
1067 | intel_csr_ucode_fini(dev_priv); |
- | |
1068 | - | ||
1069 | intel_teardown_mchbar(dev); |
- | |
Line 1070... | Line -... | ||
1070 | - | ||
1071 | destroy_workqueue(dev_priv->hotplug.dp_wq); |
- | |
1072 | destroy_workqueue(dev_priv->wq); |
- | |
1073 | destroy_workqueue(dev_priv->gpu_error.hangcheck_wq); |
1130 | |
Line 1074... | Line 1131... | ||
1074 | pm_qos_remove_request(&dev_priv->pm_qos); |
1131 | pm_qos_remove_request(&dev_priv->pm_qos); |
Line 1075... | Line 1132... | ||
1075 | 1132 | ||
1076 | i915_global_gtt_cleanup(dev); |
1133 | i915_global_gtt_cleanup(dev); |
1077 | - | ||
Line 1078... | Line -... | ||
1078 | intel_uncore_fini(dev); |
- | |
1079 | if (dev_priv->regs != NULL) |
- | |
1080 | pci_iounmap(dev->pdev, dev_priv->regs); |
1134 | |
1081 | 1135 | intel_uncore_fini(dev); |
|
- | 1136 | i915_mmio_cleanup(dev); |
|
1082 | kmem_cache_destroy(dev_priv->requests); |
1137 | |
Line 1083... | Line 1138... | ||
1083 | kmem_cache_destroy(dev_priv->vmas); |
1138 | i915_gem_load_cleanup(dev); |
1084 | kmem_cache_destroy(dev_priv->objects); |
1139 | pci_dev_put(dev_priv->bridge_dev); |
1085 | pci_dev_put(dev_priv->bridge_dev); |
1140 | i915_workqueues_cleanup(dev_priv); |
Line 1123... | Line 1178... | ||
1123 | { |
1178 | { |
1124 | mutex_lock(&dev->struct_mutex); |
1179 | mutex_lock(&dev->struct_mutex); |
1125 | i915_gem_context_close(dev, file); |
1180 | i915_gem_context_close(dev, file); |
1126 | i915_gem_release(dev, file); |
1181 | i915_gem_release(dev, file); |
1127 | mutex_unlock(&dev->struct_mutex); |
1182 | mutex_unlock(&dev->struct_mutex); |
1128 | - | ||
1129 | intel_modeset_preclose(dev, file); |
- | |
1130 | } |
1183 | } |
Line 1131... | Line 1184... | ||
1131 | 1184 | ||
1132 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
1185 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
1133 | { |
1186 | { |