WebSVN – Kolibri OS – Diff – /kernel/branches/Kolibri-A/trunk/bus/HT.inc


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                              ;;
;; Copyright (C) 2010-17 KolibriOS team.  All rights reserved.  ;;
;; Distributed under terms of the GNU General Public License    ;;
;;                                                              ;;
;;  HT.inc                                                      ;;                                                    ;;
;;                                                              ;;
;;  AMD HyperTransport bus control                              ;;
;;                                                              ;;
;;                  art_zh                ;;
;;                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
$Revision: 1554 $
 
NB_MISC_INDEX	equ	0xF0000060	; NB Misc indirect access
NB_MISC_DATA	equ	0xF0000064
PCIEIND_INDEX	equ	0xF00000E0	; PCIe Core indirect config space access
HTIU_NB_INDEX	equ	0xF0000094	; HyperTransport indirect config space access
 
;=============================================================================
;
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
;
;=============================================================================
 
org $-OS_BASE	; physical addresses needed at initial stage
 
align 4
 
;------------------------------------------
;       params:   al = nbconfig register#
;       returns: eax = register content
;
rs7xx_nbconfig_read_pci:
	and	eax, 0x0FC		 ; leave register# only
	or	eax, 0x80000000 	 ; bdf = 0:0.0
	mov	dx,  0x0CF8		 ; write to index reg
	out	dx, eax
	add	dl, 4
	in	eax, dx
	ret
align 4
 
rs7xx_nbconfig_flush_pci:
	mov	eax, 0x0B0		; a scratch reg
	mov	dx,  0xCF8
	out	dx,  eax
	ret
 
align 4
 
;------------------------------------------
;       params:   al = nbconfig register#
;                ebx = register content
;
rs7xx_nbconfig_write_pci:
	and	eax, 0x0FC		 ; leave register# only
	or	eax, 0x80000000 	 ; bdf = 0:0.0
	mov	dx,  0x0CF8		 ; write to index reg
	out	dx, eax
	add	dl, 4
	mov	eax, ebx
	out	dx, eax
	ret
 
;***************************************************************************
;   Function
;      rs7xx_unlock_bar3:     unlocks the BAR3 register of nbconfig that
;                             makes pcie config address space visible
;   -----------------------
;   in: nothing      out: nothing      destroys:   eax ebx edx
;
;***************************************************************************
align 4
rs7xx_unlock_bar3:
	mov	eax, NB_MISC_INDEX
	mov	ebx, 0x080			; NBMISCIND:0x0; write-enable
	call	rs7xx_nbconfig_write_pci	; set index
	mov	eax, NB_MISC_DATA
	call	rs7xx_nbconfig_read_pci 	; read data
	mov	ebx, eax
	and	ebx, 0xFFFFFFF7 		; clear bit3
	mov	eax, NB_MISC_DATA
	call	rs7xx_nbconfig_write_pci	; write it back
	mov	eax, NB_MISC_INDEX
	xor	ebx, ebx			; reg#0; write-locked
	call	rs7xx_nbconfig_write_pci	; set index
	ret
 
 
 
;***************************************************************************
;   Function
;      fusion_pcie_init:
;
;   Description
;       PCIe extended  config space detection and mapping
;
;***************************************************************************
 
align 4
 
 
 
; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
align 4
fusion_pcie_init:
	mov	ecx, 0xC0010058
	rdmsr
	or	edx, edx
	jnz	$				; PCIe is in the upper memory. Stop.
	xchg	dl, al
	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
	mov	ecx, edx
 
	shr	cl, 2
	mov	word[PCIe_bus_range-OS_BASE], cx
	sub	cl, 2
	jae	@f
	xor	cl, cl
@@:
	shl	edx, cl 			; edx = number of 4M pages to map
	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx
	shl	edx, 22
	dec	edx
	add	edx, eax			; the upper configspace limit
	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
 
; ---- large pages mapping  ----
; (eax = phys. address of PCIe conf.space)
;
.map_pcie_pages:
	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
	mov	ecx, PCIe_CONFIG_SPACE			; linear address
	mov	ebx, ecx
	shr	ebx, 20
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
	mov	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	; 1 page = 4M in address space
	cmp	dl, 0x34	; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
	jb	@f
	mov	dl, 0x33
	mov	byte[mmio_pcie_cfg_pdes-OS_BASE], dl
@@:
	xor	dx,  dx 			; PDEs counter
.write_pde:
	mov	dword[ebx], eax 		; map 4 buses
	add	bx,  4				; new PDE
	add	eax, 0x400000			; +4M phys.
	add	ecx, 0x400000			; +4M lin.
	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
	jae	.pcie_cfg_mapped
	inc	dl
	jmp	.write_pde
 
.pcie_cfg_mapped:
 
create_mmio_pte:
	mov	ecx, mmio_pte				; physical address
	or	ecx, (PG_NOCACHE + PG_SHARED + PG_UW)
	mov	ebx, FUSION_MMIO			; linear address
	shr	ebx, 20
	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
	mov	dword[ebx], ecx 			; Fusion MMIO tables
 
; ---- map APIC regs  ----
.map_apic_mmio:
	mov	ecx, 0x01B	; APIC BAR
	rdmsr
	and	eax, 0xFFFFF000 			; physical address
	or	eax, (PG_NOCACHE + PG_SHARED + PG_UW)
	mov	ebx, mmio_pte
	mov	[ebx], eax
 
; ---- map GPU MMRegs  ----
.map_gpu_mmr:
	mov	eax, [mmio_pcie_cfg_addr-OS_BASE]	; PCIe space
;	add	eax, 0x08018				; b:0, d:1, f:0, reg=18 << fam.14h GPU BAR
	add	eax, 0x08024				; b:0, d:1, f:0, reg=24 << fam.16h GPU BAR
	mov	eax, [eax]
 
	xor	al, al					; physical address
	or	eax, (PG_NOCACHE + PG_SHARED + PG_UW)
@@:
	add   bl, 4
	mov	[ebx], eax
	add   eax, 0x01000
	cmp   bl, 16*4	  ; map 15 pages
	jb    @b
 
	ret	; <<< OK >>>
 
; ================================================================================
 
org OS_BASE+$	; back to the linear address space
 
;--------------------------------------------------------------
align 4
rs780_read_misc:
;  in: eax(al) - reg#           out: eax = NBMISCIND data
	push	edx
	mov	edx, NB_MISC_INDEX
	and	eax, 0x07F
	mov	[edx], eax
	add	dl, 4
	mov	eax, [edx]
	pop	edx
	ret
 
;-------------------------------------------
align 4
rs780_write_misc:
;  in: eax(al) - reg#     ebx = NBMISCIND data
	push	edx
	mov	edx, NB_MISC_INDEX
	and	eax, 0x07F
	or	eax, 0x080		; set WE
	mov	[edx], eax
	add	dl, 4
	mov	[edx], ebx
	sub	dl, 4
	xor	eax,   eax
	mov	[edx], eax		; safety last
	pop	edx
	ret
 
;-------------------------------------------------------------
align 4
rs780_read_pcieind:
;  in: ah = bridge#, al = reg#           out: eax = PCIEIND data
	push	edx
	xor	edx, edx
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
	shl	edx, 15 		; device#
	add	edx, PCIEIND_INDEX	; full bdf-address
	and	eax, 0x30FF
	or	al,  al
	jnz	@f
	shl	eax, 4			; set bits 17..16 for a Core bridge
@@:
	mov	[edx], eax
	add	dl,  4
	mov	eax, [edx]
	pop	edx
	ret
 
;-------------------------------------------
align 4
rs780_write_pcieind:
;  in: ah = bridge#, al = reg#,  ebx = PCIEIND data
	push	edx
	xor	edx, edx
	mov	ah,  dl 		; bridge# :     0 = Core+GFX;   0x10 = Core+SB
	and	dl,  15 		;            0x20 = Core+GPP;  2..12 = a PortBridge
	shl	edx, 15 		; device#
	add	edx, PCIEIND_INDEX	; full bdf-address
	and	eax, 0x30FF
	or	al,  al
	jnz	@f
	shl	eax, 4			; set bits 17..16 for a Core bridge
@@:
	mov	[edx], eax
	add	dl,  4
	mov	[edx], ebx
	sub	dl,  4
	xor	eax,   eax
	mov	[edx], eax		; safety last
	pop	edx
	ret
 
;------------------------------------------------
align 4
rs780_read_htiu:
; in:  al = reg#  |  out: eax = HTIU data
;------------------------------------------------
	push	edx
	mov	edx,  HTIU_NB_INDEX
	and	eax, 0x07F
	mov	[edx], eax
	add	dl,  4
	mov	eax, [edx]
	pop	edx
	ret
;------------------------------------------------
align 4
rs780_write_htiu:
; in:  al = reg#; ebx = data
;------------------------------------------------
	push	edx
	mov	edx,  HTIU_NB_INDEX
	and	eax, 0x07F
	or	eax, 0x100
	mov	[edx], eax
	add	dl,  4
	mov	[edx], ebx
	sub	dl,  4
	xor	eax,   eax
	mov	[edx], eax
	pop	edx
	ret
 
;------------------------------------------------
align 4
sys_rdmsr:
;  in: [esp+8] = MSR#
; out: [esp+8] = MSR[63:32]
;        [eax] = MSR[31: 0]
;------------------------------------------------
	push	ecx edx
	mov	ecx, [esp+16]
	rdmsr
	mov	[esp+16], edx
	pop	edx ecx
	ret
 
;------------------------------------------------
uglobal
 
align 4
diff16 "apic_data : ", 0, $
apic_data:
 
    .counter dd ?
    .ticks   dd ?
    .t_freq  dd ?
    .gpu_r6998 dd ?
endg
 
apic_timer_reset:
	mov	eax, [pll_frequency.osc]
	shr	eax, 1					; default prescaler - fix it !!
	mov	[apic_data.t_freq], eax
	shr	eax, 4					; 16 per second
	mov	[apic_data.ticks], eax
 
	mov	ebx, LAPIC_BAR+ 0x320
	mov	edx, [ebx]
	and	edx, 0xFFFEFF00
	or	edx, 0x0002003F 			; int vector + restart
;--     mov     [ebx], edx
	mov	dword [LAPIC_BAR + 0x380], eax		; load APICTIC
 
; ret
 
init_hw_cursor:
	call	alloc_page			 ; eax = phys. addr
	push	eax
	or	eax, (PG_NOCACHE + PG_SHARED + PG_UW)	 
	mov	[mmio_pte + OS_BASE + 15*4], eax ; mapped to the end of GPU MMRegs
	mov	edi, GPU_CURSOR 		 ; lin. addr
	invlpg	[edi]
	xor	ecx, ecx
.fill64pix:
	xor	ebx, ebx
	mov	eax, 0x80000000 		; black, non-transparent
.check_pix:
	cmp	ebx, ecx
	jbe	@f
	xor	eax, eax			; transparent
@@:
	mov	[edi + ebx*4], eax
	inc	ebx
	cmp	bl, 64
	jb	.check_pix
	inc	ecx
	cmp	ecx, 16
	je	@f
;	add	edi, 64*4			; evergreen cursor is 64x64pix
	add	edi, 128*4			; si cursor is 128x128pix
	jmp	.fill64pix
@@:
	pop	eax
	mov	dword[GPU_MMR + 0x0699C], eax        ; cur_surface_addr
	mov	dword[GPU_MMR + 0x069A0], 0x000F000F ; cur_size    = 16x16
	mov	dword[GPU_MMR + 0x069A4], 0          ; cur_adr_hi
	mov	dword[GPU_MMR + 0x069A8], 0x02000100 ; cur_pos     = 512,256
	mov	dword[GPU_MMR + 0x069AC], 0          ; cur_hotspot = 0,0
 
	mov	dword[GPU_MMR + 0x06998], 0x00000301 ; set it!
 
 
 
	ret
 
 
apic_timer_int:
	push	eax
	inc	dword [apic_data.counter]
;        mov     eax,  [apic_data.ticks]
;        mov     dword [LAPIC_BAR + 0x380], eax          ; reload APICTIC
	mov	dword [LAPIC_BAR + 0x0B0], 0		; end of interrupt
;        mov     dword [LAPIC_BAR + 0x420], 0x3F            ; end of interrupt
	pop	eax
	iretd

Rev 3934	Rev 6877
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) 2010-13 KolibriOS team. All rights reserved. ;;	3	;; Copyright (C) 2010-17 KolibriOS team. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;; HT.inc ;; ;;	6	;; HT.inc ;; ;;
7	;; ;;	7	;; ;;
8	;; AMD HyperTransport bus control ;;	8	;; AMD HyperTransport bus control ;;
9	;; ;;	9	;; ;;
10	;; art_zh ;;	10	;; art_zh ;;
11	;; ;;	11	;; ;;
12	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	12	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13		13
14	$Revision: 1554 $	14	$Revision: 1554 $
15		15
16	NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access	16	NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access
17	NB_MISC_DATA equ 0xF0000064	17	NB_MISC_DATA equ 0xF0000064
18	PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access	18	PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access
19	HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access	19	HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access
20		20
21	;=============================================================================	21	;=============================================================================
22	;	22	;
23	; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets	23	; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
24	;	24	;
25	;=============================================================================	25	;=============================================================================
26		26
27	org $-OS_BASE ; physical addresses needed at initial stage	27	org $-OS_BASE ; physical addresses needed at initial stage
28		28
29	align 4	29	align 4
30		30
31	;------------------------------------------	31	;------------------------------------------
32	; params: al = nbconfig register#	32	; params: al = nbconfig register#
33	; returns: eax = register content	33	; returns: eax = register content
34	;	34	;
35	rs7xx_nbconfig_read_pci:	35	rs7xx_nbconfig_read_pci:
36	and eax, 0x0FC ; leave register# only	36	and eax, 0x0FC ; leave register# only
37	or eax, 0x80000000 ; bdf = 0:0.0	37	or eax, 0x80000000 ; bdf = 0:0.0
38	mov dx, 0x0CF8 ; write to index reg	38	mov dx, 0x0CF8 ; write to index reg
39	out dx, eax	39	out dx, eax
40	add dl, 4	40	add dl, 4
41	in eax, dx	41	in eax, dx
42	ret	42	ret
43	align 4	43	align 4
44		44
45	rs7xx_nbconfig_flush_pci:	45	rs7xx_nbconfig_flush_pci:
46	mov eax, 0x0B0 ; a scratch reg	46	mov eax, 0x0B0 ; a scratch reg
47	mov dx, 0xCF8	47	mov dx, 0xCF8
48	out dx, eax	48	out dx, eax
49	ret	49	ret
50		50
51	align 4	51	align 4
52		52
53	;------------------------------------------	53	;------------------------------------------
54	; params: al = nbconfig register#	54	; params: al = nbconfig register#
55	; ebx = register content	55	; ebx = register content
56	;	56	;
57	rs7xx_nbconfig_write_pci:	57	rs7xx_nbconfig_write_pci:
58	and eax, 0x0FC ; leave register# only	58	and eax, 0x0FC ; leave register# only
59	or eax, 0x80000000 ; bdf = 0:0.0	59	or eax, 0x80000000 ; bdf = 0:0.0
60	mov dx, 0x0CF8 ; write to index reg	60	mov dx, 0x0CF8 ; write to index reg
61	out dx, eax	61	out dx, eax
62	add dl, 4	62	add dl, 4
63	mov eax, ebx	63	mov eax, ebx
64	out dx, eax	64	out dx, eax
65	ret	65	ret
66		66
67	;***************************************************************************	67	;***************************************************************************
68	; Function	68	; Function
69	; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that	69	; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that
70	; makes pcie config address space visible	70	; makes pcie config address space visible
71	; -----------------------	71	; -----------------------
72	; in: nothing out: nothing destroys: eax ebx edx	72	; in: nothing out: nothing destroys: eax ebx edx
73	;	73	;
74	;***************************************************************************	74	;***************************************************************************
75	align 4	75	align 4
76	rs7xx_unlock_bar3:	76	rs7xx_unlock_bar3:
77	mov eax, NB_MISC_INDEX	77	mov eax, NB_MISC_INDEX
78	mov ebx, 0x080 ; NBMISCIND:0x0; write-enable	78	mov ebx, 0x080 ; NBMISCIND:0x0; write-enable
79	call rs7xx_nbconfig_write_pci ; set index	79	call rs7xx_nbconfig_write_pci ; set index
80	mov eax, NB_MISC_DATA	80	mov eax, NB_MISC_DATA
81	call rs7xx_nbconfig_read_pci ; read data	81	call rs7xx_nbconfig_read_pci ; read data
82	mov ebx, eax	82	mov ebx, eax
83	and ebx, 0xFFFFFFF7 ; clear bit3	83	and ebx, 0xFFFFFFF7 ; clear bit3
84	mov eax, NB_MISC_DATA	84	mov eax, NB_MISC_DATA
85	call rs7xx_nbconfig_write_pci ; write it back	85	call rs7xx_nbconfig_write_pci ; write it back
86	mov eax, NB_MISC_INDEX	86	mov eax, NB_MISC_INDEX
87	xor ebx, ebx ; reg#0; write-locked	87	xor ebx, ebx ; reg#0; write-locked
88	call rs7xx_nbconfig_write_pci ; set index	88	call rs7xx_nbconfig_write_pci ; set index
89	ret	89	ret
90		90
91		91
92		92
93	;***************************************************************************	93	;***************************************************************************
94	; Function	94	; Function
95	; fusion_pcie_init:	95	; fusion_pcie_init:
96	;	96	;
97	; Description	97	; Description
98	; PCIe extended config space detection and mapping	98	; PCIe extended config space detection and mapping
99	;	99	;
100	;***************************************************************************	100	;***************************************************************************
101		101
102	align 4	102	align 4
103		103
104		104
105		105
106	; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----	106	; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
107	align 4	107	align 4
108	fusion_pcie_init:	108	fusion_pcie_init:
109	mov ecx, 0xC0010058	109	mov ecx, 0xC0010058
110	rdmsr	110	rdmsr
111	or edx, edx	111	or edx, edx
112	jnz $ ; PCIe is in the upper memory. Stop.	112	jnz $ ; PCIe is in the upper memory. Stop.
113	xchg dl, al	113	xchg dl, al
114	mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address	114	mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address
115	mov ecx, edx	115	mov ecx, edx
116		116
117	shr cl, 2	117	shr cl, 2
118	mov word[PCIe_bus_range-OS_BASE], cx	118	mov word[PCIe_bus_range-OS_BASE], cx
119	sub cl, 2	119	sub cl, 2
120	jae @f	120	jae @f
121	xor cl, cl	121	xor cl, cl
122	@@:	122	@@:
123	shl edx, cl ; edx = number of 4M pages to map	123	shl edx, cl ; edx = number of 4M pages to map
124	mov word[mmio_pcie_cfg_pdes-OS_BASE], dx	124	mov word[mmio_pcie_cfg_pdes-OS_BASE], dx
125	shl edx, 22	125	shl edx, 22
126	dec edx	126	dec edx
127	add edx, eax ; the upper configspace limit	127	add edx, eax ; the upper configspace limit
128	mov dword[mmio_pcie_cfg_lim-OS_BASE], edx	128	mov dword[mmio_pcie_cfg_lim-OS_BASE], edx
129		129
130	; ---- large pages mapping ----	130	; ---- large pages mapping ----
131	; (eax = phys. address of PCIe conf.space)	131	; (eax = phys. address of PCIe conf.space)
132	;	132	;
133	.map_pcie_pages:	133	.map_pcie_pages:
134	or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!	134	or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!
135	mov ecx, PCIe_CONFIG_SPACE ; linear address	135	mov ecx, PCIe_CONFIG_SPACE ; linear address
136	mov ebx, ecx	136	mov ebx, ecx
137	shr ebx, 20	137	shr ebx, 20
138	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @	138	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
139	mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space	139	mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space
140	cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M	140	cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
141	jb @f	141	jb @f
142	mov dl, 0x33	142	mov dl, 0x33
143	mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl	143	mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl
144	@@:	144	@@:
145	xor dx, dx ; PDEs counter	145	xor dx, dx ; PDEs counter
146	.write_pde:	146	.write_pde:
147	mov dword[ebx], eax ; map 4 buses	147	mov dword[ebx], eax ; map 4 buses
148	add bx, 4 ; new PDE	148	add bx, 4 ; new PDE
149	add eax, 0x400000 ; +4M phys.	149	add eax, 0x400000 ; +4M phys.
150	add ecx, 0x400000 ; +4M lin.	150	add ecx, 0x400000 ; +4M lin.
151	cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]	151	cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
152	jae .pcie_cfg_mapped	152	jae .pcie_cfg_mapped
153	inc dl	153	inc dl
154	jmp .write_pde	154	jmp .write_pde
155		155
156	.pcie_cfg_mapped:	156	.pcie_cfg_mapped:
157		157
158	create_mmio_pte:	158	create_mmio_pte:
159	mov ecx, mmio_pte ; physical address	159	mov ecx, mmio_pte ; physical address
160	or ecx, (PG_NOCACHE + PG_SHARED + PG_UW)	160	or ecx, (PG_NOCACHE + PG_SHARED + PG_UW)
161	mov ebx, FUSION_MMIO ; linear address	161	mov ebx, FUSION_MMIO ; linear address
162	shr ebx, 20	162	shr ebx, 20
163	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @	163	add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
164	mov dword[ebx], ecx ; Fusion MMIO tables	164	mov dword[ebx], ecx ; Fusion MMIO tables
165		165
166	; ---- map APIC regs ----	166	; ---- map APIC regs ----
167	.map_apic_mmio:	167	.map_apic_mmio:
168	mov ecx, 0x01B ; APIC BAR	168	mov ecx, 0x01B ; APIC BAR
169	rdmsr	169	rdmsr
170	and eax, 0xFFFFF000 ; physical address	170	and eax, 0xFFFFF000 ; physical address
171	or eax, (PG_NOCACHE + PG_SHARED + PG_UW)	171	or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
172	mov ebx, mmio_pte	172	mov ebx, mmio_pte
173	mov [ebx], eax	173	mov [ebx], eax
174		174
175	; ---- map GPU MMRegs ----	175	; ---- map GPU MMRegs ----
176	.map_gpu_mmr:	176	.map_gpu_mmr:
177	mov eax, [mmio_pcie_cfg_addr-OS_BASE] ; PCIe space	177	mov eax, [mmio_pcie_cfg_addr-OS_BASE] ; PCIe space
178	add eax, 0x08018 ; b:0, d:1, f:0, reg=18	178	; add eax, 0x08018 ; b:0, d:1, f:0, reg=18 << fam.14h GPU BAR
-		179	add eax, 0x08024 ; b:0, d:1, f:0, reg=24 << fam.16h GPU BAR
179	mov eax, [eax]	180	mov eax, [eax]
180		181
181	xor al, al ; physical address	182	xor al, al ; physical address
182	or eax, (PG_NOCACHE + PG_SHARED + PG_UW)	183	or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
183	@@:	184	@@:
184	add bl, 4	185	add bl, 4
185	mov [ebx], eax	186	mov [ebx], eax
186	add eax, 0x01000	187	add eax, 0x01000
187	cmp bl, 16*4 ; map 15 pages	188	cmp bl, 16*4 ; map 15 pages
188	jb @b	189	jb @b
189		190
190	ret ; <<< OK >>>	191	ret ; <<< OK >>>
191		192
192	; ================================================================================	193	; ================================================================================
193		194
194	org OS_BASE+$ ; back to the linear address space	195	org OS_BASE+$ ; back to the linear address space
195		196
196	;--------------------------------------------------------------	197	;--------------------------------------------------------------
197	align 4	198	align 4
198	rs780_read_misc:	199	rs780_read_misc:
199	; in: eax(al) - reg# out: eax = NBMISCIND data	200	; in: eax(al) - reg# out: eax = NBMISCIND data
200	push edx	201	push edx
201	mov edx, NB_MISC_INDEX	202	mov edx, NB_MISC_INDEX
202	and eax, 0x07F	203	and eax, 0x07F
203	mov [edx], eax	204	mov [edx], eax
204	add dl, 4	205	add dl, 4
205	mov eax, [edx]	206	mov eax, [edx]
206	pop edx	207	pop edx
207	ret	208	ret
208		209
209	;-------------------------------------------	210	;-------------------------------------------
210	align 4	211	align 4
211	rs780_write_misc:	212	rs780_write_misc:
212	; in: eax(al) - reg# ebx = NBMISCIND data	213	; in: eax(al) - reg# ebx = NBMISCIND data
213	push edx	214	push edx
214	mov edx, NB_MISC_INDEX	215	mov edx, NB_MISC_INDEX
215	and eax, 0x07F	216	and eax, 0x07F
216	or eax, 0x080 ; set WE	217	or eax, 0x080 ; set WE
217	mov [edx], eax	218	mov [edx], eax
218	add dl, 4	219	add dl, 4
219	mov [edx], ebx	220	mov [edx], ebx
220	sub dl, 4	221	sub dl, 4
221	xor eax, eax	222	xor eax, eax
222	mov [edx], eax ; safety last	223	mov [edx], eax ; safety last
223	pop edx	224	pop edx
224	ret	225	ret
225		226
226	;-------------------------------------------------------------	227	;-------------------------------------------------------------
227	align 4	228	align 4
228	rs780_read_pcieind:	229	rs780_read_pcieind:
229	; in: ah = bridge#, al = reg# out: eax = PCIEIND data	230	; in: ah = bridge#, al = reg# out: eax = PCIEIND data
230	push edx	231	push edx
231	xor edx, edx	232	xor edx, edx
232	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB	233	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
233	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge	234	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
234	shl edx, 15 ; device#	235	shl edx, 15 ; device#
235	add edx, PCIEIND_INDEX ; full bdf-address	236	add edx, PCIEIND_INDEX ; full bdf-address
236	and eax, 0x30FF	237	and eax, 0x30FF
237	or al, al	238	or al, al
238	jnz @f	239	jnz @f
239	shl eax, 4 ; set bits 17..16 for a Core bridge	240	shl eax, 4 ; set bits 17..16 for a Core bridge
240	@@:	241	@@:
241	mov [edx], eax	242	mov [edx], eax
242	add dl, 4	243	add dl, 4
243	mov eax, [edx]	244	mov eax, [edx]
244	pop edx	245	pop edx
245	ret	246	ret
246		247
247	;-------------------------------------------	248	;-------------------------------------------
248	align 4	249	align 4
249	rs780_write_pcieind:	250	rs780_write_pcieind:
250	; in: ah = bridge#, al = reg#, ebx = PCIEIND data	251	; in: ah = bridge#, al = reg#, ebx = PCIEIND data
251	push edx	252	push edx
252	xor edx, edx	253	xor edx, edx
253	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB	254	mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
254	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge	255	and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
255	shl edx, 15 ; device#	256	shl edx, 15 ; device#
256	add edx, PCIEIND_INDEX ; full bdf-address	257	add edx, PCIEIND_INDEX ; full bdf-address
257	and eax, 0x30FF	258	and eax, 0x30FF
258	or al, al	259	or al, al
259	jnz @f	260	jnz @f
260	shl eax, 4 ; set bits 17..16 for a Core bridge	261	shl eax, 4 ; set bits 17..16 for a Core bridge
261	@@:	262	@@:
262	mov [edx], eax	263	mov [edx], eax
263	add dl, 4	264	add dl, 4
264	mov [edx], ebx	265	mov [edx], ebx
265	sub dl, 4	266	sub dl, 4
266	xor eax, eax	267	xor eax, eax
267	mov [edx], eax ; safety last	268	mov [edx], eax ; safety last
268	pop edx	269	pop edx
269	ret	270	ret
270		271
271	;------------------------------------------------	272	;------------------------------------------------
272	align 4	273	align 4
273	rs780_read_htiu:	274	rs780_read_htiu:
274	; in: al = reg# \| out: eax = HTIU data	275	; in: al = reg# \| out: eax = HTIU data
275	;------------------------------------------------	276	;------------------------------------------------
276	push edx	277	push edx
277	mov edx, HTIU_NB_INDEX	278	mov edx, HTIU_NB_INDEX
278	and eax, 0x07F	279	and eax, 0x07F
279	mov [edx], eax	280	mov [edx], eax
280	add dl, 4	281	add dl, 4
281	mov eax, [edx]	282	mov eax, [edx]
282	pop edx	283	pop edx
283	ret	284	ret
284	;------------------------------------------------	285	;------------------------------------------------
285	align 4	286	align 4
286	rs780_write_htiu:	287	rs780_write_htiu:
287	; in: al = reg#; ebx = data	288	; in: al = reg#; ebx = data
288	;------------------------------------------------	289	;------------------------------------------------
289	push edx	290	push edx
290	mov edx, HTIU_NB_INDEX	291	mov edx, HTIU_NB_INDEX
291	and eax, 0x07F	292	and eax, 0x07F
292	or eax, 0x100	293	or eax, 0x100
293	mov [edx], eax	294	mov [edx], eax
294	add dl, 4	295	add dl, 4
295	mov [edx], ebx	296	mov [edx], ebx
296	sub dl, 4	297	sub dl, 4
297	xor eax, eax	298	xor eax, eax
298	mov [edx], eax	299	mov [edx], eax
299	pop edx	300	pop edx
300	ret	301	ret
301		302
302	;------------------------------------------------	303	;------------------------------------------------
303	align 4	304	align 4
304	sys_rdmsr:	305	sys_rdmsr:
305	; in: [esp+8] = MSR#	306	; in: [esp+8] = MSR#
306	; out: [esp+8] = MSR[63:32]	307	; out: [esp+8] = MSR[63:32]
307	; [eax] = MSR[31: 0]	308	; [eax] = MSR[31: 0]
308	;------------------------------------------------	309	;------------------------------------------------
309	push ecx edx	310	push ecx edx
310	mov ecx, [esp+16]	311	mov ecx, [esp+16]
311	rdmsr	312	rdmsr
312	mov [esp+16], edx	313	mov [esp+16], edx
313	pop edx ecx	314	pop edx ecx
314	ret	315	ret
315		316
316	;------------------------------------------------	317	;------------------------------------------------
317	uglobal	318	uglobal
318		319
319	align 4	320	align 4
320	diff16 "apic_data : ", 0, $	321	diff16 "apic_data : ", 0, $
321	apic_data:	322	apic_data:
322		323
323	.counter dd ?	324	.counter dd ?
324	.ticks dd ?	325	.ticks dd ?
325	.t_freq dd ?	326	.t_freq dd ?
326	.gpu_r6998 dd ?	327	.gpu_r6998 dd ?
327	endg	328	endg
328		329
329	apic_timer_reset:	330	apic_timer_reset:
330	mov eax, [pll_frequency.osc]	331	mov eax, [pll_frequency.osc]
331	shr eax, 1 ; default prescaler - fix it !!	332	shr eax, 1 ; default prescaler - fix it !!
332	mov [apic_data.t_freq], eax	333	mov [apic_data.t_freq], eax
333	shr eax, 4 ; 16 per second	334	shr eax, 4 ; 16 per second
334	mov [apic_data.ticks], eax	335	mov [apic_data.ticks], eax
335		336
336	mov ebx, LAPIC_BAR+ 0x320	337	mov ebx, LAPIC_BAR+ 0x320
337	mov edx, [ebx]	338	mov edx, [ebx]
338	and edx, 0xFFFEFF00	339	and edx, 0xFFFEFF00
339	or edx, 0x0002003F ; int vector + restart	340	or edx, 0x0002003F ; int vector + restart
340	;-- mov [ebx], edx	341	;-- mov [ebx], edx
341	mov dword [LAPIC_BAR + 0x380], eax ; load APICTIC	342	mov dword [LAPIC_BAR + 0x380], eax ; load APICTIC
342		343
343	; ret	344	; ret
344		345
345	init_hw_cursor:	346	init_hw_cursor:
346	call alloc_page ; eax = phys. addr	347	call alloc_page ; eax = phys. addr
347	push eax	348	push eax
348	or eax, (PG_NOCACHE + PG_SHARED + PG_UW) ; i like dirty hacks	349	or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
349	mov [mmio_pte + OS_BASE + 15*4], eax ; mapped to the end of GPU MMRegs	350	mov [mmio_pte + OS_BASE + 15*4], eax ; mapped to the end of GPU MMRegs
350	mov edi, GPU_CURSOR ; lin. addr	351	mov edi, GPU_CURSOR ; lin. addr
351	invlpg [edi]	352	invlpg [edi]
352	xor ecx, ecx	353	xor ecx, ecx
353	.fill64pix:	354	.fill64pix:
354	xor ebx, ebx	355	xor ebx, ebx
355	mov eax, 0x80000000 ; black, non-transparent	356	mov eax, 0x80000000 ; black, non-transparent
356	.check_pix:	357	.check_pix:
357	cmp ebx, ecx	358	cmp ebx, ecx
358	jbe @f	359	jbe @f
359	xor eax, eax ; transparent	360	xor eax, eax ; transparent
360	@@:	361	@@:
361	mov [edi + ebx*4], eax	362	mov [edi + ebx*4], eax
362	inc ebx	363	inc ebx
363	cmp bl, 64	364	cmp bl, 64
364	jb .check_pix	365	jb .check_pix
365	inc ecx	366	inc ecx
366	cmp ecx, 16	367	cmp ecx, 16
367	je @f	368	je @f
368	add edi, 64*4 ; new line	369	; add edi, 64*4 ; evergreen cursor is 64x64pix
-		370	add edi, 128*4 ; si cursor is 128x128pix
369	jmp .fill64pix	371	jmp .fill64pix
370	@@:	372	@@:
371	pop eax	373	pop eax
372	mov dword[GPU_MMR + 0x0699C], eax ; cur_surface_addr	374	mov dword[GPU_MMR + 0x0699C], eax ; cur_surface_addr
373	mov dword[GPU_MMR + 0x069A0], 0x000F000F ; cur_size = 16x16	375	mov dword[GPU_MMR + 0x069A0], 0x000F000F ; cur_size = 16x16
374	mov dword[GPU_MMR + 0x069A4], 0 ; cur_adr_hi	376	mov dword[GPU_MMR + 0x069A4], 0 ; cur_adr_hi
375	mov dword[GPU_MMR + 0x069A8], 0x02000100 ; cur_pos = 512,256	377	mov dword[GPU_MMR + 0x069A8], 0x02000100 ; cur_pos = 512,256
376	mov dword[GPU_MMR + 0x069AC], 0 ; cur_hotspot = 0,0	378	mov dword[GPU_MMR + 0x069AC], 0 ; cur_hotspot = 0,0
377		379
378	mov dword[GPU_MMR + 0x06998], 0x00000301 ; set it!	380	mov dword[GPU_MMR + 0x06998], 0x00000301 ; set it!
379		381
380		382
381		383
382	ret	384	ret
383		385
384		386
385	apic_timer_int:	387	apic_timer_int:
386	push eax	388	push eax
387	inc dword [apic_data.counter]	389	inc dword [apic_data.counter]
388	; mov eax, [apic_data.ticks]	390	; mov eax, [apic_data.ticks]
389	; mov dword [LAPIC_BAR + 0x380], eax ; reload APICTIC	391	; mov dword [LAPIC_BAR + 0x380], eax ; reload APICTIC
390	mov dword [LAPIC_BAR + 0x0B0], 0 ; end of interrupt	392	mov dword [LAPIC_BAR + 0x0B0], 0 ; end of interrupt
391	; mov dword [LAPIC_BAR + 0x420], 0x3F ; end of interrupt	393	; mov dword [LAPIC_BAR + 0x420], 0x3F ; end of interrupt
392	pop eax	394	pop eax
393	iretd	395	iretd

Subversion Repositories Kolibri OS

(root)/kernel/branches/Kolibri-A/trunk/bus/HT.inc – Rev 3934 → 6877