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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "rv515d.h" |
31 | #include "rv515d.h" |
32 | #include "radeon.h" |
32 | #include "radeon.h" |
33 | #include "radeon_asic.h" |
33 | #include "radeon_asic.h" |
34 | #include "atom.h" |
34 | #include "atom.h" |
35 | #include "rv515_reg_safe.h" |
35 | #include "rv515_reg_safe.h" |
36 | 36 | ||
37 | /* This files gather functions specifics to: rv515 */ |
37 | /* This files gather functions specifics to: rv515 */ |
38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
38 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
39 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
40 | static void rv515_gpu_init(struct radeon_device *rdev); |
40 | static void rv515_gpu_init(struct radeon_device *rdev); |
41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
41 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
42 | 42 | ||
43 | static const u32 crtc_offsets[2] = |
43 | static const u32 crtc_offsets[2] = |
44 | { |
44 | { |
45 | 0, |
45 | 0, |
46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
46 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
47 | }; |
47 | }; |
48 | 48 | ||
49 | void rv515_debugfs(struct radeon_device *rdev) |
49 | void rv515_debugfs(struct radeon_device *rdev) |
50 | { |
50 | { |
51 | if (r100_debugfs_rbbm_init(rdev)) { |
51 | if (r100_debugfs_rbbm_init(rdev)) { |
52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
52 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
53 | } |
53 | } |
54 | if (rv515_debugfs_pipes_info_init(rdev)) { |
54 | if (rv515_debugfs_pipes_info_init(rdev)) { |
55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
55 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
56 | } |
56 | } |
57 | if (rv515_debugfs_ga_info_init(rdev)) { |
57 | if (rv515_debugfs_ga_info_init(rdev)) { |
58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
58 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
59 | } |
59 | } |
60 | } |
60 | } |
61 | 61 | ||
62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
62 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
63 | { |
63 | { |
64 | int r; |
64 | int r; |
65 | 65 | ||
66 | r = radeon_ring_lock(rdev, ring, 64); |
66 | r = radeon_ring_lock(rdev, ring, 64); |
67 | if (r) { |
67 | if (r) { |
68 | return; |
68 | return; |
69 | } |
69 | } |
70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
70 | radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); |
71 | radeon_ring_write(ring, |
71 | radeon_ring_write(ring, |
72 | ISYNC_ANY2D_IDLE3D | |
72 | ISYNC_ANY2D_IDLE3D | |
73 | ISYNC_ANY3D_IDLE2D | |
73 | ISYNC_ANY3D_IDLE2D | |
74 | ISYNC_WAIT_IDLEGUI | |
74 | ISYNC_WAIT_IDLEGUI | |
75 | ISYNC_CPSCRATCH_IDLEGUI); |
75 | ISYNC_CPSCRATCH_IDLEGUI); |
76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
76 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
77 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
78 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
79 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); |
80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); |
80 | radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); |
81 | radeon_ring_write(ring, 0); |
81 | radeon_ring_write(ring, 0); |
82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); |
82 | radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); |
83 | radeon_ring_write(ring, 0); |
83 | radeon_ring_write(ring, 0); |
84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); |
84 | radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); |
85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); |
85 | radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); |
86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); |
86 | radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); |
87 | radeon_ring_write(ring, 0); |
87 | radeon_ring_write(ring, 0); |
88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
88 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
89 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
90 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
91 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
92 | radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); |
93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
93 | radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); |
94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); |
94 | radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); |
95 | radeon_ring_write(ring, 0); |
95 | radeon_ring_write(ring, 0); |
96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
96 | radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); |
97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
97 | radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); |
98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
98 | radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); |
99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
99 | radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); |
100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); |
100 | radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); |
101 | radeon_ring_write(ring, |
101 | radeon_ring_write(ring, |
102 | ((6 << MS_X0_SHIFT) | |
102 | ((6 << MS_X0_SHIFT) | |
103 | (6 << MS_Y0_SHIFT) | |
103 | (6 << MS_Y0_SHIFT) | |
104 | (6 << MS_X1_SHIFT) | |
104 | (6 << MS_X1_SHIFT) | |
105 | (6 << MS_Y1_SHIFT) | |
105 | (6 << MS_Y1_SHIFT) | |
106 | (6 << MS_X2_SHIFT) | |
106 | (6 << MS_X2_SHIFT) | |
107 | (6 << MS_Y2_SHIFT) | |
107 | (6 << MS_Y2_SHIFT) | |
108 | (6 << MSBD0_Y_SHIFT) | |
108 | (6 << MSBD0_Y_SHIFT) | |
109 | (6 << MSBD0_X_SHIFT))); |
109 | (6 << MSBD0_X_SHIFT))); |
110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
110 | radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); |
111 | radeon_ring_write(ring, |
111 | radeon_ring_write(ring, |
112 | ((6 << MS_X3_SHIFT) | |
112 | ((6 << MS_X3_SHIFT) | |
113 | (6 << MS_Y3_SHIFT) | |
113 | (6 << MS_Y3_SHIFT) | |
114 | (6 << MS_X4_SHIFT) | |
114 | (6 << MS_X4_SHIFT) | |
115 | (6 << MS_Y4_SHIFT) | |
115 | (6 << MS_Y4_SHIFT) | |
116 | (6 << MS_X5_SHIFT) | |
116 | (6 << MS_X5_SHIFT) | |
117 | (6 << MS_Y5_SHIFT) | |
117 | (6 << MS_Y5_SHIFT) | |
118 | (6 << MSBD1_SHIFT))); |
118 | (6 << MSBD1_SHIFT))); |
119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
119 | radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); |
120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
120 | radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); |
121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); |
121 | radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); |
122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
122 | radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); |
123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
123 | radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); |
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
124 | radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
125 | radeon_ring_write(ring, PACKET0(0x20C8, 0)); |
126 | radeon_ring_write(ring, 0); |
126 | radeon_ring_write(ring, 0); |
127 | radeon_ring_unlock_commit(rdev, ring, false); |
127 | radeon_ring_unlock_commit(rdev, ring, false); |
128 | } |
128 | } |
129 | 129 | ||
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
130 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
131 | { |
131 | { |
132 | unsigned i; |
132 | unsigned i; |
133 | uint32_t tmp; |
133 | uint32_t tmp; |
134 | 134 | ||
135 | for (i = 0; i < rdev->usec_timeout; i++) { |
135 | for (i = 0; i < rdev->usec_timeout; i++) { |
136 | /* read MC_STATUS */ |
136 | /* read MC_STATUS */ |
137 | tmp = RREG32_MC(MC_STATUS); |
137 | tmp = RREG32_MC(MC_STATUS); |
138 | if (tmp & MC_STATUS_IDLE) { |
138 | if (tmp & MC_STATUS_IDLE) { |
139 | return 0; |
139 | return 0; |
140 | } |
140 | } |
141 | DRM_UDELAY(1); |
141 | DRM_UDELAY(1); |
142 | } |
142 | } |
143 | return -1; |
143 | return -1; |
144 | } |
144 | } |
145 | 145 | ||
146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
146 | void rv515_vga_render_disable(struct radeon_device *rdev) |
147 | { |
147 | { |
148 | WREG32(R_000300_VGA_RENDER_CONTROL, |
148 | WREG32(R_000300_VGA_RENDER_CONTROL, |
149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
149 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
150 | } |
150 | } |
151 | 151 | ||
152 | static void rv515_gpu_init(struct radeon_device *rdev) |
152 | static void rv515_gpu_init(struct radeon_device *rdev) |
153 | { |
153 | { |
154 | unsigned pipe_select_current, gb_pipe_select, tmp; |
154 | unsigned pipe_select_current, gb_pipe_select, tmp; |
155 | 155 | ||
156 | if (r100_gui_wait_for_idle(rdev)) { |
156 | if (r100_gui_wait_for_idle(rdev)) { |
157 | printk(KERN_WARNING "Failed to wait GUI idle while " |
157 | printk(KERN_WARNING "Failed to wait GUI idle while " |
158 | "resetting GPU. Bad things might happen.\n"); |
158 | "resetting GPU. Bad things might happen.\n"); |
159 | } |
159 | } |
160 | rv515_vga_render_disable(rdev); |
160 | rv515_vga_render_disable(rdev); |
161 | r420_pipes_init(rdev); |
161 | r420_pipes_init(rdev); |
162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
162 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); |
163 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
163 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
164 | pipe_select_current = (tmp >> 2) & 3; |
164 | pipe_select_current = (tmp >> 2) & 3; |
165 | tmp = (1 << pipe_select_current) | |
165 | tmp = (1 << pipe_select_current) | |
166 | (((gb_pipe_select >> 8) & 0xF) << 4); |
166 | (((gb_pipe_select >> 8) & 0xF) << 4); |
167 | WREG32_PLL(0x000D, tmp); |
167 | WREG32_PLL(0x000D, tmp); |
168 | if (r100_gui_wait_for_idle(rdev)) { |
168 | if (r100_gui_wait_for_idle(rdev)) { |
169 | printk(KERN_WARNING "Failed to wait GUI idle while " |
169 | printk(KERN_WARNING "Failed to wait GUI idle while " |
170 | "resetting GPU. Bad things might happen.\n"); |
170 | "resetting GPU. Bad things might happen.\n"); |
171 | } |
171 | } |
172 | if (rv515_mc_wait_for_idle(rdev)) { |
172 | if (rv515_mc_wait_for_idle(rdev)) { |
173 | printk(KERN_WARNING "Failed to wait MC idle while " |
173 | printk(KERN_WARNING "Failed to wait MC idle while " |
174 | "programming pipes. Bad things might happen.\n"); |
174 | "programming pipes. Bad things might happen.\n"); |
175 | } |
175 | } |
176 | } |
176 | } |
177 | 177 | ||
178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
178 | static void rv515_vram_get_type(struct radeon_device *rdev) |
179 | { |
179 | { |
180 | uint32_t tmp; |
180 | uint32_t tmp; |
181 | 181 | ||
182 | rdev->mc.vram_width = 128; |
182 | rdev->mc.vram_width = 128; |
183 | rdev->mc.vram_is_ddr = true; |
183 | rdev->mc.vram_is_ddr = true; |
184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
184 | tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; |
185 | switch (tmp) { |
185 | switch (tmp) { |
186 | case 0: |
186 | case 0: |
187 | rdev->mc.vram_width = 64; |
187 | rdev->mc.vram_width = 64; |
188 | break; |
188 | break; |
189 | case 1: |
189 | case 1: |
190 | rdev->mc.vram_width = 128; |
190 | rdev->mc.vram_width = 128; |
191 | break; |
191 | break; |
192 | default: |
192 | default: |
193 | rdev->mc.vram_width = 128; |
193 | rdev->mc.vram_width = 128; |
194 | break; |
194 | break; |
195 | } |
195 | } |
196 | } |
196 | } |
197 | 197 | ||
198 | static void rv515_mc_init(struct radeon_device *rdev) |
198 | static void rv515_mc_init(struct radeon_device *rdev) |
199 | { |
199 | { |
200 | 200 | ||
201 | rv515_vram_get_type(rdev); |
201 | rv515_vram_get_type(rdev); |
202 | r100_vram_init_sizes(rdev); |
202 | r100_vram_init_sizes(rdev); |
203 | radeon_vram_location(rdev, &rdev->mc, 0); |
203 | radeon_vram_location(rdev, &rdev->mc, 0); |
204 | rdev->mc.gtt_base_align = 0; |
204 | rdev->mc.gtt_base_align = 0; |
205 | if (!(rdev->flags & RADEON_IS_AGP)) |
205 | if (!(rdev->flags & RADEON_IS_AGP)) |
206 | radeon_gtt_location(rdev, &rdev->mc); |
206 | radeon_gtt_location(rdev, &rdev->mc); |
207 | radeon_update_bandwidth_info(rdev); |
207 | radeon_update_bandwidth_info(rdev); |
208 | } |
208 | } |
209 | 209 | ||
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
210 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
211 | { |
211 | { |
212 | unsigned long flags; |
212 | unsigned long flags; |
213 | uint32_t r; |
213 | uint32_t r; |
214 | 214 | ||
215 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
215 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
216 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
216 | WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
217 | r = RREG32(MC_IND_DATA); |
217 | r = RREG32(MC_IND_DATA); |
218 | WREG32(MC_IND_INDEX, 0); |
218 | WREG32(MC_IND_INDEX, 0); |
219 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
219 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
220 | 220 | ||
221 | return r; |
221 | return r; |
222 | } |
222 | } |
223 | 223 | ||
224 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
224 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
225 | { |
225 | { |
226 | unsigned long flags; |
226 | unsigned long flags; |
227 | 227 | ||
228 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
228 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
229 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
229 | WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
230 | WREG32(MC_IND_DATA, (v)); |
230 | WREG32(MC_IND_DATA, (v)); |
231 | WREG32(MC_IND_INDEX, 0); |
231 | WREG32(MC_IND_INDEX, 0); |
232 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
232 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
233 | } |
233 | } |
234 | 234 | ||
235 | #if defined(CONFIG_DEBUG_FS) |
235 | #if defined(CONFIG_DEBUG_FS) |
236 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
236 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
237 | { |
237 | { |
238 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
238 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
239 | struct drm_device *dev = node->minor->dev; |
239 | struct drm_device *dev = node->minor->dev; |
240 | struct radeon_device *rdev = dev->dev_private; |
240 | struct radeon_device *rdev = dev->dev_private; |
241 | uint32_t tmp; |
241 | uint32_t tmp; |
242 | 242 | ||
243 | tmp = RREG32(GB_PIPE_SELECT); |
243 | tmp = RREG32(GB_PIPE_SELECT); |
244 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
244 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
245 | tmp = RREG32(SU_REG_DEST); |
245 | tmp = RREG32(SU_REG_DEST); |
246 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
246 | seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
247 | tmp = RREG32(GB_TILE_CONFIG); |
247 | tmp = RREG32(GB_TILE_CONFIG); |
248 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
248 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
249 | tmp = RREG32(DST_PIPE_CONFIG); |
249 | tmp = RREG32(DST_PIPE_CONFIG); |
250 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
250 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
251 | return 0; |
251 | return 0; |
252 | } |
252 | } |
253 | 253 | ||
254 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
254 | static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
255 | { |
255 | { |
256 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
256 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
257 | struct drm_device *dev = node->minor->dev; |
257 | struct drm_device *dev = node->minor->dev; |
258 | struct radeon_device *rdev = dev->dev_private; |
258 | struct radeon_device *rdev = dev->dev_private; |
259 | uint32_t tmp; |
259 | uint32_t tmp; |
260 | 260 | ||
261 | tmp = RREG32(0x2140); |
261 | tmp = RREG32(0x2140); |
262 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
262 | seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
263 | radeon_asic_reset(rdev); |
263 | radeon_asic_reset(rdev); |
264 | tmp = RREG32(0x425C); |
264 | tmp = RREG32(0x425C); |
265 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
265 | seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
266 | return 0; |
266 | return 0; |
267 | } |
267 | } |
268 | 268 | ||
269 | static struct drm_info_list rv515_pipes_info_list[] = { |
269 | static struct drm_info_list rv515_pipes_info_list[] = { |
270 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
270 | {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
271 | }; |
271 | }; |
272 | 272 | ||
273 | static struct drm_info_list rv515_ga_info_list[] = { |
273 | static struct drm_info_list rv515_ga_info_list[] = { |
274 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
274 | {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
275 | }; |
275 | }; |
276 | #endif |
276 | #endif |
277 | 277 | ||
278 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
278 | static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
279 | { |
279 | { |
280 | #if defined(CONFIG_DEBUG_FS) |
280 | #if defined(CONFIG_DEBUG_FS) |
281 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
281 | return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
282 | #else |
282 | #else |
283 | return 0; |
283 | return 0; |
284 | #endif |
284 | #endif |
285 | } |
285 | } |
286 | 286 | ||
287 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
287 | static int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
288 | { |
288 | { |
289 | #if defined(CONFIG_DEBUG_FS) |
289 | #if defined(CONFIG_DEBUG_FS) |
290 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
290 | return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
291 | #else |
291 | #else |
292 | return 0; |
292 | return 0; |
293 | #endif |
293 | #endif |
294 | } |
294 | } |
295 | 295 | ||
296 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
296 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
297 | { |
297 | { |
298 | u32 crtc_enabled, tmp, frame_count, blackout; |
298 | u32 crtc_enabled, tmp, frame_count, blackout; |
299 | int i, j; |
299 | int i, j; |
300 | 300 | ||
301 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
301 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
302 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
302 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
303 | 303 | ||
304 | /* disable VGA render */ |
304 | /* disable VGA render */ |
305 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
305 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
306 | /* blank the display controllers */ |
306 | /* blank the display controllers */ |
307 | for (i = 0; i < rdev->num_crtc; i++) { |
307 | for (i = 0; i < rdev->num_crtc; i++) { |
308 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; |
308 | crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; |
309 | if (crtc_enabled) { |
309 | if (crtc_enabled) { |
310 | save->crtc_enabled[i] = true; |
310 | save->crtc_enabled[i] = true; |
311 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
311 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
312 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
312 | if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
313 | radeon_wait_for_vblank(rdev, i); |
313 | radeon_wait_for_vblank(rdev, i); |
314 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
314 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
315 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
315 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
316 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
316 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
317 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
317 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
318 | } |
318 | } |
319 | /* wait for the next frame */ |
319 | /* wait for the next frame */ |
320 | frame_count = radeon_get_vblank_counter(rdev, i); |
320 | frame_count = radeon_get_vblank_counter(rdev, i); |
321 | for (j = 0; j < rdev->usec_timeout; j++) { |
321 | for (j = 0; j < rdev->usec_timeout; j++) { |
322 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
322 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
323 | break; |
323 | break; |
324 | udelay(1); |
324 | udelay(1); |
325 | } |
325 | } |
326 | 326 | ||
327 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
327 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
328 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
328 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
329 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
329 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
330 | tmp &= ~AVIVO_CRTC_EN; |
330 | tmp &= ~AVIVO_CRTC_EN; |
331 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
331 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
332 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
332 | WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
333 | save->crtc_enabled[i] = false; |
333 | save->crtc_enabled[i] = false; |
334 | /* ***** */ |
334 | /* ***** */ |
335 | } else { |
335 | } else { |
336 | save->crtc_enabled[i] = false; |
336 | save->crtc_enabled[i] = false; |
337 | } |
337 | } |
338 | } |
338 | } |
339 | 339 | ||
340 | radeon_mc_wait_for_idle(rdev); |
340 | radeon_mc_wait_for_idle(rdev); |
341 | 341 | ||
342 | if (rdev->family >= CHIP_R600) { |
342 | if (rdev->family >= CHIP_R600) { |
343 | if (rdev->family >= CHIP_RV770) |
343 | if (rdev->family >= CHIP_RV770) |
344 | blackout = RREG32(R700_MC_CITF_CNTL); |
344 | blackout = RREG32(R700_MC_CITF_CNTL); |
345 | else |
345 | else |
346 | blackout = RREG32(R600_CITF_CNTL); |
346 | blackout = RREG32(R600_CITF_CNTL); |
347 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { |
347 | if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) { |
348 | /* Block CPU access */ |
348 | /* Block CPU access */ |
349 | WREG32(R600_BIF_FB_EN, 0); |
349 | WREG32(R600_BIF_FB_EN, 0); |
350 | /* blackout the MC */ |
350 | /* blackout the MC */ |
351 | blackout |= R600_BLACKOUT_MASK; |
351 | blackout |= R600_BLACKOUT_MASK; |
352 | if (rdev->family >= CHIP_RV770) |
352 | if (rdev->family >= CHIP_RV770) |
353 | WREG32(R700_MC_CITF_CNTL, blackout); |
353 | WREG32(R700_MC_CITF_CNTL, blackout); |
354 | else |
354 | else |
355 | WREG32(R600_CITF_CNTL, blackout); |
355 | WREG32(R600_CITF_CNTL, blackout); |
356 | } |
356 | } |
357 | } |
357 | } |
358 | /* wait for the MC to settle */ |
358 | /* wait for the MC to settle */ |
359 | udelay(100); |
359 | udelay(100); |
360 | 360 | ||
361 | /* lock double buffered regs */ |
361 | /* lock double buffered regs */ |
362 | for (i = 0; i < rdev->num_crtc; i++) { |
362 | for (i = 0; i < rdev->num_crtc; i++) { |
363 | if (save->crtc_enabled[i]) { |
363 | if (save->crtc_enabled[i]) { |
364 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
364 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
365 | if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { |
365 | if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { |
366 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
366 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
367 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
367 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
368 | } |
368 | } |
369 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
369 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
370 | if (!(tmp & 1)) { |
370 | if (!(tmp & 1)) { |
371 | tmp |= 1; |
371 | tmp |= 1; |
372 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
372 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
373 | } |
373 | } |
374 | } |
374 | } |
375 | } |
375 | } |
376 | } |
376 | } |
377 | 377 | ||
378 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
378 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
379 | { |
379 | { |
380 | u32 tmp, frame_count; |
380 | u32 tmp, frame_count; |
381 | int i, j; |
381 | int i, j; |
382 | 382 | ||
383 | /* update crtc base addresses */ |
383 | /* update crtc base addresses */ |
384 | for (i = 0; i < rdev->num_crtc; i++) { |
384 | for (i = 0; i < rdev->num_crtc; i++) { |
385 | if (rdev->family >= CHIP_RV770) { |
385 | if (rdev->family >= CHIP_RV770) { |
386 | if (i == 0) { |
386 | if (i == 0) { |
387 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
387 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
388 | upper_32_bits(rdev->mc.vram_start)); |
388 | upper_32_bits(rdev->mc.vram_start)); |
389 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
389 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
390 | upper_32_bits(rdev->mc.vram_start)); |
390 | upper_32_bits(rdev->mc.vram_start)); |
391 | } else { |
391 | } else { |
392 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
392 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
393 | upper_32_bits(rdev->mc.vram_start)); |
393 | upper_32_bits(rdev->mc.vram_start)); |
394 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
394 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
395 | upper_32_bits(rdev->mc.vram_start)); |
395 | upper_32_bits(rdev->mc.vram_start)); |
396 | } |
396 | } |
397 | } |
397 | } |
398 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
398 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
399 | (u32)rdev->mc.vram_start); |
399 | (u32)rdev->mc.vram_start); |
400 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
400 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
401 | (u32)rdev->mc.vram_start); |
401 | (u32)rdev->mc.vram_start); |
402 | } |
402 | } |
403 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
403 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
404 | 404 | ||
405 | /* unlock regs and wait for update */ |
405 | /* unlock regs and wait for update */ |
406 | for (i = 0; i < rdev->num_crtc; i++) { |
406 | for (i = 0; i < rdev->num_crtc; i++) { |
407 | if (save->crtc_enabled[i]) { |
407 | if (save->crtc_enabled[i]) { |
408 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
408 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
409 | if ((tmp & 0x7) != 3) { |
409 | if ((tmp & 0x7) != 3) { |
410 | tmp &= ~0x7; |
410 | tmp &= ~0x7; |
411 | tmp |= 0x3; |
411 | tmp |= 0x3; |
412 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
412 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
413 | } |
413 | } |
414 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
414 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
415 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
415 | if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
416 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
416 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
417 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
417 | WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
418 | } |
418 | } |
419 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
419 | tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
420 | if (tmp & 1) { |
420 | if (tmp & 1) { |
421 | tmp &= ~1; |
421 | tmp &= ~1; |
422 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
422 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
423 | } |
423 | } |
424 | for (j = 0; j < rdev->usec_timeout; j++) { |
424 | for (j = 0; j < rdev->usec_timeout; j++) { |
425 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
425 | tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
426 | if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) |
426 | if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) |
427 | break; |
427 | break; |
428 | udelay(1); |
428 | udelay(1); |
429 | } |
429 | } |
430 | } |
430 | } |
431 | } |
431 | } |
432 | 432 | ||
433 | if (rdev->family >= CHIP_R600) { |
433 | if (rdev->family >= CHIP_R600) { |
434 | /* unblackout the MC */ |
434 | /* unblackout the MC */ |
435 | if (rdev->family >= CHIP_RV770) |
435 | if (rdev->family >= CHIP_RV770) |
436 | tmp = RREG32(R700_MC_CITF_CNTL); |
436 | tmp = RREG32(R700_MC_CITF_CNTL); |
437 | else |
437 | else |
438 | tmp = RREG32(R600_CITF_CNTL); |
438 | tmp = RREG32(R600_CITF_CNTL); |
439 | tmp &= ~R600_BLACKOUT_MASK; |
439 | tmp &= ~R600_BLACKOUT_MASK; |
440 | if (rdev->family >= CHIP_RV770) |
440 | if (rdev->family >= CHIP_RV770) |
441 | WREG32(R700_MC_CITF_CNTL, tmp); |
441 | WREG32(R700_MC_CITF_CNTL, tmp); |
442 | else |
442 | else |
443 | WREG32(R600_CITF_CNTL, tmp); |
443 | WREG32(R600_CITF_CNTL, tmp); |
444 | /* allow CPU access */ |
444 | /* allow CPU access */ |
445 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); |
445 | WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN); |
446 | } |
446 | } |
447 | 447 | ||
448 | for (i = 0; i < rdev->num_crtc; i++) { |
448 | for (i = 0; i < rdev->num_crtc; i++) { |
449 | if (save->crtc_enabled[i]) { |
449 | if (save->crtc_enabled[i]) { |
450 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
450 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
451 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
451 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
452 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
452 | WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
453 | /* wait for the next frame */ |
453 | /* wait for the next frame */ |
454 | frame_count = radeon_get_vblank_counter(rdev, i); |
454 | frame_count = radeon_get_vblank_counter(rdev, i); |
455 | for (j = 0; j < rdev->usec_timeout; j++) { |
455 | for (j = 0; j < rdev->usec_timeout; j++) { |
456 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
456 | if (radeon_get_vblank_counter(rdev, i) != frame_count) |
457 | break; |
457 | break; |
458 | udelay(1); |
458 | udelay(1); |
459 | } |
459 | } |
460 | } |
460 | } |
461 | } |
461 | } |
462 | /* Unlock vga access */ |
462 | /* Unlock vga access */ |
463 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
463 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
464 | mdelay(1); |
464 | mdelay(1); |
465 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
465 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
466 | } |
466 | } |
467 | 467 | ||
468 | static void rv515_mc_program(struct radeon_device *rdev) |
468 | static void rv515_mc_program(struct radeon_device *rdev) |
469 | { |
469 | { |
470 | struct rv515_mc_save save; |
470 | struct rv515_mc_save save; |
471 | 471 | ||
472 | /* Stops all mc clients */ |
472 | /* Stops all mc clients */ |
473 | rv515_mc_stop(rdev, &save); |
473 | rv515_mc_stop(rdev, &save); |
474 | 474 | ||
475 | /* Wait for mc idle */ |
475 | /* Wait for mc idle */ |
476 | if (rv515_mc_wait_for_idle(rdev)) |
476 | if (rv515_mc_wait_for_idle(rdev)) |
477 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
477 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
478 | /* Write VRAM size in case we are limiting it */ |
478 | /* Write VRAM size in case we are limiting it */ |
479 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
479 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
480 | /* Program MC, should be a 32bits limited address space */ |
480 | /* Program MC, should be a 32bits limited address space */ |
481 | WREG32_MC(R_000001_MC_FB_LOCATION, |
481 | WREG32_MC(R_000001_MC_FB_LOCATION, |
482 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
482 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
483 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
483 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
484 | WREG32(R_000134_HDP_FB_LOCATION, |
484 | WREG32(R_000134_HDP_FB_LOCATION, |
485 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
485 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
486 | if (rdev->flags & RADEON_IS_AGP) { |
486 | if (rdev->flags & RADEON_IS_AGP) { |
487 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
487 | WREG32_MC(R_000002_MC_AGP_LOCATION, |
488 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
488 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
489 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
489 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
490 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
490 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
491 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
491 | WREG32_MC(R_000004_MC_AGP_BASE_2, |
492 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
492 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
493 | } else { |
493 | } else { |
494 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
494 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
495 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
495 | WREG32_MC(R_000003_MC_AGP_BASE, 0); |
496 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
496 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
497 | } |
497 | } |
498 | 498 | ||
499 | rv515_mc_resume(rdev, &save); |
499 | rv515_mc_resume(rdev, &save); |
500 | } |
500 | } |
501 | 501 | ||
502 | void rv515_clock_startup(struct radeon_device *rdev) |
502 | void rv515_clock_startup(struct radeon_device *rdev) |
503 | { |
503 | { |
504 | if (radeon_dynclks != -1 && radeon_dynclks) |
504 | if (radeon_dynclks != -1 && radeon_dynclks) |
505 | radeon_atom_set_clock_gating(rdev, 1); |
505 | radeon_atom_set_clock_gating(rdev, 1); |
506 | /* We need to force on some of the block */ |
506 | /* We need to force on some of the block */ |
507 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
507 | WREG32_PLL(R_00000F_CP_DYN_CNTL, |
508 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
508 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
509 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
509 | WREG32_PLL(R_000011_E2_DYN_CNTL, |
510 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
510 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
511 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
511 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
512 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
512 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
513 | } |
513 | } |
514 | 514 | ||
515 | static int rv515_startup(struct radeon_device *rdev) |
515 | static int rv515_startup(struct radeon_device *rdev) |
516 | { |
516 | { |
517 | int r; |
517 | int r; |
518 | 518 | ||
519 | rv515_mc_program(rdev); |
519 | rv515_mc_program(rdev); |
520 | /* Resume clock */ |
520 | /* Resume clock */ |
521 | rv515_clock_startup(rdev); |
521 | rv515_clock_startup(rdev); |
522 | /* Initialize GPU configuration (# pipes, ...) */ |
522 | /* Initialize GPU configuration (# pipes, ...) */ |
523 | rv515_gpu_init(rdev); |
523 | rv515_gpu_init(rdev); |
524 | /* Initialize GART (initialize after TTM so we can allocate |
524 | /* Initialize GART (initialize after TTM so we can allocate |
525 | * memory through TTM but finalize after TTM) */ |
525 | * memory through TTM but finalize after TTM) */ |
526 | if (rdev->flags & RADEON_IS_PCIE) { |
526 | if (rdev->flags & RADEON_IS_PCIE) { |
527 | r = rv370_pcie_gart_enable(rdev); |
527 | r = rv370_pcie_gart_enable(rdev); |
528 | if (r) |
528 | if (r) |
529 | return r; |
529 | return r; |
530 | } |
530 | } |
531 | 531 | ||
532 | /* allocate wb buffer */ |
532 | /* allocate wb buffer */ |
533 | r = radeon_wb_init(rdev); |
533 | r = radeon_wb_init(rdev); |
534 | if (r) |
534 | if (r) |
535 | return r; |
535 | return r; |
536 | 536 | ||
537 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
537 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
538 | if (r) { |
538 | if (r) { |
539 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
539 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
540 | return r; |
540 | return r; |
541 | } |
541 | } |
542 | 542 | ||
543 | /* Enable IRQ */ |
543 | /* Enable IRQ */ |
544 | if (!rdev->irq.installed) { |
544 | if (!rdev->irq.installed) { |
545 | r = radeon_irq_kms_init(rdev); |
545 | r = radeon_irq_kms_init(rdev); |
546 | if (r) |
546 | if (r) |
547 | return r; |
547 | return r; |
548 | } |
548 | } |
549 | 549 | ||
550 | rs600_irq_set(rdev); |
550 | rs600_irq_set(rdev); |
551 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
551 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
552 | /* 1M ring buffer */ |
552 | /* 1M ring buffer */ |
553 | r = r100_cp_init(rdev, 1024 * 1024); |
553 | r = r100_cp_init(rdev, 1024 * 1024); |
554 | if (r) { |
554 | if (r) { |
555 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
555 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
556 | return r; |
556 | return r; |
557 | } |
557 | } |
558 | 558 | ||
559 | r = radeon_ib_pool_init(rdev); |
559 | r = radeon_ib_pool_init(rdev); |
560 | if (r) { |
560 | if (r) { |
561 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
561 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
562 | return r; |
562 | return r; |
563 | } |
563 | } |
564 | 564 | ||
565 | return 0; |
565 | return 0; |
566 | } |
566 | } |
567 | 567 | ||
568 | 568 | ||
569 | void rv515_set_safe_registers(struct radeon_device *rdev) |
569 | void rv515_set_safe_registers(struct radeon_device *rdev) |
570 | { |
570 | { |
571 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
571 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
572 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
572 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
573 | } |
573 | } |
- | 574 | ||
- | 575 | void rv515_fini(struct radeon_device *rdev) |
|
- | 576 | { |
|
- | 577 | radeon_pm_fini(rdev); |
|
- | 578 | r100_cp_fini(rdev); |
|
- | 579 | radeon_wb_fini(rdev); |
|
- | 580 | radeon_ib_pool_fini(rdev); |
|
- | 581 | radeon_gem_fini(rdev); |
|
- | 582 | rv370_pcie_gart_fini(rdev); |
|
- | 583 | radeon_agp_fini(rdev); |
|
- | 584 | radeon_irq_kms_fini(rdev); |
|
- | 585 | radeon_fence_driver_fini(rdev); |
|
- | 586 | radeon_bo_fini(rdev); |
|
- | 587 | radeon_atombios_fini(rdev); |
|
- | 588 | kfree(rdev->bios); |
|
- | 589 | rdev->bios = NULL; |
|
- | 590 | } |
|
574 | 591 | ||
575 | int rv515_init(struct radeon_device *rdev) |
592 | int rv515_init(struct radeon_device *rdev) |
576 | { |
593 | { |
577 | int r; |
594 | int r; |
578 | 595 | ||
579 | /* Initialize scratch registers */ |
596 | /* Initialize scratch registers */ |
580 | radeon_scratch_init(rdev); |
597 | radeon_scratch_init(rdev); |
581 | /* Initialize surface registers */ |
598 | /* Initialize surface registers */ |
582 | radeon_surface_init(rdev); |
599 | radeon_surface_init(rdev); |
583 | /* TODO: disable VGA need to use VGA request */ |
600 | /* TODO: disable VGA need to use VGA request */ |
584 | /* restore some register to sane defaults */ |
601 | /* restore some register to sane defaults */ |
585 | r100_restore_sanity(rdev); |
602 | r100_restore_sanity(rdev); |
586 | /* BIOS*/ |
603 | /* BIOS*/ |
587 | if (!radeon_get_bios(rdev)) { |
604 | if (!radeon_get_bios(rdev)) { |
588 | if (ASIC_IS_AVIVO(rdev)) |
605 | if (ASIC_IS_AVIVO(rdev)) |
589 | return -EINVAL; |
606 | return -EINVAL; |
590 | } |
607 | } |
591 | if (rdev->is_atom_bios) { |
608 | if (rdev->is_atom_bios) { |
592 | r = radeon_atombios_init(rdev); |
609 | r = radeon_atombios_init(rdev); |
593 | if (r) |
610 | if (r) |
594 | return r; |
611 | return r; |
595 | } else { |
612 | } else { |
596 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
613 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
597 | return -EINVAL; |
614 | return -EINVAL; |
598 | } |
615 | } |
599 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
616 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
600 | if (radeon_asic_reset(rdev)) { |
617 | if (radeon_asic_reset(rdev)) { |
601 | dev_warn(rdev->dev, |
618 | dev_warn(rdev->dev, |
602 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
619 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
603 | RREG32(R_000E40_RBBM_STATUS), |
620 | RREG32(R_000E40_RBBM_STATUS), |
604 | RREG32(R_0007C0_CP_STAT)); |
621 | RREG32(R_0007C0_CP_STAT)); |
605 | } |
622 | } |
606 | /* check if cards are posted or not */ |
623 | /* check if cards are posted or not */ |
607 | if (radeon_boot_test_post_card(rdev) == false) |
624 | if (radeon_boot_test_post_card(rdev) == false) |
608 | return -EINVAL; |
625 | return -EINVAL; |
609 | /* Initialize clocks */ |
626 | /* Initialize clocks */ |
610 | radeon_get_clock_info(rdev->ddev); |
627 | radeon_get_clock_info(rdev->ddev); |
611 | /* initialize AGP */ |
628 | /* initialize AGP */ |
612 | if (rdev->flags & RADEON_IS_AGP) { |
629 | if (rdev->flags & RADEON_IS_AGP) { |
613 | r = radeon_agp_init(rdev); |
630 | r = radeon_agp_init(rdev); |
614 | if (r) { |
631 | if (r) { |
615 | radeon_agp_disable(rdev); |
632 | radeon_agp_disable(rdev); |
616 | } |
633 | } |
617 | } |
634 | } |
618 | /* initialize memory controller */ |
635 | /* initialize memory controller */ |
619 | rv515_mc_init(rdev); |
636 | rv515_mc_init(rdev); |
620 | rv515_debugfs(rdev); |
637 | rv515_debugfs(rdev); |
621 | /* Fence driver */ |
638 | /* Fence driver */ |
622 | r = radeon_fence_driver_init(rdev); |
639 | r = radeon_fence_driver_init(rdev); |
623 | if (r) |
640 | if (r) |
624 | return r; |
641 | return r; |
625 | /* Memory manager */ |
642 | /* Memory manager */ |
626 | r = radeon_bo_init(rdev); |
643 | r = radeon_bo_init(rdev); |
627 | if (r) |
644 | if (r) |
628 | return r; |
645 | return r; |
629 | r = rv370_pcie_gart_init(rdev); |
646 | r = rv370_pcie_gart_init(rdev); |
630 | if (r) |
647 | if (r) |
631 | return r; |
648 | return r; |
632 | rv515_set_safe_registers(rdev); |
649 | rv515_set_safe_registers(rdev); |
633 | 650 | ||
634 | /* Initialize power management */ |
651 | /* Initialize power management */ |
635 | radeon_pm_init(rdev); |
652 | radeon_pm_init(rdev); |
636 | 653 | ||
637 | rdev->accel_working = true; |
654 | rdev->accel_working = true; |
638 | r = rv515_startup(rdev); |
655 | r = rv515_startup(rdev); |
639 | if (r) { |
656 | if (r) { |
640 | /* Somethings want wront with the accel init stop accel */ |
657 | /* Somethings want wront with the accel init stop accel */ |
641 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
658 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
- | 659 | r100_cp_fini(rdev); |
|
- | 660 | radeon_wb_fini(rdev); |
|
- | 661 | radeon_ib_pool_fini(rdev); |
|
- | 662 | radeon_irq_kms_fini(rdev); |
|
- | 663 | rv370_pcie_gart_fini(rdev); |
|
- | 664 | radeon_agp_fini(rdev); |
|
642 | rdev->accel_working = false; |
665 | rdev->accel_working = false; |
643 | } |
666 | } |
644 | return 0; |
667 | return 0; |
645 | } |
668 | } |
646 | 669 | ||
647 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
670 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) |
648 | { |
671 | { |
649 | int index_reg = 0x6578 + crtc->crtc_offset; |
672 | int index_reg = 0x6578 + crtc->crtc_offset; |
650 | int data_reg = 0x657c + crtc->crtc_offset; |
673 | int data_reg = 0x657c + crtc->crtc_offset; |
651 | 674 | ||
652 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
675 | WREG32(0x659C + crtc->crtc_offset, 0x0); |
653 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
676 | WREG32(0x6594 + crtc->crtc_offset, 0x705); |
654 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
677 | WREG32(0x65A4 + crtc->crtc_offset, 0x10001); |
655 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
678 | WREG32(0x65D8 + crtc->crtc_offset, 0x0); |
656 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
679 | WREG32(0x65B0 + crtc->crtc_offset, 0x0); |
657 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
680 | WREG32(0x65C0 + crtc->crtc_offset, 0x0); |
658 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
681 | WREG32(0x65D4 + crtc->crtc_offset, 0x0); |
659 | WREG32(index_reg, 0x0); |
682 | WREG32(index_reg, 0x0); |
660 | WREG32(data_reg, 0x841880A8); |
683 | WREG32(data_reg, 0x841880A8); |
661 | WREG32(index_reg, 0x1); |
684 | WREG32(index_reg, 0x1); |
662 | WREG32(data_reg, 0x84208680); |
685 | WREG32(data_reg, 0x84208680); |
663 | WREG32(index_reg, 0x2); |
686 | WREG32(index_reg, 0x2); |
664 | WREG32(data_reg, 0xBFF880B0); |
687 | WREG32(data_reg, 0xBFF880B0); |
665 | WREG32(index_reg, 0x100); |
688 | WREG32(index_reg, 0x100); |
666 | WREG32(data_reg, 0x83D88088); |
689 | WREG32(data_reg, 0x83D88088); |
667 | WREG32(index_reg, 0x101); |
690 | WREG32(index_reg, 0x101); |
668 | WREG32(data_reg, 0x84608680); |
691 | WREG32(data_reg, 0x84608680); |
669 | WREG32(index_reg, 0x102); |
692 | WREG32(index_reg, 0x102); |
670 | WREG32(data_reg, 0xBFF080D0); |
693 | WREG32(data_reg, 0xBFF080D0); |
671 | WREG32(index_reg, 0x200); |
694 | WREG32(index_reg, 0x200); |
672 | WREG32(data_reg, 0x83988068); |
695 | WREG32(data_reg, 0x83988068); |
673 | WREG32(index_reg, 0x201); |
696 | WREG32(index_reg, 0x201); |
674 | WREG32(data_reg, 0x84A08680); |
697 | WREG32(data_reg, 0x84A08680); |
675 | WREG32(index_reg, 0x202); |
698 | WREG32(index_reg, 0x202); |
676 | WREG32(data_reg, 0xBFF080F8); |
699 | WREG32(data_reg, 0xBFF080F8); |
677 | WREG32(index_reg, 0x300); |
700 | WREG32(index_reg, 0x300); |
678 | WREG32(data_reg, 0x83588058); |
701 | WREG32(data_reg, 0x83588058); |
679 | WREG32(index_reg, 0x301); |
702 | WREG32(index_reg, 0x301); |
680 | WREG32(data_reg, 0x84E08660); |
703 | WREG32(data_reg, 0x84E08660); |
681 | WREG32(index_reg, 0x302); |
704 | WREG32(index_reg, 0x302); |
682 | WREG32(data_reg, 0xBFF88120); |
705 | WREG32(data_reg, 0xBFF88120); |
683 | WREG32(index_reg, 0x400); |
706 | WREG32(index_reg, 0x400); |
684 | WREG32(data_reg, 0x83188040); |
707 | WREG32(data_reg, 0x83188040); |
685 | WREG32(index_reg, 0x401); |
708 | WREG32(index_reg, 0x401); |
686 | WREG32(data_reg, 0x85008660); |
709 | WREG32(data_reg, 0x85008660); |
687 | WREG32(index_reg, 0x402); |
710 | WREG32(index_reg, 0x402); |
688 | WREG32(data_reg, 0xBFF88150); |
711 | WREG32(data_reg, 0xBFF88150); |
689 | WREG32(index_reg, 0x500); |
712 | WREG32(index_reg, 0x500); |
690 | WREG32(data_reg, 0x82D88030); |
713 | WREG32(data_reg, 0x82D88030); |
691 | WREG32(index_reg, 0x501); |
714 | WREG32(index_reg, 0x501); |
692 | WREG32(data_reg, 0x85408640); |
715 | WREG32(data_reg, 0x85408640); |
693 | WREG32(index_reg, 0x502); |
716 | WREG32(index_reg, 0x502); |
694 | WREG32(data_reg, 0xBFF88180); |
717 | WREG32(data_reg, 0xBFF88180); |
695 | WREG32(index_reg, 0x600); |
718 | WREG32(index_reg, 0x600); |
696 | WREG32(data_reg, 0x82A08018); |
719 | WREG32(data_reg, 0x82A08018); |
697 | WREG32(index_reg, 0x601); |
720 | WREG32(index_reg, 0x601); |
698 | WREG32(data_reg, 0x85808620); |
721 | WREG32(data_reg, 0x85808620); |
699 | WREG32(index_reg, 0x602); |
722 | WREG32(index_reg, 0x602); |
700 | WREG32(data_reg, 0xBFF081B8); |
723 | WREG32(data_reg, 0xBFF081B8); |
701 | WREG32(index_reg, 0x700); |
724 | WREG32(index_reg, 0x700); |
702 | WREG32(data_reg, 0x82608010); |
725 | WREG32(data_reg, 0x82608010); |
703 | WREG32(index_reg, 0x701); |
726 | WREG32(index_reg, 0x701); |
704 | WREG32(data_reg, 0x85A08600); |
727 | WREG32(data_reg, 0x85A08600); |
705 | WREG32(index_reg, 0x702); |
728 | WREG32(index_reg, 0x702); |
706 | WREG32(data_reg, 0x800081F0); |
729 | WREG32(data_reg, 0x800081F0); |
707 | WREG32(index_reg, 0x800); |
730 | WREG32(index_reg, 0x800); |
708 | WREG32(data_reg, 0x8228BFF8); |
731 | WREG32(data_reg, 0x8228BFF8); |
709 | WREG32(index_reg, 0x801); |
732 | WREG32(index_reg, 0x801); |
710 | WREG32(data_reg, 0x85E085E0); |
733 | WREG32(data_reg, 0x85E085E0); |
711 | WREG32(index_reg, 0x802); |
734 | WREG32(index_reg, 0x802); |
712 | WREG32(data_reg, 0xBFF88228); |
735 | WREG32(data_reg, 0xBFF88228); |
713 | WREG32(index_reg, 0x10000); |
736 | WREG32(index_reg, 0x10000); |
714 | WREG32(data_reg, 0x82A8BF00); |
737 | WREG32(data_reg, 0x82A8BF00); |
715 | WREG32(index_reg, 0x10001); |
738 | WREG32(index_reg, 0x10001); |
716 | WREG32(data_reg, 0x82A08CC0); |
739 | WREG32(data_reg, 0x82A08CC0); |
717 | WREG32(index_reg, 0x10002); |
740 | WREG32(index_reg, 0x10002); |
718 | WREG32(data_reg, 0x8008BEF8); |
741 | WREG32(data_reg, 0x8008BEF8); |
719 | WREG32(index_reg, 0x10100); |
742 | WREG32(index_reg, 0x10100); |
720 | WREG32(data_reg, 0x81F0BF28); |
743 | WREG32(data_reg, 0x81F0BF28); |
721 | WREG32(index_reg, 0x10101); |
744 | WREG32(index_reg, 0x10101); |
722 | WREG32(data_reg, 0x83608CA0); |
745 | WREG32(data_reg, 0x83608CA0); |
723 | WREG32(index_reg, 0x10102); |
746 | WREG32(index_reg, 0x10102); |
724 | WREG32(data_reg, 0x8018BED0); |
747 | WREG32(data_reg, 0x8018BED0); |
725 | WREG32(index_reg, 0x10200); |
748 | WREG32(index_reg, 0x10200); |
726 | WREG32(data_reg, 0x8148BF38); |
749 | WREG32(data_reg, 0x8148BF38); |
727 | WREG32(index_reg, 0x10201); |
750 | WREG32(index_reg, 0x10201); |
728 | WREG32(data_reg, 0x84408C80); |
751 | WREG32(data_reg, 0x84408C80); |
729 | WREG32(index_reg, 0x10202); |
752 | WREG32(index_reg, 0x10202); |
730 | WREG32(data_reg, 0x8008BEB8); |
753 | WREG32(data_reg, 0x8008BEB8); |
731 | WREG32(index_reg, 0x10300); |
754 | WREG32(index_reg, 0x10300); |
732 | WREG32(data_reg, 0x80B0BF78); |
755 | WREG32(data_reg, 0x80B0BF78); |
733 | WREG32(index_reg, 0x10301); |
756 | WREG32(index_reg, 0x10301); |
734 | WREG32(data_reg, 0x85008C20); |
757 | WREG32(data_reg, 0x85008C20); |
735 | WREG32(index_reg, 0x10302); |
758 | WREG32(index_reg, 0x10302); |
736 | WREG32(data_reg, 0x8020BEA0); |
759 | WREG32(data_reg, 0x8020BEA0); |
737 | WREG32(index_reg, 0x10400); |
760 | WREG32(index_reg, 0x10400); |
738 | WREG32(data_reg, 0x8028BF90); |
761 | WREG32(data_reg, 0x8028BF90); |
739 | WREG32(index_reg, 0x10401); |
762 | WREG32(index_reg, 0x10401); |
740 | WREG32(data_reg, 0x85E08BC0); |
763 | WREG32(data_reg, 0x85E08BC0); |
741 | WREG32(index_reg, 0x10402); |
764 | WREG32(index_reg, 0x10402); |
742 | WREG32(data_reg, 0x8018BE90); |
765 | WREG32(data_reg, 0x8018BE90); |
743 | WREG32(index_reg, 0x10500); |
766 | WREG32(index_reg, 0x10500); |
744 | WREG32(data_reg, 0xBFB8BFB0); |
767 | WREG32(data_reg, 0xBFB8BFB0); |
745 | WREG32(index_reg, 0x10501); |
768 | WREG32(index_reg, 0x10501); |
746 | WREG32(data_reg, 0x86C08B40); |
769 | WREG32(data_reg, 0x86C08B40); |
747 | WREG32(index_reg, 0x10502); |
770 | WREG32(index_reg, 0x10502); |
748 | WREG32(data_reg, 0x8010BE90); |
771 | WREG32(data_reg, 0x8010BE90); |
749 | WREG32(index_reg, 0x10600); |
772 | WREG32(index_reg, 0x10600); |
750 | WREG32(data_reg, 0xBF58BFC8); |
773 | WREG32(data_reg, 0xBF58BFC8); |
751 | WREG32(index_reg, 0x10601); |
774 | WREG32(index_reg, 0x10601); |
752 | WREG32(data_reg, 0x87A08AA0); |
775 | WREG32(data_reg, 0x87A08AA0); |
753 | WREG32(index_reg, 0x10602); |
776 | WREG32(index_reg, 0x10602); |
754 | WREG32(data_reg, 0x8010BE98); |
777 | WREG32(data_reg, 0x8010BE98); |
755 | WREG32(index_reg, 0x10700); |
778 | WREG32(index_reg, 0x10700); |
756 | WREG32(data_reg, 0xBF10BFF0); |
779 | WREG32(data_reg, 0xBF10BFF0); |
757 | WREG32(index_reg, 0x10701); |
780 | WREG32(index_reg, 0x10701); |
758 | WREG32(data_reg, 0x886089E0); |
781 | WREG32(data_reg, 0x886089E0); |
759 | WREG32(index_reg, 0x10702); |
782 | WREG32(index_reg, 0x10702); |
760 | WREG32(data_reg, 0x8018BEB0); |
783 | WREG32(data_reg, 0x8018BEB0); |
761 | WREG32(index_reg, 0x10800); |
784 | WREG32(index_reg, 0x10800); |
762 | WREG32(data_reg, 0xBED8BFE8); |
785 | WREG32(data_reg, 0xBED8BFE8); |
763 | WREG32(index_reg, 0x10801); |
786 | WREG32(index_reg, 0x10801); |
764 | WREG32(data_reg, 0x89408940); |
787 | WREG32(data_reg, 0x89408940); |
765 | WREG32(index_reg, 0x10802); |
788 | WREG32(index_reg, 0x10802); |
766 | WREG32(data_reg, 0xBFE8BED8); |
789 | WREG32(data_reg, 0xBFE8BED8); |
767 | WREG32(index_reg, 0x20000); |
790 | WREG32(index_reg, 0x20000); |
768 | WREG32(data_reg, 0x80008000); |
791 | WREG32(data_reg, 0x80008000); |
769 | WREG32(index_reg, 0x20001); |
792 | WREG32(index_reg, 0x20001); |
770 | WREG32(data_reg, 0x90008000); |
793 | WREG32(data_reg, 0x90008000); |
771 | WREG32(index_reg, 0x20002); |
794 | WREG32(index_reg, 0x20002); |
772 | WREG32(data_reg, 0x80008000); |
795 | WREG32(data_reg, 0x80008000); |
773 | WREG32(index_reg, 0x20003); |
796 | WREG32(index_reg, 0x20003); |
774 | WREG32(data_reg, 0x80008000); |
797 | WREG32(data_reg, 0x80008000); |
775 | WREG32(index_reg, 0x20100); |
798 | WREG32(index_reg, 0x20100); |
776 | WREG32(data_reg, 0x80108000); |
799 | WREG32(data_reg, 0x80108000); |
777 | WREG32(index_reg, 0x20101); |
800 | WREG32(index_reg, 0x20101); |
778 | WREG32(data_reg, 0x8FE0BF70); |
801 | WREG32(data_reg, 0x8FE0BF70); |
779 | WREG32(index_reg, 0x20102); |
802 | WREG32(index_reg, 0x20102); |
780 | WREG32(data_reg, 0xBFE880C0); |
803 | WREG32(data_reg, 0xBFE880C0); |
781 | WREG32(index_reg, 0x20103); |
804 | WREG32(index_reg, 0x20103); |
782 | WREG32(data_reg, 0x80008000); |
805 | WREG32(data_reg, 0x80008000); |
783 | WREG32(index_reg, 0x20200); |
806 | WREG32(index_reg, 0x20200); |
784 | WREG32(data_reg, 0x8018BFF8); |
807 | WREG32(data_reg, 0x8018BFF8); |
785 | WREG32(index_reg, 0x20201); |
808 | WREG32(index_reg, 0x20201); |
786 | WREG32(data_reg, 0x8F80BF08); |
809 | WREG32(data_reg, 0x8F80BF08); |
787 | WREG32(index_reg, 0x20202); |
810 | WREG32(index_reg, 0x20202); |
788 | WREG32(data_reg, 0xBFD081A0); |
811 | WREG32(data_reg, 0xBFD081A0); |
789 | WREG32(index_reg, 0x20203); |
812 | WREG32(index_reg, 0x20203); |
790 | WREG32(data_reg, 0xBFF88000); |
813 | WREG32(data_reg, 0xBFF88000); |
791 | WREG32(index_reg, 0x20300); |
814 | WREG32(index_reg, 0x20300); |
792 | WREG32(data_reg, 0x80188000); |
815 | WREG32(data_reg, 0x80188000); |
793 | WREG32(index_reg, 0x20301); |
816 | WREG32(index_reg, 0x20301); |
794 | WREG32(data_reg, 0x8EE0BEC0); |
817 | WREG32(data_reg, 0x8EE0BEC0); |
795 | WREG32(index_reg, 0x20302); |
818 | WREG32(index_reg, 0x20302); |
796 | WREG32(data_reg, 0xBFB082A0); |
819 | WREG32(data_reg, 0xBFB082A0); |
797 | WREG32(index_reg, 0x20303); |
820 | WREG32(index_reg, 0x20303); |
798 | WREG32(data_reg, 0x80008000); |
821 | WREG32(data_reg, 0x80008000); |
799 | WREG32(index_reg, 0x20400); |
822 | WREG32(index_reg, 0x20400); |
800 | WREG32(data_reg, 0x80188000); |
823 | WREG32(data_reg, 0x80188000); |
801 | WREG32(index_reg, 0x20401); |
824 | WREG32(index_reg, 0x20401); |
802 | WREG32(data_reg, 0x8E00BEA0); |
825 | WREG32(data_reg, 0x8E00BEA0); |
803 | WREG32(index_reg, 0x20402); |
826 | WREG32(index_reg, 0x20402); |
804 | WREG32(data_reg, 0xBF8883C0); |
827 | WREG32(data_reg, 0xBF8883C0); |
805 | WREG32(index_reg, 0x20403); |
828 | WREG32(index_reg, 0x20403); |
806 | WREG32(data_reg, 0x80008000); |
829 | WREG32(data_reg, 0x80008000); |
807 | WREG32(index_reg, 0x20500); |
830 | WREG32(index_reg, 0x20500); |
808 | WREG32(data_reg, 0x80188000); |
831 | WREG32(data_reg, 0x80188000); |
809 | WREG32(index_reg, 0x20501); |
832 | WREG32(index_reg, 0x20501); |
810 | WREG32(data_reg, 0x8D00BE90); |
833 | WREG32(data_reg, 0x8D00BE90); |
811 | WREG32(index_reg, 0x20502); |
834 | WREG32(index_reg, 0x20502); |
812 | WREG32(data_reg, 0xBF588500); |
835 | WREG32(data_reg, 0xBF588500); |
813 | WREG32(index_reg, 0x20503); |
836 | WREG32(index_reg, 0x20503); |
814 | WREG32(data_reg, 0x80008008); |
837 | WREG32(data_reg, 0x80008008); |
815 | WREG32(index_reg, 0x20600); |
838 | WREG32(index_reg, 0x20600); |
816 | WREG32(data_reg, 0x80188000); |
839 | WREG32(data_reg, 0x80188000); |
817 | WREG32(index_reg, 0x20601); |
840 | WREG32(index_reg, 0x20601); |
818 | WREG32(data_reg, 0x8BC0BE98); |
841 | WREG32(data_reg, 0x8BC0BE98); |
819 | WREG32(index_reg, 0x20602); |
842 | WREG32(index_reg, 0x20602); |
820 | WREG32(data_reg, 0xBF308660); |
843 | WREG32(data_reg, 0xBF308660); |
821 | WREG32(index_reg, 0x20603); |
844 | WREG32(index_reg, 0x20603); |
822 | WREG32(data_reg, 0x80008008); |
845 | WREG32(data_reg, 0x80008008); |
823 | WREG32(index_reg, 0x20700); |
846 | WREG32(index_reg, 0x20700); |
824 | WREG32(data_reg, 0x80108000); |
847 | WREG32(data_reg, 0x80108000); |
825 | WREG32(index_reg, 0x20701); |
848 | WREG32(index_reg, 0x20701); |
826 | WREG32(data_reg, 0x8A80BEB0); |
849 | WREG32(data_reg, 0x8A80BEB0); |
827 | WREG32(index_reg, 0x20702); |
850 | WREG32(index_reg, 0x20702); |
828 | WREG32(data_reg, 0xBF0087C0); |
851 | WREG32(data_reg, 0xBF0087C0); |
829 | WREG32(index_reg, 0x20703); |
852 | WREG32(index_reg, 0x20703); |
830 | WREG32(data_reg, 0x80008008); |
853 | WREG32(data_reg, 0x80008008); |
831 | WREG32(index_reg, 0x20800); |
854 | WREG32(index_reg, 0x20800); |
832 | WREG32(data_reg, 0x80108000); |
855 | WREG32(data_reg, 0x80108000); |
833 | WREG32(index_reg, 0x20801); |
856 | WREG32(index_reg, 0x20801); |
834 | WREG32(data_reg, 0x8920BED0); |
857 | WREG32(data_reg, 0x8920BED0); |
835 | WREG32(index_reg, 0x20802); |
858 | WREG32(index_reg, 0x20802); |
836 | WREG32(data_reg, 0xBED08920); |
859 | WREG32(data_reg, 0xBED08920); |
837 | WREG32(index_reg, 0x20803); |
860 | WREG32(index_reg, 0x20803); |
838 | WREG32(data_reg, 0x80008010); |
861 | WREG32(data_reg, 0x80008010); |
839 | WREG32(index_reg, 0x30000); |
862 | WREG32(index_reg, 0x30000); |
840 | WREG32(data_reg, 0x90008000); |
863 | WREG32(data_reg, 0x90008000); |
841 | WREG32(index_reg, 0x30001); |
864 | WREG32(index_reg, 0x30001); |
842 | WREG32(data_reg, 0x80008000); |
865 | WREG32(data_reg, 0x80008000); |
843 | WREG32(index_reg, 0x30100); |
866 | WREG32(index_reg, 0x30100); |
844 | WREG32(data_reg, 0x8FE0BF90); |
867 | WREG32(data_reg, 0x8FE0BF90); |
845 | WREG32(index_reg, 0x30101); |
868 | WREG32(index_reg, 0x30101); |
846 | WREG32(data_reg, 0xBFF880A0); |
869 | WREG32(data_reg, 0xBFF880A0); |
847 | WREG32(index_reg, 0x30200); |
870 | WREG32(index_reg, 0x30200); |
848 | WREG32(data_reg, 0x8F60BF40); |
871 | WREG32(data_reg, 0x8F60BF40); |
849 | WREG32(index_reg, 0x30201); |
872 | WREG32(index_reg, 0x30201); |
850 | WREG32(data_reg, 0xBFE88180); |
873 | WREG32(data_reg, 0xBFE88180); |
851 | WREG32(index_reg, 0x30300); |
874 | WREG32(index_reg, 0x30300); |
852 | WREG32(data_reg, 0x8EC0BF00); |
875 | WREG32(data_reg, 0x8EC0BF00); |
853 | WREG32(index_reg, 0x30301); |
876 | WREG32(index_reg, 0x30301); |
854 | WREG32(data_reg, 0xBFC88280); |
877 | WREG32(data_reg, 0xBFC88280); |
855 | WREG32(index_reg, 0x30400); |
878 | WREG32(index_reg, 0x30400); |
856 | WREG32(data_reg, 0x8DE0BEE0); |
879 | WREG32(data_reg, 0x8DE0BEE0); |
857 | WREG32(index_reg, 0x30401); |
880 | WREG32(index_reg, 0x30401); |
858 | WREG32(data_reg, 0xBFA083A0); |
881 | WREG32(data_reg, 0xBFA083A0); |
859 | WREG32(index_reg, 0x30500); |
882 | WREG32(index_reg, 0x30500); |
860 | WREG32(data_reg, 0x8CE0BED0); |
883 | WREG32(data_reg, 0x8CE0BED0); |
861 | WREG32(index_reg, 0x30501); |
884 | WREG32(index_reg, 0x30501); |
862 | WREG32(data_reg, 0xBF7884E0); |
885 | WREG32(data_reg, 0xBF7884E0); |
863 | WREG32(index_reg, 0x30600); |
886 | WREG32(index_reg, 0x30600); |
864 | WREG32(data_reg, 0x8BA0BED8); |
887 | WREG32(data_reg, 0x8BA0BED8); |
865 | WREG32(index_reg, 0x30601); |
888 | WREG32(index_reg, 0x30601); |
866 | WREG32(data_reg, 0xBF508640); |
889 | WREG32(data_reg, 0xBF508640); |
867 | WREG32(index_reg, 0x30700); |
890 | WREG32(index_reg, 0x30700); |
868 | WREG32(data_reg, 0x8A60BEE8); |
891 | WREG32(data_reg, 0x8A60BEE8); |
869 | WREG32(index_reg, 0x30701); |
892 | WREG32(index_reg, 0x30701); |
870 | WREG32(data_reg, 0xBF2087A0); |
893 | WREG32(data_reg, 0xBF2087A0); |
871 | WREG32(index_reg, 0x30800); |
894 | WREG32(index_reg, 0x30800); |
872 | WREG32(data_reg, 0x8900BF00); |
895 | WREG32(data_reg, 0x8900BF00); |
873 | WREG32(index_reg, 0x30801); |
896 | WREG32(index_reg, 0x30801); |
874 | WREG32(data_reg, 0xBF008900); |
897 | WREG32(data_reg, 0xBF008900); |
875 | } |
898 | } |
876 | 899 | ||
877 | struct rv515_watermark { |
900 | struct rv515_watermark { |
878 | u32 lb_request_fifo_depth; |
901 | u32 lb_request_fifo_depth; |
879 | fixed20_12 num_line_pair; |
902 | fixed20_12 num_line_pair; |
880 | fixed20_12 estimated_width; |
903 | fixed20_12 estimated_width; |
881 | fixed20_12 worst_case_latency; |
904 | fixed20_12 worst_case_latency; |
882 | fixed20_12 consumption_rate; |
905 | fixed20_12 consumption_rate; |
883 | fixed20_12 active_time; |
906 | fixed20_12 active_time; |
884 | fixed20_12 dbpp; |
907 | fixed20_12 dbpp; |
885 | fixed20_12 priority_mark_max; |
908 | fixed20_12 priority_mark_max; |
886 | fixed20_12 priority_mark; |
909 | fixed20_12 priority_mark; |
887 | fixed20_12 sclk; |
910 | fixed20_12 sclk; |
888 | }; |
911 | }; |
889 | 912 | ||
890 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
913 | static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, |
891 | struct radeon_crtc *crtc, |
914 | struct radeon_crtc *crtc, |
892 | struct rv515_watermark *wm, |
915 | struct rv515_watermark *wm, |
893 | bool low) |
916 | bool low) |
894 | { |
917 | { |
895 | struct drm_display_mode *mode = &crtc->base.mode; |
918 | struct drm_display_mode *mode = &crtc->base.mode; |
896 | fixed20_12 a, b, c; |
919 | fixed20_12 a, b, c; |
897 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
920 | fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; |
898 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
921 | fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; |
899 | fixed20_12 sclk; |
922 | fixed20_12 sclk; |
900 | u32 selected_sclk; |
923 | u32 selected_sclk; |
901 | 924 | ||
902 | if (!crtc->base.enabled) { |
925 | if (!crtc->base.enabled) { |
903 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
926 | /* FIXME: wouldn't it better to set priority mark to maximum */ |
904 | wm->lb_request_fifo_depth = 4; |
927 | wm->lb_request_fifo_depth = 4; |
905 | return; |
928 | return; |
906 | } |
929 | } |
907 | 930 | ||
908 | /* rv6xx, rv7xx */ |
931 | /* rv6xx, rv7xx */ |
909 | if ((rdev->family >= CHIP_RV610) && |
932 | if ((rdev->family >= CHIP_RV610) && |
910 | (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
933 | (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) |
911 | selected_sclk = radeon_dpm_get_sclk(rdev, low); |
934 | selected_sclk = radeon_dpm_get_sclk(rdev, low); |
912 | else |
935 | else |
913 | selected_sclk = rdev->pm.current_sclk; |
936 | selected_sclk = rdev->pm.current_sclk; |
914 | 937 | ||
915 | /* sclk in Mhz */ |
938 | /* sclk in Mhz */ |
916 | a.full = dfixed_const(100); |
939 | a.full = dfixed_const(100); |
917 | sclk.full = dfixed_const(selected_sclk); |
940 | sclk.full = dfixed_const(selected_sclk); |
918 | sclk.full = dfixed_div(sclk, a); |
941 | sclk.full = dfixed_div(sclk, a); |
919 | 942 | ||
920 | if (crtc->vsc.full > dfixed_const(2)) |
943 | if (crtc->vsc.full > dfixed_const(2)) |
921 | wm->num_line_pair.full = dfixed_const(2); |
944 | wm->num_line_pair.full = dfixed_const(2); |
922 | else |
945 | else |
923 | wm->num_line_pair.full = dfixed_const(1); |
946 | wm->num_line_pair.full = dfixed_const(1); |
924 | 947 | ||
925 | b.full = dfixed_const(mode->crtc_hdisplay); |
948 | b.full = dfixed_const(mode->crtc_hdisplay); |
926 | c.full = dfixed_const(256); |
949 | c.full = dfixed_const(256); |
927 | a.full = dfixed_div(b, c); |
950 | a.full = dfixed_div(b, c); |
928 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
951 | request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); |
929 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
952 | request_fifo_depth.full = dfixed_ceil(request_fifo_depth); |
930 | if (a.full < dfixed_const(4)) { |
953 | if (a.full < dfixed_const(4)) { |
931 | wm->lb_request_fifo_depth = 4; |
954 | wm->lb_request_fifo_depth = 4; |
932 | } else { |
955 | } else { |
933 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
956 | wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); |
934 | } |
957 | } |
935 | 958 | ||
936 | /* Determine consumption rate |
959 | /* Determine consumption rate |
937 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
960 | * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) |
938 | * vtaps = number of vertical taps, |
961 | * vtaps = number of vertical taps, |
939 | * vsc = vertical scaling ratio, defined as source/destination |
962 | * vsc = vertical scaling ratio, defined as source/destination |
940 | * hsc = horizontal scaling ration, defined as source/destination |
963 | * hsc = horizontal scaling ration, defined as source/destination |
941 | */ |
964 | */ |
942 | a.full = dfixed_const(mode->clock); |
965 | a.full = dfixed_const(mode->clock); |
943 | b.full = dfixed_const(1000); |
966 | b.full = dfixed_const(1000); |
944 | a.full = dfixed_div(a, b); |
967 | a.full = dfixed_div(a, b); |
945 | pclk.full = dfixed_div(b, a); |
968 | pclk.full = dfixed_div(b, a); |
946 | if (crtc->rmx_type != RMX_OFF) { |
969 | if (crtc->rmx_type != RMX_OFF) { |
947 | b.full = dfixed_const(2); |
970 | b.full = dfixed_const(2); |
948 | if (crtc->vsc.full > b.full) |
971 | if (crtc->vsc.full > b.full) |
949 | b.full = crtc->vsc.full; |
972 | b.full = crtc->vsc.full; |
950 | b.full = dfixed_mul(b, crtc->hsc); |
973 | b.full = dfixed_mul(b, crtc->hsc); |
951 | c.full = dfixed_const(2); |
974 | c.full = dfixed_const(2); |
952 | b.full = dfixed_div(b, c); |
975 | b.full = dfixed_div(b, c); |
953 | consumption_time.full = dfixed_div(pclk, b); |
976 | consumption_time.full = dfixed_div(pclk, b); |
954 | } else { |
977 | } else { |
955 | consumption_time.full = pclk.full; |
978 | consumption_time.full = pclk.full; |
956 | } |
979 | } |
957 | a.full = dfixed_const(1); |
980 | a.full = dfixed_const(1); |
958 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
981 | wm->consumption_rate.full = dfixed_div(a, consumption_time); |
959 | 982 | ||
960 | 983 | ||
961 | /* Determine line time |
984 | /* Determine line time |
962 | * LineTime = total time for one line of displayhtotal |
985 | * LineTime = total time for one line of displayhtotal |
963 | * LineTime = total number of horizontal pixels |
986 | * LineTime = total number of horizontal pixels |
964 | * pclk = pixel clock period(ns) |
987 | * pclk = pixel clock period(ns) |
965 | */ |
988 | */ |
966 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
989 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
967 | line_time.full = dfixed_mul(a, pclk); |
990 | line_time.full = dfixed_mul(a, pclk); |
968 | 991 | ||
969 | /* Determine active time |
992 | /* Determine active time |
970 | * ActiveTime = time of active region of display within one line, |
993 | * ActiveTime = time of active region of display within one line, |
971 | * hactive = total number of horizontal active pixels |
994 | * hactive = total number of horizontal active pixels |
972 | * htotal = total number of horizontal pixels |
995 | * htotal = total number of horizontal pixels |
973 | */ |
996 | */ |
974 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
997 | a.full = dfixed_const(crtc->base.mode.crtc_htotal); |
975 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
998 | b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
976 | wm->active_time.full = dfixed_mul(line_time, b); |
999 | wm->active_time.full = dfixed_mul(line_time, b); |
977 | wm->active_time.full = dfixed_div(wm->active_time, a); |
1000 | wm->active_time.full = dfixed_div(wm->active_time, a); |
978 | 1001 | ||
979 | /* Determine chunk time |
1002 | /* Determine chunk time |
980 | * ChunkTime = the time it takes the DCP to send one chunk of data |
1003 | * ChunkTime = the time it takes the DCP to send one chunk of data |
981 | * to the LB which consists of pipeline delay and inter chunk gap |
1004 | * to the LB which consists of pipeline delay and inter chunk gap |
982 | * sclk = system clock(Mhz) |
1005 | * sclk = system clock(Mhz) |
983 | */ |
1006 | */ |
984 | a.full = dfixed_const(600 * 1000); |
1007 | a.full = dfixed_const(600 * 1000); |
985 | chunk_time.full = dfixed_div(a, sclk); |
1008 | chunk_time.full = dfixed_div(a, sclk); |
986 | read_delay_latency.full = dfixed_const(1000); |
1009 | read_delay_latency.full = dfixed_const(1000); |
987 | 1010 | ||
988 | /* Determine the worst case latency |
1011 | /* Determine the worst case latency |
989 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
1012 | * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) |
990 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
1013 | * WorstCaseLatency = worst case time from urgent to when the MC starts |
991 | * to return data |
1014 | * to return data |
992 | * READ_DELAY_IDLE_MAX = constant of 1us |
1015 | * READ_DELAY_IDLE_MAX = constant of 1us |
993 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
1016 | * ChunkTime = time it takes the DCP to send one chunk of data to the LB |
994 | * which consists of pipeline delay and inter chunk gap |
1017 | * which consists of pipeline delay and inter chunk gap |
995 | */ |
1018 | */ |
996 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
1019 | if (dfixed_trunc(wm->num_line_pair) > 1) { |
997 | a.full = dfixed_const(3); |
1020 | a.full = dfixed_const(3); |
998 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
1021 | wm->worst_case_latency.full = dfixed_mul(a, chunk_time); |
999 | wm->worst_case_latency.full += read_delay_latency.full; |
1022 | wm->worst_case_latency.full += read_delay_latency.full; |
1000 | } else { |
1023 | } else { |
1001 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
1024 | wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; |
1002 | } |
1025 | } |
1003 | 1026 | ||
1004 | /* Determine the tolerable latency |
1027 | /* Determine the tolerable latency |
1005 | * TolerableLatency = Any given request has only 1 line time |
1028 | * TolerableLatency = Any given request has only 1 line time |
1006 | * for the data to be returned |
1029 | * for the data to be returned |
1007 | * LBRequestFifoDepth = Number of chunk requests the LB can |
1030 | * LBRequestFifoDepth = Number of chunk requests the LB can |
1008 | * put into the request FIFO for a display |
1031 | * put into the request FIFO for a display |
1009 | * LineTime = total time for one line of display |
1032 | * LineTime = total time for one line of display |
1010 | * ChunkTime = the time it takes the DCP to send one chunk |
1033 | * ChunkTime = the time it takes the DCP to send one chunk |
1011 | * of data to the LB which consists of |
1034 | * of data to the LB which consists of |
1012 | * pipeline delay and inter chunk gap |
1035 | * pipeline delay and inter chunk gap |
1013 | */ |
1036 | */ |
1014 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
1037 | if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { |
1015 | tolerable_latency.full = line_time.full; |
1038 | tolerable_latency.full = line_time.full; |
1016 | } else { |
1039 | } else { |
1017 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
1040 | tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); |
1018 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
1041 | tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; |
1019 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
1042 | tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); |
1020 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
1043 | tolerable_latency.full = line_time.full - tolerable_latency.full; |
1021 | } |
1044 | } |
1022 | /* We assume worst case 32bits (4 bytes) */ |
1045 | /* We assume worst case 32bits (4 bytes) */ |
1023 | wm->dbpp.full = dfixed_const(2 * 16); |
1046 | wm->dbpp.full = dfixed_const(2 * 16); |
1024 | 1047 | ||
1025 | /* Determine the maximum priority mark |
1048 | /* Determine the maximum priority mark |
1026 | * width = viewport width in pixels |
1049 | * width = viewport width in pixels |
1027 | */ |
1050 | */ |
1028 | a.full = dfixed_const(16); |
1051 | a.full = dfixed_const(16); |
1029 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
1052 | wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); |
1030 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
1053 | wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); |
1031 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
1054 | wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); |
1032 | 1055 | ||
1033 | /* Determine estimated width */ |
1056 | /* Determine estimated width */ |
1034 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
1057 | estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; |
1035 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
1058 | estimated_width.full = dfixed_div(estimated_width, consumption_time); |
1036 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
1059 | if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { |
1037 | wm->priority_mark.full = wm->priority_mark_max.full; |
1060 | wm->priority_mark.full = wm->priority_mark_max.full; |
1038 | } else { |
1061 | } else { |
1039 | a.full = dfixed_const(16); |
1062 | a.full = dfixed_const(16); |
1040 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
1063 | wm->priority_mark.full = dfixed_div(estimated_width, a); |
1041 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
1064 | wm->priority_mark.full = dfixed_ceil(wm->priority_mark); |
1042 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
1065 | wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; |
1043 | } |
1066 | } |
1044 | } |
1067 | } |
1045 | 1068 | ||
1046 | static void rv515_compute_mode_priority(struct radeon_device *rdev, |
1069 | static void rv515_compute_mode_priority(struct radeon_device *rdev, |
1047 | struct rv515_watermark *wm0, |
1070 | struct rv515_watermark *wm0, |
1048 | struct rv515_watermark *wm1, |
1071 | struct rv515_watermark *wm1, |
1049 | struct drm_display_mode *mode0, |
1072 | struct drm_display_mode *mode0, |
1050 | struct drm_display_mode *mode1, |
1073 | struct drm_display_mode *mode1, |
1051 | u32 *d1mode_priority_a_cnt, |
1074 | u32 *d1mode_priority_a_cnt, |
1052 | u32 *d2mode_priority_a_cnt) |
1075 | u32 *d2mode_priority_a_cnt) |
1053 | { |
1076 | { |
1054 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
1077 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
1055 | fixed20_12 a, b; |
1078 | fixed20_12 a, b; |
1056 | 1079 | ||
1057 | *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1080 | *d1mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1058 | *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1081 | *d2mode_priority_a_cnt = MODE_PRIORITY_OFF; |
1059 | 1082 | ||
1060 | if (mode0 && mode1) { |
1083 | if (mode0 && mode1) { |
1061 | if (dfixed_trunc(wm0->dbpp) > 64) |
1084 | if (dfixed_trunc(wm0->dbpp) > 64) |
1062 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1085 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1063 | else |
1086 | else |
1064 | a.full = wm0->num_line_pair.full; |
1087 | a.full = wm0->num_line_pair.full; |
1065 | if (dfixed_trunc(wm1->dbpp) > 64) |
1088 | if (dfixed_trunc(wm1->dbpp) > 64) |
1066 | b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1089 | b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1067 | else |
1090 | else |
1068 | b.full = wm1->num_line_pair.full; |
1091 | b.full = wm1->num_line_pair.full; |
1069 | a.full += b.full; |
1092 | a.full += b.full; |
1070 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1093 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1071 | if (wm0->consumption_rate.full > fill_rate.full) { |
1094 | if (wm0->consumption_rate.full > fill_rate.full) { |
1072 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1095 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1073 | b.full = dfixed_mul(b, wm0->active_time); |
1096 | b.full = dfixed_mul(b, wm0->active_time); |
1074 | a.full = dfixed_const(16); |
1097 | a.full = dfixed_const(16); |
1075 | b.full = dfixed_div(b, a); |
1098 | b.full = dfixed_div(b, a); |
1076 | a.full = dfixed_mul(wm0->worst_case_latency, |
1099 | a.full = dfixed_mul(wm0->worst_case_latency, |
1077 | wm0->consumption_rate); |
1100 | wm0->consumption_rate); |
1078 | priority_mark02.full = a.full + b.full; |
1101 | priority_mark02.full = a.full + b.full; |
1079 | } else { |
1102 | } else { |
1080 | a.full = dfixed_mul(wm0->worst_case_latency, |
1103 | a.full = dfixed_mul(wm0->worst_case_latency, |
1081 | wm0->consumption_rate); |
1104 | wm0->consumption_rate); |
1082 | b.full = dfixed_const(16 * 1000); |
1105 | b.full = dfixed_const(16 * 1000); |
1083 | priority_mark02.full = dfixed_div(a, b); |
1106 | priority_mark02.full = dfixed_div(a, b); |
1084 | } |
1107 | } |
1085 | if (wm1->consumption_rate.full > fill_rate.full) { |
1108 | if (wm1->consumption_rate.full > fill_rate.full) { |
1086 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1109 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1087 | b.full = dfixed_mul(b, wm1->active_time); |
1110 | b.full = dfixed_mul(b, wm1->active_time); |
1088 | a.full = dfixed_const(16); |
1111 | a.full = dfixed_const(16); |
1089 | b.full = dfixed_div(b, a); |
1112 | b.full = dfixed_div(b, a); |
1090 | a.full = dfixed_mul(wm1->worst_case_latency, |
1113 | a.full = dfixed_mul(wm1->worst_case_latency, |
1091 | wm1->consumption_rate); |
1114 | wm1->consumption_rate); |
1092 | priority_mark12.full = a.full + b.full; |
1115 | priority_mark12.full = a.full + b.full; |
1093 | } else { |
1116 | } else { |
1094 | a.full = dfixed_mul(wm1->worst_case_latency, |
1117 | a.full = dfixed_mul(wm1->worst_case_latency, |
1095 | wm1->consumption_rate); |
1118 | wm1->consumption_rate); |
1096 | b.full = dfixed_const(16 * 1000); |
1119 | b.full = dfixed_const(16 * 1000); |
1097 | priority_mark12.full = dfixed_div(a, b); |
1120 | priority_mark12.full = dfixed_div(a, b); |
1098 | } |
1121 | } |
1099 | if (wm0->priority_mark.full > priority_mark02.full) |
1122 | if (wm0->priority_mark.full > priority_mark02.full) |
1100 | priority_mark02.full = wm0->priority_mark.full; |
1123 | priority_mark02.full = wm0->priority_mark.full; |
1101 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1124 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1102 | priority_mark02.full = wm0->priority_mark_max.full; |
1125 | priority_mark02.full = wm0->priority_mark_max.full; |
1103 | if (wm1->priority_mark.full > priority_mark12.full) |
1126 | if (wm1->priority_mark.full > priority_mark12.full) |
1104 | priority_mark12.full = wm1->priority_mark.full; |
1127 | priority_mark12.full = wm1->priority_mark.full; |
1105 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1128 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1106 | priority_mark12.full = wm1->priority_mark_max.full; |
1129 | priority_mark12.full = wm1->priority_mark_max.full; |
1107 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1130 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1108 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1131 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1109 | if (rdev->disp_priority == 2) { |
1132 | if (rdev->disp_priority == 2) { |
1110 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1133 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1111 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1134 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1112 | } |
1135 | } |
1113 | } else if (mode0) { |
1136 | } else if (mode0) { |
1114 | if (dfixed_trunc(wm0->dbpp) > 64) |
1137 | if (dfixed_trunc(wm0->dbpp) > 64) |
1115 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1138 | a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair); |
1116 | else |
1139 | else |
1117 | a.full = wm0->num_line_pair.full; |
1140 | a.full = wm0->num_line_pair.full; |
1118 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1141 | fill_rate.full = dfixed_div(wm0->sclk, a); |
1119 | if (wm0->consumption_rate.full > fill_rate.full) { |
1142 | if (wm0->consumption_rate.full > fill_rate.full) { |
1120 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1143 | b.full = wm0->consumption_rate.full - fill_rate.full; |
1121 | b.full = dfixed_mul(b, wm0->active_time); |
1144 | b.full = dfixed_mul(b, wm0->active_time); |
1122 | a.full = dfixed_const(16); |
1145 | a.full = dfixed_const(16); |
1123 | b.full = dfixed_div(b, a); |
1146 | b.full = dfixed_div(b, a); |
1124 | a.full = dfixed_mul(wm0->worst_case_latency, |
1147 | a.full = dfixed_mul(wm0->worst_case_latency, |
1125 | wm0->consumption_rate); |
1148 | wm0->consumption_rate); |
1126 | priority_mark02.full = a.full + b.full; |
1149 | priority_mark02.full = a.full + b.full; |
1127 | } else { |
1150 | } else { |
1128 | a.full = dfixed_mul(wm0->worst_case_latency, |
1151 | a.full = dfixed_mul(wm0->worst_case_latency, |
1129 | wm0->consumption_rate); |
1152 | wm0->consumption_rate); |
1130 | b.full = dfixed_const(16); |
1153 | b.full = dfixed_const(16); |
1131 | priority_mark02.full = dfixed_div(a, b); |
1154 | priority_mark02.full = dfixed_div(a, b); |
1132 | } |
1155 | } |
1133 | if (wm0->priority_mark.full > priority_mark02.full) |
1156 | if (wm0->priority_mark.full > priority_mark02.full) |
1134 | priority_mark02.full = wm0->priority_mark.full; |
1157 | priority_mark02.full = wm0->priority_mark.full; |
1135 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1158 | if (wm0->priority_mark_max.full > priority_mark02.full) |
1136 | priority_mark02.full = wm0->priority_mark_max.full; |
1159 | priority_mark02.full = wm0->priority_mark_max.full; |
1137 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1160 | *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1138 | if (rdev->disp_priority == 2) |
1161 | if (rdev->disp_priority == 2) |
1139 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1162 | *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1140 | } else if (mode1) { |
1163 | } else if (mode1) { |
1141 | if (dfixed_trunc(wm1->dbpp) > 64) |
1164 | if (dfixed_trunc(wm1->dbpp) > 64) |
1142 | a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1165 | a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair); |
1143 | else |
1166 | else |
1144 | a.full = wm1->num_line_pair.full; |
1167 | a.full = wm1->num_line_pair.full; |
1145 | fill_rate.full = dfixed_div(wm1->sclk, a); |
1168 | fill_rate.full = dfixed_div(wm1->sclk, a); |
1146 | if (wm1->consumption_rate.full > fill_rate.full) { |
1169 | if (wm1->consumption_rate.full > fill_rate.full) { |
1147 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1170 | b.full = wm1->consumption_rate.full - fill_rate.full; |
1148 | b.full = dfixed_mul(b, wm1->active_time); |
1171 | b.full = dfixed_mul(b, wm1->active_time); |
1149 | a.full = dfixed_const(16); |
1172 | a.full = dfixed_const(16); |
1150 | b.full = dfixed_div(b, a); |
1173 | b.full = dfixed_div(b, a); |
1151 | a.full = dfixed_mul(wm1->worst_case_latency, |
1174 | a.full = dfixed_mul(wm1->worst_case_latency, |
1152 | wm1->consumption_rate); |
1175 | wm1->consumption_rate); |
1153 | priority_mark12.full = a.full + b.full; |
1176 | priority_mark12.full = a.full + b.full; |
1154 | } else { |
1177 | } else { |
1155 | a.full = dfixed_mul(wm1->worst_case_latency, |
1178 | a.full = dfixed_mul(wm1->worst_case_latency, |
1156 | wm1->consumption_rate); |
1179 | wm1->consumption_rate); |
1157 | b.full = dfixed_const(16 * 1000); |
1180 | b.full = dfixed_const(16 * 1000); |
1158 | priority_mark12.full = dfixed_div(a, b); |
1181 | priority_mark12.full = dfixed_div(a, b); |
1159 | } |
1182 | } |
1160 | if (wm1->priority_mark.full > priority_mark12.full) |
1183 | if (wm1->priority_mark.full > priority_mark12.full) |
1161 | priority_mark12.full = wm1->priority_mark.full; |
1184 | priority_mark12.full = wm1->priority_mark.full; |
1162 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1185 | if (wm1->priority_mark_max.full > priority_mark12.full) |
1163 | priority_mark12.full = wm1->priority_mark_max.full; |
1186 | priority_mark12.full = wm1->priority_mark_max.full; |
1164 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1187 | *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1165 | if (rdev->disp_priority == 2) |
1188 | if (rdev->disp_priority == 2) |
1166 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1189 | *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1167 | } |
1190 | } |
1168 | } |
1191 | } |
1169 | 1192 | ||
1170 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
1193 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev) |
1171 | { |
1194 | { |
1172 | struct drm_display_mode *mode0 = NULL; |
1195 | struct drm_display_mode *mode0 = NULL; |
1173 | struct drm_display_mode *mode1 = NULL; |
1196 | struct drm_display_mode *mode1 = NULL; |
1174 | struct rv515_watermark wm0_high, wm0_low; |
1197 | struct rv515_watermark wm0_high, wm0_low; |
1175 | struct rv515_watermark wm1_high, wm1_low; |
1198 | struct rv515_watermark wm1_high, wm1_low; |
1176 | u32 tmp; |
1199 | u32 tmp; |
1177 | u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; |
1200 | u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; |
1178 | u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; |
1201 | u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; |
1179 | 1202 | ||
1180 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1203 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1181 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
1204 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
1182 | if (rdev->mode_info.crtcs[1]->base.enabled) |
1205 | if (rdev->mode_info.crtcs[1]->base.enabled) |
1183 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
1206 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
1184 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
1207 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
1185 | 1208 | ||
1186 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); |
1209 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); |
1187 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); |
1210 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); |
1188 | 1211 | ||
1189 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); |
1212 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); |
1190 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); |
1213 | rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); |
1191 | 1214 | ||
1192 | tmp = wm0_high.lb_request_fifo_depth; |
1215 | tmp = wm0_high.lb_request_fifo_depth; |
1193 | tmp |= wm1_high.lb_request_fifo_depth << 16; |
1216 | tmp |= wm1_high.lb_request_fifo_depth << 16; |
1194 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
1217 | WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
1195 | 1218 | ||
1196 | rv515_compute_mode_priority(rdev, |
1219 | rv515_compute_mode_priority(rdev, |
1197 | &wm0_high, &wm1_high, |
1220 | &wm0_high, &wm1_high, |
1198 | mode0, mode1, |
1221 | mode0, mode1, |
1199 | &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); |
1222 | &d1mode_priority_a_cnt, &d2mode_priority_a_cnt); |
1200 | rv515_compute_mode_priority(rdev, |
1223 | rv515_compute_mode_priority(rdev, |
1201 | &wm0_low, &wm1_low, |
1224 | &wm0_low, &wm1_low, |
1202 | mode0, mode1, |
1225 | mode0, mode1, |
1203 | &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); |
1226 | &d1mode_priority_b_cnt, &d2mode_priority_b_cnt); |
1204 | 1227 | ||
1205 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
1228 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
1206 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); |
1229 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); |
1207 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1230 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
1208 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); |
1231 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); |
1209 | } |
1232 | } |
1210 | 1233 | ||
1211 | void rv515_bandwidth_update(struct radeon_device *rdev) |
1234 | void rv515_bandwidth_update(struct radeon_device *rdev) |
1212 | { |
1235 | { |
1213 | uint32_t tmp; |
1236 | uint32_t tmp; |
1214 | struct drm_display_mode *mode0 = NULL; |
1237 | struct drm_display_mode *mode0 = NULL; |
1215 | struct drm_display_mode *mode1 = NULL; |
1238 | struct drm_display_mode *mode1 = NULL; |
1216 | 1239 | ||
1217 | if (!rdev->mode_info.mode_config_initialized) |
1240 | if (!rdev->mode_info.mode_config_initialized) |
1218 | return; |
1241 | return; |
1219 | 1242 | ||
1220 | radeon_update_display_priority(rdev); |
1243 | radeon_update_display_priority(rdev); |
1221 | 1244 | ||
1222 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1245 | if (rdev->mode_info.crtcs[0]->base.enabled) |
1223 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
1246 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
1224 | if (rdev->mode_info.crtcs[1]->base.enabled) |
1247 | if (rdev->mode_info.crtcs[1]->base.enabled) |
1225 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
1248 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
1226 | /* |
1249 | /* |
1227 | * Set display0/1 priority up in the memory controller for |
1250 | * Set display0/1 priority up in the memory controller for |
1228 | * modes if the user specifies HIGH for displaypriority |
1251 | * modes if the user specifies HIGH for displaypriority |
1229 | * option. |
1252 | * option. |
1230 | */ |
1253 | */ |
1231 | if ((rdev->disp_priority == 2) && |
1254 | if ((rdev->disp_priority == 2) && |
1232 | (rdev->family == CHIP_RV515)) { |
1255 | (rdev->family == CHIP_RV515)) { |
1233 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1256 | tmp = RREG32_MC(MC_MISC_LAT_TIMER); |
1234 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
1257 | tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
1235 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
1258 | tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
1236 | if (mode1) |
1259 | if (mode1) |
1237 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
1260 | tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
1238 | if (mode0) |
1261 | if (mode0) |
1239 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
1262 | tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
1240 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
1263 | WREG32_MC(MC_MISC_LAT_TIMER, tmp); |
1241 | } |
1264 | } |
1242 | rv515_bandwidth_avivo_update(rdev); |
1265 | rv515_bandwidth_avivo_update(rdev); |
1243 | }><>><>><>>>>>>>>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
1266 | }><>><>><>>>>>>>>>>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |