WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_ib.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 *          Christian König
 */
#include 
#include "radeon.h"
 
/*
 * IB
 * IBs (Indirect Buffers) and areas of GPU accessible memory where
 * commands are stored.  You can put a pointer to the IB in the
 * command ring and the hw will fetch the commands from the IB
 * and execute them.  Generally userspace acceleration drivers
 * produce command buffers which are send to the kernel and
 * put in IBs for execution by the requested ring.
 */
static int radeon_debugfs_sa_init(struct radeon_device *rdev);
 
/**
 * radeon_ib_get - request an IB (Indirect Buffer)
 *
 * @rdev: radeon_device pointer
 * @ring: ring index the IB is associated with
 * @ib: IB object returned
 * @size: requested IB size
 *
 * Request an IB (all asics).  IBs are allocated using the
 * suballocator.
 * Returns 0 on success, error on failure.
 */
int radeon_ib_get(struct radeon_device *rdev, int ring,
		  struct radeon_ib *ib, struct radeon_vm *vm,
		  unsigned size)
{
	int r;
 
	r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
	if (r) {
		dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
		return r;
	}
 
 
 
 
	radeon_sync_create(&ib->sync);
 
	ib->ring = ring;
	ib->fence = NULL;
	ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
	ib->vm = vm;
	if (vm) {
		/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
		 * space and soffset is the offset inside the pool bo
		 */
		ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
	} else {
		ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
	}
	ib->is_const_ib = false;
 
	return 0;
}
 
/**
 * radeon_ib_free - free an IB (Indirect Buffer)
 *
 * @rdev: radeon_device pointer
 * @ib: IB object to free
 *
 * Free an IB (all asics).
 */
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
{
	radeon_sync_free(rdev, &ib->sync, ib->fence);
	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
	radeon_fence_unref(&ib->fence);
}
 
/**
 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
 *
 * @rdev: radeon_device pointer
 * @ib: IB object to schedule
 * @const_ib: Const IB to schedule (SI only)
 * @hdp_flush: Whether or not to perform an HDP cache flush
 *
 * Schedule an IB on the associated ring (all asics).
 * Returns 0 on success, error on failure.
 *
 * On SI, there are two parallel engines fed from the primary ring,
 * the CE (Constant Engine) and the DE (Drawing Engine).  Since
 * resource descriptors have moved to memory, the CE allows you to
 * prime the caches while the DE is updating register state so that
 * the resource descriptors will be already in cache when the draw is
 * processed.  To accomplish this, the userspace driver submits two
 * IBs, one for the CE and one for the DE.  If there is a CE IB (called
 * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
 * to SI there was just a DE IB.
 */
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
		       struct radeon_ib *const_ib, bool hdp_flush)
{
	struct radeon_ring *ring = &rdev->ring[ib->ring];
	int r = 0;
 
	if (!ib->length_dw || !ring->ready) {
		/* TODO: Nothings in the ib we should report. */
		dev_err(rdev->dev, "couldn't schedule ib\n");
		return -EINVAL;
	}
 
	/* 64 dwords should be enough for fence too */
	r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
	if (r) {
		dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
		return r;
	}
 
	/* grab a vm id if necessary */
	if (ib->vm) {
		struct radeon_fence *vm_id_fence;
		vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
		radeon_sync_fence(&ib->sync, vm_id_fence);
	}
 
	/* sync with other rings */
	r = radeon_sync_rings(rdev, &ib->sync, ib->ring);
	if (r) {
		dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
		radeon_ring_unlock_undo(rdev, ring);
		return r;
	}
 
	if (ib->vm)
		radeon_vm_flush(rdev, ib->vm, ib->ring,
				ib->sync.last_vm_update);
 
	if (const_ib) {
		radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
		radeon_sync_free(rdev, &const_ib->sync, NULL);
	}
	radeon_ring_ib_execute(rdev, ib->ring, ib);
	r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
	if (r) {
		dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
		radeon_ring_unlock_undo(rdev, ring);
		return r;
	}
	if (const_ib) {
		const_ib->fence = radeon_fence_ref(ib->fence);
	}
 
	if (ib->vm)
		radeon_vm_fence(rdev, ib->vm, ib->fence);
 
	radeon_ring_unlock_commit(rdev, ring, hdp_flush);
	return 0;
}
 
/**
 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
 *
 * @rdev: radeon_device pointer
 *
 * Initialize the suballocator to manage a pool of memory
 * for use as IBs (all asics).
 * Returns 0 on success, error on failure.
 */
int radeon_ib_pool_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->ib_pool_ready) {
		return 0;
	}
 
	if (rdev->family >= CHIP_BONAIRE) {
		r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
					      RADEON_IB_POOL_SIZE*64*1024,
					      RADEON_GPU_PAGE_SIZE,
					      RADEON_GEM_DOMAIN_GTT,
					      RADEON_GEM_GTT_WC);
	} else {
		/* Before CIK, it's better to stick to cacheable GTT due
		 * to the command stream checking
		 */
		r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
					      RADEON_IB_POOL_SIZE*64*1024,
					      RADEON_GPU_PAGE_SIZE,
					      RADEON_GEM_DOMAIN_GTT, 0);
	}
	if (r) {
		return r;
	}
 
	r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
	if (r) {
		return r;
	}
 
	rdev->ib_pool_ready = true;
	if (radeon_debugfs_sa_init(rdev)) {
		dev_err(rdev->dev, "failed to register debugfs file for SA\n");
	}
	return 0;
}
 
/**
 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the suballocator managing the pool of memory
 * for use as IBs (all asics).
 */
void radeon_ib_pool_fini(struct radeon_device *rdev)
{
	if (rdev->ib_pool_ready) {
		radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
		radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
		rdev->ib_pool_ready = false;
	}
}
 
/**
 * radeon_ib_ring_tests - test IBs on the rings
 *
 * @rdev: radeon_device pointer
 *
 * Test an IB (Indirect Buffer) on each ring.
 * If the test fails, disable the ring.
 * Returns 0 on success, error if the primary GFX ring
 * IB test fails.
 */
int radeon_ib_ring_tests(struct radeon_device *rdev)
{
	unsigned i;
	int r;
 
	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		struct radeon_ring *ring = &rdev->ring[i];
 
		if (!ring->ready)
			continue;
 
		r = radeon_ib_test(rdev, i, ring);
		if (r) {
			radeon_fence_driver_force_completion(rdev, i);
			ring->ready = false;
			rdev->needs_reset = false;
 
			if (i == RADEON_RING_TYPE_GFX_INDEX) {
				/* oh, oh, that's really bad */
				DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
		                rdev->accel_working = false;
				return r;
 
			} else {
				/* still not good, but we can live with it */
				DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
			}
		}
	}
	return 0;
}
 
/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
 
static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
 
	radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
 
	return 0;
 
}
 
static struct drm_info_list radeon_debugfs_sa_list[] = {
        {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
};
 
#endif
 
static int radeon_debugfs_sa_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
#else
	return 0;
#endif
}

Rev 5078	Rev 5271
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	* Christian König	27	* Christian König
28	*/	28	*/
29	#include	29	#include
30	#include "radeon.h"	30	#include "radeon.h"
31		31
32	/*	32	/*
33	* IB	33	* IB
34	* IBs (Indirect Buffers) and areas of GPU accessible memory where	34	* IBs (Indirect Buffers) and areas of GPU accessible memory where
35	* commands are stored. You can put a pointer to the IB in the	35	* commands are stored. You can put a pointer to the IB in the
36	* command ring and the hw will fetch the commands from the IB	36	* command ring and the hw will fetch the commands from the IB
37	* and execute them. Generally userspace acceleration drivers	37	* and execute them. Generally userspace acceleration drivers
38	* produce command buffers which are send to the kernel and	38	* produce command buffers which are send to the kernel and
39	* put in IBs for execution by the requested ring.	39	* put in IBs for execution by the requested ring.
40	*/	40	*/
41	static int radeon_debugfs_sa_init(struct radeon_device *rdev);	41	static int radeon_debugfs_sa_init(struct radeon_device *rdev);
42		42
43	/**	43	/**
44	* radeon_ib_get - request an IB (Indirect Buffer)	44	* radeon_ib_get - request an IB (Indirect Buffer)
45	*	45	*
46	* @rdev: radeon_device pointer	46	* @rdev: radeon_device pointer
47	* @ring: ring index the IB is associated with	47	* @ring: ring index the IB is associated with
48	* @ib: IB object returned	48	* @ib: IB object returned
49	* @size: requested IB size	49	* @size: requested IB size
50	*	50	*
51	* Request an IB (all asics). IBs are allocated using the	51	* Request an IB (all asics). IBs are allocated using the
52	* suballocator.	52	* suballocator.
53	* Returns 0 on success, error on failure.	53	* Returns 0 on success, error on failure.
54	*/	54	*/
55	int radeon_ib_get(struct radeon_device *rdev, int ring,	55	int radeon_ib_get(struct radeon_device *rdev, int ring,
56	struct radeon_ib ib, struct radeon_vm vm,	56	struct radeon_ib ib, struct radeon_vm vm,
57	unsigned size)	57	unsigned size)
58	{	58	{
59	int r;	59	int r;
60		60
61	r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);	61	r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
62	if (r) {	62	if (r) {
63	dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);	63	dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
64	return r;	64	return r;
65	}	65	}
66		66
67	r = radeon_semaphore_create(rdev, &ib->semaphore);	-
68	if (r) {	-
69	return r;	-
70	}	67	radeon_sync_create(&ib->sync);
71		68
72	ib->ring = ring;	69	ib->ring = ring;
73	ib->fence = NULL;	70	ib->fence = NULL;
74	ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);	71	ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
75	ib->vm = vm;	72	ib->vm = vm;
76	if (vm) {	73	if (vm) {
77	/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address	74	/* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
78	* space and soffset is the offset inside the pool bo	75	* space and soffset is the offset inside the pool bo
79	*/	76	*/
80	ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;	77	ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
81	} else {	78	} else {
82	ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);	79	ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
83	}	80	}
84	ib->is_const_ib = false;	81	ib->is_const_ib = false;
85		82
86	return 0;	83	return 0;
87	}	84	}
88		85
89	/**	86	/**
90	* radeon_ib_free - free an IB (Indirect Buffer)	87	* radeon_ib_free - free an IB (Indirect Buffer)
91	*	88	*
92	* @rdev: radeon_device pointer	89	* @rdev: radeon_device pointer
93	* @ib: IB object to free	90	* @ib: IB object to free
94	*	91	*
95	* Free an IB (all asics).	92	* Free an IB (all asics).
96	*/	93	*/
97	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib)	94	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib)
98	{	95	{
99	radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);	96	radeon_sync_free(rdev, &ib->sync, ib->fence);
100	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);	97	radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
101	radeon_fence_unref(&ib->fence);	98	radeon_fence_unref(&ib->fence);
102	}	99	}
103		100
104	/**	101	/**
105	* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring	102	* radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
106	*	103	*
107	* @rdev: radeon_device pointer	104	* @rdev: radeon_device pointer
108	* @ib: IB object to schedule	105	* @ib: IB object to schedule
109	* @const_ib: Const IB to schedule (SI only)	106	* @const_ib: Const IB to schedule (SI only)
110	* @hdp_flush: Whether or not to perform an HDP cache flush	107	* @hdp_flush: Whether or not to perform an HDP cache flush
111	*	108	*
112	* Schedule an IB on the associated ring (all asics).	109	* Schedule an IB on the associated ring (all asics).
113	* Returns 0 on success, error on failure.	110	* Returns 0 on success, error on failure.
114	*	111	*
115	* On SI, there are two parallel engines fed from the primary ring,	112	* On SI, there are two parallel engines fed from the primary ring,
116	* the CE (Constant Engine) and the DE (Drawing Engine). Since	113	* the CE (Constant Engine) and the DE (Drawing Engine). Since
117	* resource descriptors have moved to memory, the CE allows you to	114	* resource descriptors have moved to memory, the CE allows you to
118	* prime the caches while the DE is updating register state so that	115	* prime the caches while the DE is updating register state so that
119	* the resource descriptors will be already in cache when the draw is	116	* the resource descriptors will be already in cache when the draw is
120	* processed. To accomplish this, the userspace driver submits two	117	* processed. To accomplish this, the userspace driver submits two
121	* IBs, one for the CE and one for the DE. If there is a CE IB (called	118	* IBs, one for the CE and one for the DE. If there is a CE IB (called
122	* a CONST_IB), it will be put on the ring prior to the DE IB. Prior	119	* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
123	* to SI there was just a DE IB.	120	* to SI there was just a DE IB.
124	*/	121	*/
125	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,	122	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
126	struct radeon_ib *const_ib, bool hdp_flush)	123	struct radeon_ib *const_ib, bool hdp_flush)
127	{	124	{
128	struct radeon_ring *ring = &rdev->ring[ib->ring];	125	struct radeon_ring *ring = &rdev->ring[ib->ring];
129	int r = 0;	126	int r = 0;
130		127
131	if (!ib->length_dw \|\| !ring->ready) {	128	if (!ib->length_dw \|\| !ring->ready) {
132	/* TODO: Nothings in the ib we should report. */	129	/* TODO: Nothings in the ib we should report. */
133	dev_err(rdev->dev, "couldn't schedule ib\n");	130	dev_err(rdev->dev, "couldn't schedule ib\n");
134	return -EINVAL;	131	return -EINVAL;
135	}	132	}
136		133
137	/* 64 dwords should be enough for fence too */	134	/* 64 dwords should be enough for fence too */
138	r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);	135	r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
139	if (r) {	136	if (r) {
140	dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);	137	dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
141	return r;	138	return r;
142	}	139	}
143		140
144	/* grab a vm id if necessary */	141	/* grab a vm id if necessary */
145	if (ib->vm) {	142	if (ib->vm) {
146	struct radeon_fence *vm_id_fence;	143	struct radeon_fence *vm_id_fence;
147	vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);	144	vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
148	radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);	145	radeon_sync_fence(&ib->sync, vm_id_fence);
149	}	146	}
150		147
151	/* sync with other rings */	148	/* sync with other rings */
152	r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);	149	r = radeon_sync_rings(rdev, &ib->sync, ib->ring);
153	if (r) {	150	if (r) {
154	dev_err(rdev->dev, "failed to sync rings (%d)\n", r);	151	dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
155	radeon_ring_unlock_undo(rdev, ring);	152	radeon_ring_unlock_undo(rdev, ring);
156	return r;	153	return r;
157	}	154	}
158		155
159	if (ib->vm)	156	if (ib->vm)
160	radeon_vm_flush(rdev, ib->vm, ib->ring);	157	radeon_vm_flush(rdev, ib->vm, ib->ring,
-		158	ib->sync.last_vm_update);
161		159
162	if (const_ib) {	160	if (const_ib) {
163	radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);	161	radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
164	radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);	162	radeon_sync_free(rdev, &const_ib->sync, NULL);
165	}	163	}
166	radeon_ring_ib_execute(rdev, ib->ring, ib);	164	radeon_ring_ib_execute(rdev, ib->ring, ib);
167	r = radeon_fence_emit(rdev, &ib->fence, ib->ring);	165	r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
168	if (r) {	166	if (r) {
169	dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);	167	dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
170	radeon_ring_unlock_undo(rdev, ring);	168	radeon_ring_unlock_undo(rdev, ring);
171	return r;	169	return r;
172	}	170	}
173	if (const_ib) {	171	if (const_ib) {
174	const_ib->fence = radeon_fence_ref(ib->fence);	172	const_ib->fence = radeon_fence_ref(ib->fence);
175	}	173	}
176		174
177	if (ib->vm)	175	if (ib->vm)
178	radeon_vm_fence(rdev, ib->vm, ib->fence);	176	radeon_vm_fence(rdev, ib->vm, ib->fence);
179		177
180	radeon_ring_unlock_commit(rdev, ring, hdp_flush);	178	radeon_ring_unlock_commit(rdev, ring, hdp_flush);
181	return 0;	179	return 0;
182	}	180	}
183		181
184	/**	182	/**
185	* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool	183	* radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
186	*	184	*
187	* @rdev: radeon_device pointer	185	* @rdev: radeon_device pointer
188	*	186	*
189	* Initialize the suballocator to manage a pool of memory	187	* Initialize the suballocator to manage a pool of memory
190	* for use as IBs (all asics).	188	* for use as IBs (all asics).
191	* Returns 0 on success, error on failure.	189	* Returns 0 on success, error on failure.
192	*/	190	*/
193	int radeon_ib_pool_init(struct radeon_device *rdev)	191	int radeon_ib_pool_init(struct radeon_device *rdev)
194	{	192	{
195	int r;	193	int r;
196		194
197	if (rdev->ib_pool_ready) {	195	if (rdev->ib_pool_ready) {
198	return 0;	196	return 0;
199	}	197	}
200		198
201	if (rdev->family >= CHIP_BONAIRE) {	199	if (rdev->family >= CHIP_BONAIRE) {
202	r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,	200	r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
203	RADEON_IB_POOL_SIZE641024,	201	RADEON_IB_POOL_SIZE641024,
204	RADEON_GPU_PAGE_SIZE,	202	RADEON_GPU_PAGE_SIZE,
205	RADEON_GEM_DOMAIN_GTT,	203	RADEON_GEM_DOMAIN_GTT,
206	RADEON_GEM_GTT_WC);	204	RADEON_GEM_GTT_WC);
207	} else {	205	} else {
208	/* Before CIK, it's better to stick to cacheable GTT due	206	/* Before CIK, it's better to stick to cacheable GTT due
209	* to the command stream checking	207	* to the command stream checking
210	*/	208	*/
211	r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,	209	r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
212	RADEON_IB_POOL_SIZE641024,	210	RADEON_IB_POOL_SIZE641024,
213	RADEON_GPU_PAGE_SIZE,	211	RADEON_GPU_PAGE_SIZE,
214	RADEON_GEM_DOMAIN_GTT, 0);	212	RADEON_GEM_DOMAIN_GTT, 0);
215	}	213	}
216	if (r) {	214	if (r) {
217	return r;	215	return r;
218	}	216	}
219		217
220	r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);	218	r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
221	if (r) {	219	if (r) {
222	return r;	220	return r;
223	}	221	}
224		222
225	rdev->ib_pool_ready = true;	223	rdev->ib_pool_ready = true;
226	if (radeon_debugfs_sa_init(rdev)) {	224	if (radeon_debugfs_sa_init(rdev)) {
227	dev_err(rdev->dev, "failed to register debugfs file for SA\n");	225	dev_err(rdev->dev, "failed to register debugfs file for SA\n");
228	}	226	}
229	return 0;	227	return 0;
230	}	228	}
231		229
232	/**	230	/**
233	* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool	231	* radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
234	*	232	*
235	* @rdev: radeon_device pointer	233	* @rdev: radeon_device pointer
236	*	234	*
237	* Tear down the suballocator managing the pool of memory	235	* Tear down the suballocator managing the pool of memory
238	* for use as IBs (all asics).	236	* for use as IBs (all asics).
239	*/	237	*/
240	void radeon_ib_pool_fini(struct radeon_device *rdev)	238	void radeon_ib_pool_fini(struct radeon_device *rdev)
241	{	239	{
242	if (rdev->ib_pool_ready) {	240	if (rdev->ib_pool_ready) {
243	radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);	241	radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
244	radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);	242	radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
245	rdev->ib_pool_ready = false;	243	rdev->ib_pool_ready = false;
246	}	244	}
247	}	245	}
248		246
249	/**	247	/**
250	* radeon_ib_ring_tests - test IBs on the rings	248	* radeon_ib_ring_tests - test IBs on the rings
251	*	249	*
252	* @rdev: radeon_device pointer	250	* @rdev: radeon_device pointer
253	*	251	*
254	* Test an IB (Indirect Buffer) on each ring.	252	* Test an IB (Indirect Buffer) on each ring.
255	* If the test fails, disable the ring.	253	* If the test fails, disable the ring.
256	* Returns 0 on success, error if the primary GFX ring	254	* Returns 0 on success, error if the primary GFX ring
257	* IB test fails.	255	* IB test fails.
258	*/	256	*/
259	int radeon_ib_ring_tests(struct radeon_device *rdev)	257	int radeon_ib_ring_tests(struct radeon_device *rdev)
260	{	258	{
261	unsigned i;	259	unsigned i;
262	int r;	260	int r;
263		261
264	for (i = 0; i < RADEON_NUM_RINGS; ++i) {	262	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
265	struct radeon_ring *ring = &rdev->ring[i];	263	struct radeon_ring *ring = &rdev->ring[i];
266		264
267	if (!ring->ready)	265	if (!ring->ready)
268	continue;	266	continue;
269		267
270	r = radeon_ib_test(rdev, i, ring);	268	r = radeon_ib_test(rdev, i, ring);
271	if (r) {	269	if (r) {
-		270	radeon_fence_driver_force_completion(rdev, i);
272	ring->ready = false;	271	ring->ready = false;
273	rdev->needs_reset = false;	272	rdev->needs_reset = false;
274		273
275	if (i == RADEON_RING_TYPE_GFX_INDEX) {	274	if (i == RADEON_RING_TYPE_GFX_INDEX) {
276	/* oh, oh, that's really bad */	275	/* oh, oh, that's really bad */
277	DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);	276	DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
278	rdev->accel_working = false;	277	rdev->accel_working = false;
279	return r;	278	return r;
280		279
281	} else {	280	} else {
282	/* still not good, but we can live with it */	281	/* still not good, but we can live with it */
283	DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);	282	DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
284	}	283	}
285	}	284	}
286	}	285	}
287	return 0;	286	return 0;
288	}	287	}
289		288
290	/*	289	/*
291	* Debugfs info	290	* Debugfs info
292	*/	291	*/
293	#if defined(CONFIG_DEBUG_FS)	292	#if defined(CONFIG_DEBUG_FS)
294		293
295	static int radeon_debugfs_sa_info(struct seq_file m, void data)	294	static int radeon_debugfs_sa_info(struct seq_file m, void data)
296	{	295	{
297	struct drm_info_node node = (struct drm_info_node ) m->private;	296	struct drm_info_node node = (struct drm_info_node ) m->private;
298	struct drm_device *dev = node->minor->dev;	297	struct drm_device *dev = node->minor->dev;
299	struct radeon_device *rdev = dev->dev_private;	298	struct radeon_device *rdev = dev->dev_private;
300		299
301	radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);	300	radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
302		301
303	return 0;	302	return 0;
304		303
305	}	304	}
306		305
307	static struct drm_info_list radeon_debugfs_sa_list[] = {	306	static struct drm_info_list radeon_debugfs_sa_list[] = {
308	{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},	307	{"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
309	};	308	};
310		309
311	#endif	310	#endif
312		311
313	static int radeon_debugfs_sa_init(struct radeon_device *rdev)	312	static int radeon_debugfs_sa_init(struct radeon_device *rdev)
314	{	313	{
315	#if defined(CONFIG_DEBUG_FS)	314	#if defined(CONFIG_DEBUG_FS)
316	return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);	315	return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
317	#else	316	#else
318	return 0;	317	return 0;
319	#endif	318	#endif
320	}	319	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_ib.c – Rev 5078 → 5271