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1 | /* |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: Dave Airlie |
23 | * Authors: Dave Airlie |
24 | * Alex Deucher |
24 | * Alex Deucher |
25 | */ |
25 | */ |
26 | #include "drmP.h" |
26 | #include "drmP.h" |
27 | #include "radeon_drm.h" |
27 | #include "radeon_drm.h" |
28 | #include "radeon.h" |
28 | #include "radeon.h" |
29 | 29 | ||
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | #include |
31 | #include |
32 | 32 | ||
33 | #include "drm_crtc_helper.h" |
33 | #include "drm_crtc_helper.h" |
34 | #include "drm_edid.h" |
34 | #include "drm_edid.h" |
35 | 35 | ||
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
37 | 37 | ||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
39 | { |
39 | { |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
41 | struct drm_device *dev = crtc->dev; |
41 | struct drm_device *dev = crtc->dev; |
42 | struct radeon_device *rdev = dev->dev_private; |
42 | struct radeon_device *rdev = dev->dev_private; |
43 | int i; |
43 | int i; |
44 | 44 | ||
45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
45 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
47 | 47 | ||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
51 | 51 | ||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
55 | 55 | ||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
59 | 59 | ||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
61 | for (i = 0; i < 256; i++) { |
61 | for (i = 0; i < 256; i++) { |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
63 | (radeon_crtc->lut_r[i] << 20) | |
63 | (radeon_crtc->lut_r[i] << 20) | |
64 | (radeon_crtc->lut_g[i] << 10) | |
64 | (radeon_crtc->lut_g[i] << 10) | |
65 | (radeon_crtc->lut_b[i] << 0)); |
65 | (radeon_crtc->lut_b[i] << 0)); |
66 | } |
66 | } |
67 | 67 | ||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
69 | } |
69 | } |
70 | 70 | ||
71 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
71 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
72 | { |
72 | { |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
74 | struct drm_device *dev = crtc->dev; |
74 | struct drm_device *dev = crtc->dev; |
75 | struct radeon_device *rdev = dev->dev_private; |
75 | struct radeon_device *rdev = dev->dev_private; |
76 | int i; |
76 | int i; |
77 | 77 | ||
78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
78 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
79 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
80 | 80 | ||
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
81 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
82 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
83 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
84 | 84 | ||
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
85 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
86 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
87 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
88 | 88 | ||
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
89 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
90 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
91 | 91 | ||
92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
92 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
93 | for (i = 0; i < 256; i++) { |
93 | for (i = 0; i < 256; i++) { |
94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
94 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
95 | (radeon_crtc->lut_r[i] << 20) | |
95 | (radeon_crtc->lut_r[i] << 20) | |
96 | (radeon_crtc->lut_g[i] << 10) | |
96 | (radeon_crtc->lut_g[i] << 10) | |
97 | (radeon_crtc->lut_b[i] << 0)); |
97 | (radeon_crtc->lut_b[i] << 0)); |
98 | } |
98 | } |
99 | } |
99 | } |
100 | 100 | ||
101 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
101 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
102 | { |
102 | { |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
103 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
104 | struct drm_device *dev = crtc->dev; |
104 | struct drm_device *dev = crtc->dev; |
105 | struct radeon_device *rdev = dev->dev_private; |
105 | struct radeon_device *rdev = dev->dev_private; |
106 | int i; |
106 | int i; |
107 | 107 | ||
108 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
108 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
109 | 109 | ||
110 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
110 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
111 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
111 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
112 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
112 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
113 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
113 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
114 | NI_GRPH_PRESCALE_BYPASS); |
114 | NI_GRPH_PRESCALE_BYPASS); |
115 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
115 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
116 | NI_OVL_PRESCALE_BYPASS); |
116 | NI_OVL_PRESCALE_BYPASS); |
117 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
117 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
118 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
118 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
119 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
119 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
120 | 120 | ||
121 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
121 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
122 | 122 | ||
123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
123 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
124 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
124 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
125 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
125 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
126 | 126 | ||
127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
127 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
128 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
128 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
129 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
129 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
130 | 130 | ||
131 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
131 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
132 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
132 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
133 | 133 | ||
134 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
134 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
135 | for (i = 0; i < 256; i++) { |
135 | for (i = 0; i < 256; i++) { |
136 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
136 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
137 | (radeon_crtc->lut_r[i] << 20) | |
137 | (radeon_crtc->lut_r[i] << 20) | |
138 | (radeon_crtc->lut_g[i] << 10) | |
138 | (radeon_crtc->lut_g[i] << 10) | |
139 | (radeon_crtc->lut_b[i] << 0)); |
139 | (radeon_crtc->lut_b[i] << 0)); |
140 | } |
140 | } |
141 | 141 | ||
142 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
142 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
143 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
143 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
144 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
144 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
145 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
145 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
146 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
146 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
147 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
147 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
148 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
148 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
149 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
149 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
150 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
150 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
151 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
151 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
152 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
152 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
153 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
153 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
154 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
154 | (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) | |
155 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
155 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
156 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
156 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
157 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
157 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
158 | 158 | ||
159 | } |
159 | } |
160 | 160 | ||
161 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
161 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
162 | { |
162 | { |
163 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
163 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
164 | struct drm_device *dev = crtc->dev; |
164 | struct drm_device *dev = crtc->dev; |
165 | struct radeon_device *rdev = dev->dev_private; |
165 | struct radeon_device *rdev = dev->dev_private; |
166 | int i; |
166 | int i; |
167 | uint32_t dac2_cntl; |
167 | uint32_t dac2_cntl; |
168 | 168 | ||
169 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
169 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
170 | if (radeon_crtc->crtc_id == 0) |
170 | if (radeon_crtc->crtc_id == 0) |
171 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
171 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
172 | else |
172 | else |
173 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
173 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
174 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
174 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
175 | 175 | ||
176 | WREG8(RADEON_PALETTE_INDEX, 0); |
176 | WREG8(RADEON_PALETTE_INDEX, 0); |
177 | for (i = 0; i < 256; i++) { |
177 | for (i = 0; i < 256; i++) { |
178 | WREG32(RADEON_PALETTE_30_DATA, |
178 | WREG32(RADEON_PALETTE_30_DATA, |
179 | (radeon_crtc->lut_r[i] << 20) | |
179 | (radeon_crtc->lut_r[i] << 20) | |
180 | (radeon_crtc->lut_g[i] << 10) | |
180 | (radeon_crtc->lut_g[i] << 10) | |
181 | (radeon_crtc->lut_b[i] << 0)); |
181 | (radeon_crtc->lut_b[i] << 0)); |
182 | } |
182 | } |
183 | } |
183 | } |
184 | 184 | ||
185 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
185 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
186 | { |
186 | { |
187 | struct drm_device *dev = crtc->dev; |
187 | struct drm_device *dev = crtc->dev; |
188 | struct radeon_device *rdev = dev->dev_private; |
188 | struct radeon_device *rdev = dev->dev_private; |
189 | 189 | ||
190 | if (!crtc->enabled) |
190 | if (!crtc->enabled) |
191 | return; |
191 | return; |
192 | 192 | ||
193 | if (ASIC_IS_DCE5(rdev)) |
193 | if (ASIC_IS_DCE5(rdev)) |
194 | dce5_crtc_load_lut(crtc); |
194 | dce5_crtc_load_lut(crtc); |
195 | else if (ASIC_IS_DCE4(rdev)) |
195 | else if (ASIC_IS_DCE4(rdev)) |
196 | dce4_crtc_load_lut(crtc); |
196 | dce4_crtc_load_lut(crtc); |
197 | else if (ASIC_IS_AVIVO(rdev)) |
197 | else if (ASIC_IS_AVIVO(rdev)) |
198 | avivo_crtc_load_lut(crtc); |
198 | avivo_crtc_load_lut(crtc); |
199 | else |
199 | else |
200 | legacy_crtc_load_lut(crtc); |
200 | legacy_crtc_load_lut(crtc); |
201 | } |
201 | } |
202 | 202 | ||
203 | /** Sets the color ramps on behalf of fbcon */ |
203 | /** Sets the color ramps on behalf of fbcon */ |
204 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
204 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
205 | u16 blue, int regno) |
205 | u16 blue, int regno) |
206 | { |
206 | { |
207 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
207 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
208 | 208 | ||
209 | radeon_crtc->lut_r[regno] = red >> 6; |
209 | radeon_crtc->lut_r[regno] = red >> 6; |
210 | radeon_crtc->lut_g[regno] = green >> 6; |
210 | radeon_crtc->lut_g[regno] = green >> 6; |
211 | radeon_crtc->lut_b[regno] = blue >> 6; |
211 | radeon_crtc->lut_b[regno] = blue >> 6; |
212 | } |
212 | } |
213 | 213 | ||
214 | /** Gets the color ramps on behalf of fbcon */ |
214 | /** Gets the color ramps on behalf of fbcon */ |
215 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
215 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
216 | u16 *blue, int regno) |
216 | u16 *blue, int regno) |
217 | { |
217 | { |
218 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
218 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
219 | 219 | ||
220 | *red = radeon_crtc->lut_r[regno] << 6; |
220 | *red = radeon_crtc->lut_r[regno] << 6; |
221 | *green = radeon_crtc->lut_g[regno] << 6; |
221 | *green = radeon_crtc->lut_g[regno] << 6; |
222 | *blue = radeon_crtc->lut_b[regno] << 6; |
222 | *blue = radeon_crtc->lut_b[regno] << 6; |
223 | } |
223 | } |
224 | 224 | ||
225 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
225 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
226 | u16 *blue, uint32_t start, uint32_t size) |
226 | u16 *blue, uint32_t start, uint32_t size) |
227 | { |
227 | { |
228 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
228 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
229 | int end = (start + size > 256) ? 256 : start + size, i; |
229 | int end = (start + size > 256) ? 256 : start + size, i; |
230 | 230 | ||
231 | /* userspace palettes are always correct as is */ |
231 | /* userspace palettes are always correct as is */ |
232 | for (i = start; i < end; i++) { |
232 | for (i = start; i < end; i++) { |
233 | radeon_crtc->lut_r[i] = red[i] >> 6; |
233 | radeon_crtc->lut_r[i] = red[i] >> 6; |
234 | radeon_crtc->lut_g[i] = green[i] >> 6; |
234 | radeon_crtc->lut_g[i] = green[i] >> 6; |
235 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
235 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
236 | } |
236 | } |
237 | radeon_crtc_load_lut(crtc); |
237 | radeon_crtc_load_lut(crtc); |
238 | } |
238 | } |
239 | 239 | ||
240 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
240 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
241 | { |
241 | { |
242 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
242 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
243 | 243 | ||
244 | drm_crtc_cleanup(crtc); |
244 | drm_crtc_cleanup(crtc); |
245 | kfree(radeon_crtc); |
245 | kfree(radeon_crtc); |
246 | } |
246 | } |
247 | 247 | ||
248 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
248 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
249 | .cursor_set = NULL, |
249 | .cursor_set = NULL, |
250 | .cursor_move = NULL, |
250 | .cursor_move = NULL, |
251 | .gamma_set = radeon_crtc_gamma_set, |
251 | .gamma_set = radeon_crtc_gamma_set, |
252 | .set_config = drm_crtc_helper_set_config, |
252 | .set_config = drm_crtc_helper_set_config, |
253 | .destroy = radeon_crtc_destroy, |
253 | .destroy = radeon_crtc_destroy, |
254 | .page_flip = NULL, |
254 | .page_flip = NULL, |
255 | }; |
255 | }; |
256 | 256 | ||
257 | static void radeon_crtc_init(struct drm_device *dev, int index) |
257 | static void radeon_crtc_init(struct drm_device *dev, int index) |
258 | { |
258 | { |
259 | struct radeon_device *rdev = dev->dev_private; |
259 | struct radeon_device *rdev = dev->dev_private; |
260 | struct radeon_crtc *radeon_crtc; |
260 | struct radeon_crtc *radeon_crtc; |
261 | int i; |
261 | int i; |
262 | 262 | ||
263 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
263 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
264 | if (radeon_crtc == NULL) |
264 | if (radeon_crtc == NULL) |
265 | return; |
265 | return; |
266 | 266 | ||
267 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
267 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
268 | 268 | ||
269 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
269 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
270 | radeon_crtc->crtc_id = index; |
270 | radeon_crtc->crtc_id = index; |
271 | rdev->mode_info.crtcs[index] = radeon_crtc; |
271 | rdev->mode_info.crtcs[index] = radeon_crtc; |
272 | 272 | ||
273 | #if 0 |
273 | #if 0 |
274 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
274 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
275 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
275 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
276 | radeon_crtc->mode_set.num_connectors = 0; |
276 | radeon_crtc->mode_set.num_connectors = 0; |
277 | #endif |
277 | #endif |
278 | 278 | ||
279 | for (i = 0; i < 256; i++) { |
279 | for (i = 0; i < 256; i++) { |
280 | radeon_crtc->lut_r[i] = i << 2; |
280 | radeon_crtc->lut_r[i] = i << 2; |
281 | radeon_crtc->lut_g[i] = i << 2; |
281 | radeon_crtc->lut_g[i] = i << 2; |
282 | radeon_crtc->lut_b[i] = i << 2; |
282 | radeon_crtc->lut_b[i] = i << 2; |
283 | } |
283 | } |
284 | 284 | ||
285 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
285 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
286 | radeon_atombios_init_crtc(dev, radeon_crtc); |
286 | radeon_atombios_init_crtc(dev, radeon_crtc); |
287 | else |
287 | else |
288 | radeon_legacy_init_crtc(dev, radeon_crtc); |
288 | radeon_legacy_init_crtc(dev, radeon_crtc); |
289 | } |
289 | } |
290 | 290 | ||
291 | static const char *encoder_names[36] = { |
291 | static const char *encoder_names[36] = { |
292 | "NONE", |
292 | "NONE", |
293 | "INTERNAL_LVDS", |
293 | "INTERNAL_LVDS", |
294 | "INTERNAL_TMDS1", |
294 | "INTERNAL_TMDS1", |
295 | "INTERNAL_TMDS2", |
295 | "INTERNAL_TMDS2", |
296 | "INTERNAL_DAC1", |
296 | "INTERNAL_DAC1", |
297 | "INTERNAL_DAC2", |
297 | "INTERNAL_DAC2", |
298 | "INTERNAL_SDVOA", |
298 | "INTERNAL_SDVOA", |
299 | "INTERNAL_SDVOB", |
299 | "INTERNAL_SDVOB", |
300 | "SI170B", |
300 | "SI170B", |
301 | "CH7303", |
301 | "CH7303", |
302 | "CH7301", |
302 | "CH7301", |
303 | "INTERNAL_DVO1", |
303 | "INTERNAL_DVO1", |
304 | "EXTERNAL_SDVOA", |
304 | "EXTERNAL_SDVOA", |
305 | "EXTERNAL_SDVOB", |
305 | "EXTERNAL_SDVOB", |
306 | "TITFP513", |
306 | "TITFP513", |
307 | "INTERNAL_LVTM1", |
307 | "INTERNAL_LVTM1", |
308 | "VT1623", |
308 | "VT1623", |
309 | "HDMI_SI1930", |
309 | "HDMI_SI1930", |
310 | "HDMI_INTERNAL", |
310 | "HDMI_INTERNAL", |
311 | "INTERNAL_KLDSCP_TMDS1", |
311 | "INTERNAL_KLDSCP_TMDS1", |
312 | "INTERNAL_KLDSCP_DVO1", |
312 | "INTERNAL_KLDSCP_DVO1", |
313 | "INTERNAL_KLDSCP_DAC1", |
313 | "INTERNAL_KLDSCP_DAC1", |
314 | "INTERNAL_KLDSCP_DAC2", |
314 | "INTERNAL_KLDSCP_DAC2", |
315 | "SI178", |
315 | "SI178", |
316 | "MVPU_FPGA", |
316 | "MVPU_FPGA", |
317 | "INTERNAL_DDI", |
317 | "INTERNAL_DDI", |
318 | "VT1625", |
318 | "VT1625", |
319 | "HDMI_SI1932", |
319 | "HDMI_SI1932", |
320 | "DP_AN9801", |
320 | "DP_AN9801", |
321 | "DP_DP501", |
321 | "DP_DP501", |
322 | "INTERNAL_UNIPHY", |
322 | "INTERNAL_UNIPHY", |
323 | "INTERNAL_KLDSCP_LVTMA", |
323 | "INTERNAL_KLDSCP_LVTMA", |
324 | "INTERNAL_UNIPHY1", |
324 | "INTERNAL_UNIPHY1", |
325 | "INTERNAL_UNIPHY2", |
325 | "INTERNAL_UNIPHY2", |
326 | "NUTMEG", |
326 | "NUTMEG", |
327 | "TRAVIS", |
327 | "TRAVIS", |
328 | }; |
328 | }; |
329 | 329 | ||
330 | static const char *connector_names[15] = { |
330 | static const char *connector_names[15] = { |
331 | "Unknown", |
331 | "Unknown", |
332 | "VGA", |
332 | "VGA", |
333 | "DVI-I", |
333 | "DVI-I", |
334 | "DVI-D", |
334 | "DVI-D", |
335 | "DVI-A", |
335 | "DVI-A", |
336 | "Composite", |
336 | "Composite", |
337 | "S-video", |
337 | "S-video", |
338 | "LVDS", |
338 | "LVDS", |
339 | "Component", |
339 | "Component", |
340 | "DIN", |
340 | "DIN", |
341 | "DisplayPort", |
341 | "DisplayPort", |
342 | "HDMI-A", |
342 | "HDMI-A", |
343 | "HDMI-B", |
343 | "HDMI-B", |
344 | "TV", |
344 | "TV", |
345 | "eDP", |
345 | "eDP", |
346 | }; |
346 | }; |
347 | 347 | ||
348 | static const char *hpd_names[6] = { |
348 | static const char *hpd_names[6] = { |
349 | "HPD1", |
349 | "HPD1", |
350 | "HPD2", |
350 | "HPD2", |
351 | "HPD3", |
351 | "HPD3", |
352 | "HPD4", |
352 | "HPD4", |
353 | "HPD5", |
353 | "HPD5", |
354 | "HPD6", |
354 | "HPD6", |
355 | }; |
355 | }; |
356 | 356 | ||
357 | static void radeon_print_display_setup(struct drm_device *dev) |
357 | static void radeon_print_display_setup(struct drm_device *dev) |
358 | { |
358 | { |
359 | struct drm_connector *connector; |
359 | struct drm_connector *connector; |
360 | struct radeon_connector *radeon_connector; |
360 | struct radeon_connector *radeon_connector; |
361 | struct drm_encoder *encoder; |
361 | struct drm_encoder *encoder; |
362 | struct radeon_encoder *radeon_encoder; |
362 | struct radeon_encoder *radeon_encoder; |
363 | uint32_t devices; |
363 | uint32_t devices; |
364 | int i = 0; |
364 | int i = 0; |
365 | 365 | ||
366 | DRM_INFO("Radeon Display Connectors\n"); |
366 | DRM_INFO("Radeon Display Connectors\n"); |
367 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
367 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
368 | radeon_connector = to_radeon_connector(connector); |
368 | radeon_connector = to_radeon_connector(connector); |
369 | DRM_INFO("Connector %d:\n", i); |
369 | DRM_INFO("Connector %d:\n", i); |
370 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
370 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
371 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
371 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
372 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
372 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
373 | if (radeon_connector->ddc_bus) { |
373 | if (radeon_connector->ddc_bus) { |
374 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
374 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
375 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
375 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
376 | radeon_connector->ddc_bus->rec.mask_data_reg, |
376 | radeon_connector->ddc_bus->rec.mask_data_reg, |
377 | radeon_connector->ddc_bus->rec.a_clk_reg, |
377 | radeon_connector->ddc_bus->rec.a_clk_reg, |
378 | radeon_connector->ddc_bus->rec.a_data_reg, |
378 | radeon_connector->ddc_bus->rec.a_data_reg, |
379 | radeon_connector->ddc_bus->rec.en_clk_reg, |
379 | radeon_connector->ddc_bus->rec.en_clk_reg, |
380 | radeon_connector->ddc_bus->rec.en_data_reg, |
380 | radeon_connector->ddc_bus->rec.en_data_reg, |
381 | radeon_connector->ddc_bus->rec.y_clk_reg, |
381 | radeon_connector->ddc_bus->rec.y_clk_reg, |
382 | radeon_connector->ddc_bus->rec.y_data_reg); |
382 | radeon_connector->ddc_bus->rec.y_data_reg); |
383 | if (radeon_connector->router.ddc_valid) |
383 | if (radeon_connector->router.ddc_valid) |
384 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
384 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
385 | radeon_connector->router.ddc_mux_control_pin, |
385 | radeon_connector->router.ddc_mux_control_pin, |
386 | radeon_connector->router.ddc_mux_state); |
386 | radeon_connector->router.ddc_mux_state); |
387 | if (radeon_connector->router.cd_valid) |
387 | if (radeon_connector->router.cd_valid) |
388 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
388 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
389 | radeon_connector->router.cd_mux_control_pin, |
389 | radeon_connector->router.cd_mux_control_pin, |
390 | radeon_connector->router.cd_mux_state); |
390 | radeon_connector->router.cd_mux_state); |
391 | } else { |
391 | } else { |
392 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
392 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
393 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
393 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
394 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
394 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
395 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
395 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
396 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
396 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
397 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
397 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
398 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
398 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
399 | } |
399 | } |
400 | DRM_INFO(" Encoders:\n"); |
400 | DRM_INFO(" Encoders:\n"); |
401 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
401 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
402 | radeon_encoder = to_radeon_encoder(encoder); |
402 | radeon_encoder = to_radeon_encoder(encoder); |
403 | devices = radeon_encoder->devices & radeon_connector->devices; |
403 | devices = radeon_encoder->devices & radeon_connector->devices; |
404 | if (devices) { |
404 | if (devices) { |
405 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
405 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
406 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
406 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
407 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
407 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
408 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
408 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
409 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
409 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
410 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
410 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
411 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
411 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
412 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
412 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
413 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
413 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
414 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
414 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
415 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
415 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
416 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
416 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
417 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
417 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
418 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
418 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
419 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
419 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
420 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
420 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
421 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
421 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
422 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
422 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
423 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
423 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
424 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
424 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
425 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
425 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
426 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
426 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
427 | } |
427 | } |
428 | } |
428 | } |
429 | i++; |
429 | i++; |
430 | } |
430 | } |
431 | } |
431 | } |
432 | 432 | ||
433 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
433 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
434 | { |
434 | { |
435 | struct radeon_device *rdev = dev->dev_private; |
435 | struct radeon_device *rdev = dev->dev_private; |
436 | struct drm_connector *drm_connector; |
436 | struct drm_connector *drm_connector; |
437 | bool ret = false; |
437 | bool ret = false; |
438 | 438 | ||
439 | if (rdev->bios) { |
439 | if (rdev->bios) { |
440 | if (rdev->is_atom_bios) { |
440 | if (rdev->is_atom_bios) { |
441 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
441 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
442 | if (ret == false) |
442 | if (ret == false) |
443 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
443 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
444 | } else { |
444 | } else { |
445 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
445 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
446 | if (ret == false) |
446 | if (ret == false) |
447 | ret = radeon_get_legacy_connector_info_from_table(dev); |
447 | ret = radeon_get_legacy_connector_info_from_table(dev); |
448 | } |
448 | } |
449 | } else { |
449 | } else { |
450 | if (!ASIC_IS_AVIVO(rdev)) |
450 | if (!ASIC_IS_AVIVO(rdev)) |
451 | ret = radeon_get_legacy_connector_info_from_table(dev); |
451 | ret = radeon_get_legacy_connector_info_from_table(dev); |
452 | } |
452 | } |
453 | if (ret) { |
453 | if (ret) { |
454 | radeon_setup_encoder_clones(dev); |
454 | radeon_setup_encoder_clones(dev); |
455 | radeon_print_display_setup(dev); |
455 | radeon_print_display_setup(dev); |
456 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
456 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
457 | radeon_ddc_dump(drm_connector); |
457 | radeon_ddc_dump(drm_connector); |
458 | } |
458 | } |
459 | 459 | ||
460 | return ret; |
460 | return ret; |
461 | } |
461 | } |
462 | 462 | ||
463 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
463 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
464 | { |
464 | { |
465 | struct drm_device *dev = radeon_connector->base.dev; |
465 | struct drm_device *dev = radeon_connector->base.dev; |
466 | struct radeon_device *rdev = dev->dev_private; |
466 | struct radeon_device *rdev = dev->dev_private; |
467 | int ret = 0; |
467 | int ret = 0; |
468 | 468 | ||
469 | /* on hw with routers, select right port */ |
469 | /* on hw with routers, select right port */ |
470 | if (radeon_connector->router.ddc_valid) |
470 | if (radeon_connector->router.ddc_valid) |
471 | radeon_router_select_ddc_port(radeon_connector); |
471 | radeon_router_select_ddc_port(radeon_connector); |
472 | 472 | ||
473 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
473 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
474 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
474 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
475 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
475 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
476 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
476 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
477 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
477 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
478 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
478 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
479 | } |
479 | } |
480 | if (!radeon_connector->ddc_bus) |
480 | if (!radeon_connector->ddc_bus) |
481 | return -1; |
481 | return -1; |
482 | if (!radeon_connector->edid) { |
482 | if (!radeon_connector->edid) { |
483 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
483 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
484 | } |
484 | } |
485 | 485 | ||
486 | if (!radeon_connector->edid) { |
486 | if (!radeon_connector->edid) { |
487 | if (rdev->is_atom_bios) { |
487 | if (rdev->is_atom_bios) { |
488 | /* some laptops provide a hardcoded edid in rom for LCDs */ |
488 | /* some laptops provide a hardcoded edid in rom for LCDs */ |
489 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || |
489 | if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) || |
490 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) |
490 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP))) |
491 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
491 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
492 | } else |
492 | } else |
493 | /* some servers provide a hardcoded edid in rom for KVMs */ |
493 | /* some servers provide a hardcoded edid in rom for KVMs */ |
494 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
494 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); |
495 | } |
495 | } |
496 | if (radeon_connector->edid) { |
496 | if (radeon_connector->edid) { |
497 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
497 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
498 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
498 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
499 | return ret; |
499 | return ret; |
500 | } |
500 | } |
501 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
501 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
502 | return 0; |
502 | return 0; |
503 | } |
503 | } |
504 | 504 | ||
505 | static int radeon_ddc_dump(struct drm_connector *connector) |
505 | static int radeon_ddc_dump(struct drm_connector *connector) |
506 | { |
506 | { |
507 | struct edid *edid; |
507 | struct edid *edid; |
508 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
508 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
509 | int ret = 0; |
509 | int ret = 0; |
510 | 510 | ||
511 | /* on hw with routers, select right port */ |
511 | /* on hw with routers, select right port */ |
512 | if (radeon_connector->router.ddc_valid) |
512 | if (radeon_connector->router.ddc_valid) |
513 | radeon_router_select_ddc_port(radeon_connector); |
513 | radeon_router_select_ddc_port(radeon_connector); |
514 | 514 | ||
515 | if (!radeon_connector->ddc_bus) |
515 | if (!radeon_connector->ddc_bus) |
516 | return -1; |
516 | return -1; |
517 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
517 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
- | 518 | /* Log EDID retrieval status here. In particular with regard to |
|
- | 519 | * connectors with requires_extended_probe flag set, that will prevent |
|
- | 520 | * function radeon_dvi_detect() to fetch EDID on this connector, |
|
- | 521 | * as long as there is no valid EDID header found */ |
|
518 | if (edid) { |
522 | if (edid) { |
- | 523 | DRM_INFO("Radeon display connector %s: Found valid EDID", |
|
- | 524 | drm_get_connector_name(connector)); |
|
519 | kfree(edid); |
525 | kfree(edid); |
- | 526 | } else { |
|
- | 527 | DRM_INFO("Radeon display connector %s: No monitor connected or invalid EDID", |
|
- | 528 | drm_get_connector_name(connector)); |
|
520 | } |
529 | } |
521 | return ret; |
530 | return ret; |
522 | } |
531 | } |
523 | 532 | ||
524 | /* avivo */ |
533 | /* avivo */ |
525 | static void avivo_get_fb_div(struct radeon_pll *pll, |
534 | static void avivo_get_fb_div(struct radeon_pll *pll, |
526 | u32 target_clock, |
535 | u32 target_clock, |
527 | u32 post_div, |
536 | u32 post_div, |
528 | u32 ref_div, |
537 | u32 ref_div, |
529 | u32 *fb_div, |
538 | u32 *fb_div, |
530 | u32 *frac_fb_div) |
539 | u32 *frac_fb_div) |
531 | { |
540 | { |
532 | u32 tmp = post_div * ref_div; |
541 | u32 tmp = post_div * ref_div; |
533 | 542 | ||
534 | tmp *= target_clock; |
543 | tmp *= target_clock; |
535 | *fb_div = tmp / pll->reference_freq; |
544 | *fb_div = tmp / pll->reference_freq; |
536 | *frac_fb_div = tmp % pll->reference_freq; |
545 | *frac_fb_div = tmp % pll->reference_freq; |
537 | 546 | ||
538 | if (*fb_div > pll->max_feedback_div) |
547 | if (*fb_div > pll->max_feedback_div) |
539 | *fb_div = pll->max_feedback_div; |
548 | *fb_div = pll->max_feedback_div; |
540 | else if (*fb_div < pll->min_feedback_div) |
549 | else if (*fb_div < pll->min_feedback_div) |
541 | *fb_div = pll->min_feedback_div; |
550 | *fb_div = pll->min_feedback_div; |
542 | } |
551 | } |
543 | 552 | ||
544 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
553 | static u32 avivo_get_post_div(struct radeon_pll *pll, |
545 | u32 target_clock) |
554 | u32 target_clock) |
546 | { |
555 | { |
547 | u32 vco, post_div, tmp; |
556 | u32 vco, post_div, tmp; |
548 | 557 | ||
549 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
558 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
550 | return pll->post_div; |
559 | return pll->post_div; |
551 | 560 | ||
552 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
561 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
553 | if (pll->flags & RADEON_PLL_IS_LCD) |
562 | if (pll->flags & RADEON_PLL_IS_LCD) |
554 | vco = pll->lcd_pll_out_min; |
563 | vco = pll->lcd_pll_out_min; |
555 | else |
564 | else |
556 | vco = pll->pll_out_min; |
565 | vco = pll->pll_out_min; |
557 | } else { |
566 | } else { |
558 | if (pll->flags & RADEON_PLL_IS_LCD) |
567 | if (pll->flags & RADEON_PLL_IS_LCD) |
559 | vco = pll->lcd_pll_out_max; |
568 | vco = pll->lcd_pll_out_max; |
560 | else |
569 | else |
561 | vco = pll->pll_out_max; |
570 | vco = pll->pll_out_max; |
562 | } |
571 | } |
563 | 572 | ||
564 | post_div = vco / target_clock; |
573 | post_div = vco / target_clock; |
565 | tmp = vco % target_clock; |
574 | tmp = vco % target_clock; |
566 | 575 | ||
567 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
576 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) { |
568 | if (tmp) |
577 | if (tmp) |
569 | post_div++; |
578 | post_div++; |
570 | } else { |
579 | } else { |
571 | if (!tmp) |
580 | if (!tmp) |
572 | post_div--; |
581 | post_div--; |
573 | } |
582 | } |
574 | 583 | ||
575 | if (post_div > pll->max_post_div) |
584 | if (post_div > pll->max_post_div) |
576 | post_div = pll->max_post_div; |
585 | post_div = pll->max_post_div; |
577 | else if (post_div < pll->min_post_div) |
586 | else if (post_div < pll->min_post_div) |
578 | post_div = pll->min_post_div; |
587 | post_div = pll->min_post_div; |
579 | 588 | ||
580 | return post_div; |
589 | return post_div; |
581 | } |
590 | } |
582 | 591 | ||
583 | #define MAX_TOLERANCE 10 |
592 | #define MAX_TOLERANCE 10 |
584 | 593 | ||
585 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
594 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
586 | u32 freq, |
595 | u32 freq, |
587 | u32 *dot_clock_p, |
596 | u32 *dot_clock_p, |
588 | u32 *fb_div_p, |
597 | u32 *fb_div_p, |
589 | u32 *frac_fb_div_p, |
598 | u32 *frac_fb_div_p, |
590 | u32 *ref_div_p, |
599 | u32 *ref_div_p, |
591 | u32 *post_div_p) |
600 | u32 *post_div_p) |
592 | { |
601 | { |
593 | u32 target_clock = freq / 10; |
602 | u32 target_clock = freq / 10; |
594 | u32 post_div = avivo_get_post_div(pll, target_clock); |
603 | u32 post_div = avivo_get_post_div(pll, target_clock); |
595 | u32 ref_div = pll->min_ref_div; |
604 | u32 ref_div = pll->min_ref_div; |
596 | u32 fb_div = 0, frac_fb_div = 0, tmp; |
605 | u32 fb_div = 0, frac_fb_div = 0, tmp; |
597 | 606 | ||
598 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
607 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
599 | ref_div = pll->reference_div; |
608 | ref_div = pll->reference_div; |
600 | 609 | ||
601 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
610 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
602 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); |
611 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); |
603 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; |
612 | frac_fb_div = (100 * frac_fb_div) / pll->reference_freq; |
604 | if (frac_fb_div >= 5) { |
613 | if (frac_fb_div >= 5) { |
605 | frac_fb_div -= 5; |
614 | frac_fb_div -= 5; |
606 | frac_fb_div = frac_fb_div / 10; |
615 | frac_fb_div = frac_fb_div / 10; |
607 | frac_fb_div++; |
616 | frac_fb_div++; |
608 | } |
617 | } |
609 | if (frac_fb_div >= 10) { |
618 | if (frac_fb_div >= 10) { |
610 | fb_div++; |
619 | fb_div++; |
611 | frac_fb_div = 0; |
620 | frac_fb_div = 0; |
612 | } |
621 | } |
613 | } else { |
622 | } else { |
614 | while (ref_div <= pll->max_ref_div) { |
623 | while (ref_div <= pll->max_ref_div) { |
615 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, |
624 | avivo_get_fb_div(pll, target_clock, post_div, ref_div, |
616 | &fb_div, &frac_fb_div); |
625 | &fb_div, &frac_fb_div); |
617 | if (frac_fb_div >= (pll->reference_freq / 2)) |
626 | if (frac_fb_div >= (pll->reference_freq / 2)) |
618 | fb_div++; |
627 | fb_div++; |
619 | frac_fb_div = 0; |
628 | frac_fb_div = 0; |
620 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); |
629 | tmp = (pll->reference_freq * fb_div) / (post_div * ref_div); |
621 | tmp = (tmp * 10000) / target_clock; |
630 | tmp = (tmp * 10000) / target_clock; |
622 | 631 | ||
623 | if (tmp > (10000 + MAX_TOLERANCE)) |
632 | if (tmp > (10000 + MAX_TOLERANCE)) |
624 | ref_div++; |
633 | ref_div++; |
625 | else if (tmp >= (10000 - MAX_TOLERANCE)) |
634 | else if (tmp >= (10000 - MAX_TOLERANCE)) |
626 | break; |
635 | break; |
627 | else |
636 | else |
628 | ref_div++; |
637 | ref_div++; |
629 | } |
638 | } |
630 | } |
639 | } |
631 | 640 | ||
632 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / |
641 | *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / |
633 | (ref_div * post_div * 10); |
642 | (ref_div * post_div * 10); |
634 | *fb_div_p = fb_div; |
643 | *fb_div_p = fb_div; |
635 | *frac_fb_div_p = frac_fb_div; |
644 | *frac_fb_div_p = frac_fb_div; |
636 | *ref_div_p = ref_div; |
645 | *ref_div_p = ref_div; |
637 | *post_div_p = post_div; |
646 | *post_div_p = post_div; |
638 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
647 | DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
639 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); |
648 | *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div); |
640 | } |
649 | } |
641 | 650 | ||
642 | /* pre-avivo */ |
651 | /* pre-avivo */ |
643 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
652 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
644 | { |
653 | { |
645 | uint64_t mod; |
654 | uint64_t mod; |
646 | 655 | ||
647 | n += d / 2; |
656 | n += d / 2; |
648 | 657 | ||
649 | mod = do_div(n, d); |
658 | mod = do_div(n, d); |
650 | return n; |
659 | return n; |
651 | } |
660 | } |
652 | 661 | ||
653 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
662 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
654 | uint64_t freq, |
663 | uint64_t freq, |
655 | uint32_t *dot_clock_p, |
664 | uint32_t *dot_clock_p, |
656 | uint32_t *fb_div_p, |
665 | uint32_t *fb_div_p, |
657 | uint32_t *frac_fb_div_p, |
666 | uint32_t *frac_fb_div_p, |
658 | uint32_t *ref_div_p, |
667 | uint32_t *ref_div_p, |
659 | uint32_t *post_div_p) |
668 | uint32_t *post_div_p) |
660 | { |
669 | { |
661 | uint32_t min_ref_div = pll->min_ref_div; |
670 | uint32_t min_ref_div = pll->min_ref_div; |
662 | uint32_t max_ref_div = pll->max_ref_div; |
671 | uint32_t max_ref_div = pll->max_ref_div; |
663 | uint32_t min_post_div = pll->min_post_div; |
672 | uint32_t min_post_div = pll->min_post_div; |
664 | uint32_t max_post_div = pll->max_post_div; |
673 | uint32_t max_post_div = pll->max_post_div; |
665 | uint32_t min_fractional_feed_div = 0; |
674 | uint32_t min_fractional_feed_div = 0; |
666 | uint32_t max_fractional_feed_div = 0; |
675 | uint32_t max_fractional_feed_div = 0; |
667 | uint32_t best_vco = pll->best_vco; |
676 | uint32_t best_vco = pll->best_vco; |
668 | uint32_t best_post_div = 1; |
677 | uint32_t best_post_div = 1; |
669 | uint32_t best_ref_div = 1; |
678 | uint32_t best_ref_div = 1; |
670 | uint32_t best_feedback_div = 1; |
679 | uint32_t best_feedback_div = 1; |
671 | uint32_t best_frac_feedback_div = 0; |
680 | uint32_t best_frac_feedback_div = 0; |
672 | uint32_t best_freq = -1; |
681 | uint32_t best_freq = -1; |
673 | uint32_t best_error = 0xffffffff; |
682 | uint32_t best_error = 0xffffffff; |
674 | uint32_t best_vco_diff = 1; |
683 | uint32_t best_vco_diff = 1; |
675 | uint32_t post_div; |
684 | uint32_t post_div; |
676 | u32 pll_out_min, pll_out_max; |
685 | u32 pll_out_min, pll_out_max; |
677 | 686 | ||
678 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
687 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
679 | freq = freq * 1000; |
688 | freq = freq * 1000; |
680 | 689 | ||
681 | if (pll->flags & RADEON_PLL_IS_LCD) { |
690 | if (pll->flags & RADEON_PLL_IS_LCD) { |
682 | pll_out_min = pll->lcd_pll_out_min; |
691 | pll_out_min = pll->lcd_pll_out_min; |
683 | pll_out_max = pll->lcd_pll_out_max; |
692 | pll_out_max = pll->lcd_pll_out_max; |
684 | } else { |
693 | } else { |
685 | pll_out_min = pll->pll_out_min; |
694 | pll_out_min = pll->pll_out_min; |
686 | pll_out_max = pll->pll_out_max; |
695 | pll_out_max = pll->pll_out_max; |
687 | } |
696 | } |
688 | 697 | ||
689 | if (pll_out_min > 64800) |
698 | if (pll_out_min > 64800) |
690 | pll_out_min = 64800; |
699 | pll_out_min = 64800; |
691 | 700 | ||
692 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
701 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
693 | min_ref_div = max_ref_div = pll->reference_div; |
702 | min_ref_div = max_ref_div = pll->reference_div; |
694 | else { |
703 | else { |
695 | while (min_ref_div < max_ref_div-1) { |
704 | while (min_ref_div < max_ref_div-1) { |
696 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
705 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
697 | uint32_t pll_in = pll->reference_freq / mid; |
706 | uint32_t pll_in = pll->reference_freq / mid; |
698 | if (pll_in < pll->pll_in_min) |
707 | if (pll_in < pll->pll_in_min) |
699 | max_ref_div = mid; |
708 | max_ref_div = mid; |
700 | else if (pll_in > pll->pll_in_max) |
709 | else if (pll_in > pll->pll_in_max) |
701 | min_ref_div = mid; |
710 | min_ref_div = mid; |
702 | else |
711 | else |
703 | break; |
712 | break; |
704 | } |
713 | } |
705 | } |
714 | } |
706 | 715 | ||
707 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
716 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
708 | min_post_div = max_post_div = pll->post_div; |
717 | min_post_div = max_post_div = pll->post_div; |
709 | 718 | ||
710 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
719 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
711 | min_fractional_feed_div = pll->min_frac_feedback_div; |
720 | min_fractional_feed_div = pll->min_frac_feedback_div; |
712 | max_fractional_feed_div = pll->max_frac_feedback_div; |
721 | max_fractional_feed_div = pll->max_frac_feedback_div; |
713 | } |
722 | } |
714 | 723 | ||
715 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
724 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
716 | uint32_t ref_div; |
725 | uint32_t ref_div; |
717 | 726 | ||
718 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
727 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
719 | continue; |
728 | continue; |
720 | 729 | ||
721 | /* legacy radeons only have a few post_divs */ |
730 | /* legacy radeons only have a few post_divs */ |
722 | if (pll->flags & RADEON_PLL_LEGACY) { |
731 | if (pll->flags & RADEON_PLL_LEGACY) { |
723 | if ((post_div == 5) || |
732 | if ((post_div == 5) || |
724 | (post_div == 7) || |
733 | (post_div == 7) || |
725 | (post_div == 9) || |
734 | (post_div == 9) || |
726 | (post_div == 10) || |
735 | (post_div == 10) || |
727 | (post_div == 11) || |
736 | (post_div == 11) || |
728 | (post_div == 13) || |
737 | (post_div == 13) || |
729 | (post_div == 14) || |
738 | (post_div == 14) || |
730 | (post_div == 15)) |
739 | (post_div == 15)) |
731 | continue; |
740 | continue; |
732 | } |
741 | } |
733 | 742 | ||
734 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
743 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
735 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
744 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
736 | uint32_t pll_in = pll->reference_freq / ref_div; |
745 | uint32_t pll_in = pll->reference_freq / ref_div; |
737 | uint32_t min_feed_div = pll->min_feedback_div; |
746 | uint32_t min_feed_div = pll->min_feedback_div; |
738 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
747 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
739 | 748 | ||
740 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
749 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
741 | continue; |
750 | continue; |
742 | 751 | ||
743 | while (min_feed_div < max_feed_div) { |
752 | while (min_feed_div < max_feed_div) { |
744 | uint32_t vco; |
753 | uint32_t vco; |
745 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
754 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
746 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
755 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
747 | uint32_t frac_feedback_div; |
756 | uint32_t frac_feedback_div; |
748 | uint64_t tmp; |
757 | uint64_t tmp; |
749 | 758 | ||
750 | feedback_div = (min_feed_div + max_feed_div) / 2; |
759 | feedback_div = (min_feed_div + max_feed_div) / 2; |
751 | 760 | ||
752 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
761 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
753 | vco = radeon_div(tmp, ref_div); |
762 | vco = radeon_div(tmp, ref_div); |
754 | 763 | ||
755 | if (vco < pll_out_min) { |
764 | if (vco < pll_out_min) { |
756 | min_feed_div = feedback_div + 1; |
765 | min_feed_div = feedback_div + 1; |
757 | continue; |
766 | continue; |
758 | } else if (vco > pll_out_max) { |
767 | } else if (vco > pll_out_max) { |
759 | max_feed_div = feedback_div; |
768 | max_feed_div = feedback_div; |
760 | continue; |
769 | continue; |
761 | } |
770 | } |
762 | 771 | ||
763 | while (min_frac_feed_div < max_frac_feed_div) { |
772 | while (min_frac_feed_div < max_frac_feed_div) { |
764 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
773 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
765 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
774 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
766 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
775 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
767 | current_freq = radeon_div(tmp, ref_div * post_div); |
776 | current_freq = radeon_div(tmp, ref_div * post_div); |
768 | 777 | ||
769 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
778 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
770 | if (freq < current_freq) |
779 | if (freq < current_freq) |
771 | error = 0xffffffff; |
780 | error = 0xffffffff; |
772 | else |
781 | else |
773 | error = freq - current_freq; |
782 | error = freq - current_freq; |
774 | } else |
783 | } else |
775 | error = abs(current_freq - freq); |
784 | error = abs(current_freq - freq); |
776 | vco_diff = abs(vco - best_vco); |
785 | vco_diff = abs(vco - best_vco); |
777 | 786 | ||
778 | if ((best_vco == 0 && error < best_error) || |
787 | if ((best_vco == 0 && error < best_error) || |
779 | (best_vco != 0 && |
788 | (best_vco != 0 && |
780 | ((best_error > 100 && error < best_error - 100) || |
789 | ((best_error > 100 && error < best_error - 100) || |
781 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
790 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
782 | best_post_div = post_div; |
791 | best_post_div = post_div; |
783 | best_ref_div = ref_div; |
792 | best_ref_div = ref_div; |
784 | best_feedback_div = feedback_div; |
793 | best_feedback_div = feedback_div; |
785 | best_frac_feedback_div = frac_feedback_div; |
794 | best_frac_feedback_div = frac_feedback_div; |
786 | best_freq = current_freq; |
795 | best_freq = current_freq; |
787 | best_error = error; |
796 | best_error = error; |
788 | best_vco_diff = vco_diff; |
797 | best_vco_diff = vco_diff; |
789 | } else if (current_freq == freq) { |
798 | } else if (current_freq == freq) { |
790 | if (best_freq == -1) { |
799 | if (best_freq == -1) { |
791 | best_post_div = post_div; |
800 | best_post_div = post_div; |
792 | best_ref_div = ref_div; |
801 | best_ref_div = ref_div; |
793 | best_feedback_div = feedback_div; |
802 | best_feedback_div = feedback_div; |
794 | best_frac_feedback_div = frac_feedback_div; |
803 | best_frac_feedback_div = frac_feedback_div; |
795 | best_freq = current_freq; |
804 | best_freq = current_freq; |
796 | best_error = error; |
805 | best_error = error; |
797 | best_vco_diff = vco_diff; |
806 | best_vco_diff = vco_diff; |
798 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
807 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
799 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
808 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
800 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
809 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
801 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
810 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
802 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
811 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
803 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
812 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
804 | best_post_div = post_div; |
813 | best_post_div = post_div; |
805 | best_ref_div = ref_div; |
814 | best_ref_div = ref_div; |
806 | best_feedback_div = feedback_div; |
815 | best_feedback_div = feedback_div; |
807 | best_frac_feedback_div = frac_feedback_div; |
816 | best_frac_feedback_div = frac_feedback_div; |
808 | best_freq = current_freq; |
817 | best_freq = current_freq; |
809 | best_error = error; |
818 | best_error = error; |
810 | best_vco_diff = vco_diff; |
819 | best_vco_diff = vco_diff; |
811 | } |
820 | } |
812 | } |
821 | } |
813 | if (current_freq < freq) |
822 | if (current_freq < freq) |
814 | min_frac_feed_div = frac_feedback_div + 1; |
823 | min_frac_feed_div = frac_feedback_div + 1; |
815 | else |
824 | else |
816 | max_frac_feed_div = frac_feedback_div; |
825 | max_frac_feed_div = frac_feedback_div; |
817 | } |
826 | } |
818 | if (current_freq < freq) |
827 | if (current_freq < freq) |
819 | min_feed_div = feedback_div + 1; |
828 | min_feed_div = feedback_div + 1; |
820 | else |
829 | else |
821 | max_feed_div = feedback_div; |
830 | max_feed_div = feedback_div; |
822 | } |
831 | } |
823 | } |
832 | } |
824 | } |
833 | } |
825 | 834 | ||
826 | *dot_clock_p = best_freq / 10000; |
835 | *dot_clock_p = best_freq / 10000; |
827 | *fb_div_p = best_feedback_div; |
836 | *fb_div_p = best_feedback_div; |
828 | *frac_fb_div_p = best_frac_feedback_div; |
837 | *frac_fb_div_p = best_frac_feedback_div; |
829 | *ref_div_p = best_ref_div; |
838 | *ref_div_p = best_ref_div; |
830 | *post_div_p = best_post_div; |
839 | *post_div_p = best_post_div; |
831 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
840 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
832 | (long long)freq, |
841 | (long long)freq, |
833 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
842 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
834 | best_ref_div, best_post_div); |
843 | best_ref_div, best_post_div); |
835 | 844 | ||
836 | } |
845 | } |
837 | 846 | ||
838 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
847 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
839 | { |
848 | { |
840 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
849 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
841 | 850 | ||
842 | drm_framebuffer_cleanup(fb); |
851 | drm_framebuffer_cleanup(fb); |
843 | kfree(radeon_fb); |
852 | kfree(radeon_fb); |
844 | } |
853 | } |
845 | 854 | ||
846 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
855 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
847 | struct drm_file *file_priv, |
856 | struct drm_file *file_priv, |
848 | unsigned int *handle) |
857 | unsigned int *handle) |
849 | { |
858 | { |
850 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
859 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
851 | 860 | ||
852 | return NULL; |
861 | return NULL; |
853 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
862 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
854 | } |
863 | } |
855 | 864 | ||
856 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
865 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
857 | .destroy = radeon_user_framebuffer_destroy, |
866 | .destroy = radeon_user_framebuffer_destroy, |
858 | .create_handle = radeon_user_framebuffer_create_handle, |
867 | .create_handle = radeon_user_framebuffer_create_handle, |
859 | }; |
868 | }; |
860 | 869 | ||
861 | void |
870 | void |
862 | radeon_framebuffer_init(struct drm_device *dev, |
871 | radeon_framebuffer_init(struct drm_device *dev, |
863 | struct radeon_framebuffer *rfb, |
872 | struct radeon_framebuffer *rfb, |
864 | struct drm_mode_fb_cmd *mode_cmd, |
873 | struct drm_mode_fb_cmd *mode_cmd, |
865 | struct drm_gem_object *obj) |
874 | struct drm_gem_object *obj) |
866 | { |
875 | { |
867 | rfb->obj = obj; |
876 | rfb->obj = obj; |
868 | drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
877 | drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
869 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
878 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
870 | } |
879 | } |
871 | 880 | ||
872 | 881 | ||
873 | 882 | ||
874 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
883 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
875 | // .fb_create = radeon_user_framebuffer_create, |
884 | // .fb_create = radeon_user_framebuffer_create, |
876 | // .output_poll_changed = radeon_output_poll_changed |
885 | // .output_poll_changed = radeon_output_poll_changed |
877 | }; |
886 | }; |
878 | 887 | ||
879 | struct drm_prop_enum_list { |
888 | struct drm_prop_enum_list { |
880 | int type; |
889 | int type; |
881 | char *name; |
890 | char *name; |
882 | }; |
891 | }; |
883 | 892 | ||
884 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
893 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
885 | { { 0, "driver" }, |
894 | { { 0, "driver" }, |
886 | { 1, "bios" }, |
895 | { 1, "bios" }, |
887 | }; |
896 | }; |
888 | 897 | ||
889 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
898 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
890 | { { TV_STD_NTSC, "ntsc" }, |
899 | { { TV_STD_NTSC, "ntsc" }, |
891 | { TV_STD_PAL, "pal" }, |
900 | { TV_STD_PAL, "pal" }, |
892 | { TV_STD_PAL_M, "pal-m" }, |
901 | { TV_STD_PAL_M, "pal-m" }, |
893 | { TV_STD_PAL_60, "pal-60" }, |
902 | { TV_STD_PAL_60, "pal-60" }, |
894 | { TV_STD_NTSC_J, "ntsc-j" }, |
903 | { TV_STD_NTSC_J, "ntsc-j" }, |
895 | { TV_STD_SCART_PAL, "scart-pal" }, |
904 | { TV_STD_SCART_PAL, "scart-pal" }, |
896 | { TV_STD_PAL_CN, "pal-cn" }, |
905 | { TV_STD_PAL_CN, "pal-cn" }, |
897 | { TV_STD_SECAM, "secam" }, |
906 | { TV_STD_SECAM, "secam" }, |
898 | }; |
907 | }; |
899 | 908 | ||
900 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
909 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
901 | { { UNDERSCAN_OFF, "off" }, |
910 | { { UNDERSCAN_OFF, "off" }, |
902 | { UNDERSCAN_ON, "on" }, |
911 | { UNDERSCAN_ON, "on" }, |
903 | { UNDERSCAN_AUTO, "auto" }, |
912 | { UNDERSCAN_AUTO, "auto" }, |
904 | }; |
913 | }; |
905 | 914 | ||
906 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
915 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
907 | { |
916 | { |
908 | int i, sz; |
917 | int i, sz; |
909 | 918 | ||
910 | if (rdev->is_atom_bios) { |
919 | if (rdev->is_atom_bios) { |
911 | rdev->mode_info.coherent_mode_property = |
920 | rdev->mode_info.coherent_mode_property = |
912 | drm_property_create(rdev->ddev, |
921 | drm_property_create(rdev->ddev, |
913 | DRM_MODE_PROP_RANGE, |
922 | DRM_MODE_PROP_RANGE, |
914 | "coherent", 2); |
923 | "coherent", 2); |
915 | if (!rdev->mode_info.coherent_mode_property) |
924 | if (!rdev->mode_info.coherent_mode_property) |
916 | return -ENOMEM; |
925 | return -ENOMEM; |
917 | 926 | ||
918 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
927 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
919 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
928 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
920 | } |
929 | } |
921 | 930 | ||
922 | if (!ASIC_IS_AVIVO(rdev)) { |
931 | if (!ASIC_IS_AVIVO(rdev)) { |
923 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
932 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
924 | rdev->mode_info.tmds_pll_property = |
933 | rdev->mode_info.tmds_pll_property = |
925 | drm_property_create(rdev->ddev, |
934 | drm_property_create(rdev->ddev, |
926 | DRM_MODE_PROP_ENUM, |
935 | DRM_MODE_PROP_ENUM, |
927 | "tmds_pll", sz); |
936 | "tmds_pll", sz); |
928 | for (i = 0; i < sz; i++) { |
937 | for (i = 0; i < sz; i++) { |
929 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
938 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
930 | i, |
939 | i, |
931 | radeon_tmds_pll_enum_list[i].type, |
940 | radeon_tmds_pll_enum_list[i].type, |
932 | radeon_tmds_pll_enum_list[i].name); |
941 | radeon_tmds_pll_enum_list[i].name); |
933 | } |
942 | } |
934 | } |
943 | } |
935 | 944 | ||
936 | rdev->mode_info.load_detect_property = |
945 | rdev->mode_info.load_detect_property = |
937 | drm_property_create(rdev->ddev, |
946 | drm_property_create(rdev->ddev, |
938 | DRM_MODE_PROP_RANGE, |
947 | DRM_MODE_PROP_RANGE, |
939 | "load detection", 2); |
948 | "load detection", 2); |
940 | if (!rdev->mode_info.load_detect_property) |
949 | if (!rdev->mode_info.load_detect_property) |
941 | return -ENOMEM; |
950 | return -ENOMEM; |
942 | rdev->mode_info.load_detect_property->values[0] = 0; |
951 | rdev->mode_info.load_detect_property->values[0] = 0; |
943 | rdev->mode_info.load_detect_property->values[1] = 1; |
952 | rdev->mode_info.load_detect_property->values[1] = 1; |
944 | 953 | ||
945 | drm_mode_create_scaling_mode_property(rdev->ddev); |
954 | drm_mode_create_scaling_mode_property(rdev->ddev); |
946 | 955 | ||
947 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
956 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
948 | rdev->mode_info.tv_std_property = |
957 | rdev->mode_info.tv_std_property = |
949 | drm_property_create(rdev->ddev, |
958 | drm_property_create(rdev->ddev, |
950 | DRM_MODE_PROP_ENUM, |
959 | DRM_MODE_PROP_ENUM, |
951 | "tv standard", sz); |
960 | "tv standard", sz); |
952 | for (i = 0; i < sz; i++) { |
961 | for (i = 0; i < sz; i++) { |
953 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
962 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
954 | i, |
963 | i, |
955 | radeon_tv_std_enum_list[i].type, |
964 | radeon_tv_std_enum_list[i].type, |
956 | radeon_tv_std_enum_list[i].name); |
965 | radeon_tv_std_enum_list[i].name); |
957 | } |
966 | } |
958 | 967 | ||
959 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
968 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
960 | rdev->mode_info.underscan_property = |
969 | rdev->mode_info.underscan_property = |
961 | drm_property_create(rdev->ddev, |
970 | drm_property_create(rdev->ddev, |
962 | DRM_MODE_PROP_ENUM, |
971 | DRM_MODE_PROP_ENUM, |
963 | "underscan", sz); |
972 | "underscan", sz); |
964 | for (i = 0; i < sz; i++) { |
973 | for (i = 0; i < sz; i++) { |
965 | drm_property_add_enum(rdev->mode_info.underscan_property, |
974 | drm_property_add_enum(rdev->mode_info.underscan_property, |
966 | i, |
975 | i, |
967 | radeon_underscan_enum_list[i].type, |
976 | radeon_underscan_enum_list[i].type, |
968 | radeon_underscan_enum_list[i].name); |
977 | radeon_underscan_enum_list[i].name); |
969 | } |
978 | } |
970 | 979 | ||
971 | rdev->mode_info.underscan_hborder_property = |
980 | rdev->mode_info.underscan_hborder_property = |
972 | drm_property_create(rdev->ddev, |
981 | drm_property_create(rdev->ddev, |
973 | DRM_MODE_PROP_RANGE, |
982 | DRM_MODE_PROP_RANGE, |
974 | "underscan hborder", 2); |
983 | "underscan hborder", 2); |
975 | if (!rdev->mode_info.underscan_hborder_property) |
984 | if (!rdev->mode_info.underscan_hborder_property) |
976 | return -ENOMEM; |
985 | return -ENOMEM; |
977 | rdev->mode_info.underscan_hborder_property->values[0] = 0; |
986 | rdev->mode_info.underscan_hborder_property->values[0] = 0; |
978 | rdev->mode_info.underscan_hborder_property->values[1] = 128; |
987 | rdev->mode_info.underscan_hborder_property->values[1] = 128; |
979 | 988 | ||
980 | rdev->mode_info.underscan_vborder_property = |
989 | rdev->mode_info.underscan_vborder_property = |
981 | drm_property_create(rdev->ddev, |
990 | drm_property_create(rdev->ddev, |
982 | DRM_MODE_PROP_RANGE, |
991 | DRM_MODE_PROP_RANGE, |
983 | "underscan vborder", 2); |
992 | "underscan vborder", 2); |
984 | if (!rdev->mode_info.underscan_vborder_property) |
993 | if (!rdev->mode_info.underscan_vborder_property) |
985 | return -ENOMEM; |
994 | return -ENOMEM; |
986 | rdev->mode_info.underscan_vborder_property->values[0] = 0; |
995 | rdev->mode_info.underscan_vborder_property->values[0] = 0; |
987 | rdev->mode_info.underscan_vborder_property->values[1] = 128; |
996 | rdev->mode_info.underscan_vborder_property->values[1] = 128; |
988 | 997 | ||
989 | return 0; |
998 | return 0; |
990 | } |
999 | } |
991 | 1000 | ||
992 | void radeon_update_display_priority(struct radeon_device *rdev) |
1001 | void radeon_update_display_priority(struct radeon_device *rdev) |
993 | { |
1002 | { |
994 | /* adjustment options for the display watermarks */ |
1003 | /* adjustment options for the display watermarks */ |
995 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
1004 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
996 | /* set display priority to high for r3xx, rv515 chips |
1005 | /* set display priority to high for r3xx, rv515 chips |
997 | * this avoids flickering due to underflow to the |
1006 | * this avoids flickering due to underflow to the |
998 | * display controllers during heavy acceleration. |
1007 | * display controllers during heavy acceleration. |
999 | * Don't force high on rs4xx igp chips as it seems to |
1008 | * Don't force high on rs4xx igp chips as it seems to |
1000 | * affect the sound card. See kernel bug 15982. |
1009 | * affect the sound card. See kernel bug 15982. |
1001 | */ |
1010 | */ |
1002 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1011 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
1003 | !(rdev->flags & RADEON_IS_IGP)) |
1012 | !(rdev->flags & RADEON_IS_IGP)) |
1004 | rdev->disp_priority = 2; |
1013 | rdev->disp_priority = 2; |
1005 | else |
1014 | else |
1006 | rdev->disp_priority = 0; |
1015 | rdev->disp_priority = 0; |
1007 | } else |
1016 | } else |
1008 | rdev->disp_priority = radeon_disp_priority; |
1017 | rdev->disp_priority = radeon_disp_priority; |
1009 | 1018 | ||
1010 | } |
1019 | } |
1011 | 1020 | ||
1012 | int radeon_modeset_init(struct radeon_device *rdev) |
1021 | int radeon_modeset_init(struct radeon_device *rdev) |
1013 | { |
1022 | { |
1014 | int i; |
1023 | int i; |
1015 | int ret; |
1024 | int ret; |
1016 | - | ||
1017 | ENTER(); |
- | |
1018 | 1025 | ||
1019 | drm_mode_config_init(rdev->ddev); |
1026 | drm_mode_config_init(rdev->ddev); |
1020 | rdev->mode_info.mode_config_initialized = true; |
1027 | rdev->mode_info.mode_config_initialized = true; |
1021 | 1028 | ||
1022 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1029 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1023 | 1030 | ||
1024 | if (ASIC_IS_DCE5(rdev)) { |
1031 | if (ASIC_IS_DCE5(rdev)) { |
1025 | rdev->ddev->mode_config.max_width = 16384; |
1032 | rdev->ddev->mode_config.max_width = 16384; |
1026 | rdev->ddev->mode_config.max_height = 16384; |
1033 | rdev->ddev->mode_config.max_height = 16384; |
1027 | } else if (ASIC_IS_AVIVO(rdev)) { |
1034 | } else if (ASIC_IS_AVIVO(rdev)) { |
1028 | rdev->ddev->mode_config.max_width = 8192; |
1035 | rdev->ddev->mode_config.max_width = 8192; |
1029 | rdev->ddev->mode_config.max_height = 8192; |
1036 | rdev->ddev->mode_config.max_height = 8192; |
1030 | } else { |
1037 | } else { |
1031 | rdev->ddev->mode_config.max_width = 4096; |
1038 | rdev->ddev->mode_config.max_width = 4096; |
1032 | rdev->ddev->mode_config.max_height = 4096; |
1039 | rdev->ddev->mode_config.max_height = 4096; |
1033 | } |
1040 | } |
1034 | 1041 | ||
1035 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1042 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1036 | 1043 | ||
1037 | ret = radeon_modeset_create_props(rdev); |
1044 | ret = radeon_modeset_create_props(rdev); |
1038 | if (ret) { |
1045 | if (ret) { |
1039 | return ret; |
1046 | return ret; |
1040 | } |
1047 | } |
1041 | 1048 | ||
1042 | /* init i2c buses */ |
1049 | /* init i2c buses */ |
1043 | radeon_i2c_init(rdev); |
1050 | radeon_i2c_init(rdev); |
1044 | 1051 | ||
1045 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1052 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1046 | if (!rdev->is_atom_bios) { |
1053 | if (!rdev->is_atom_bios) { |
1047 | /* check for hardcoded EDID in BIOS */ |
1054 | /* check for hardcoded EDID in BIOS */ |
1048 | radeon_combios_check_hardcoded_edid(rdev); |
1055 | radeon_combios_check_hardcoded_edid(rdev); |
1049 | } |
1056 | } |
1050 | 1057 | ||
1051 | /* allocate crtcs */ |
1058 | /* allocate crtcs */ |
1052 | for (i = 0; i < rdev->num_crtc; i++) { |
1059 | for (i = 0; i < rdev->num_crtc; i++) { |
1053 | radeon_crtc_init(rdev->ddev, i); |
1060 | radeon_crtc_init(rdev->ddev, i); |
1054 | } |
1061 | } |
1055 | 1062 | ||
1056 | /* okay we should have all the bios connectors */ |
1063 | /* okay we should have all the bios connectors */ |
1057 | ret = radeon_setup_enc_conn(rdev->ddev); |
1064 | ret = radeon_setup_enc_conn(rdev->ddev); |
1058 | if (!ret) { |
1065 | if (!ret) { |
1059 | return ret; |
1066 | return ret; |
1060 | } |
1067 | } |
1061 | 1068 | ||
1062 | /* init dig PHYs */ |
1069 | /* init dig PHYs */ |
1063 | if (rdev->is_atom_bios) |
1070 | if (rdev->is_atom_bios) |
1064 | radeon_atom_encoder_init(rdev); |
1071 | radeon_atom_encoder_init(rdev); |
1065 | 1072 | ||
1066 | /* initialize hpd */ |
1073 | /* initialize hpd */ |
1067 | // radeon_hpd_init(rdev); |
1074 | // radeon_hpd_init(rdev); |
1068 | 1075 | ||
1069 | /* Initialize power management */ |
1076 | /* Initialize power management */ |
1070 | // radeon_pm_init(rdev); |
1077 | // radeon_pm_init(rdev); |
1071 | 1078 | ||
1072 | radeon_fbdev_init(rdev); |
1079 | radeon_fbdev_init(rdev); |
1073 | // drm_kms_helper_poll_init(rdev->ddev); |
1080 | // drm_kms_helper_poll_init(rdev->ddev); |
1074 | - | ||
1075 | LEAVE(); |
- | |
1076 | 1081 | ||
1077 | return 0; |
1082 | return 0; |
1078 | } |
1083 | } |
1079 | 1084 | ||
1080 | void radeon_modeset_fini(struct radeon_device *rdev) |
1085 | void radeon_modeset_fini(struct radeon_device *rdev) |
1081 | { |
1086 | { |
1082 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1087 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1083 | 1088 | ||
1084 | if (rdev->mode_info.mode_config_initialized) { |
1089 | if (rdev->mode_info.mode_config_initialized) { |
1085 | // drm_kms_helper_poll_fini(rdev->ddev); |
1090 | // drm_kms_helper_poll_fini(rdev->ddev); |
1086 | // radeon_hpd_fini(rdev); |
1091 | // radeon_hpd_fini(rdev); |
1087 | drm_mode_config_cleanup(rdev->ddev); |
1092 | drm_mode_config_cleanup(rdev->ddev); |
1088 | rdev->mode_info.mode_config_initialized = false; |
1093 | rdev->mode_info.mode_config_initialized = false; |
1089 | } |
1094 | } |
1090 | /* free i2c buses */ |
1095 | /* free i2c buses */ |
1091 | radeon_i2c_fini(rdev); |
1096 | radeon_i2c_fini(rdev); |
1092 | } |
1097 | } |
1093 | 1098 | ||
1094 | static bool is_hdtv_mode(struct drm_display_mode *mode) |
1099 | static bool is_hdtv_mode(struct drm_display_mode *mode) |
1095 | { |
1100 | { |
1096 | /* try and guess if this is a tv or a monitor */ |
1101 | /* try and guess if this is a tv or a monitor */ |
1097 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
1102 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
1098 | (mode->vdisplay == 576) || /* 576p */ |
1103 | (mode->vdisplay == 576) || /* 576p */ |
1099 | (mode->vdisplay == 720) || /* 720p */ |
1104 | (mode->vdisplay == 720) || /* 720p */ |
1100 | (mode->vdisplay == 1080)) /* 1080p */ |
1105 | (mode->vdisplay == 1080)) /* 1080p */ |
1101 | return true; |
1106 | return true; |
1102 | else |
1107 | else |
1103 | return false; |
1108 | return false; |
1104 | } |
1109 | } |
1105 | 1110 | ||
1106 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1111 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
1107 | struct drm_display_mode *mode, |
1112 | struct drm_display_mode *mode, |
1108 | struct drm_display_mode *adjusted_mode) |
1113 | struct drm_display_mode *adjusted_mode) |
1109 | { |
1114 | { |
1110 | struct drm_device *dev = crtc->dev; |
1115 | struct drm_device *dev = crtc->dev; |
1111 | struct radeon_device *rdev = dev->dev_private; |
1116 | struct radeon_device *rdev = dev->dev_private; |
1112 | struct drm_encoder *encoder; |
1117 | struct drm_encoder *encoder; |
1113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1118 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1114 | struct radeon_encoder *radeon_encoder; |
1119 | struct radeon_encoder *radeon_encoder; |
1115 | struct drm_connector *connector; |
1120 | struct drm_connector *connector; |
1116 | struct radeon_connector *radeon_connector; |
1121 | struct radeon_connector *radeon_connector; |
1117 | bool first = true; |
1122 | bool first = true; |
1118 | u32 src_v = 1, dst_v = 1; |
1123 | u32 src_v = 1, dst_v = 1; |
1119 | u32 src_h = 1, dst_h = 1; |
1124 | u32 src_h = 1, dst_h = 1; |
1120 | 1125 | ||
1121 | radeon_crtc->h_border = 0; |
1126 | radeon_crtc->h_border = 0; |
1122 | radeon_crtc->v_border = 0; |
1127 | radeon_crtc->v_border = 0; |
1123 | 1128 | ||
1124 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1129 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1125 | if (encoder->crtc != crtc) |
1130 | if (encoder->crtc != crtc) |
1126 | continue; |
1131 | continue; |
1127 | radeon_encoder = to_radeon_encoder(encoder); |
1132 | radeon_encoder = to_radeon_encoder(encoder); |
1128 | connector = radeon_get_connector_for_encoder(encoder); |
1133 | connector = radeon_get_connector_for_encoder(encoder); |
1129 | radeon_connector = to_radeon_connector(connector); |
1134 | radeon_connector = to_radeon_connector(connector); |
1130 | 1135 | ||
1131 | if (first) { |
1136 | if (first) { |
1132 | /* set scaling */ |
1137 | /* set scaling */ |
1133 | if (radeon_encoder->rmx_type == RMX_OFF) |
1138 | if (radeon_encoder->rmx_type == RMX_OFF) |
1134 | radeon_crtc->rmx_type = RMX_OFF; |
1139 | radeon_crtc->rmx_type = RMX_OFF; |
1135 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1140 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
1136 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1141 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
1137 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1142 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1138 | else |
1143 | else |
1139 | radeon_crtc->rmx_type = RMX_OFF; |
1144 | radeon_crtc->rmx_type = RMX_OFF; |
1140 | /* copy native mode */ |
1145 | /* copy native mode */ |
1141 | memcpy(&radeon_crtc->native_mode, |
1146 | memcpy(&radeon_crtc->native_mode, |
1142 | &radeon_encoder->native_mode, |
1147 | &radeon_encoder->native_mode, |
1143 | sizeof(struct drm_display_mode)); |
1148 | sizeof(struct drm_display_mode)); |
1144 | src_v = crtc->mode.vdisplay; |
1149 | src_v = crtc->mode.vdisplay; |
1145 | dst_v = radeon_crtc->native_mode.vdisplay; |
1150 | dst_v = radeon_crtc->native_mode.vdisplay; |
1146 | src_h = crtc->mode.hdisplay; |
1151 | src_h = crtc->mode.hdisplay; |
1147 | dst_h = radeon_crtc->native_mode.hdisplay; |
1152 | dst_h = radeon_crtc->native_mode.hdisplay; |
1148 | 1153 | ||
1149 | /* fix up for overscan on hdmi */ |
1154 | /* fix up for overscan on hdmi */ |
1150 | if (ASIC_IS_AVIVO(rdev) && |
1155 | if (ASIC_IS_AVIVO(rdev) && |
1151 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
1156 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
1152 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1157 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
1153 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
1158 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
1154 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
1159 | drm_detect_hdmi_monitor(radeon_connector->edid) && |
1155 | is_hdtv_mode(mode)))) { |
1160 | is_hdtv_mode(mode)))) { |
1156 | if (radeon_encoder->underscan_hborder != 0) |
1161 | if (radeon_encoder->underscan_hborder != 0) |
1157 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
1162 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
1158 | else |
1163 | else |
1159 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
1164 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
1160 | if (radeon_encoder->underscan_vborder != 0) |
1165 | if (radeon_encoder->underscan_vborder != 0) |
1161 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
1166 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
1162 | else |
1167 | else |
1163 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
1168 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
1164 | radeon_crtc->rmx_type = RMX_FULL; |
1169 | radeon_crtc->rmx_type = RMX_FULL; |
1165 | src_v = crtc->mode.vdisplay; |
1170 | src_v = crtc->mode.vdisplay; |
1166 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
1171 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
1167 | src_h = crtc->mode.hdisplay; |
1172 | src_h = crtc->mode.hdisplay; |
1168 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
1173 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
1169 | } |
1174 | } |
1170 | first = false; |
1175 | first = false; |
1171 | } else { |
1176 | } else { |
1172 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1177 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
1173 | /* WARNING: Right now this can't happen but |
1178 | /* WARNING: Right now this can't happen but |
1174 | * in the future we need to check that scaling |
1179 | * in the future we need to check that scaling |
1175 | * are consistent across different encoder |
1180 | * are consistent across different encoder |
1176 | * (ie all encoder can work with the same |
1181 | * (ie all encoder can work with the same |
1177 | * scaling). |
1182 | * scaling). |
1178 | */ |
1183 | */ |
1179 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1184 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1180 | return false; |
1185 | return false; |
1181 | } |
1186 | } |
1182 | } |
1187 | } |
1183 | } |
1188 | } |
1184 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1189 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1185 | fixed20_12 a, b; |
1190 | fixed20_12 a, b; |
1186 | a.full = dfixed_const(src_v); |
1191 | a.full = dfixed_const(src_v); |
1187 | b.full = dfixed_const(dst_v); |
1192 | b.full = dfixed_const(dst_v); |
1188 | radeon_crtc->vsc.full = dfixed_div(a, b); |
1193 | radeon_crtc->vsc.full = dfixed_div(a, b); |
1189 | a.full = dfixed_const(src_h); |
1194 | a.full = dfixed_const(src_h); |
1190 | b.full = dfixed_const(dst_h); |
1195 | b.full = dfixed_const(dst_h); |
1191 | radeon_crtc->hsc.full = dfixed_div(a, b); |
1196 | radeon_crtc->hsc.full = dfixed_div(a, b); |
1192 | } else { |
1197 | } else { |
1193 | radeon_crtc->vsc.full = dfixed_const(1); |
1198 | radeon_crtc->vsc.full = dfixed_const(1); |
1194 | radeon_crtc->hsc.full = dfixed_const(1); |
1199 | radeon_crtc->hsc.full = dfixed_const(1); |
1195 | } |
1200 | } |
1196 | return true; |
1201 | return true; |
1197 | } |
1202 | } |
1198 | 1203 | ||
1199 | /* |
1204 | /* |
1200 | * Retrieve current video scanout position of crtc on a given gpu. |
1205 | * Retrieve current video scanout position of crtc on a given gpu. |
1201 | * |
1206 | * |
1202 | * \param dev Device to query. |
1207 | * \param dev Device to query. |
1203 | * \param crtc Crtc to query. |
1208 | * \param crtc Crtc to query. |
1204 | * \param *vpos Location where vertical scanout position should be stored. |
1209 | * \param *vpos Location where vertical scanout position should be stored. |
1205 | * \param *hpos Location where horizontal scanout position should go. |
1210 | * \param *hpos Location where horizontal scanout position should go. |
1206 | * |
1211 | * |
1207 | * Returns vpos as a positive number while in active scanout area. |
1212 | * Returns vpos as a positive number while in active scanout area. |
1208 | * Returns vpos as a negative number inside vblank, counting the number |
1213 | * Returns vpos as a negative number inside vblank, counting the number |
1209 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
1214 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
1210 | * until start of active scanout / end of vblank." |
1215 | * until start of active scanout / end of vblank." |
1211 | * |
1216 | * |
1212 | * \return Flags, or'ed together as follows: |
1217 | * \return Flags, or'ed together as follows: |
1213 | * |
1218 | * |
1214 | * DRM_SCANOUTPOS_VALID = Query successful. |
1219 | * DRM_SCANOUTPOS_VALID = Query successful. |
1215 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1220 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
1216 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
1221 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
1217 | * this flag means that returned position may be offset by a constant but |
1222 | * this flag means that returned position may be offset by a constant but |
1218 | * unknown small number of scanlines wrt. real scanout position. |
1223 | * unknown small number of scanlines wrt. real scanout position. |
1219 | * |
1224 | * |
1220 | */ |
1225 | */ |
1221 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
1226 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos) |
1222 | { |
1227 | { |
1223 | u32 stat_crtc = 0, vbl = 0, position = 0; |
1228 | u32 stat_crtc = 0, vbl = 0, position = 0; |
1224 | int vbl_start, vbl_end, vtotal, ret = 0; |
1229 | int vbl_start, vbl_end, vtotal, ret = 0; |
1225 | bool in_vbl = true; |
1230 | bool in_vbl = true; |
1226 | 1231 | ||
1227 | struct radeon_device *rdev = dev->dev_private; |
1232 | struct radeon_device *rdev = dev->dev_private; |
1228 | 1233 | ||
1229 | if (ASIC_IS_DCE4(rdev)) { |
1234 | if (ASIC_IS_DCE4(rdev)) { |
1230 | if (crtc == 0) { |
1235 | if (crtc == 0) { |
1231 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1236 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1232 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1237 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1233 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1238 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1234 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1239 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
1235 | ret |= DRM_SCANOUTPOS_VALID; |
1240 | ret |= DRM_SCANOUTPOS_VALID; |
1236 | } |
1241 | } |
1237 | if (crtc == 1) { |
1242 | if (crtc == 1) { |
1238 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1243 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1239 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1244 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1240 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1245 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1241 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1246 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
1242 | ret |= DRM_SCANOUTPOS_VALID; |
1247 | ret |= DRM_SCANOUTPOS_VALID; |
1243 | } |
1248 | } |
1244 | if (crtc == 2) { |
1249 | if (crtc == 2) { |
1245 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1250 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1246 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1251 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1247 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1252 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1248 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1253 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
1249 | ret |= DRM_SCANOUTPOS_VALID; |
1254 | ret |= DRM_SCANOUTPOS_VALID; |
1250 | } |
1255 | } |
1251 | if (crtc == 3) { |
1256 | if (crtc == 3) { |
1252 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1257 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1253 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1258 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1254 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1259 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1255 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1260 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
1256 | ret |= DRM_SCANOUTPOS_VALID; |
1261 | ret |= DRM_SCANOUTPOS_VALID; |
1257 | } |
1262 | } |
1258 | if (crtc == 4) { |
1263 | if (crtc == 4) { |
1259 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1264 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1260 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1265 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1261 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1266 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1262 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1267 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
1263 | ret |= DRM_SCANOUTPOS_VALID; |
1268 | ret |= DRM_SCANOUTPOS_VALID; |
1264 | } |
1269 | } |
1265 | if (crtc == 5) { |
1270 | if (crtc == 5) { |
1266 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1271 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1267 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1272 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1268 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1273 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
1269 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1274 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
1270 | ret |= DRM_SCANOUTPOS_VALID; |
1275 | ret |= DRM_SCANOUTPOS_VALID; |
1271 | } |
1276 | } |
1272 | } else if (ASIC_IS_AVIVO(rdev)) { |
1277 | } else if (ASIC_IS_AVIVO(rdev)) { |
1273 | if (crtc == 0) { |
1278 | if (crtc == 0) { |
1274 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
1279 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
1275 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
1280 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
1276 | ret |= DRM_SCANOUTPOS_VALID; |
1281 | ret |= DRM_SCANOUTPOS_VALID; |
1277 | } |
1282 | } |
1278 | if (crtc == 1) { |
1283 | if (crtc == 1) { |
1279 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
1284 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
1280 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
1285 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
1281 | ret |= DRM_SCANOUTPOS_VALID; |
1286 | ret |= DRM_SCANOUTPOS_VALID; |
1282 | } |
1287 | } |
1283 | } else { |
1288 | } else { |
1284 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
1289 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
1285 | if (crtc == 0) { |
1290 | if (crtc == 0) { |
1286 | /* Assume vbl_end == 0, get vbl_start from |
1291 | /* Assume vbl_end == 0, get vbl_start from |
1287 | * upper 16 bits. |
1292 | * upper 16 bits. |
1288 | */ |
1293 | */ |
1289 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
1294 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
1290 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1295 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1291 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
1296 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
1292 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1297 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1293 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
1298 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
1294 | if (!(stat_crtc & 1)) |
1299 | if (!(stat_crtc & 1)) |
1295 | in_vbl = false; |
1300 | in_vbl = false; |
1296 | 1301 | ||
1297 | ret |= DRM_SCANOUTPOS_VALID; |
1302 | ret |= DRM_SCANOUTPOS_VALID; |
1298 | } |
1303 | } |
1299 | if (crtc == 1) { |
1304 | if (crtc == 1) { |
1300 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
1305 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
1301 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1306 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
1302 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1307 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
1303 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
1308 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
1304 | if (!(stat_crtc & 1)) |
1309 | if (!(stat_crtc & 1)) |
1305 | in_vbl = false; |
1310 | in_vbl = false; |
1306 | 1311 | ||
1307 | ret |= DRM_SCANOUTPOS_VALID; |
1312 | ret |= DRM_SCANOUTPOS_VALID; |
1308 | } |
1313 | } |
1309 | } |
1314 | } |
1310 | 1315 | ||
1311 | /* Decode into vertical and horizontal scanout position. */ |
1316 | /* Decode into vertical and horizontal scanout position. */ |
1312 | *vpos = position & 0x1fff; |
1317 | *vpos = position & 0x1fff; |
1313 | *hpos = (position >> 16) & 0x1fff; |
1318 | *hpos = (position >> 16) & 0x1fff; |
1314 | 1319 | ||
1315 | /* Valid vblank area boundaries from gpu retrieved? */ |
1320 | /* Valid vblank area boundaries from gpu retrieved? */ |
1316 | if (vbl > 0) { |
1321 | if (vbl > 0) { |
1317 | /* Yes: Decode. */ |
1322 | /* Yes: Decode. */ |
1318 | ret |= DRM_SCANOUTPOS_ACCURATE; |
1323 | ret |= DRM_SCANOUTPOS_ACCURATE; |
1319 | vbl_start = vbl & 0x1fff; |
1324 | vbl_start = vbl & 0x1fff; |
1320 | vbl_end = (vbl >> 16) & 0x1fff; |
1325 | vbl_end = (vbl >> 16) & 0x1fff; |
1321 | } |
1326 | } |
1322 | else { |
1327 | else { |
1323 | /* No: Fake something reasonable which gives at least ok results. */ |
1328 | /* No: Fake something reasonable which gives at least ok results. */ |
1324 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
1329 | vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; |
1325 | vbl_end = 0; |
1330 | vbl_end = 0; |
1326 | } |
1331 | } |
1327 | 1332 | ||
1328 | /* Test scanout position against vblank region. */ |
1333 | /* Test scanout position against vblank region. */ |
1329 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
1334 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
1330 | in_vbl = false; |
1335 | in_vbl = false; |
1331 | 1336 | ||
1332 | /* Check if inside vblank area and apply corrective offsets: |
1337 | /* Check if inside vblank area and apply corrective offsets: |
1333 | * vpos will then be >=0 in video scanout area, but negative |
1338 | * vpos will then be >=0 in video scanout area, but negative |
1334 | * within vblank area, counting down the number of lines until |
1339 | * within vblank area, counting down the number of lines until |
1335 | * start of scanout. |
1340 | * start of scanout. |
1336 | */ |
1341 | */ |
1337 | 1342 | ||
1338 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
1343 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
1339 | if (in_vbl && (*vpos >= vbl_start)) { |
1344 | if (in_vbl && (*vpos >= vbl_start)) { |
1340 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
1345 | vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; |
1341 | *vpos = *vpos - vtotal; |
1346 | *vpos = *vpos - vtotal; |
1342 | } |
1347 | } |
1343 | 1348 | ||
1344 | /* Correct for shifted end of vbl at vbl_end. */ |
1349 | /* Correct for shifted end of vbl at vbl_end. */ |
1345 | *vpos = *vpos - vbl_end; |
1350 | *vpos = *vpos - vbl_end; |
1346 | 1351 | ||
1347 | /* In vblank? */ |
1352 | /* In vblank? */ |
1348 | if (in_vbl) |
1353 | if (in_vbl) |
1349 | ret |= DRM_SCANOUTPOS_INVBL; |
1354 | ret |= DRM_SCANOUTPOS_INVBL; |
1350 | 1355 | ||
1351 | return ret; |
1356 | return ret; |
1352 | }>>>>>>>>>>>>>>>>>>>>>=>>>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |
1357 | }>>>>>>>>>>>>>>>>>>>>>=>>>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |