WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
//#include 
#include 
#include 
#include 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"
 
#include "bitmap.h"
#include "display.h"
 
 
#include 
 
 
int radeon_no_wb   =  1;
int radeon_modeset = -1;
int radeon_dynclks = -1;
int radeon_r4xx_atom = 0;
int radeon_agpmode = 0;
int radeon_vram_limit = 0;
int radeon_gart_size = 512; /* default gart size */
int radeon_benchmarking = 0;
int radeon_testing = 0;
int radeon_connector_table = 0;
int radeon_tv = 1;
int radeon_new_pll = -1;
int radeon_dynpm = -1;
int radeon_audio = 1;
int radeon_hw_i2c = 0;
int radeon_pcie_gen2 = 0;
int radeon_disp_priority = 0;
int radeon_lockup_timeout = 10000;
 
 
int irq_override = 0;
 
 
extern display_t *rdisplay;
struct drm_device *main_drm_device;
 
 
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
int init_display(struct radeon_device *rdev, videomode_t *mode);
int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
 
int get_modes(videomode_t *mode, u32_t *count);
int set_user_mode(videomode_t *mode);
int r100_2D_test(struct radeon_device *rdev);
 
 
 /* Legacy VGA regions */
#define VGA_RSRC_NONE          0x00
#define VGA_RSRC_LEGACY_IO     0x01
#define VGA_RSRC_LEGACY_MEM    0x02
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
/* Non-legacy access */
#define VGA_RSRC_NORMAL_IO     0x04
#define VGA_RSRC_NORMAL_MEM    0x08
 
 
static const char radeon_family_name[][16] = {
	"R100",
	"RV100",
	"RS100",
	"RV200",
	"RS200",
	"R200",
	"RV250",
	"RS300",
	"RV280",
	"R300",
	"R350",
	"RV350",
	"RV380",
	"R420",
	"R423",
	"RV410",
	"RS400",
	"RS480",
	"RS600",
	"RS690",
	"RS740",
	"RV515",
	"R520",
	"RV530",
	"RV560",
	"RV570",
	"R580",
	"R600",
	"RV610",
	"RV630",
	"RV670",
	"RV620",
	"RV635",
	"RS780",
	"RS880",
	"RV770",
	"RV730",
	"RV710",
	"RV740",
	"CEDAR",
	"REDWOOD",
	"JUNIPER",
	"CYPRESS",
	"HEMLOCK",
	"PALM",
	"SUMO",
	"SUMO2",
	"BARTS",
	"TURKS",
	"CAICOS",
	"CAYMAN",
	"ARUBA",
	"TAHITI",
	"PITCAIRN",
	"VERDE",
	"LAST",
};
 
/**
 * radeon_surface_init - Clear GPU surface registers.
 *
 * @rdev: radeon_device pointer
 *
 * Clear GPU surface registers (r1xx-r5xx).
 */
void radeon_surface_init(struct radeon_device *rdev)
{
    /* FIXME: check this out */
    if (rdev->family < CHIP_R600) {
        int i;
 
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
           radeon_clear_surface_reg(rdev, i);
        }
		/* enable surfaces */
		WREG32(RADEON_SURFACE_CNTL, 0);
    }
}
 
/*
 * GPU scratch registers helpers function.
 */
/**
 * radeon_scratch_init - Init scratch register driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Init CP scratch register driver information (r1xx-r5xx)
 */
void radeon_scratch_init(struct radeon_device *rdev)
{
    int i;
 
    /* FIXME: check this out */
    if (rdev->family < CHIP_R300) {
        rdev->scratch.num_reg = 5;
    } else {
        rdev->scratch.num_reg = 7;
    }
	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
    for (i = 0; i < rdev->scratch.num_reg; i++) {
        rdev->scratch.free[i] = true;
		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
    }
}
 
/**
 * radeon_scratch_get - Allocate a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Allocate a CP scratch register for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}
 
/**
 * radeon_scratch_free - Free a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Free a CP scratch register allocated for use by the driver (all asics)
 */
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}
 
/*
 * radeon_wb_*()
 * Writeback is the the method by which the the GPU updates special pages
 * in memory with the status of certain GPU events (fences, ring pointers,
 * etc.).
 */
 
/**
 * radeon_wb_disable - Disable Writeback
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback (all asics).  Used for suspend.
 */
void radeon_wb_disable(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->wb.wb_obj) {
		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		if (unlikely(r != 0))
			return;
		radeon_bo_kunmap(rdev->wb.wb_obj);
		radeon_bo_unpin(rdev->wb.wb_obj);
		radeon_bo_unreserve(rdev->wb.wb_obj);
	}
	rdev->wb.enabled = false;
}
 
/**
 * radeon_wb_fini - Disable Writeback and free memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
void radeon_wb_fini(struct radeon_device *rdev)
{
	radeon_wb_disable(rdev);
	if (rdev->wb.wb_obj) {
		radeon_bo_unref(&rdev->wb.wb_obj);
		rdev->wb.wb = NULL;
		rdev->wb.wb_obj = NULL;
	}
}
 
/**
 * radeon_wb_init- Init Writeback driver info and allocate memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
int radeon_wb_init(struct radeon_device *rdev)
{
	int r;
 
	if (rdev->wb.wb_obj == NULL) {
		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
				     RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
		if (r) {
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}
	}
	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
	if (unlikely(r != 0)) {
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
			  &rdev->wb.gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->wb.wb_obj);
		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
	radeon_bo_unreserve(rdev->wb.wb_obj);
	if (r) {
		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
 
	/* clear wb memory */
	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
	/* disable event_write fences */
	rdev->wb.use_event = false;
	/* disabled via module param */
	if (radeon_no_wb == 1) {
		rdev->wb.enabled = false;
	} else {
		if (rdev->flags & RADEON_IS_AGP) {
		/* often unreliable on AGP */
			rdev->wb.enabled = false;
		} else if (rdev->family < CHIP_R300) {
			/* often unreliable on pre-r300 */
			rdev->wb.enabled = false;
		} else {
			rdev->wb.enabled = true;
			/* event_write fences are only available on r600+ */
			if (rdev->family >= CHIP_R600) {
				rdev->wb.use_event = true;
	}
		}
	}
	/* always use writeback/events on NI, APUs */
	if (rdev->family >= CHIP_PALM) {
		rdev->wb.enabled = true;
		rdev->wb.use_event = true;
	}
 
	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 
	return 0;
}
 
/**
 * radeon_vram_location - try to find VRAM location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 * @base: base address at which to put VRAM
 *
 * Function will place try to place VRAM at base address provided
 * as parameter (which is so far either PCI aperture address or
 * for IGP TOM base address).
 *
 * If there is not enough space to fit the unvisible VRAM in the 32bits
 * address space then we limit the VRAM size to the aperture.
 *
 * If we are using AGP and if the AGP aperture doesn't allow us to have
 * room for all the VRAM than we restrict the VRAM to the PCI aperture
 * size and print a warning.
 *
 * This function will never fails, worst case are limiting VRAM.
 *
 * Note: GTT start, end, size should be initialized before calling this
 * function on AGP platform.
 *
 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 * not IGP.
 *
 * Note: we use mc_vram_size as on some board we need to program the mc to
 * cover the whole aperture even if VRAM size is inferior to aperture size
 * Novell bug 204882 + along with lots of ubuntu ones
 *
 * Note: when limiting vram it's safe to overwritte real_vram_size because
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 * ones)
 *
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
 * explicitly check for that thought.
 *
 * FIXME: when reducing VRAM size align new size on power of 2.
 */
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
{
	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 
	mc->vram_start = base;
	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
		}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
	if (limit && limit < mc->real_vram_size)
		mc->real_vram_size = limit;
	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
			mc->mc_vram_size >> 20, mc->vram_start,
			mc->vram_end, mc->real_vram_size >> 20);
}
 
/**
 * radeon_gtt_location - try to find GTT location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 *
 * Function will place try to place GTT before or after VRAM.
 *
 * If GTT size is bigger than space left then we ajust GTT size.
 * Thus function will never fails.
 *
 * FIXME: when reducing GTT size align new size on power of 2.
 */
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
{
	u64 size_af, size_bf;
 
	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
	size_bf = mc->vram_start & ~mc->gtt_base_align;
	if (size_bf > size_af) {
		if (mc->gtt_size > size_bf) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_bf;
		}
		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
	} else {
		if (mc->gtt_size > size_af) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_af;
		}
		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
	}
	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
}
 
/*
 * GPU helpers function.
 */
/**
 * radeon_card_posted - check if the hw has already been initialized
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic has been initialized (all asics).
 * Used at driver startup.
 * Returns true if initialized or false if not.
 */
bool radeon_card_posted(struct radeon_device *rdev)
{
	uint32_t reg;
 
	/* first check CRTCs */
	if (ASIC_IS_DCE41(rdev)) {
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_DCE4(rdev)) {
		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_AVIVO(rdev)) {
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}
 
	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 
	if (reg)
		return true;
 
	return false;
 
}
 
/**
 * radeon_update_bandwidth_info - update display bandwidth params
 *
 * @rdev: radeon_device pointer
 *
 * Used when sclk/mclk are switched or display modes are set.
 * params are used to calculate display watermarks (all asics)
 */
void radeon_update_bandwidth_info(struct radeon_device *rdev)
{
	fixed20_12 a;
	u32 sclk = rdev->pm.current_sclk;
	u32 mclk = rdev->pm.current_mclk;
 
	/* sclk/mclk in Mhz */
		a.full = dfixed_const(100);
		rdev->pm.sclk.full = dfixed_const(sclk);
		rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
		rdev->pm.mclk.full = dfixed_const(mclk);
		rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 
	if (rdev->flags & RADEON_IS_IGP) {
		a.full = dfixed_const(16);
		/* core_bandwidth = sclk(Mhz) * 16 */
		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
	}
}
 
/**
 * radeon_boot_test_post_card - check and possibly initialize the hw
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic is initialized and if not, attempt to initialize
 * it (all asics).
 * Returns true if initialized or false if not.
 */
bool radeon_boot_test_post_card(struct radeon_device *rdev)
{
	if (radeon_card_posted(rdev))
		return true;
 
	if (rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios)
			atom_asic_init(rdev->mode_info.atom_context);
		else
			radeon_combios_asic_init(rdev->ddev);
		return true;
	} else {
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		return false;
	}
}
 
/**
 * radeon_dummy_page_init - init dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
int radeon_dummy_page_init(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page)
		return 0;
    rdev->dummy_page.page = (void*)AllocPage();
	if (rdev->dummy_page.page == NULL)
		return -ENOMEM;
    rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3);
	if (!rdev->dummy_page.addr) {
//       __free_page(rdev->dummy_page.page);
		rdev->dummy_page.page = NULL;
		return -ENOMEM;
	}
	return 0;
}
 
/**
 * radeon_dummy_page_fini - free dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void radeon_dummy_page_fini(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page == NULL)
		return;
    KernelFree((void*)rdev->dummy_page.addr);
	rdev->dummy_page.page = NULL;
}
 
 
/* ATOM accessor methods */
/*
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 * driver registers callbacks to access registers and the interpreter
 * in the driver parses the tables and executes then to program specific
 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 * atombios.h, and atom.c
 */
 
/**
 * cail_pll_read - read PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 * Returns the value of the PLL register.
 */
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->pll_rreg(rdev, reg);
    return r;
}
 
/**
 * cail_pll_write - write PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 * @val: value to write to the pll register
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 */
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->pll_wreg(rdev, reg, val);
}
 
/**
 * cail_mc_read - read MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 *
 * Provides an MC register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MC register.
 */
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->mc_rreg(rdev, reg);
    return r;
}
 
/**
 * cail_mc_write - write MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 * @val: value to write to the pll register
 *
 * Provides a MC register accessor for the atom interpreter (r4xx+).
 */
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->mc_wreg(rdev, reg, val);
}
 
/**
 * cail_reg_write - write MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 * @val: value to write to the pll register
 *
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 */
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    WREG32(reg*4, val);
}
 
/**
 * cail_reg_read - read MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 *
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MMIO register.
 */
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = RREG32(reg*4);
    return r;
}
 
/**
 * cail_ioreg_write - write IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 * @val: value to write to the pll register
 *
 * Provides a IO register accessor for the atom interpreter (r4xx+).
 */
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;
 
	WREG32_IO(reg*4, val);
}
 
/**
 * cail_ioreg_read - read IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 *
 * Provides an IO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the IO register.
 */
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;
 
	r = RREG32_IO(reg*4);
	return r;
}
 
/**
 * radeon_atombios_init - init the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info and register access callbacks for the
 * ATOM interpreter (r4xx+).
 * Returns 0 on sucess, -ENOMEM on failure.
 * Called at driver startup.
 */
int radeon_atombios_init(struct radeon_device *rdev)
{
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
 
	if (!atom_card_info)
		return -ENOMEM;
 
	rdev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = rdev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
	/* needed for iio ops */
	if (rdev->rio_mem) {
		atom_card_info->ioreg_read = cail_ioreg_read;
		atom_card_info->ioreg_write = cail_ioreg_write;
	} else {
		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
		atom_card_info->ioreg_read = cail_reg_read;
		atom_card_info->ioreg_write = cail_reg_write;
	}
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;
 
	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
	mutex_init(&rdev->mode_info.atom_context->mutex);
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
    return 0;
}
 
/**
 * radeon_atombios_fini - free the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info and register access callbacks for the ATOM
 * interpreter (r4xx+).
 * Called at driver shutdown.
 */
void radeon_atombios_fini(struct radeon_device *rdev)
{
	if (rdev->mode_info.atom_context) {
		kfree(rdev->mode_info.atom_context->scratch);
	kfree(rdev->mode_info.atom_context);
	}
	kfree(rdev->mode_info.atom_card_info);
}
 
/* COMBIOS */
/*
 * COMBIOS is the bios format prior to ATOM. It provides
 * command tables similar to ATOM, but doesn't have a unified
 * parser.  See radeon_combios.c
 */
 
/**
 * radeon_combios_init - init the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info for combios (r1xx-r3xx).
 * Returns 0 on sucess.
 * Called at driver startup.
 */
int radeon_combios_init(struct radeon_device *rdev)
{
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}
 
/**
 * radeon_combios_fini - free the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info for combios (r1xx-r3xx).
 * Called at driver shutdown.
 */
void radeon_combios_fini(struct radeon_device *rdev)
{
}
 
/* if we get transitioned to only one device, take VGA back */
/**
 * radeon_vga_set_decode - enable/disable vga decode
 *
 * @cookie: radeon_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
{
	struct radeon_device *rdev = cookie;
	radeon_vga_set_state(rdev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
 
/**
 * radeon_check_pot_argument - check that argument is a power of two
 *
 * @arg: value to check
 *
 * Validates that a certain argument is a power of two (all asics).
 * Returns true if argument is valid.
 */
static bool radeon_check_pot_argument(int arg)
{
	return (arg & (arg - 1)) == 0;
}
 
/**
 * radeon_check_arguments - validate module params
 *
 * @rdev: radeon_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
static void radeon_check_arguments(struct radeon_device *rdev)
{
	/* vramlimit must be a power of two */
	if (!radeon_check_pot_argument(radeon_vram_limit)) {
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
				radeon_vram_limit);
		radeon_vram_limit = 0;
	}
 
	/* gtt size must be power of two and greater or equal to 32M */
	if (radeon_gart_size < 32) {
		dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
				radeon_gart_size);
		radeon_gart_size = 512;
 
	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
				radeon_gart_size);
		radeon_gart_size = 512;
	}
	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
 
	/* AGP mode can only be -1, 1, 2, 4, 8 */
	switch (radeon_agpmode) {
	case -1:
	case 0:
	case 1:
	case 2:
	case 4:
	case 8:
		break;
	default:
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		radeon_agpmode = 0;
		break;
	}
}
 
int radeon_device_init(struct radeon_device *rdev,
               struct drm_device *ddev,
               struct pci_dev *pdev,
               uint32_t flags)
{
	int r, i;
	int dma_bits;
 
    rdev->shutdown = false;
    rdev->ddev = ddev;
    rdev->pdev = pdev;
    rdev->flags = flags;
    rdev->family = flags & RADEON_FAMILY_MASK;
    rdev->is_atom_bios = false;
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
    rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
	rdev->accel_working = false;
	/* set up ring ids */
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		rdev->ring[i].idx = i;
	}
 
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
		pdev->subsystem_vendor, pdev->subsystem_device);
 
    /* mutex initialization are all done here so we
     * can recall function without having locking issues */
	mutex_init(&rdev->ring_lock);
	mutex_init(&rdev->dc_hw_i2c_mutex);
	atomic_set(&rdev->ih.lock, 0);
	mutex_init(&rdev->gem.mutex);
	mutex_init(&rdev->pm.mutex);
	mutex_init(&rdev->gpu_clock_mutex);
	init_rwsem(&rdev->pm.mclk_lock);
	init_rwsem(&rdev->exclusive_lock);
	init_waitqueue_head(&rdev->irq.vblank_queue);
	r = radeon_gem_init(rdev);
	if (r)
		return r;
	/* initialize vm here */
	mutex_init(&rdev->vm_manager.lock);
	/* Adjust VM size here.
	 * Currently set to 4GB ((1 << 20) 4k pages).
	 * Max GPUVM size for cayman and SI is 40 bits.
	 */
	rdev->vm_manager.max_pfn = 1 << 20;
	INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
 
	/* Set asic functions */
	r = radeon_asic_init(rdev);
	if (r)
		return r;
	radeon_check_arguments(rdev);
 
	/* all of the newer IGP chips have an internal gart
	 * However some rs4xx report as AGP, so remove that here.
	 */
	if ((rdev->family >= CHIP_RS400) &&
	    (rdev->flags & RADEON_IS_IGP)) {
		rdev->flags &= ~RADEON_IS_AGP;
	}
 
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
		radeon_agp_disable(rdev);
    }
 
	/* set DMA mask + need_dma32 flags.
	 * PCIE - can handle 40-bits.
	 * IGP - can handle 40-bits
	 * AGP - generally dma32 is safest
	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
	 */
	rdev->need_dma32 = false;
	if (rdev->flags & RADEON_IS_AGP)
		rdev->need_dma32 = true;
	if ((rdev->flags & RADEON_IS_PCI) &&
	    (rdev->family <= CHIP_RS740))
		rdev->need_dma32 = true;
 
	dma_bits = rdev->need_dma32 ? 32 : 40;
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
    if (r) {
		rdev->need_dma32 = true;
		dma_bits = 32;
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
    }
 
    /* Registers mapping */
    /* TODO: block userspace mapping of io register */
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
    if (rdev->rmmio == NULL) {
        return -ENOMEM;
    }
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
			break;
		}
	}
	if (rdev->rio_mem == NULL)
		DRM_ERROR("Unable to find PCI I/O BAR\n");
 
 
	r = radeon_init(rdev);
	if (r)
        return r;
 
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		/* Acceleration not working on AGP card try again
		 * with fallback to PCI or PCIE GART
		 */
		radeon_asic_reset(rdev);
		radeon_fini(rdev);
		radeon_agp_disable(rdev);
		r = radeon_init(rdev);
		if (r)
		return r;
	}
//	if (radeon_testing) {
//		radeon_test_moves(rdev);
//    }
//	if ((radeon_testing & 2)) {
//		radeon_test_syncing(rdev);
//	}
   if (radeon_benchmarking) {
		radeon_benchmark(rdev, radeon_benchmarking);
    }
	return 0;
}
 
/**
 * radeon_gpu_reset - reset the asic
 *
 * @rdev: radeon device pointer
 *
 * Attempt the reset the GPU if it has hung (all asics).
 * Returns 0 for success or an error on failure.
 */
int radeon_gpu_reset(struct radeon_device *rdev)
{
    unsigned ring_sizes[RADEON_NUM_RINGS];
    uint32_t *ring_data[RADEON_NUM_RINGS];
 
    bool saved = false;
 
    int i, r;
    int resched;
 
//    down_write(&rdev->exclusive_lock);
    radeon_save_bios_scratch_regs(rdev);
    /* block TTM */
//    resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
    radeon_suspend(rdev);
 
    for (i = 0; i < RADEON_NUM_RINGS; ++i) {
        ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
                           &ring_data[i]);
        if (ring_sizes[i]) {
            saved = true;
            dev_info(rdev->dev, "Saved %d dwords of commands "
                 "on ring %d.\n", ring_sizes[i], i);
        }
    }
 
retry:
    r = radeon_asic_reset(rdev);
    if (!r) {
        dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
        radeon_resume(rdev);
    }
 
    radeon_restore_bios_scratch_regs(rdev);
    drm_helper_resume_force_mode(rdev->ddev);
 
    if (!r) {
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
            radeon_ring_restore(rdev, &rdev->ring[i],
                        ring_sizes[i], ring_data[i]);
            ring_sizes[i] = 0;
            ring_data[i] = NULL;
        }
 
        r = radeon_ib_ring_tests(rdev);
        if (r) {
            dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
            if (saved) {
                saved = false;
                radeon_suspend(rdev);
                goto retry;
            }
        }
    } else {
        for (i = 0; i < RADEON_NUM_RINGS; ++i) {
            kfree(ring_data[i]);
        }
    }
 
//    ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
    if (r) {
        /* bad news, how to tell it to userspace ? */
        dev_info(rdev->dev, "GPU reset failed\n");
    }
 
//    up_write(&rdev->exclusive_lock);
    return r;
}
 
 
 
/*
 * Driver load/unload
 */
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
    struct radeon_device *rdev;
    int r;
 
    ENTER();
 
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
    if (rdev == NULL) {
        return -ENOMEM;
    };
 
    dev->dev_private = (void *)rdev;
 
    /* update BUS flag */
    if (drm_device_is_agp(dev)) {
        flags |= RADEON_IS_AGP;
    } else if (drm_device_is_pcie(dev)) {
        flags |= RADEON_IS_PCIE;
    } else {
        flags |= RADEON_IS_PCI;
    }
 
    /* radeon_device_init should report only fatal error
     * like memory allocation failure or iomapping failure,
     * or memory manager initialization failure, it must
     * properly initialize the GPU MC controller and permit
     * VRAM allocation
     */
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
    if (r) {
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
        return r;
    }
    /* Again modeset_init should fail only on fatal error
     * otherwise it should provide enough functionalities
     * for shadowfb to run
     */
    if( radeon_modeset )
    {
        r = radeon_modeset_init(rdev);
        if (r) {
            return r;
        }
    };
    return 0;
}
 
videomode_t usermode;
 
 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
    static struct drm_device *dev;
    int ret;
 
    ENTER();
 
    dev = kzalloc(sizeof(*dev), 0);
    if (!dev)
        return -ENOMEM;
 
 //   ret = pci_enable_device(pdev);
 //   if (ret)
 //       goto err_g1;
 
 //   pci_set_master(pdev);
 
 //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
 //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
 //       goto err_g2;
 //   }
 
    dev->pdev = pdev;
    dev->pci_device = pdev->device;
    dev->pci_vendor = pdev->vendor;
 
    INIT_LIST_HEAD(&dev->filelist);
    INIT_LIST_HEAD(&dev->ctxlist);
    INIT_LIST_HEAD(&dev->vmalist);
    INIT_LIST_HEAD(&dev->maplist);
 
    spin_lock_init(&dev->count_lock);
    mutex_init(&dev->struct_mutex);
    mutex_init(&dev->ctxlist_mutex);
 
 
    ret = radeon_driver_load_kms(dev, ent->driver_data );
    if (ret)
        goto err_g4;
 
    main_drm_device = dev;
 
    if( radeon_modeset )
        init_display_kms(dev->dev_private, &usermode);
    else
        init_display(dev->dev_private, &usermode);
 
 
    LEAVE();
 
    return 0;
 
err_g4:
//    drm_put_minor(&dev->primary);
//err_g3:
//    if (drm_core_check_feature(dev, DRIVER_MODESET))
//        drm_put_minor(&dev->control);
//err_g2:
//    pci_disable_device(pdev);
//err_g1:
    free(dev);
 
    LEAVE();
 
    return ret;
}
 
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_start(dev->pdev, resource);
}
 
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_len(dev->pdev, resource);
}
 
 
uint32_t __div64_32(uint64_t *n, uint32_t base)
{
        uint64_t rem = *n;
        uint64_t b = base;
        uint64_t res, d = 1;
        uint32_t high = rem >> 32;
 
        /* Reduce the thing a bit first */
        res = 0;
        if (high >= base) {
                high /= base;
                res = (uint64_t) high << 32;
                rem -= (uint64_t) (high*base) << 32;
        }
 
        while ((int64_t)b > 0 && b < rem) {
                b = b+b;
                d = d+d;
        }
 
        do {
                if (rem >= b) {
                        rem -= b;
                        res += d;
                }
                b >>= 1;
                d >>= 1;
        } while (d);
 
        *n = res;
        return rem;
}
 
 
static struct pci_device_id pciidlist[] = {
    radeon_PCI_IDS
};
 
 
#define CURRENT_API     0x0200      /*      2.00     */
#define COMPATIBLE_API  0x0100      /*      1.00     */
 
#define API_VERSION     (COMPATIBLE_API << 16) | CURRENT_API
 
#define SRV_GETVERSION      0
#define SRV_ENUM_MODES      1
#define SRV_SET_MODE        2
#define SRV_GET_CAPS            3
 
#define SRV_CREATE_SURFACE      10
#define SRV_DESTROY_SURFACE     11
#define SRV_LOCK_SURFACE        12
#define SRV_UNLOCK_SURFACE      13
#define SRV_RESIZE_SURFACE      14
#define SRV_BLIT_BITMAP         15
#define SRV_BLIT_TEXTURE        16
#define SRV_BLIT_VIDEO          17
 
 
 
 
 
 
int r600_video_blit(uint64_t src_offset, int  x, int y,
                    int w, int h, int pitch);
 
#define check_input(size) \
    if( unlikely((inp==NULL)||(io->inp_size != (size))) )   \
        break;
 
#define check_output(size) \
    if( unlikely((outp==NULL)||(io->out_size != (size))) )   \
        break;
 
int _stdcall display_handler(ioctl_t *io)
{
    int    retval = -1;
    u32_t *inp;
    u32_t *outp;
 
    inp = io->input;
    outp = io->output;
 
    switch(io->io_code)
    {
        case SRV_GETVERSION:
            check_output(4);
            *outp  = API_VERSION;
            retval = 0;
            break;
 
        case SRV_ENUM_MODES:
            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
                       inp, io->inp_size, io->out_size );
            check_output(4);
            if( radeon_modeset)
                retval = get_modes((videomode_t*)inp, outp);
            break;
 
        case SRV_SET_MODE:
            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
                       inp, io->inp_size);
            check_input(sizeof(videomode_t));
            if( radeon_modeset )
                retval = set_user_mode((videomode_t*)inp);
            break;
 
        case SRV_GET_CAPS:
            retval = get_driver_caps((hwcaps_t*)inp);
            break;
 
 
 
        case SRV_CREATE_SURFACE:
//            check_input(8);
            retval = create_surface(main_drm_device, (struct io_call_10*)inp);
 
 
            break;
 
        case SRV_LOCK_SURFACE:
            retval = lock_surface((struct io_call_12*)inp);
            break;
 
        case SRV_BLIT_BITMAP:
            srv_blit_bitmap( inp[0], inp[1], inp[2],
                        inp[3], inp[4], inp[5], inp[6]);
 
    };
 
    return retval;
}
 
static char  log[256];
static pci_dev_t device;
 
u32_t drvEntry(int action, char *cmdline)
{
    struct radeon_device *rdev = NULL;
 
    const struct pci_device_id  *ent;
 
    int     err;
    u32_t   retval = 0;
 
    if(action != 1)
        return 0;
 
    if( GetService("DISPLAY") != 0 )
        return 0;
 
    if( cmdline && *cmdline )
        parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
 
    if(!dbg_open(log))
    {
        strcpy(log, "/RD/1/DRIVERS/atikms.log");
 
        if(!dbg_open(log))
        {
            printf("Can't open %s\nExit\n", log);
            return 0;
        };
    }
    dbgprintf("Radeon RC12 preview 1 cmdline %s\n", cmdline);
 
    enum_pci_devices();
 
    ent = find_pci_device(&device, pciidlist);
 
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return 0;
    };
 
    dbgprintf("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    err = drm_get_dev(&device.pci_dev, ent);
 
    rdev = rdisplay->ddev->dev_private;
 
    err = RegService("DISPLAY", display_handler);
 
    if( err != 0)
        dbgprintf("Set DISPLAY handler\n");
 
    return err;
};
 
#define PCI_CLASS_REVISION      0x08
#define PCI_CLASS_DISPLAY_VGA   0x0300
 
int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
{
    u16_t vendor, device;
    u32_t class;
    int   ret = 0;
 
    vendor   = id & 0xffff;
    device   = (id >> 16) & 0xffff;
 
    if(vendor == 0x1002)
    {
        class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
        class >>= 16;
 
        if( class == PCI_CLASS_DISPLAY_VGA)
            ret = 1;
    }
    return ret;
}

Rev 3031	Rev 3120
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	//#include	28	//#include
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include "radeon_reg.h"	33	#include "radeon_reg.h"
34	#include "radeon.h"	34	#include "radeon.h"
35	#include "atom.h"	35	#include "atom.h"
-		36
-		37	#include "bitmap.h"
36	#include "display.h"	38	#include "display.h"
-		39
37		40
38	#include	41	#include
39		42
40		43
41	int radeon_no_wb = 1;	44	int radeon_no_wb = 1;
42	int radeon_modeset = -1;	45	int radeon_modeset = -1;
43	int radeon_dynclks = -1;	46	int radeon_dynclks = -1;
44	int radeon_r4xx_atom = 0;	47	int radeon_r4xx_atom = 0;
45	int radeon_agpmode = 0;	48	int radeon_agpmode = 0;
46	int radeon_vram_limit = 0;	49	int radeon_vram_limit = 0;
47	int radeon_gart_size = 512; /* default gart size */	50	int radeon_gart_size = 512; /* default gart size */
48	int radeon_benchmarking = 0;	51	int radeon_benchmarking = 0;
49	int radeon_testing = 0;	52	int radeon_testing = 0;
50	int radeon_connector_table = 0;	53	int radeon_connector_table = 0;
51	int radeon_tv = 1;	54	int radeon_tv = 1;
52	int radeon_new_pll = -1;	55	int radeon_new_pll = -1;
53	int radeon_dynpm = -1;	56	int radeon_dynpm = -1;
54	int radeon_audio = 1;	57	int radeon_audio = 1;
55	int radeon_hw_i2c = 0;	58	int radeon_hw_i2c = 0;
56	int radeon_pcie_gen2 = 0;	59	int radeon_pcie_gen2 = 0;
57	int radeon_disp_priority = 0;	60	int radeon_disp_priority = 0;
58	int radeon_lockup_timeout = 10000;	61	int radeon_lockup_timeout = 10000;
59		62
60		63
61	int irq_override = 0;	64	int irq_override = 0;
62		65
63		66
64	extern display_t *rdisplay;	67	extern display_t *rdisplay;
-		68	struct drm_device *main_drm_device;
-		69
65		70
66	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);	71	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);
67	int init_display(struct radeon_device rdev, videomode_t mode);	72	int init_display(struct radeon_device rdev, videomode_t mode);
68	int init_display_kms(struct radeon_device rdev, videomode_t mode);	73	int init_display_kms(struct radeon_device rdev, videomode_t mode);
69		74
70	int get_modes(videomode_t mode, u32_t count);	75	int get_modes(videomode_t mode, u32_t count);
71	int set_user_mode(videomode_t *mode);	76	int set_user_mode(videomode_t *mode);
72	int r100_2D_test(struct radeon_device *rdev);	77	int r100_2D_test(struct radeon_device *rdev);
73		78
74		79
75	/* Legacy VGA regions */	80	/* Legacy VGA regions */
76	#define VGA_RSRC_NONE 0x00	81	#define VGA_RSRC_NONE 0x00
77	#define VGA_RSRC_LEGACY_IO 0x01	82	#define VGA_RSRC_LEGACY_IO 0x01
78	#define VGA_RSRC_LEGACY_MEM 0x02	83	#define VGA_RSRC_LEGACY_MEM 0x02
79	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)	84	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
80	/* Non-legacy access */	85	/* Non-legacy access */
81	#define VGA_RSRC_NORMAL_IO 0x04	86	#define VGA_RSRC_NORMAL_IO 0x04
82	#define VGA_RSRC_NORMAL_MEM 0x08	87	#define VGA_RSRC_NORMAL_MEM 0x08
83		88
84		89
85	static const char radeon_family_name[][16] = {	90	static const char radeon_family_name[][16] = {
86	"R100",	91	"R100",
87	"RV100",	92	"RV100",
88	"RS100",	93	"RS100",
89	"RV200",	94	"RV200",
90	"RS200",	95	"RS200",
91	"R200",	96	"R200",
92	"RV250",	97	"RV250",
93	"RS300",	98	"RS300",
94	"RV280",	99	"RV280",
95	"R300",	100	"R300",
96	"R350",	101	"R350",
97	"RV350",	102	"RV350",
98	"RV380",	103	"RV380",
99	"R420",	104	"R420",
100	"R423",	105	"R423",
101	"RV410",	106	"RV410",
102	"RS400",	107	"RS400",
103	"RS480",	108	"RS480",
104	"RS600",	109	"RS600",
105	"RS690",	110	"RS690",
106	"RS740",	111	"RS740",
107	"RV515",	112	"RV515",
108	"R520",	113	"R520",
109	"RV530",	114	"RV530",
110	"RV560",	115	"RV560",
111	"RV570",	116	"RV570",
112	"R580",	117	"R580",
113	"R600",	118	"R600",
114	"RV610",	119	"RV610",
115	"RV630",	120	"RV630",
116	"RV670",	121	"RV670",
117	"RV620",	122	"RV620",
118	"RV635",	123	"RV635",
119	"RS780",	124	"RS780",
120	"RS880",	125	"RS880",
121	"RV770",	126	"RV770",
122	"RV730",	127	"RV730",
123	"RV710",	128	"RV710",
124	"RV740",	129	"RV740",
125	"CEDAR",	130	"CEDAR",
126	"REDWOOD",	131	"REDWOOD",
127	"JUNIPER",	132	"JUNIPER",
128	"CYPRESS",	133	"CYPRESS",
129	"HEMLOCK",	134	"HEMLOCK",
130	"PALM",	135	"PALM",
131	"SUMO",	136	"SUMO",
132	"SUMO2",	137	"SUMO2",
133	"BARTS",	138	"BARTS",
134	"TURKS",	139	"TURKS",
135	"CAICOS",	140	"CAICOS",
136	"CAYMAN",	141	"CAYMAN",
137	"ARUBA",	142	"ARUBA",
138	"TAHITI",	143	"TAHITI",
139	"PITCAIRN",	144	"PITCAIRN",
140	"VERDE",	145	"VERDE",
141	"LAST",	146	"LAST",
142	};	147	};
143		148
144	/**	149	/**
145	* radeon_surface_init - Clear GPU surface registers.	150	* radeon_surface_init - Clear GPU surface registers.
146	*	151	*
147	* @rdev: radeon_device pointer	152	* @rdev: radeon_device pointer
148	*	153	*
149	* Clear GPU surface registers (r1xx-r5xx).	154	* Clear GPU surface registers (r1xx-r5xx).
150	*/	155	*/
151	void radeon_surface_init(struct radeon_device *rdev)	156	void radeon_surface_init(struct radeon_device *rdev)
152	{	157	{
153	/* FIXME: check this out */	158	/* FIXME: check this out */
154	if (rdev->family < CHIP_R600) {	159	if (rdev->family < CHIP_R600) {
155	int i;	160	int i;
156		161
157	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {	162	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
158	radeon_clear_surface_reg(rdev, i);	163	radeon_clear_surface_reg(rdev, i);
159	}	164	}
160	/* enable surfaces */	165	/* enable surfaces */
161	WREG32(RADEON_SURFACE_CNTL, 0);	166	WREG32(RADEON_SURFACE_CNTL, 0);
162	}	167	}
163	}	168	}
164		169
165	/*	170	/*
166	* GPU scratch registers helpers function.	171	* GPU scratch registers helpers function.
167	*/	172	*/
168	/**	173	/**
169	* radeon_scratch_init - Init scratch register driver information.	174	* radeon_scratch_init - Init scratch register driver information.
170	*	175	*
171	* @rdev: radeon_device pointer	176	* @rdev: radeon_device pointer
172	*	177	*
173	* Init CP scratch register driver information (r1xx-r5xx)	178	* Init CP scratch register driver information (r1xx-r5xx)
174	*/	179	*/
175	void radeon_scratch_init(struct radeon_device *rdev)	180	void radeon_scratch_init(struct radeon_device *rdev)
176	{	181	{
177	int i;	182	int i;
178		183
179	/* FIXME: check this out */	184	/* FIXME: check this out */
180	if (rdev->family < CHIP_R300) {	185	if (rdev->family < CHIP_R300) {
181	rdev->scratch.num_reg = 5;	186	rdev->scratch.num_reg = 5;
182	} else {	187	} else {
183	rdev->scratch.num_reg = 7;	188	rdev->scratch.num_reg = 7;
184	}	189	}
185	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;	190	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
186	for (i = 0; i < rdev->scratch.num_reg; i++) {	191	for (i = 0; i < rdev->scratch.num_reg; i++) {
187	rdev->scratch.free[i] = true;	192	rdev->scratch.free[i] = true;
188	rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);	193	rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
189	}	194	}
190	}	195	}
191		196
192	/**	197	/**
193	* radeon_scratch_get - Allocate a scratch register	198	* radeon_scratch_get - Allocate a scratch register
194	*	199	*
195	* @rdev: radeon_device pointer	200	* @rdev: radeon_device pointer
196	* @reg: scratch register mmio offset	201	* @reg: scratch register mmio offset
197	*	202	*
198	* Allocate a CP scratch register for use by the driver (all asics).	203	* Allocate a CP scratch register for use by the driver (all asics).
199	* Returns 0 on success or -EINVAL on failure.	204	* Returns 0 on success or -EINVAL on failure.
200	*/	205	*/
201	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)	206	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
202	{	207	{
203	int i;	208	int i;
204		209
205	for (i = 0; i < rdev->scratch.num_reg; i++) {	210	for (i = 0; i < rdev->scratch.num_reg; i++) {
206	if (rdev->scratch.free[i]) {	211	if (rdev->scratch.free[i]) {
207	rdev->scratch.free[i] = false;	212	rdev->scratch.free[i] = false;
208	*reg = rdev->scratch.reg[i];	213	*reg = rdev->scratch.reg[i];
209	return 0;	214	return 0;
210	}	215	}
211	}	216	}
212	return -EINVAL;	217	return -EINVAL;
213	}	218	}
214		219
215	/**	220	/**
216	* radeon_scratch_free - Free a scratch register	221	* radeon_scratch_free - Free a scratch register
217	*	222	*
218	* @rdev: radeon_device pointer	223	* @rdev: radeon_device pointer
219	* @reg: scratch register mmio offset	224	* @reg: scratch register mmio offset
220	*	225	*
221	* Free a CP scratch register allocated for use by the driver (all asics)	226	* Free a CP scratch register allocated for use by the driver (all asics)
222	*/	227	*/
223	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)	228	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
224	{	229	{
225	int i;	230	int i;
226		231
227	for (i = 0; i < rdev->scratch.num_reg; i++) {	232	for (i = 0; i < rdev->scratch.num_reg; i++) {
228	if (rdev->scratch.reg[i] == reg) {	233	if (rdev->scratch.reg[i] == reg) {
229	rdev->scratch.free[i] = true;	234	rdev->scratch.free[i] = true;
230	return;	235	return;
231	}	236	}
232	}	237	}
233	}	238	}
234		239
235	/*	240	/*
236	* radeon_wb_*()	241	* radeon_wb_*()
237	* Writeback is the the method by which the the GPU updates special pages	242	* Writeback is the the method by which the the GPU updates special pages
238	* in memory with the status of certain GPU events (fences, ring pointers,	243	* in memory with the status of certain GPU events (fences, ring pointers,
239	* etc.).	244	* etc.).
240	*/	245	*/
241		246
242	/**	247	/**
243	* radeon_wb_disable - Disable Writeback	248	* radeon_wb_disable - Disable Writeback
244	*	249	*
245	* @rdev: radeon_device pointer	250	* @rdev: radeon_device pointer
246	*	251	*
247	* Disables Writeback (all asics). Used for suspend.	252	* Disables Writeback (all asics). Used for suspend.
248	*/	253	*/
249	void radeon_wb_disable(struct radeon_device *rdev)	254	void radeon_wb_disable(struct radeon_device *rdev)
250	{	255	{
251	int r;	256	int r;
252		257
253	if (rdev->wb.wb_obj) {	258	if (rdev->wb.wb_obj) {
254	r = radeon_bo_reserve(rdev->wb.wb_obj, false);	259	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
255	if (unlikely(r != 0))	260	if (unlikely(r != 0))
256	return;	261	return;
257	radeon_bo_kunmap(rdev->wb.wb_obj);	262	radeon_bo_kunmap(rdev->wb.wb_obj);
258	radeon_bo_unpin(rdev->wb.wb_obj);	263	radeon_bo_unpin(rdev->wb.wb_obj);
259	radeon_bo_unreserve(rdev->wb.wb_obj);	264	radeon_bo_unreserve(rdev->wb.wb_obj);
260	}	265	}
261	rdev->wb.enabled = false;	266	rdev->wb.enabled = false;
262	}	267	}
263		268
264	/**	269	/**
265	* radeon_wb_fini - Disable Writeback and free memory	270	* radeon_wb_fini - Disable Writeback and free memory
266	*	271	*
267	* @rdev: radeon_device pointer	272	* @rdev: radeon_device pointer
268	*	273	*
269	* Disables Writeback and frees the Writeback memory (all asics).	274	* Disables Writeback and frees the Writeback memory (all asics).
270	* Used at driver shutdown.	275	* Used at driver shutdown.
271	*/	276	*/
272	void radeon_wb_fini(struct radeon_device *rdev)	277	void radeon_wb_fini(struct radeon_device *rdev)
273	{	278	{
274	radeon_wb_disable(rdev);	279	radeon_wb_disable(rdev);
275	if (rdev->wb.wb_obj) {	280	if (rdev->wb.wb_obj) {
276	radeon_bo_unref(&rdev->wb.wb_obj);	281	radeon_bo_unref(&rdev->wb.wb_obj);
277	rdev->wb.wb = NULL;	282	rdev->wb.wb = NULL;
278	rdev->wb.wb_obj = NULL;	283	rdev->wb.wb_obj = NULL;
279	}	284	}
280	}	285	}
281		286
282	/**	287	/**
283	* radeon_wb_init- Init Writeback driver info and allocate memory	288	* radeon_wb_init- Init Writeback driver info and allocate memory
284	*	289	*
285	* @rdev: radeon_device pointer	290	* @rdev: radeon_device pointer
286	*	291	*
287	* Disables Writeback and frees the Writeback memory (all asics).	292	* Disables Writeback and frees the Writeback memory (all asics).
288	* Used at driver startup.	293	* Used at driver startup.
289	* Returns 0 on success or an -error on failure.	294	* Returns 0 on success or an -error on failure.
290	*/	295	*/
291	int radeon_wb_init(struct radeon_device *rdev)	296	int radeon_wb_init(struct radeon_device *rdev)
292	{	297	{
293	int r;	298	int r;
294		299
295	if (rdev->wb.wb_obj == NULL) {	300	if (rdev->wb.wb_obj == NULL) {
296	r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,	301	r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
297	RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);	302	RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
298	if (r) {	303	if (r) {
299	dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);	304	dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
300	return r;	305	return r;
301	}	306	}
302	}	307	}
303	r = radeon_bo_reserve(rdev->wb.wb_obj, false);	308	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
304	if (unlikely(r != 0)) {	309	if (unlikely(r != 0)) {
305	radeon_wb_fini(rdev);	310	radeon_wb_fini(rdev);
306	return r;	311	return r;
307	}	312	}
308	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,	313	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
309	&rdev->wb.gpu_addr);	314	&rdev->wb.gpu_addr);
310	if (r) {	315	if (r) {
311	radeon_bo_unreserve(rdev->wb.wb_obj);	316	radeon_bo_unreserve(rdev->wb.wb_obj);
312	dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);	317	dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
313	radeon_wb_fini(rdev);	318	radeon_wb_fini(rdev);
314	return r;	319	return r;
315	}	320	}
316	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);	321	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
317	radeon_bo_unreserve(rdev->wb.wb_obj);	322	radeon_bo_unreserve(rdev->wb.wb_obj);
318	if (r) {	323	if (r) {
319	dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);	324	dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
320	radeon_wb_fini(rdev);	325	radeon_wb_fini(rdev);
321	return r;	326	return r;
322	}	327	}
323		328
324	/* clear wb memory */	329	/* clear wb memory */
325	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);	330	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
326	/* disable event_write fences */	331	/* disable event_write fences */
327	rdev->wb.use_event = false;	332	rdev->wb.use_event = false;
328	/* disabled via module param */	333	/* disabled via module param */
329	if (radeon_no_wb == 1) {	334	if (radeon_no_wb == 1) {
330	rdev->wb.enabled = false;	335	rdev->wb.enabled = false;
331	} else {	336	} else {
332	if (rdev->flags & RADEON_IS_AGP) {	337	if (rdev->flags & RADEON_IS_AGP) {
333	/* often unreliable on AGP */	338	/* often unreliable on AGP */
334	rdev->wb.enabled = false;	339	rdev->wb.enabled = false;
335	} else if (rdev->family < CHIP_R300) {	340	} else if (rdev->family < CHIP_R300) {
336	/* often unreliable on pre-r300 */	341	/* often unreliable on pre-r300 */
337	rdev->wb.enabled = false;	342	rdev->wb.enabled = false;
338	} else {	343	} else {
339	rdev->wb.enabled = true;	344	rdev->wb.enabled = true;
340	/* event_write fences are only available on r600+ */	345	/* event_write fences are only available on r600+ */
341	if (rdev->family >= CHIP_R600) {	346	if (rdev->family >= CHIP_R600) {
342	rdev->wb.use_event = true;	347	rdev->wb.use_event = true;
343	}	348	}
344	}	349	}
345	}	350	}
346	/* always use writeback/events on NI, APUs */	351	/* always use writeback/events on NI, APUs */
347	if (rdev->family >= CHIP_PALM) {	352	if (rdev->family >= CHIP_PALM) {
348	rdev->wb.enabled = true;	353	rdev->wb.enabled = true;
349	rdev->wb.use_event = true;	354	rdev->wb.use_event = true;
350	}	355	}
351		356
352	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");	357	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
353		358
354	return 0;	359	return 0;
355	}	360	}
356		361
357	/**	362	/**
358	* radeon_vram_location - try to find VRAM location	363	* radeon_vram_location - try to find VRAM location
359	* @rdev: radeon device structure holding all necessary informations	364	* @rdev: radeon device structure holding all necessary informations
360	* @mc: memory controller structure holding memory informations	365	* @mc: memory controller structure holding memory informations
361	* @base: base address at which to put VRAM	366	* @base: base address at which to put VRAM
362	*	367	*
363	* Function will place try to place VRAM at base address provided	368	* Function will place try to place VRAM at base address provided
364	* as parameter (which is so far either PCI aperture address or	369	* as parameter (which is so far either PCI aperture address or
365	* for IGP TOM base address).	370	* for IGP TOM base address).
366	*	371	*
367	* If there is not enough space to fit the unvisible VRAM in the 32bits	372	* If there is not enough space to fit the unvisible VRAM in the 32bits
368	* address space then we limit the VRAM size to the aperture.	373	* address space then we limit the VRAM size to the aperture.
369	*	374	*
370	* If we are using AGP and if the AGP aperture doesn't allow us to have	375	* If we are using AGP and if the AGP aperture doesn't allow us to have
371	* room for all the VRAM than we restrict the VRAM to the PCI aperture	376	* room for all the VRAM than we restrict the VRAM to the PCI aperture
372	* size and print a warning.	377	* size and print a warning.
373	*	378	*
374	* This function will never fails, worst case are limiting VRAM.	379	* This function will never fails, worst case are limiting VRAM.
375	*	380	*
376	* Note: GTT start, end, size should be initialized before calling this	381	* Note: GTT start, end, size should be initialized before calling this
377	* function on AGP platform.	382	* function on AGP platform.
378	*	383	*
379	* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,	384	* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
380	* this shouldn't be a problem as we are using the PCI aperture as a reference.	385	* this shouldn't be a problem as we are using the PCI aperture as a reference.
381	* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but	386	* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
382	* not IGP.	387	* not IGP.
383	*	388	*
384	* Note: we use mc_vram_size as on some board we need to program the mc to	389	* Note: we use mc_vram_size as on some board we need to program the mc to
385	* cover the whole aperture even if VRAM size is inferior to aperture size	390	* cover the whole aperture even if VRAM size is inferior to aperture size
386	* Novell bug 204882 + along with lots of ubuntu ones	391	* Novell bug 204882 + along with lots of ubuntu ones
387	*	392	*
388	* Note: when limiting vram it's safe to overwritte real_vram_size because	393	* Note: when limiting vram it's safe to overwritte real_vram_size because
389	* we are not in case where real_vram_size is inferior to mc_vram_size (ie	394	* we are not in case where real_vram_size is inferior to mc_vram_size (ie
390	* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu	395	* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
391	* ones)	396	* ones)
392	*	397	*
393	* Note: IGP TOM addr should be the same as the aperture addr, we don't	398	* Note: IGP TOM addr should be the same as the aperture addr, we don't
394	* explicitly check for that thought.	399	* explicitly check for that thought.
395	*	400	*
396	* FIXME: when reducing VRAM size align new size on power of 2.	401	* FIXME: when reducing VRAM size align new size on power of 2.
397	*/	402	*/
398	void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base)	403	void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base)
399	{	404	{
400	uint64_t limit = (uint64_t)radeon_vram_limit << 20;	405	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
401		406
402	mc->vram_start = base;	407	mc->vram_start = base;
403	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {	408	if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
404	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");	409	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
405	mc->real_vram_size = mc->aper_size;	410	mc->real_vram_size = mc->aper_size;
406	mc->mc_vram_size = mc->aper_size;	411	mc->mc_vram_size = mc->aper_size;
407	}	412	}
408	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;	413	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
409	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {	414	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
410	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");	415	dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
411	mc->real_vram_size = mc->aper_size;	416	mc->real_vram_size = mc->aper_size;
412	mc->mc_vram_size = mc->aper_size;	417	mc->mc_vram_size = mc->aper_size;
413	}	418	}
414	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;	419	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
415	if (limit && limit < mc->real_vram_size)	420	if (limit && limit < mc->real_vram_size)
416	mc->real_vram_size = limit;	421	mc->real_vram_size = limit;
417	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",	422	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
418	mc->mc_vram_size >> 20, mc->vram_start,	423	mc->mc_vram_size >> 20, mc->vram_start,
419	mc->vram_end, mc->real_vram_size >> 20);	424	mc->vram_end, mc->real_vram_size >> 20);
420	}	425	}
421		426
422	/**	427	/**
423	* radeon_gtt_location - try to find GTT location	428	* radeon_gtt_location - try to find GTT location
424	* @rdev: radeon device structure holding all necessary informations	429	* @rdev: radeon device structure holding all necessary informations
425	* @mc: memory controller structure holding memory informations	430	* @mc: memory controller structure holding memory informations
426	*	431	*
427	* Function will place try to place GTT before or after VRAM.	432	* Function will place try to place GTT before or after VRAM.
428	*	433	*
429	* If GTT size is bigger than space left then we ajust GTT size.	434	* If GTT size is bigger than space left then we ajust GTT size.
430	* Thus function will never fails.	435	* Thus function will never fails.
431	*	436	*
432	* FIXME: when reducing GTT size align new size on power of 2.	437	* FIXME: when reducing GTT size align new size on power of 2.
433	*/	438	*/
434	void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc)	439	void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc)
435	{	440	{
436	u64 size_af, size_bf;	441	u64 size_af, size_bf;
437		442
438	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;	443	size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
439	size_bf = mc->vram_start & ~mc->gtt_base_align;	444	size_bf = mc->vram_start & ~mc->gtt_base_align;
440	if (size_bf > size_af) {	445	if (size_bf > size_af) {
441	if (mc->gtt_size > size_bf) {	446	if (mc->gtt_size > size_bf) {
442	dev_warn(rdev->dev, "limiting GTT\n");	447	dev_warn(rdev->dev, "limiting GTT\n");
443	mc->gtt_size = size_bf;	448	mc->gtt_size = size_bf;
444	}	449	}
445	mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;	450	mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
446	} else {	451	} else {
447	if (mc->gtt_size > size_af) {	452	if (mc->gtt_size > size_af) {
448	dev_warn(rdev->dev, "limiting GTT\n");	453	dev_warn(rdev->dev, "limiting GTT\n");
449	mc->gtt_size = size_af;	454	mc->gtt_size = size_af;
450	}	455	}
451	mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;	456	mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
452	}	457	}
453	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;	458	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
454	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",	459	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
455	mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);	460	mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
456	}	461	}
457		462
458	/*	463	/*
459	* GPU helpers function.	464	* GPU helpers function.
460	*/	465	*/
461	/**	466	/**
462	* radeon_card_posted - check if the hw has already been initialized	467	* radeon_card_posted - check if the hw has already been initialized
463	*	468	*
464	* @rdev: radeon_device pointer	469	* @rdev: radeon_device pointer
465	*	470	*
466	* Check if the asic has been initialized (all asics).	471	* Check if the asic has been initialized (all asics).
467	* Used at driver startup.	472	* Used at driver startup.
468	* Returns true if initialized or false if not.	473	* Returns true if initialized or false if not.
469	*/	474	*/
470	bool radeon_card_posted(struct radeon_device *rdev)	475	bool radeon_card_posted(struct radeon_device *rdev)
471	{	476	{
472	uint32_t reg;	477	uint32_t reg;
473		478
474	/* first check CRTCs */	479	/* first check CRTCs */
475	if (ASIC_IS_DCE41(rdev)) {	480	if (ASIC_IS_DCE41(rdev)) {
476	reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|	481	reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|
477	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);	482	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
478	if (reg & EVERGREEN_CRTC_MASTER_EN)	483	if (reg & EVERGREEN_CRTC_MASTER_EN)
479	return true;	484	return true;
480	} else if (ASIC_IS_DCE4(rdev)) {	485	} else if (ASIC_IS_DCE4(rdev)) {
481	reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|	486	reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|
482	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) \|	487	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) \|
483	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) \|	488	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) \|
484	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) \|	489	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) \|
485	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) \|	490	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) \|
486	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);	491	RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
487	if (reg & EVERGREEN_CRTC_MASTER_EN)	492	if (reg & EVERGREEN_CRTC_MASTER_EN)
488	return true;	493	return true;
489	} else if (ASIC_IS_AVIVO(rdev)) {	494	} else if (ASIC_IS_AVIVO(rdev)) {
490	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|	495	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
491	RREG32(AVIVO_D2CRTC_CONTROL);	496	RREG32(AVIVO_D2CRTC_CONTROL);
492	if (reg & AVIVO_CRTC_EN) {	497	if (reg & AVIVO_CRTC_EN) {
493	return true;	498	return true;
494	}	499	}
495	} else {	500	} else {

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 3031 → 3120