Rev 5078 | Only display areas with differences | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 5078 | Rev 6104 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright 2008 Red Hat Inc. |
2 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2009 Jerome Glisse. |
3 | * Copyright 2009 Jerome Glisse. |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
13 | * all copies or substantial portions of the Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Dave Airlie |
24 | * Dave Airlie |
25 | * Jerome Glisse |
25 | * Jerome Glisse |
26 | */ |
26 | */ |
27 | #include |
27 | #include |
28 | #include "radeon.h" |
28 | #include "radeon.h" |
29 | #include |
29 | #include |
30 | 30 | ||
31 | #if __OS_HAS_AGP |
31 | #if IS_ENABLED(CONFIG_AGP) |
32 | 32 | ||
33 | struct radeon_agpmode_quirk { |
33 | struct radeon_agpmode_quirk { |
34 | u32 hostbridge_vendor; |
34 | u32 hostbridge_vendor; |
35 | u32 hostbridge_device; |
35 | u32 hostbridge_device; |
36 | u32 chip_vendor; |
36 | u32 chip_vendor; |
37 | u32 chip_device; |
37 | u32 chip_device; |
38 | u32 subsys_vendor; |
38 | u32 subsys_vendor; |
39 | u32 subsys_device; |
39 | u32 subsys_device; |
40 | u32 default_mode; |
40 | u32 default_mode; |
41 | }; |
41 | }; |
42 | 42 | ||
43 | static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { |
43 | static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { |
44 | /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */ |
44 | /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */ |
45 | { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4}, |
45 | { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4}, |
46 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ |
46 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ |
47 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4}, |
47 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4}, |
48 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */ |
48 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */ |
49 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964, |
49 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964, |
50 | 0x148c, 0x2073, 4}, |
50 | 0x148c, 0x2073, 4}, |
51 | /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ |
51 | /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ |
52 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59, |
52 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59, |
53 | PCI_VENDOR_ID_IBM, 0x052f, 1}, |
53 | PCI_VENDOR_ID_IBM, 0x052f, 1}, |
54 | /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */ |
54 | /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */ |
55 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50, |
55 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50, |
56 | PCI_VENDOR_ID_IBM, 0x0550, 1}, |
56 | PCI_VENDOR_ID_IBM, 0x0550, 1}, |
- | 57 | /* Intel 82855PM host bridge / RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] needs AGPMode 1 (Thinkpad T40p) */ |
|
- | 58 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, |
|
- | 59 | PCI_VENDOR_ID_IBM, 0x054d, 1}, |
|
57 | /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */ |
60 | /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */ |
58 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57, |
61 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57, |
59 | PCI_VENDOR_ID_IBM, 0x0530, 1}, |
62 | PCI_VENDOR_ID_IBM, 0x0530, 1}, |
60 | /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */ |
63 | /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */ |
61 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54, |
64 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54, |
62 | PCI_VENDOR_ID_IBM, 0x054f, 2}, |
65 | PCI_VENDOR_ID_IBM, 0x054f, 2}, |
63 | /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */ |
66 | /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */ |
64 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
67 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
65 | PCI_VENDOR_ID_SONY, 0x816b, 2}, |
68 | PCI_VENDOR_ID_SONY, 0x816b, 2}, |
66 | /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */ |
69 | /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */ |
67 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
70 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
68 | PCI_VENDOR_ID_SONY, 0x8195, 8}, |
71 | PCI_VENDOR_ID_SONY, 0x8195, 8}, |
69 | /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ |
72 | /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ |
70 | { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, |
73 | { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, |
71 | PCI_VENDOR_ID_DELL, 0x00e3, 2}, |
74 | PCI_VENDOR_ID_DELL, 0x00e3, 2}, |
72 | /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */ |
75 | /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */ |
73 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, |
76 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, |
74 | PCI_VENDOR_ID_DELL, 0x0149, 1}, |
77 | PCI_VENDOR_ID_DELL, 0x0149, 1}, |
75 | /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */ |
78 | /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */ |
76 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, |
79 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, |
77 | PCI_VENDOR_ID_IBM, 0x0531, 1}, |
80 | PCI_VENDOR_ID_IBM, 0x0531, 1}, |
78 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ |
81 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ |
79 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
82 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
80 | 0x1025, 0x0061, 1}, |
83 | 0x1025, 0x0061, 1}, |
81 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */ |
84 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */ |
82 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
85 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
83 | 0x1025, 0x0064, 1}, |
86 | 0x1025, 0x0064, 1}, |
84 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */ |
87 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */ |
85 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
88 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
86 | PCI_VENDOR_ID_ASUSTEK, 0x1942, 1}, |
89 | PCI_VENDOR_ID_ASUSTEK, 0x1942, 1}, |
87 | /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */ |
90 | /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */ |
88 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
91 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
89 | 0x10cf, 0x127f, 1}, |
92 | 0x10cf, 0x127f, 1}, |
90 | /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */ |
93 | /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */ |
91 | { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
94 | { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
92 | 0x1787, 0x5960, 4}, |
95 | 0x1787, 0x5960, 4}, |
93 | /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */ |
96 | /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */ |
94 | { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960, |
97 | { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960, |
95 | 0x17af, 0x2020, 4}, |
98 | 0x17af, 0x2020, 4}, |
96 | /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */ |
99 | /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */ |
97 | { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153, |
100 | { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153, |
98 | PCI_VENDOR_ID_ASUSTEK, 0x003c, 4}, |
101 | PCI_VENDOR_ID_ASUSTEK, 0x003c, 4}, |
99 | /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */ |
102 | /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */ |
100 | { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c, |
103 | { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c, |
101 | PCI_VENDOR_ID_ATI, 0x013a, 2}, |
104 | PCI_VENDOR_ID_ATI, 0x013a, 2}, |
102 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */ |
105 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */ |
103 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
106 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
104 | PCI_VENDOR_ID_ASUSTEK, 0x004c, 2}, |
107 | PCI_VENDOR_ID_ASUSTEK, 0x004c, 2}, |
105 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */ |
108 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */ |
106 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
109 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
107 | PCI_VENDOR_ID_ASUSTEK, 0x0054, 2}, |
110 | PCI_VENDOR_ID_ASUSTEK, 0x0054, 2}, |
108 | /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ |
111 | /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ |
109 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d, |
112 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d, |
110 | 0x174b, 0x7149, 4}, |
113 | 0x174b, 0x7149, 4}, |
111 | /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */ |
114 | /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */ |
112 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
115 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
113 | 0x1462, 0x0380, 4}, |
116 | 0x1462, 0x0380, 4}, |
114 | /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */ |
117 | /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */ |
115 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964, |
118 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964, |
116 | 0x148c, 0x2073, 4}, |
119 | 0x148c, 0x2073, 4}, |
117 | /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */ |
120 | /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */ |
118 | { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61, |
121 | { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61, |
119 | PCI_VENDOR_ID_SONY, 0x8175, 1}, |
122 | PCI_VENDOR_ID_SONY, 0x8175, 1}, |
120 | { 0, 0, 0, 0, 0, 0, 0 }, |
123 | { 0, 0, 0, 0, 0, 0, 0 }, |
121 | }; |
124 | }; |
122 | #endif |
125 | #endif |
123 | 126 | ||
124 | int radeon_agp_init(struct radeon_device *rdev) |
127 | int radeon_agp_init(struct radeon_device *rdev) |
125 | { |
128 | { |
126 | #if __OS_HAS_AGP |
129 | #if IS_ENABLED(CONFIG_AGP) |
127 | struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list; |
130 | struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list; |
128 | struct drm_agp_mode mode; |
131 | struct drm_agp_mode mode; |
129 | struct drm_agp_info info; |
132 | struct drm_agp_info info; |
130 | uint32_t agp_status; |
133 | uint32_t agp_status; |
131 | int default_mode; |
134 | int default_mode; |
132 | bool is_v3; |
135 | bool is_v3; |
133 | int ret; |
136 | int ret; |
134 | 137 | ||
135 | /* Acquire AGP. */ |
138 | /* Acquire AGP. */ |
136 | ret = drm_agp_acquire(rdev->ddev); |
139 | ret = drm_agp_acquire(rdev->ddev); |
137 | if (ret) { |
140 | if (ret) { |
138 | DRM_ERROR("Unable to acquire AGP: %d\n", ret); |
141 | DRM_ERROR("Unable to acquire AGP: %d\n", ret); |
139 | return ret; |
142 | return ret; |
140 | } |
143 | } |
141 | 144 | ||
142 | ret = drm_agp_info(rdev->ddev, &info); |
145 | ret = drm_agp_info(rdev->ddev, &info); |
143 | if (ret) { |
146 | if (ret) { |
144 | drm_agp_release(rdev->ddev); |
147 | drm_agp_release(rdev->ddev); |
145 | DRM_ERROR("Unable to get AGP info: %d\n", ret); |
148 | DRM_ERROR("Unable to get AGP info: %d\n", ret); |
146 | return ret; |
149 | return ret; |
147 | } |
150 | } |
148 | 151 | ||
149 | if (rdev->ddev->agp->agp_info.aper_size < 32) { |
152 | if (rdev->ddev->agp->agp_info.aper_size < 32) { |
150 | drm_agp_release(rdev->ddev); |
153 | drm_agp_release(rdev->ddev); |
151 | dev_warn(rdev->dev, "AGP aperture too small (%zuM) " |
154 | dev_warn(rdev->dev, "AGP aperture too small (%zuM) " |
152 | "need at least 32M, disabling AGP\n", |
155 | "need at least 32M, disabling AGP\n", |
153 | rdev->ddev->agp->agp_info.aper_size); |
156 | rdev->ddev->agp->agp_info.aper_size); |
154 | return -EINVAL; |
157 | return -EINVAL; |
155 | } |
158 | } |
156 | 159 | ||
157 | mode.mode = info.mode; |
160 | mode.mode = info.mode; |
158 | /* chips with the agp to pcie bridge don't have the AGP_STATUS register |
161 | /* chips with the agp to pcie bridge don't have the AGP_STATUS register |
159 | * Just use the whatever mode the host sets up. |
162 | * Just use the whatever mode the host sets up. |
160 | */ |
163 | */ |
161 | if (rdev->family <= CHIP_RV350) |
164 | if (rdev->family <= CHIP_RV350) |
162 | agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; |
165 | agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; |
163 | else |
166 | else |
164 | agp_status = mode.mode; |
167 | agp_status = mode.mode; |
165 | is_v3 = !!(agp_status & RADEON_AGPv3_MODE); |
168 | is_v3 = !!(agp_status & RADEON_AGPv3_MODE); |
166 | 169 | ||
167 | if (is_v3) { |
170 | if (is_v3) { |
168 | default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; |
171 | default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; |
169 | } else { |
172 | } else { |
170 | if (agp_status & RADEON_AGP_4X_MODE) { |
173 | if (agp_status & RADEON_AGP_4X_MODE) { |
171 | default_mode = 4; |
174 | default_mode = 4; |
172 | } else if (agp_status & RADEON_AGP_2X_MODE) { |
175 | } else if (agp_status & RADEON_AGP_2X_MODE) { |
173 | default_mode = 2; |
176 | default_mode = 2; |
174 | } else { |
177 | } else { |
175 | default_mode = 1; |
178 | default_mode = 1; |
176 | } |
179 | } |
177 | } |
180 | } |
178 | 181 | ||
179 | /* Apply AGPMode Quirks */ |
182 | /* Apply AGPMode Quirks */ |
180 | while (p && p->chip_device != 0) { |
183 | while (p && p->chip_device != 0) { |
181 | if (info.id_vendor == p->hostbridge_vendor && |
184 | if (info.id_vendor == p->hostbridge_vendor && |
182 | info.id_device == p->hostbridge_device && |
185 | info.id_device == p->hostbridge_device && |
183 | rdev->pdev->vendor == p->chip_vendor && |
186 | rdev->pdev->vendor == p->chip_vendor && |
184 | rdev->pdev->device == p->chip_device && |
187 | rdev->pdev->device == p->chip_device && |
185 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
188 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
186 | rdev->pdev->subsystem_device == p->subsys_device) { |
189 | rdev->pdev->subsystem_device == p->subsys_device) { |
187 | default_mode = p->default_mode; |
190 | default_mode = p->default_mode; |
188 | } |
191 | } |
189 | ++p; |
192 | ++p; |
190 | } |
193 | } |
191 | 194 | ||
192 | if (radeon_agpmode > 0) { |
195 | if (radeon_agpmode > 0) { |
193 | if ((radeon_agpmode < (is_v3 ? 4 : 1)) || |
196 | if ((radeon_agpmode < (is_v3 ? 4 : 1)) || |
194 | (radeon_agpmode > (is_v3 ? 8 : 4)) || |
197 | (radeon_agpmode > (is_v3 ? 8 : 4)) || |
195 | (radeon_agpmode & (radeon_agpmode - 1))) { |
198 | (radeon_agpmode & (radeon_agpmode - 1))) { |
196 | DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n", |
199 | DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n", |
197 | radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4", |
200 | radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4", |
198 | default_mode); |
201 | default_mode); |
199 | radeon_agpmode = default_mode; |
202 | radeon_agpmode = default_mode; |
200 | } else { |
203 | } else { |
201 | DRM_INFO("AGP mode requested: %d\n", radeon_agpmode); |
204 | DRM_INFO("AGP mode requested: %d\n", radeon_agpmode); |
202 | } |
205 | } |
203 | } else { |
206 | } else { |
204 | radeon_agpmode = default_mode; |
207 | radeon_agpmode = default_mode; |
205 | } |
208 | } |
206 | 209 | ||
207 | mode.mode &= ~RADEON_AGP_MODE_MASK; |
210 | mode.mode &= ~RADEON_AGP_MODE_MASK; |
208 | if (is_v3) { |
211 | if (is_v3) { |
209 | switch (radeon_agpmode) { |
212 | switch (radeon_agpmode) { |
210 | case 8: |
213 | case 8: |
211 | mode.mode |= RADEON_AGPv3_8X_MODE; |
214 | mode.mode |= RADEON_AGPv3_8X_MODE; |
212 | break; |
215 | break; |
213 | case 4: |
216 | case 4: |
214 | default: |
217 | default: |
215 | mode.mode |= RADEON_AGPv3_4X_MODE; |
218 | mode.mode |= RADEON_AGPv3_4X_MODE; |
216 | break; |
219 | break; |
217 | } |
220 | } |
218 | } else { |
221 | } else { |
219 | switch (radeon_agpmode) { |
222 | switch (radeon_agpmode) { |
220 | case 4: |
223 | case 4: |
221 | mode.mode |= RADEON_AGP_4X_MODE; |
224 | mode.mode |= RADEON_AGP_4X_MODE; |
222 | break; |
225 | break; |
223 | case 2: |
226 | case 2: |
224 | mode.mode |= RADEON_AGP_2X_MODE; |
227 | mode.mode |= RADEON_AGP_2X_MODE; |
225 | break; |
228 | break; |
226 | case 1: |
229 | case 1: |
227 | default: |
230 | default: |
228 | mode.mode |= RADEON_AGP_1X_MODE; |
231 | mode.mode |= RADEON_AGP_1X_MODE; |
229 | break; |
232 | break; |
230 | } |
233 | } |
231 | } |
234 | } |
232 | 235 | ||
233 | mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */ |
236 | mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */ |
234 | ret = drm_agp_enable(rdev->ddev, mode); |
237 | ret = drm_agp_enable(rdev->ddev, mode); |
235 | if (ret) { |
238 | if (ret) { |
236 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); |
239 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); |
237 | drm_agp_release(rdev->ddev); |
240 | drm_agp_release(rdev->ddev); |
238 | return ret; |
241 | return ret; |
239 | } |
242 | } |
240 | 243 | ||
241 | rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base; |
244 | rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base; |
242 | rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20; |
245 | rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20; |
243 | rdev->mc.gtt_start = rdev->mc.agp_base; |
246 | rdev->mc.gtt_start = rdev->mc.agp_base; |
244 | rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; |
247 | rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; |
245 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
248 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n", |
246 | rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end); |
249 | rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end); |
247 | 250 | ||
248 | /* workaround some hw issues */ |
251 | /* workaround some hw issues */ |
249 | if (rdev->family < CHIP_R200) { |
252 | if (rdev->family < CHIP_R200) { |
250 | WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); |
253 | WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); |
251 | } |
254 | } |
252 | return 0; |
255 | return 0; |
253 | #else |
256 | #else |
254 | return -1; |
257 | return -1; |
255 | #endif |
258 | #endif |
256 | } |
259 | } |
257 | 260 | ||
258 | void radeon_agp_resume(struct radeon_device *rdev) |
261 | void radeon_agp_resume(struct radeon_device *rdev) |
259 | { |
262 | { |
260 | #if __OS_HAS_AGP |
263 | #if IS_ENABLED(CONFIG_AGP) |
261 | int r; |
264 | int r; |
262 | if (rdev->flags & RADEON_IS_AGP) { |
265 | if (rdev->flags & RADEON_IS_AGP) { |
263 | r = radeon_agp_init(rdev); |
266 | r = radeon_agp_init(rdev); |
264 | if (r) |
267 | if (r) |
265 | dev_warn(rdev->dev, "radeon AGP reinit failed\n"); |
268 | dev_warn(rdev->dev, "radeon AGP reinit failed\n"); |
266 | } |
269 | } |
267 | #endif |
270 | #endif |
268 | } |
271 | } |
269 | 272 | ||
270 | void radeon_agp_fini(struct radeon_device *rdev) |
273 | void radeon_agp_fini(struct radeon_device *rdev) |
271 | { |
274 | { |
272 | #if __OS_HAS_AGP |
275 | #if IS_ENABLED(CONFIG_AGP) |
273 | if (rdev->ddev->agp && rdev->ddev->agp->acquired) { |
276 | if (rdev->ddev->agp && rdev->ddev->agp->acquired) { |
274 | drm_agp_release(rdev->ddev); |
277 | drm_agp_release(rdev->ddev); |
275 | } |
278 | } |
276 | #endif |
279 | #endif |
277 | } |
280 | } |
278 | 281 | ||
279 | void radeon_agp_suspend(struct radeon_device *rdev) |
282 | void radeon_agp_suspend(struct radeon_device *rdev) |
280 | { |
283 | { |
281 | radeon_agp_fini(rdev); |
284 | radeon_agp_fini(rdev); |
282 | }>><>>=>> |
285 | }>><>>=>> |