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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #ifndef __RADEON_H__ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | 30 | ||
31 | /* TODO: Here are things that needs to be done : |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
34 | * related to surface |
34 | * related to surface |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
36 | * - Vblank : look at Jesse's rework and what we should do |
36 | * - Vblank : look at Jesse's rework and what we should do |
37 | * - r600/r700: gart & cp |
37 | * - r600/r700: gart & cp |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
39 | * - power management stuff |
39 | * - power management stuff |
40 | * - Barrier in gart code |
40 | * - Barrier in gart code |
41 | * - Unmappabled vram ? |
41 | * - Unmappabled vram ? |
42 | * - TESTING, TESTING, TESTING |
42 | * - TESTING, TESTING, TESTING |
43 | */ |
43 | */ |
44 | 44 | ||
45 | /* Initialization path: |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
46 | * We expect that acceleration initialization might fail for various |
47 | * reasons even thought we work hard to make it works on most |
47 | * reasons even thought we work hard to make it works on most |
48 | * configurations. In order to still have a working userspace in such |
48 | * configurations. In order to still have a working userspace in such |
49 | * situation the init path must succeed up to the memory controller |
49 | * situation the init path must succeed up to the memory controller |
50 | * initialization point. Failure before this point are considered as |
50 | * initialization point. Failure before this point are considered as |
51 | * fatal error. Here is the init callchain : |
51 | * fatal error. Here is the init callchain : |
52 | * radeon_device_init perform common structure, mutex initialization |
52 | * radeon_device_init perform common structure, mutex initialization |
53 | * asic_init setup the GPU memory layout and perform all |
53 | * asic_init setup the GPU memory layout and perform all |
54 | * one time initialization (failure in this |
54 | * one time initialization (failure in this |
55 | * function are considered fatal) |
55 | * function are considered fatal) |
56 | * asic_startup setup the GPU acceleration, in order to |
56 | * asic_startup setup the GPU acceleration, in order to |
57 | * follow guideline the first thing this |
57 | * follow guideline the first thing this |
58 | * function should do is setting the GPU |
58 | * function should do is setting the GPU |
59 | * memory controller (only MC setup failure |
59 | * memory controller (only MC setup failure |
60 | * are considered as fatal) |
60 | * are considered as fatal) |
61 | */ |
61 | */ |
- | 62 | ||
62 | 63 | #include |
|
63 | #include |
64 | #include |
64 | 65 | ||
65 | #include |
66 | #include |
66 | #include |
67 | #include |
67 | 68 | ||
68 | #include |
69 | #include |
69 | #include |
70 | #include |
70 | #include |
71 | #include |
71 | #include |
72 | #include |
72 | 73 | ||
73 | 74 | ||
74 | #include |
75 | #include |
75 | 76 | ||
76 | #include |
77 | #include |
77 | #include "drm_edid.h" |
78 | #include "drm_edid.h" |
78 | 79 | ||
79 | #include "radeon_family.h" |
80 | #include "radeon_family.h" |
80 | #include "radeon_mode.h" |
81 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
82 | #include "radeon_reg.h" |
82 | 83 | ||
83 | #include |
84 | #include |
84 | 85 | ||
85 | /* |
86 | /* |
86 | * Modules parameters. |
87 | * Modules parameters. |
87 | */ |
88 | */ |
88 | extern int radeon_no_wb; |
89 | extern int radeon_no_wb; |
89 | extern int radeon_modeset; |
90 | extern int radeon_modeset; |
90 | extern int radeon_dynclks; |
91 | extern int radeon_dynclks; |
91 | extern int radeon_r4xx_atom; |
92 | extern int radeon_r4xx_atom; |
92 | extern int radeon_agpmode; |
93 | extern int radeon_agpmode; |
93 | extern int radeon_vram_limit; |
94 | extern int radeon_vram_limit; |
94 | extern int radeon_gart_size; |
95 | extern int radeon_gart_size; |
95 | extern int radeon_benchmarking; |
96 | extern int radeon_benchmarking; |
96 | extern int radeon_testing; |
97 | extern int radeon_testing; |
97 | extern int radeon_connector_table; |
98 | extern int radeon_connector_table; |
98 | extern int radeon_tv; |
99 | extern int radeon_tv; |
99 | extern int radeon_new_pll; |
100 | extern int radeon_new_pll; |
100 | extern int radeon_dynpm; |
101 | extern int radeon_dynpm; |
101 | extern int radeon_audio; |
102 | extern int radeon_audio; |
102 | 103 | ||
103 | typedef struct pm_message { |
104 | typedef struct pm_message { |
104 | int event; |
105 | int event; |
105 | } pm_message_t; |
106 | } pm_message_t; |
106 | 107 | ||
107 | typedef struct |
108 | typedef struct |
108 | { |
109 | { |
109 | int width; |
110 | int width; |
110 | int height; |
111 | int height; |
111 | int bpp; |
112 | int bpp; |
112 | int freq; |
113 | int freq; |
113 | }videomode_t; |
114 | }videomode_t; |
114 | 115 | ||
115 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
116 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
116 | { |
117 | { |
117 | return *(const volatile uint8_t __force *) addr; |
118 | return *(const volatile uint8_t __force *) addr; |
118 | } |
119 | } |
119 | 120 | ||
120 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
121 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
121 | { |
122 | { |
122 | return *(const volatile uint16_t __force *) addr; |
123 | return *(const volatile uint16_t __force *) addr; |
123 | } |
124 | } |
124 | 125 | ||
125 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
126 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
126 | { |
127 | { |
127 | return *(const volatile uint32_t __force *) addr; |
128 | return *(const volatile uint32_t __force *) addr; |
128 | } |
129 | } |
129 | 130 | ||
130 | #define readb __raw_readb |
131 | #define readb __raw_readb |
131 | #define readw __raw_readw |
132 | #define readw __raw_readw |
132 | #define readl __raw_readl |
133 | #define readl __raw_readl |
133 | 134 | ||
134 | 135 | ||
135 | 136 | ||
136 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
137 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
137 | { |
138 | { |
138 | *(volatile uint8_t __force *) addr = b; |
139 | *(volatile uint8_t __force *) addr = b; |
139 | } |
140 | } |
140 | 141 | ||
141 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
142 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
142 | { |
143 | { |
143 | *(volatile uint16_t __force *) addr = b; |
144 | *(volatile uint16_t __force *) addr = b; |
144 | } |
145 | } |
145 | 146 | ||
146 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
147 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
147 | { |
148 | { |
148 | *(volatile uint32_t __force *) addr = b; |
149 | *(volatile uint32_t __force *) addr = b; |
149 | } |
150 | } |
150 | 151 | ||
151 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
152 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
152 | { |
153 | { |
153 | *(volatile __u64 *)addr = b; |
154 | *(volatile __u64 *)addr = b; |
154 | } |
155 | } |
155 | 156 | ||
156 | #define writeb __raw_writeb |
157 | #define writeb __raw_writeb |
157 | #define writew __raw_writew |
158 | #define writew __raw_writew |
158 | #define writel __raw_writel |
159 | #define writel __raw_writel |
159 | #define writeq __raw_writeq |
160 | #define writeq __raw_writeq |
160 | 161 | ||
161 | 162 | ||
162 | /* |
163 | /* |
163 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
164 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
164 | * symbol; |
165 | * symbol; |
165 | */ |
166 | */ |
166 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
167 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
167 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
168 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
168 | #define RADEON_IB_POOL_SIZE 16 |
169 | #define RADEON_IB_POOL_SIZE 16 |
169 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
170 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
170 | #define RADEONFB_CONN_LIMIT 4 |
171 | #define RADEONFB_CONN_LIMIT 4 |
171 | #define RADEON_BIOS_NUM_SCRATCH 8 |
172 | #define RADEON_BIOS_NUM_SCRATCH 8 |
172 | 173 | ||
173 | /* |
174 | /* |
174 | * Errata workarounds. |
175 | * Errata workarounds. |
175 | */ |
176 | */ |
176 | enum radeon_pll_errata { |
177 | enum radeon_pll_errata { |
177 | CHIP_ERRATA_R300_CG = 0x00000001, |
178 | CHIP_ERRATA_R300_CG = 0x00000001, |
178 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
179 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
179 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
180 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
180 | }; |
181 | }; |
181 | 182 | ||
182 | 183 | ||
183 | struct radeon_device; |
184 | struct radeon_device; |
184 | 185 | ||
185 | 186 | ||
186 | /* |
187 | /* |
187 | * BIOS. |
188 | * BIOS. |
188 | */ |
189 | */ |
189 | #define ATRM_BIOS_PAGE 4096 |
190 | #define ATRM_BIOS_PAGE 4096 |
190 | 191 | ||
191 | #if defined(CONFIG_VGA_SWITCHEROO) |
192 | #if defined(CONFIG_VGA_SWITCHEROO) |
192 | bool radeon_atrm_supported(struct pci_dev *pdev); |
193 | bool radeon_atrm_supported(struct pci_dev *pdev); |
193 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
194 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
194 | #else |
195 | #else |
195 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
196 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
196 | { |
197 | { |
197 | return false; |
198 | return false; |
198 | } |
199 | } |
199 | 200 | ||
200 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
201 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
201 | return -EINVAL; |
202 | return -EINVAL; |
202 | } |
203 | } |
203 | #endif |
204 | #endif |
204 | bool radeon_get_bios(struct radeon_device *rdev); |
205 | bool radeon_get_bios(struct radeon_device *rdev); |
205 | 206 | ||
206 | 207 | ||
207 | /* |
208 | /* |
208 | * Dummy page |
209 | * Dummy page |
209 | */ |
210 | */ |
210 | struct radeon_dummy_page { |
211 | struct radeon_dummy_page { |
211 | struct page *page; |
212 | struct page *page; |
212 | dma_addr_t addr; |
213 | dma_addr_t addr; |
213 | }; |
214 | }; |
214 | int radeon_dummy_page_init(struct radeon_device *rdev); |
215 | int radeon_dummy_page_init(struct radeon_device *rdev); |
215 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
216 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
216 | 217 | ||
217 | 218 | ||
218 | /* |
219 | /* |
219 | * Clocks |
220 | * Clocks |
220 | */ |
221 | */ |
221 | struct radeon_clock { |
222 | struct radeon_clock { |
222 | struct radeon_pll p1pll; |
223 | struct radeon_pll p1pll; |
223 | struct radeon_pll p2pll; |
224 | struct radeon_pll p2pll; |
224 | struct radeon_pll dcpll; |
225 | struct radeon_pll dcpll; |
225 | struct radeon_pll spll; |
226 | struct radeon_pll spll; |
226 | struct radeon_pll mpll; |
227 | struct radeon_pll mpll; |
227 | /* 10 Khz units */ |
228 | /* 10 Khz units */ |
228 | uint32_t default_mclk; |
229 | uint32_t default_mclk; |
229 | uint32_t default_sclk; |
230 | uint32_t default_sclk; |
230 | uint32_t default_dispclk; |
231 | uint32_t default_dispclk; |
231 | uint32_t dp_extclk; |
232 | uint32_t dp_extclk; |
232 | }; |
233 | }; |
233 | 234 | ||
234 | /* |
235 | /* |
235 | * Power management |
236 | * Power management |
236 | */ |
237 | */ |
237 | int radeon_pm_init(struct radeon_device *rdev); |
238 | int radeon_pm_init(struct radeon_device *rdev); |
238 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
239 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
239 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
240 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
240 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
241 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
241 | 242 | ||
242 | /* |
243 | /* |
243 | * Fences. |
244 | * Fences. |
244 | */ |
245 | */ |
245 | struct radeon_fence_driver { |
246 | struct radeon_fence_driver { |
246 | uint32_t scratch_reg; |
247 | uint32_t scratch_reg; |
247 | atomic_t seq; |
248 | atomic_t seq; |
248 | uint32_t last_seq; |
249 | uint32_t last_seq; |
249 | unsigned long count_timeout; |
250 | unsigned long count_timeout; |
250 | // wait_queue_head_t queue; |
251 | // wait_queue_head_t queue; |
251 | rwlock_t lock; |
252 | rwlock_t lock; |
252 | struct list_head created; |
253 | struct list_head created; |
253 | struct list_head emited; |
254 | struct list_head emited; |
254 | struct list_head signaled; |
255 | struct list_head signaled; |
255 | bool initialized; |
256 | bool initialized; |
256 | }; |
257 | }; |
257 | 258 | ||
258 | struct radeon_fence { |
259 | struct radeon_fence { |
259 | struct radeon_device *rdev; |
260 | struct radeon_device *rdev; |
260 | struct kref kref; |
261 | struct kref kref; |
261 | struct list_head list; |
262 | struct list_head list; |
262 | /* protected by radeon_fence.lock */ |
263 | /* protected by radeon_fence.lock */ |
263 | uint32_t seq; |
264 | uint32_t seq; |
264 | unsigned long timeout; |
265 | unsigned long timeout; |
265 | bool emited; |
266 | bool emited; |
266 | bool signaled; |
267 | bool signaled; |
267 | }; |
268 | }; |
268 | 269 | ||
269 | int radeon_fence_driver_init(struct radeon_device *rdev); |
270 | int radeon_fence_driver_init(struct radeon_device *rdev); |
270 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
271 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
271 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
272 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
272 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
273 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
273 | void radeon_fence_process(struct radeon_device *rdev); |
274 | void radeon_fence_process(struct radeon_device *rdev); |
274 | bool radeon_fence_signaled(struct radeon_fence *fence); |
275 | bool radeon_fence_signaled(struct radeon_fence *fence); |
275 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
276 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
276 | int radeon_fence_wait_next(struct radeon_device *rdev); |
277 | int radeon_fence_wait_next(struct radeon_device *rdev); |
277 | int radeon_fence_wait_last(struct radeon_device *rdev); |
278 | int radeon_fence_wait_last(struct radeon_device *rdev); |
278 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
279 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
279 | void radeon_fence_unref(struct radeon_fence **fence); |
280 | void radeon_fence_unref(struct radeon_fence **fence); |
280 | 281 | ||
281 | /* |
282 | /* |
282 | * Tiling registers |
283 | * Tiling registers |
283 | */ |
284 | */ |
284 | struct radeon_surface_reg { |
285 | struct radeon_surface_reg { |
285 | struct radeon_bo *bo; |
286 | struct radeon_bo *bo; |
286 | }; |
287 | }; |
287 | 288 | ||
288 | #define RADEON_GEM_MAX_SURFACES 8 |
289 | #define RADEON_GEM_MAX_SURFACES 8 |
289 | 290 | ||
290 | /* |
291 | /* |
291 | * TTM. |
292 | * TTM. |
292 | */ |
293 | */ |
293 | struct radeon_mman { |
294 | struct radeon_mman { |
294 | struct ttm_bo_global_ref bo_global_ref; |
295 | struct ttm_bo_global_ref bo_global_ref; |
295 | struct ttm_global_reference mem_global_ref; |
296 | struct ttm_global_reference mem_global_ref; |
296 | struct ttm_bo_device bdev; |
297 | struct ttm_bo_device bdev; |
297 | bool mem_global_referenced; |
298 | bool mem_global_referenced; |
298 | bool initialized; |
299 | bool initialized; |
299 | }; |
300 | }; |
300 | 301 | ||
301 | struct radeon_bo { |
302 | struct radeon_bo { |
302 | /* Protected by gem.mutex */ |
303 | /* Protected by gem.mutex */ |
303 | struct list_head list; |
304 | struct list_head list; |
304 | /* Protected by tbo.reserved */ |
305 | /* Protected by tbo.reserved */ |
305 | u32 placements[3]; |
306 | u32 placements[3]; |
306 | struct ttm_placement placement; |
307 | struct ttm_placement placement; |
307 | struct ttm_buffer_object tbo; |
308 | struct ttm_buffer_object tbo; |
308 | struct ttm_bo_kmap_obj kmap; |
309 | struct ttm_bo_kmap_obj kmap; |
309 | unsigned pin_count; |
310 | unsigned pin_count; |
310 | void *kptr; |
311 | void *kptr; |
311 | u32 cpu_addr; |
312 | u32 cpu_addr; |
312 | u32 tiling_flags; |
313 | u32 tiling_flags; |
313 | u32 pitch; |
314 | u32 pitch; |
314 | int surface_reg; |
315 | int surface_reg; |
315 | /* Constant after initialization */ |
316 | /* Constant after initialization */ |
316 | struct radeon_device *rdev; |
317 | struct radeon_device *rdev; |
317 | struct drm_gem_object *gobj; |
318 | struct drm_gem_object *gobj; |
318 | u32 domain; |
319 | u32 domain; |
319 | }; |
320 | }; |
320 | 321 | ||
321 | struct radeon_bo_list { |
322 | struct radeon_bo_list { |
322 | struct list_head list; |
323 | struct list_head list; |
323 | struct radeon_bo *bo; |
324 | struct radeon_bo *bo; |
324 | uint64_t gpu_offset; |
325 | uint64_t gpu_offset; |
325 | unsigned rdomain; |
326 | unsigned rdomain; |
326 | unsigned wdomain; |
327 | unsigned wdomain; |
327 | u32 tiling_flags; |
328 | u32 tiling_flags; |
328 | }; |
329 | }; |
329 | 330 | ||
330 | /* |
331 | /* |
331 | * GEM objects. |
332 | * GEM objects. |
332 | */ |
333 | */ |
333 | struct radeon_gem { |
334 | struct radeon_gem { |
- | 335 | struct mutex mutex; |
|
334 | struct list_head objects; |
336 | struct list_head objects; |
335 | }; |
337 | }; |
336 | 338 | ||
337 | int radeon_gem_init(struct radeon_device *rdev); |
339 | int radeon_gem_init(struct radeon_device *rdev); |
338 | void radeon_gem_fini(struct radeon_device *rdev); |
340 | void radeon_gem_fini(struct radeon_device *rdev); |
339 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
341 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
340 | int alignment, int initial_domain, |
342 | int alignment, int initial_domain, |
341 | bool discardable, bool kernel, |
343 | bool discardable, bool kernel, |
342 | struct drm_gem_object **obj); |
344 | struct drm_gem_object **obj); |
343 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
345 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
344 | uint64_t *gpu_addr); |
346 | uint64_t *gpu_addr); |
345 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
347 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
346 | 348 | ||
347 | 349 | ||
348 | /* |
350 | /* |
349 | * GART structures, functions & helpers |
351 | * GART structures, functions & helpers |
350 | */ |
352 | */ |
351 | struct radeon_mc; |
353 | struct radeon_mc; |
352 | 354 | ||
353 | struct radeon_gart_table_ram { |
355 | struct radeon_gart_table_ram { |
354 | volatile uint32_t *ptr; |
356 | volatile uint32_t *ptr; |
355 | }; |
357 | }; |
356 | 358 | ||
357 | struct radeon_gart_table_vram { |
359 | struct radeon_gart_table_vram { |
358 | struct radeon_bo *robj; |
360 | struct radeon_bo *robj; |
359 | volatile uint32_t *ptr; |
361 | volatile uint32_t *ptr; |
360 | }; |
362 | }; |
361 | 363 | ||
362 | union radeon_gart_table { |
364 | union radeon_gart_table { |
363 | struct radeon_gart_table_ram ram; |
365 | struct radeon_gart_table_ram ram; |
364 | struct radeon_gart_table_vram vram; |
366 | struct radeon_gart_table_vram vram; |
365 | }; |
367 | }; |
366 | 368 | ||
367 | #define RADEON_GPU_PAGE_SIZE 4096 |
369 | #define RADEON_GPU_PAGE_SIZE 4096 |
368 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
370 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
369 | 371 | ||
370 | struct radeon_gart { |
372 | struct radeon_gart { |
371 | dma_addr_t table_addr; |
373 | dma_addr_t table_addr; |
372 | unsigned num_gpu_pages; |
374 | unsigned num_gpu_pages; |
373 | unsigned num_cpu_pages; |
375 | unsigned num_cpu_pages; |
374 | unsigned table_size; |
376 | unsigned table_size; |
375 | union radeon_gart_table table; |
377 | union radeon_gart_table table; |
376 | struct page **pages; |
378 | struct page **pages; |
377 | dma_addr_t *pages_addr; |
379 | dma_addr_t *pages_addr; |
378 | bool ready; |
380 | bool ready; |
379 | }; |
381 | }; |
380 | 382 | ||
381 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
383 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
382 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
384 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
383 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
385 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
384 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
386 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
385 | int radeon_gart_init(struct radeon_device *rdev); |
387 | int radeon_gart_init(struct radeon_device *rdev); |
386 | void radeon_gart_fini(struct radeon_device *rdev); |
388 | void radeon_gart_fini(struct radeon_device *rdev); |
387 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
389 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
388 | int pages); |
390 | int pages); |
389 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
391 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
390 | int pages, u32_t *pagelist); |
392 | int pages, u32_t *pagelist); |
391 | 393 | ||
392 | 394 | ||
393 | /* |
395 | /* |
394 | * GPU MC structures, functions & helpers |
396 | * GPU MC structures, functions & helpers |
395 | */ |
397 | */ |
396 | struct radeon_mc { |
398 | struct radeon_mc { |
397 | resource_size_t aper_size; |
399 | resource_size_t aper_size; |
398 | resource_size_t aper_base; |
400 | resource_size_t aper_base; |
399 | resource_size_t agp_base; |
401 | resource_size_t agp_base; |
400 | /* for some chips with <= 32MB we need to lie |
402 | /* for some chips with <= 32MB we need to lie |
401 | * about vram size near mc fb location */ |
403 | * about vram size near mc fb location */ |
402 | u64 mc_vram_size; |
404 | u64 mc_vram_size; |
403 | u64 visible_vram_size; |
405 | u64 visible_vram_size; |
404 | u64 gtt_size; |
406 | u64 gtt_size; |
405 | u64 gtt_start; |
407 | u64 gtt_start; |
406 | u64 gtt_end; |
408 | u64 gtt_end; |
407 | u64 vram_start; |
409 | u64 vram_start; |
408 | u64 vram_end; |
410 | u64 vram_end; |
409 | unsigned vram_width; |
411 | unsigned vram_width; |
410 | u64 real_vram_size; |
412 | u64 real_vram_size; |
411 | int vram_mtrr; |
413 | int vram_mtrr; |
412 | bool vram_is_ddr; |
414 | bool vram_is_ddr; |
413 | bool igp_sideport_enabled; |
415 | bool igp_sideport_enabled; |
414 | }; |
416 | }; |
415 | 417 | ||
416 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
418 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
417 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
419 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
418 | 420 | ||
419 | /* |
421 | /* |
420 | * GPU scratch registers structures, functions & helpers |
422 | * GPU scratch registers structures, functions & helpers |
421 | */ |
423 | */ |
422 | struct radeon_scratch { |
424 | struct radeon_scratch { |
423 | unsigned num_reg; |
425 | unsigned num_reg; |
424 | bool free[32]; |
426 | bool free[32]; |
425 | uint32_t reg[32]; |
427 | uint32_t reg[32]; |
426 | }; |
428 | }; |
427 | 429 | ||
428 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
430 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
429 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
431 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
430 | 432 | ||
431 | 433 | ||
432 | /* |
434 | /* |
433 | * IRQS. |
435 | * IRQS. |
434 | */ |
436 | */ |
435 | struct radeon_irq { |
437 | struct radeon_irq { |
436 | bool installed; |
438 | bool installed; |
437 | bool sw_int; |
439 | bool sw_int; |
438 | /* FIXME: use a define max crtc rather than hardcode it */ |
440 | /* FIXME: use a define max crtc rather than hardcode it */ |
439 | bool crtc_vblank_int[2]; |
441 | bool crtc_vblank_int[2]; |
440 | /* FIXME: use defines for max hpd/dacs */ |
442 | /* FIXME: use defines for max hpd/dacs */ |
441 | bool hpd[6]; |
443 | bool hpd[6]; |
442 | spinlock_t sw_lock; |
444 | spinlock_t sw_lock; |
443 | int sw_refcount; |
445 | int sw_refcount; |
444 | }; |
446 | }; |
445 | 447 | ||
446 | int radeon_irq_kms_init(struct radeon_device *rdev); |
448 | int radeon_irq_kms_init(struct radeon_device *rdev); |
447 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
449 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
448 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
450 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
449 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
451 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
450 | 452 | ||
451 | /* |
453 | /* |
452 | * CP & ring. |
454 | * CP & ring. |
453 | */ |
455 | */ |
454 | struct radeon_ib { |
456 | struct radeon_ib { |
455 | struct list_head list; |
457 | struct list_head list; |
456 | unsigned idx; |
458 | unsigned idx; |
457 | uint64_t gpu_addr; |
459 | uint64_t gpu_addr; |
458 | struct radeon_fence *fence; |
460 | struct radeon_fence *fence; |
459 | uint32_t *ptr; |
461 | uint32_t *ptr; |
460 | uint32_t length_dw; |
462 | uint32_t length_dw; |
461 | bool free; |
463 | bool free; |
462 | }; |
464 | }; |
463 | 465 | ||
464 | /* |
466 | /* |
465 | * locking - |
467 | * locking - |
466 | * mutex protects scheduled_ibs, ready, alloc_bm |
468 | * mutex protects scheduled_ibs, ready, alloc_bm |
467 | */ |
469 | */ |
468 | struct radeon_ib_pool { |
470 | struct radeon_ib_pool { |
469 | // struct mutex mutex; |
471 | struct mutex mutex; |
470 | struct radeon_bo *robj; |
472 | struct radeon_bo *robj; |
471 | struct list_head bogus_ib; |
473 | struct list_head bogus_ib; |
472 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
474 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
473 | bool ready; |
475 | bool ready; |
474 | unsigned head_id; |
476 | unsigned head_id; |
475 | }; |
477 | }; |
476 | 478 | ||
477 | struct radeon_cp { |
479 | struct radeon_cp { |
478 | struct radeon_bo *ring_obj; |
480 | struct radeon_bo *ring_obj; |
479 | volatile uint32_t *ring; |
481 | volatile uint32_t *ring; |
480 | unsigned rptr; |
482 | unsigned rptr; |
481 | unsigned wptr; |
483 | unsigned wptr; |
482 | unsigned wptr_old; |
484 | unsigned wptr_old; |
483 | unsigned ring_size; |
485 | unsigned ring_size; |
484 | unsigned ring_free_dw; |
486 | unsigned ring_free_dw; |
485 | int count_dw; |
487 | int count_dw; |
486 | uint64_t gpu_addr; |
488 | uint64_t gpu_addr; |
487 | uint32_t align_mask; |
489 | uint32_t align_mask; |
488 | uint32_t ptr_mask; |
490 | uint32_t ptr_mask; |
489 | // struct mutex mutex; |
491 | struct mutex mutex; |
490 | bool ready; |
492 | bool ready; |
491 | }; |
493 | }; |
492 | 494 | ||
493 | /* |
495 | /* |
494 | * R6xx+ IH ring |
496 | * R6xx+ IH ring |
495 | */ |
497 | */ |
496 | struct r600_ih { |
498 | struct r600_ih { |
497 | struct radeon_bo *ring_obj; |
499 | struct radeon_bo *ring_obj; |
498 | volatile uint32_t *ring; |
500 | volatile uint32_t *ring; |
499 | unsigned rptr; |
501 | unsigned rptr; |
500 | unsigned wptr; |
502 | unsigned wptr; |
501 | unsigned wptr_old; |
503 | unsigned wptr_old; |
502 | unsigned ring_size; |
504 | unsigned ring_size; |
503 | uint64_t gpu_addr; |
505 | uint64_t gpu_addr; |
504 | uint32_t ptr_mask; |
506 | uint32_t ptr_mask; |
505 | spinlock_t lock; |
507 | spinlock_t lock; |
506 | bool enabled; |
508 | bool enabled; |
507 | }; |
509 | }; |
508 | 510 | ||
509 | struct r600_blit { |
511 | struct r600_blit { |
- | 512 | struct mutex mutex; |
|
510 | struct radeon_bo *shader_obj; |
513 | struct radeon_bo *shader_obj; |
511 | u64 shader_gpu_addr; |
514 | u64 shader_gpu_addr; |
512 | u32 vs_offset, ps_offset; |
515 | u32 vs_offset, ps_offset; |
513 | u32 state_offset; |
516 | u32 state_offset; |
514 | u32 state_len; |
517 | u32 state_len; |
515 | u32 vb_used, vb_total; |
518 | u32 vb_used, vb_total; |
516 | struct radeon_ib *vb_ib; |
519 | struct radeon_ib *vb_ib; |
517 | }; |
520 | }; |
518 | 521 | ||
519 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
522 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
520 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
523 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
521 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
524 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
522 | int radeon_ib_pool_init(struct radeon_device *rdev); |
525 | int radeon_ib_pool_init(struct radeon_device *rdev); |
523 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
526 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
524 | int radeon_ib_test(struct radeon_device *rdev); |
527 | int radeon_ib_test(struct radeon_device *rdev); |
525 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
528 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
526 | /* Ring access between begin & end cannot sleep */ |
529 | /* Ring access between begin & end cannot sleep */ |
527 | void radeon_ring_free_size(struct radeon_device *rdev); |
530 | void radeon_ring_free_size(struct radeon_device *rdev); |
528 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
531 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
529 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
532 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
530 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
533 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
531 | int radeon_ring_test(struct radeon_device *rdev); |
534 | int radeon_ring_test(struct radeon_device *rdev); |
532 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
535 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
533 | void radeon_ring_fini(struct radeon_device *rdev); |
536 | void radeon_ring_fini(struct radeon_device *rdev); |
534 | 537 | ||
535 | 538 | ||
536 | /* |
539 | /* |
537 | * CS. |
540 | * CS. |
538 | */ |
541 | */ |
539 | struct radeon_cs_reloc { |
542 | struct radeon_cs_reloc { |
540 | // struct drm_gem_object *gobj; |
543 | // struct drm_gem_object *gobj; |
541 | struct radeon_bo *robj; |
544 | struct radeon_bo *robj; |
542 | // struct radeon_bo_list lobj; |
545 | struct radeon_bo_list lobj; |
543 | uint32_t handle; |
546 | uint32_t handle; |
544 | uint32_t flags; |
547 | uint32_t flags; |
545 | }; |
548 | }; |
546 | 549 | ||
547 | struct radeon_cs_chunk { |
550 | struct radeon_cs_chunk { |
548 | uint32_t chunk_id; |
551 | uint32_t chunk_id; |
549 | uint32_t length_dw; |
552 | uint32_t length_dw; |
550 | int kpage_idx[2]; |
553 | int kpage_idx[2]; |
551 | uint32_t *kpage[2]; |
554 | uint32_t *kpage[2]; |
552 | uint32_t *kdata; |
555 | uint32_t *kdata; |
553 | void __user *user_ptr; |
556 | void __user *user_ptr; |
554 | int last_copied_page; |
557 | int last_copied_page; |
555 | int last_page_index; |
558 | int last_page_index; |
556 | }; |
559 | }; |
557 | 560 | ||
558 | struct radeon_cs_parser { |
561 | struct radeon_cs_parser { |
559 | struct device *dev; |
562 | struct device *dev; |
560 | struct radeon_device *rdev; |
563 | struct radeon_device *rdev; |
561 | // struct drm_file *filp; |
564 | // struct drm_file *filp; |
562 | /* chunks */ |
565 | /* chunks */ |
563 | unsigned nchunks; |
566 | unsigned nchunks; |
564 | struct radeon_cs_chunk *chunks; |
567 | struct radeon_cs_chunk *chunks; |
565 | uint64_t *chunks_array; |
568 | uint64_t *chunks_array; |
566 | /* IB */ |
569 | /* IB */ |
567 | unsigned idx; |
570 | unsigned idx; |
568 | /* relocations */ |
571 | /* relocations */ |
569 | unsigned nrelocs; |
572 | unsigned nrelocs; |
570 | struct radeon_cs_reloc *relocs; |
573 | struct radeon_cs_reloc *relocs; |
571 | struct radeon_cs_reloc **relocs_ptr; |
574 | struct radeon_cs_reloc **relocs_ptr; |
572 | struct list_head validated; |
575 | struct list_head validated; |
573 | /* indices of various chunks */ |
576 | /* indices of various chunks */ |
574 | int chunk_ib_idx; |
577 | int chunk_ib_idx; |
575 | int chunk_relocs_idx; |
578 | int chunk_relocs_idx; |
576 | struct radeon_ib *ib; |
579 | struct radeon_ib *ib; |
577 | void *track; |
580 | void *track; |
578 | unsigned family; |
581 | unsigned family; |
579 | int parser_error; |
582 | int parser_error; |
580 | }; |
583 | }; |
581 | 584 | ||
582 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
585 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
583 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
586 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
584 | 587 | ||
585 | 588 | ||
586 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
589 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
587 | { |
590 | { |
588 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
591 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
589 | u32 pg_idx, pg_offset; |
592 | u32 pg_idx, pg_offset; |
590 | u32 idx_value = 0; |
593 | u32 idx_value = 0; |
591 | int new_page; |
594 | int new_page; |
592 | 595 | ||
593 | pg_idx = (idx * 4) / PAGE_SIZE; |
596 | pg_idx = (idx * 4) / PAGE_SIZE; |
594 | pg_offset = (idx * 4) % PAGE_SIZE; |
597 | pg_offset = (idx * 4) % PAGE_SIZE; |
595 | 598 | ||
596 | if (ibc->kpage_idx[0] == pg_idx) |
599 | if (ibc->kpage_idx[0] == pg_idx) |
597 | return ibc->kpage[0][pg_offset/4]; |
600 | return ibc->kpage[0][pg_offset/4]; |
598 | if (ibc->kpage_idx[1] == pg_idx) |
601 | if (ibc->kpage_idx[1] == pg_idx) |
599 | return ibc->kpage[1][pg_offset/4]; |
602 | return ibc->kpage[1][pg_offset/4]; |
600 | 603 | ||
601 | new_page = radeon_cs_update_pages(p, pg_idx); |
604 | new_page = radeon_cs_update_pages(p, pg_idx); |
602 | if (new_page < 0) { |
605 | if (new_page < 0) { |
603 | p->parser_error = new_page; |
606 | p->parser_error = new_page; |
604 | return 0; |
607 | return 0; |
605 | } |
608 | } |
606 | 609 | ||
607 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
610 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
608 | return idx_value; |
611 | return idx_value; |
609 | } |
612 | } |
610 | 613 | ||
611 | struct radeon_cs_packet { |
614 | struct radeon_cs_packet { |
612 | unsigned idx; |
615 | unsigned idx; |
613 | unsigned type; |
616 | unsigned type; |
614 | unsigned reg; |
617 | unsigned reg; |
615 | unsigned opcode; |
618 | unsigned opcode; |
616 | int count; |
619 | int count; |
617 | unsigned one_reg_wr; |
620 | unsigned one_reg_wr; |
618 | }; |
621 | }; |
619 | 622 | ||
620 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
623 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
621 | struct radeon_cs_packet *pkt, |
624 | struct radeon_cs_packet *pkt, |
622 | unsigned idx, unsigned reg); |
625 | unsigned idx, unsigned reg); |
623 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
626 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
624 | struct radeon_cs_packet *pkt); |
627 | struct radeon_cs_packet *pkt); |
625 | 628 | ||
626 | 629 | ||
627 | /* |
630 | /* |
628 | * AGP |
631 | * AGP |
629 | */ |
632 | */ |
630 | int radeon_agp_init(struct radeon_device *rdev); |
633 | int radeon_agp_init(struct radeon_device *rdev); |
631 | void radeon_agp_resume(struct radeon_device *rdev); |
634 | void radeon_agp_resume(struct radeon_device *rdev); |
632 | void radeon_agp_fini(struct radeon_device *rdev); |
635 | void radeon_agp_fini(struct radeon_device *rdev); |
633 | 636 | ||
634 | 637 | ||
635 | /* |
638 | /* |
636 | * Writeback |
639 | * Writeback |
637 | */ |
640 | */ |
638 | struct radeon_wb { |
641 | struct radeon_wb { |
639 | struct radeon_bo *wb_obj; |
642 | struct radeon_bo *wb_obj; |
640 | volatile uint32_t *wb; |
643 | volatile uint32_t *wb; |
641 | uint64_t gpu_addr; |
644 | uint64_t gpu_addr; |
642 | }; |
645 | }; |
643 | 646 | ||
644 | /** |
647 | /** |
645 | * struct radeon_pm - power management datas |
648 | * struct radeon_pm - power management datas |
646 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
649 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
647 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
650 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
648 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
651 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
649 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
652 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
650 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
653 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
651 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
654 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
652 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
655 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
653 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
656 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
654 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
657 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
655 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
658 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
656 | * @needed_bandwidth: current bandwidth needs |
659 | * @needed_bandwidth: current bandwidth needs |
657 | * |
660 | * |
658 | * It keeps track of various data needed to take powermanagement decision. |
661 | * It keeps track of various data needed to take powermanagement decision. |
659 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
662 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
660 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
663 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
661 | * (type of memory, bus size, efficiency, ...) |
664 | * (type of memory, bus size, efficiency, ...) |
662 | */ |
665 | */ |
663 | enum radeon_pm_state { |
666 | enum radeon_pm_state { |
664 | PM_STATE_DISABLED, |
667 | PM_STATE_DISABLED, |
665 | PM_STATE_MINIMUM, |
668 | PM_STATE_MINIMUM, |
666 | PM_STATE_PAUSED, |
669 | PM_STATE_PAUSED, |
667 | PM_STATE_ACTIVE |
670 | PM_STATE_ACTIVE |
668 | }; |
671 | }; |
669 | enum radeon_pm_action { |
672 | enum radeon_pm_action { |
670 | PM_ACTION_NONE, |
673 | PM_ACTION_NONE, |
671 | PM_ACTION_MINIMUM, |
674 | PM_ACTION_MINIMUM, |
672 | PM_ACTION_DOWNCLOCK, |
675 | PM_ACTION_DOWNCLOCK, |
673 | PM_ACTION_UPCLOCK |
676 | PM_ACTION_UPCLOCK |
674 | }; |
677 | }; |
675 | 678 | ||
676 | enum radeon_voltage_type { |
679 | enum radeon_voltage_type { |
677 | VOLTAGE_NONE = 0, |
680 | VOLTAGE_NONE = 0, |
678 | VOLTAGE_GPIO, |
681 | VOLTAGE_GPIO, |
679 | VOLTAGE_VDDC, |
682 | VOLTAGE_VDDC, |
680 | VOLTAGE_SW |
683 | VOLTAGE_SW |
681 | }; |
684 | }; |
682 | 685 | ||
683 | enum radeon_pm_state_type { |
686 | enum radeon_pm_state_type { |
684 | POWER_STATE_TYPE_DEFAULT, |
687 | POWER_STATE_TYPE_DEFAULT, |
685 | POWER_STATE_TYPE_POWERSAVE, |
688 | POWER_STATE_TYPE_POWERSAVE, |
686 | POWER_STATE_TYPE_BATTERY, |
689 | POWER_STATE_TYPE_BATTERY, |
687 | POWER_STATE_TYPE_BALANCED, |
690 | POWER_STATE_TYPE_BALANCED, |
688 | POWER_STATE_TYPE_PERFORMANCE, |
691 | POWER_STATE_TYPE_PERFORMANCE, |
689 | }; |
692 | }; |
690 | 693 | ||
691 | enum radeon_pm_clock_mode_type { |
694 | enum radeon_pm_clock_mode_type { |
692 | POWER_MODE_TYPE_DEFAULT, |
695 | POWER_MODE_TYPE_DEFAULT, |
693 | POWER_MODE_TYPE_LOW, |
696 | POWER_MODE_TYPE_LOW, |
694 | POWER_MODE_TYPE_MID, |
697 | POWER_MODE_TYPE_MID, |
695 | POWER_MODE_TYPE_HIGH, |
698 | POWER_MODE_TYPE_HIGH, |
696 | }; |
699 | }; |
697 | 700 | ||
698 | struct radeon_voltage { |
701 | struct radeon_voltage { |
699 | enum radeon_voltage_type type; |
702 | enum radeon_voltage_type type; |
700 | /* gpio voltage */ |
703 | /* gpio voltage */ |
701 | struct radeon_gpio_rec gpio; |
704 | struct radeon_gpio_rec gpio; |
702 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
705 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
703 | bool active_high; /* voltage drop is active when bit is high */ |
706 | bool active_high; /* voltage drop is active when bit is high */ |
704 | /* VDDC voltage */ |
707 | /* VDDC voltage */ |
705 | u8 vddc_id; /* index into vddc voltage table */ |
708 | u8 vddc_id; /* index into vddc voltage table */ |
706 | u8 vddci_id; /* index into vddci voltage table */ |
709 | u8 vddci_id; /* index into vddci voltage table */ |
707 | bool vddci_enabled; |
710 | bool vddci_enabled; |
708 | /* r6xx+ sw */ |
711 | /* r6xx+ sw */ |
709 | u32 voltage; |
712 | u32 voltage; |
710 | }; |
713 | }; |
711 | 714 | ||
712 | struct radeon_pm_non_clock_info { |
715 | struct radeon_pm_non_clock_info { |
713 | /* pcie lanes */ |
716 | /* pcie lanes */ |
714 | int pcie_lanes; |
717 | int pcie_lanes; |
715 | /* standardized non-clock flags */ |
718 | /* standardized non-clock flags */ |
716 | u32 flags; |
719 | u32 flags; |
717 | }; |
720 | }; |
718 | 721 | ||
719 | struct radeon_pm_clock_info { |
722 | struct radeon_pm_clock_info { |
720 | /* memory clock */ |
723 | /* memory clock */ |
721 | u32 mclk; |
724 | u32 mclk; |
722 | /* engine clock */ |
725 | /* engine clock */ |
723 | u32 sclk; |
726 | u32 sclk; |
724 | /* voltage info */ |
727 | /* voltage info */ |
725 | struct radeon_voltage voltage; |
728 | struct radeon_voltage voltage; |
726 | /* standardized clock flags - not sure we'll need these */ |
729 | /* standardized clock flags - not sure we'll need these */ |
727 | u32 flags; |
730 | u32 flags; |
728 | }; |
731 | }; |
729 | 732 | ||
730 | struct radeon_power_state { |
733 | struct radeon_power_state { |
731 | enum radeon_pm_state_type type; |
734 | enum radeon_pm_state_type type; |
732 | /* XXX: use a define for num clock modes */ |
735 | /* XXX: use a define for num clock modes */ |
733 | struct radeon_pm_clock_info clock_info[8]; |
736 | struct radeon_pm_clock_info clock_info[8]; |
734 | /* number of valid clock modes in this power state */ |
737 | /* number of valid clock modes in this power state */ |
735 | int num_clock_modes; |
738 | int num_clock_modes; |
736 | struct radeon_pm_clock_info *default_clock_mode; |
739 | struct radeon_pm_clock_info *default_clock_mode; |
737 | /* non clock info about this state */ |
740 | /* non clock info about this state */ |
738 | struct radeon_pm_non_clock_info non_clock_info; |
741 | struct radeon_pm_non_clock_info non_clock_info; |
739 | bool voltage_drop_active; |
742 | bool voltage_drop_active; |
740 | }; |
743 | }; |
741 | 744 | ||
742 | /* |
745 | /* |
743 | * Some modes are overclocked by very low value, accept them |
746 | * Some modes are overclocked by very low value, accept them |
744 | */ |
747 | */ |
745 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
748 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
746 | 749 | ||
747 | struct radeon_pm { |
750 | struct radeon_pm { |
748 | // struct mutex mutex; |
751 | struct mutex mutex; |
749 | // struct delayed_work idle_work; |
752 | // struct delayed_work idle_work; |
750 | enum radeon_pm_state state; |
753 | enum radeon_pm_state state; |
751 | enum radeon_pm_action planned_action; |
754 | enum radeon_pm_action planned_action; |
752 | unsigned long action_timeout; |
755 | unsigned long action_timeout; |
753 | bool downclocked; |
756 | bool downclocked; |
754 | int active_crtcs; |
757 | int active_crtcs; |
755 | int req_vblank; |
758 | int req_vblank; |
756 | fixed20_12 max_bandwidth; |
759 | fixed20_12 max_bandwidth; |
757 | fixed20_12 igp_sideport_mclk; |
760 | fixed20_12 igp_sideport_mclk; |
758 | fixed20_12 igp_system_mclk; |
761 | fixed20_12 igp_system_mclk; |
759 | fixed20_12 igp_ht_link_clk; |
762 | fixed20_12 igp_ht_link_clk; |
760 | fixed20_12 igp_ht_link_width; |
763 | fixed20_12 igp_ht_link_width; |
761 | fixed20_12 k8_bandwidth; |
764 | fixed20_12 k8_bandwidth; |
762 | fixed20_12 sideport_bandwidth; |
765 | fixed20_12 sideport_bandwidth; |
763 | fixed20_12 ht_bandwidth; |
766 | fixed20_12 ht_bandwidth; |
764 | fixed20_12 core_bandwidth; |
767 | fixed20_12 core_bandwidth; |
765 | fixed20_12 sclk; |
768 | fixed20_12 sclk; |
766 | fixed20_12 needed_bandwidth; |
769 | fixed20_12 needed_bandwidth; |
767 | /* XXX: use a define for num power modes */ |
770 | /* XXX: use a define for num power modes */ |
768 | struct radeon_power_state power_state[8]; |
771 | struct radeon_power_state power_state[8]; |
769 | /* number of valid power states */ |
772 | /* number of valid power states */ |
770 | int num_power_states; |
773 | int num_power_states; |
771 | struct radeon_power_state *current_power_state; |
774 | struct radeon_power_state *current_power_state; |
772 | struct radeon_pm_clock_info *current_clock_mode; |
775 | struct radeon_pm_clock_info *current_clock_mode; |
773 | struct radeon_power_state *requested_power_state; |
776 | struct radeon_power_state *requested_power_state; |
774 | struct radeon_pm_clock_info *requested_clock_mode; |
777 | struct radeon_pm_clock_info *requested_clock_mode; |
775 | struct radeon_power_state *default_power_state; |
778 | struct radeon_power_state *default_power_state; |
776 | }; |
779 | }; |
777 | 780 | ||
778 | /* |
781 | /* |
779 | * ASIC specific functions. |
782 | * ASIC specific functions. |
780 | */ |
783 | */ |
781 | struct radeon_asic { |
784 | struct radeon_asic { |
782 | int (*init)(struct radeon_device *rdev); |
785 | int (*init)(struct radeon_device *rdev); |
783 | void (*fini)(struct radeon_device *rdev); |
786 | void (*fini)(struct radeon_device *rdev); |
784 | int (*resume)(struct radeon_device *rdev); |
787 | int (*resume)(struct radeon_device *rdev); |
785 | int (*suspend)(struct radeon_device *rdev); |
788 | int (*suspend)(struct radeon_device *rdev); |
786 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
789 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
787 | int (*gpu_reset)(struct radeon_device *rdev); |
790 | int (*gpu_reset)(struct radeon_device *rdev); |
788 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
791 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
789 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
792 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
790 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
793 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
791 | void (*cp_fini)(struct radeon_device *rdev); |
794 | void (*cp_fini)(struct radeon_device *rdev); |
792 | void (*cp_disable)(struct radeon_device *rdev); |
795 | void (*cp_disable)(struct radeon_device *rdev); |
793 | void (*cp_commit)(struct radeon_device *rdev); |
796 | void (*cp_commit)(struct radeon_device *rdev); |
794 | void (*ring_start)(struct radeon_device *rdev); |
797 | void (*ring_start)(struct radeon_device *rdev); |
795 | int (*ring_test)(struct radeon_device *rdev); |
798 | int (*ring_test)(struct radeon_device *rdev); |
796 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
799 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
797 | int (*irq_set)(struct radeon_device *rdev); |
800 | int (*irq_set)(struct radeon_device *rdev); |
798 | int (*irq_process)(struct radeon_device *rdev); |
801 | int (*irq_process)(struct radeon_device *rdev); |
799 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
802 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
800 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
803 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
801 | int (*cs_parse)(struct radeon_cs_parser *p); |
804 | int (*cs_parse)(struct radeon_cs_parser *p); |
802 | int (*copy_blit)(struct radeon_device *rdev, |
805 | int (*copy_blit)(struct radeon_device *rdev, |
803 | uint64_t src_offset, |
806 | uint64_t src_offset, |
804 | uint64_t dst_offset, |
807 | uint64_t dst_offset, |
805 | unsigned num_pages, |
808 | unsigned num_pages, |
806 | struct radeon_fence *fence); |
809 | struct radeon_fence *fence); |
807 | int (*copy_dma)(struct radeon_device *rdev, |
810 | int (*copy_dma)(struct radeon_device *rdev, |
808 | uint64_t src_offset, |
811 | uint64_t src_offset, |
809 | uint64_t dst_offset, |
812 | uint64_t dst_offset, |
810 | unsigned num_pages, |
813 | unsigned num_pages, |
811 | struct radeon_fence *fence); |
814 | struct radeon_fence *fence); |
812 | int (*copy)(struct radeon_device *rdev, |
815 | int (*copy)(struct radeon_device *rdev, |
813 | uint64_t src_offset, |
816 | uint64_t src_offset, |
814 | uint64_t dst_offset, |
817 | uint64_t dst_offset, |
815 | unsigned num_pages, |
818 | unsigned num_pages, |
816 | struct radeon_fence *fence); |
819 | struct radeon_fence *fence); |
817 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
820 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
818 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
821 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
819 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
822 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
820 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
823 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
821 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
824 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
822 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
825 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
823 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
826 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
824 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
827 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
825 | uint32_t tiling_flags, uint32_t pitch, |
828 | uint32_t tiling_flags, uint32_t pitch, |
826 | uint32_t offset, uint32_t obj_size); |
829 | uint32_t offset, uint32_t obj_size); |
827 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
830 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
828 | void (*bandwidth_update)(struct radeon_device *rdev); |
831 | void (*bandwidth_update)(struct radeon_device *rdev); |
829 | void (*hpd_init)(struct radeon_device *rdev); |
832 | void (*hpd_init)(struct radeon_device *rdev); |
830 | void (*hpd_fini)(struct radeon_device *rdev); |
833 | void (*hpd_fini)(struct radeon_device *rdev); |
831 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
834 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
832 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
835 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
833 | /* ioctl hw specific callback. Some hw might want to perform special |
836 | /* ioctl hw specific callback. Some hw might want to perform special |
834 | * operation on specific ioctl. For instance on wait idle some hw |
837 | * operation on specific ioctl. For instance on wait idle some hw |
835 | * might want to perform and HDP flush through MMIO as it seems that |
838 | * might want to perform and HDP flush through MMIO as it seems that |
836 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
839 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
837 | * through ring. |
840 | * through ring. |
838 | */ |
841 | */ |
839 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
842 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
840 | }; |
843 | }; |
841 | 844 | ||
842 | /* |
845 | /* |
843 | * Asic structures |
846 | * Asic structures |
844 | */ |
847 | */ |
845 | struct r100_asic { |
848 | struct r100_asic { |
846 | const unsigned *reg_safe_bm; |
849 | const unsigned *reg_safe_bm; |
847 | unsigned reg_safe_bm_size; |
850 | unsigned reg_safe_bm_size; |
848 | u32 hdp_cntl; |
851 | u32 hdp_cntl; |
849 | }; |
852 | }; |
850 | 853 | ||
851 | struct r300_asic { |
854 | struct r300_asic { |
852 | const unsigned *reg_safe_bm; |
855 | const unsigned *reg_safe_bm; |
853 | unsigned reg_safe_bm_size; |
856 | unsigned reg_safe_bm_size; |
854 | u32 resync_scratch; |
857 | u32 resync_scratch; |
855 | u32 hdp_cntl; |
858 | u32 hdp_cntl; |
856 | }; |
859 | }; |
857 | 860 | ||
858 | struct r600_asic { |
861 | struct r600_asic { |
859 | unsigned max_pipes; |
862 | unsigned max_pipes; |
860 | unsigned max_tile_pipes; |
863 | unsigned max_tile_pipes; |
861 | unsigned max_simds; |
864 | unsigned max_simds; |
862 | unsigned max_backends; |
865 | unsigned max_backends; |
863 | unsigned max_gprs; |
866 | unsigned max_gprs; |
864 | unsigned max_threads; |
867 | unsigned max_threads; |
865 | unsigned max_stack_entries; |
868 | unsigned max_stack_entries; |
866 | unsigned max_hw_contexts; |
869 | unsigned max_hw_contexts; |
867 | unsigned max_gs_threads; |
870 | unsigned max_gs_threads; |
868 | unsigned sx_max_export_size; |
871 | unsigned sx_max_export_size; |
869 | unsigned sx_max_export_pos_size; |
872 | unsigned sx_max_export_pos_size; |
870 | unsigned sx_max_export_smx_size; |
873 | unsigned sx_max_export_smx_size; |
871 | unsigned sq_num_cf_insts; |
874 | unsigned sq_num_cf_insts; |
872 | unsigned tiling_nbanks; |
875 | unsigned tiling_nbanks; |
873 | unsigned tiling_npipes; |
876 | unsigned tiling_npipes; |
874 | unsigned tiling_group_size; |
877 | unsigned tiling_group_size; |
875 | }; |
878 | }; |
876 | 879 | ||
877 | struct rv770_asic { |
880 | struct rv770_asic { |
878 | unsigned max_pipes; |
881 | unsigned max_pipes; |
879 | unsigned max_tile_pipes; |
882 | unsigned max_tile_pipes; |
880 | unsigned max_simds; |
883 | unsigned max_simds; |
881 | unsigned max_backends; |
884 | unsigned max_backends; |
882 | unsigned max_gprs; |
885 | unsigned max_gprs; |
883 | unsigned max_threads; |
886 | unsigned max_threads; |
884 | unsigned max_stack_entries; |
887 | unsigned max_stack_entries; |
885 | unsigned max_hw_contexts; |
888 | unsigned max_hw_contexts; |
886 | unsigned max_gs_threads; |
889 | unsigned max_gs_threads; |
887 | unsigned sx_max_export_size; |
890 | unsigned sx_max_export_size; |
888 | unsigned sx_max_export_pos_size; |
891 | unsigned sx_max_export_pos_size; |
889 | unsigned sx_max_export_smx_size; |
892 | unsigned sx_max_export_smx_size; |
890 | unsigned sq_num_cf_insts; |
893 | unsigned sq_num_cf_insts; |
891 | unsigned sx_num_of_sets; |
894 | unsigned sx_num_of_sets; |
892 | unsigned sc_prim_fifo_size; |
895 | unsigned sc_prim_fifo_size; |
893 | unsigned sc_hiz_tile_fifo_size; |
896 | unsigned sc_hiz_tile_fifo_size; |
894 | unsigned sc_earlyz_tile_fifo_fize; |
897 | unsigned sc_earlyz_tile_fifo_fize; |
895 | unsigned tiling_nbanks; |
898 | unsigned tiling_nbanks; |
896 | unsigned tiling_npipes; |
899 | unsigned tiling_npipes; |
897 | unsigned tiling_group_size; |
900 | unsigned tiling_group_size; |
898 | }; |
901 | }; |
899 | 902 | ||
900 | union radeon_asic_config { |
903 | union radeon_asic_config { |
901 | struct r300_asic r300; |
904 | struct r300_asic r300; |
902 | struct r100_asic r100; |
905 | struct r100_asic r100; |
903 | struct r600_asic r600; |
906 | struct r600_asic r600; |
904 | struct rv770_asic rv770; |
907 | struct rv770_asic rv770; |
905 | }; |
908 | }; |
906 | 909 | ||
907 | 910 | ||
908 | /* |
911 | /* |
909 | 912 | ||
910 | 913 | ||
911 | 914 | ||
912 | 915 | ||
913 | /* |
916 | /* |
914 | * Core structure, functions and helpers. |
917 | * Core structure, functions and helpers. |
915 | */ |
918 | */ |
916 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
919 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
917 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
920 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
918 | 921 | ||
919 | struct radeon_device { |
922 | struct radeon_device { |
920 | struct device *dev; |
923 | struct device *dev; |
921 | struct drm_device *ddev; |
924 | struct drm_device *ddev; |
922 | struct pci_dev *pdev; |
925 | struct pci_dev *pdev; |
923 | /* ASIC */ |
926 | /* ASIC */ |
924 | union radeon_asic_config config; |
927 | union radeon_asic_config config; |
925 | enum radeon_family family; |
928 | enum radeon_family family; |
926 | unsigned long flags; |
929 | unsigned long flags; |
927 | int usec_timeout; |
930 | int usec_timeout; |
928 | enum radeon_pll_errata pll_errata; |
931 | enum radeon_pll_errata pll_errata; |
929 | int num_gb_pipes; |
932 | int num_gb_pipes; |
930 | int num_z_pipes; |
933 | int num_z_pipes; |
931 | int disp_priority; |
934 | int disp_priority; |
932 | /* BIOS */ |
935 | /* BIOS */ |
933 | uint8_t *bios; |
936 | uint8_t *bios; |
934 | bool is_atom_bios; |
937 | bool is_atom_bios; |
935 | uint16_t bios_header_start; |
938 | uint16_t bios_header_start; |
936 | struct radeon_bo *stollen_vga_memory; |
939 | struct radeon_bo *stollen_vga_memory; |
937 | struct fb_info *fbdev_info; |
940 | struct fb_info *fbdev_info; |
938 | struct radeon_bo *fbdev_rbo; |
941 | struct radeon_bo *fbdev_rbo; |
939 | struct radeon_framebuffer *fbdev_rfb; |
942 | struct radeon_framebuffer *fbdev_rfb; |
940 | /* Register mmio */ |
943 | /* Register mmio */ |
941 | unsigned long rmmio_base; |
944 | unsigned long rmmio_base; |
942 | unsigned long rmmio_size; |
945 | unsigned long rmmio_size; |
943 | void *rmmio; |
946 | void *rmmio; |
944 | radeon_rreg_t mc_rreg; |
947 | radeon_rreg_t mc_rreg; |
945 | radeon_wreg_t mc_wreg; |
948 | radeon_wreg_t mc_wreg; |
946 | radeon_rreg_t pll_rreg; |
949 | radeon_rreg_t pll_rreg; |
947 | radeon_wreg_t pll_wreg; |
950 | radeon_wreg_t pll_wreg; |
948 | uint32_t pcie_reg_mask; |
951 | uint32_t pcie_reg_mask; |
949 | radeon_rreg_t pciep_rreg; |
952 | radeon_rreg_t pciep_rreg; |
950 | radeon_wreg_t pciep_wreg; |
953 | radeon_wreg_t pciep_wreg; |
951 | struct radeon_clock clock; |
954 | struct radeon_clock clock; |
952 | struct radeon_mc mc; |
955 | struct radeon_mc mc; |
953 | struct radeon_gart gart; |
956 | struct radeon_gart gart; |
954 | struct radeon_mode_info mode_info; |
957 | struct radeon_mode_info mode_info; |
955 | struct radeon_scratch scratch; |
958 | struct radeon_scratch scratch; |
956 | struct radeon_mman mman; |
959 | struct radeon_mman mman; |
957 | struct radeon_fence_driver fence_drv; |
960 | struct radeon_fence_driver fence_drv; |
958 | struct radeon_cp cp; |
961 | struct radeon_cp cp; |
959 | struct radeon_ib_pool ib_pool; |
962 | struct radeon_ib_pool ib_pool; |
960 | // struct radeon_irq irq; |
963 | // struct radeon_irq irq; |
961 | struct radeon_asic *asic; |
964 | struct radeon_asic *asic; |
962 | struct radeon_gem gem; |
965 | struct radeon_gem gem; |
963 | struct radeon_pm pm; |
966 | struct radeon_pm pm; |
964 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
967 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
965 | // struct mutex cs_mutex; |
968 | struct mutex cs_mutex; |
966 | struct radeon_wb wb; |
969 | struct radeon_wb wb; |
967 | struct radeon_dummy_page dummy_page; |
970 | struct radeon_dummy_page dummy_page; |
968 | bool gpu_lockup; |
971 | bool gpu_lockup; |
969 | bool shutdown; |
972 | bool shutdown; |
970 | bool suspend; |
973 | bool suspend; |
971 | bool need_dma32; |
974 | bool need_dma32; |
972 | bool accel_working; |
975 | bool accel_working; |
973 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
976 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
974 | const struct firmware *me_fw; /* all family ME firmware */ |
977 | const struct firmware *me_fw; /* all family ME firmware */ |
975 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
978 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
976 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
979 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
977 | struct r600_blit r600_blit; |
980 | struct r600_blit r600_blit; |
978 | int msi_enabled; /* msi enabled */ |
981 | int msi_enabled; /* msi enabled */ |
979 | int num_crtc; /* number of crtcs */ |
982 | int num_crtc; /* number of crtcs */ |
- | 983 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
|
980 | 984 | ||
981 | /* audio stuff */ |
985 | /* audio stuff */ |
982 | // struct timer_list audio_timer; |
986 | // struct timer_list audio_timer; |
983 | int audio_channels; |
987 | int audio_channels; |
984 | int audio_rate; |
988 | int audio_rate; |
985 | int audio_bits_per_sample; |
989 | int audio_bits_per_sample; |
986 | uint8_t audio_status_bits; |
990 | uint8_t audio_status_bits; |
987 | uint8_t audio_category_code; |
991 | uint8_t audio_category_code; |
988 | 992 | ||
989 | bool powered_down; |
993 | bool powered_down; |
990 | }; |
994 | }; |
991 | 995 | ||
992 | int radeon_device_init(struct radeon_device *rdev, |
996 | int radeon_device_init(struct radeon_device *rdev, |
993 | struct drm_device *ddev, |
997 | struct drm_device *ddev, |
994 | struct pci_dev *pdev, |
998 | struct pci_dev *pdev, |
995 | uint32_t flags); |
999 | uint32_t flags); |
996 | void radeon_device_fini(struct radeon_device *rdev); |
1000 | void radeon_device_fini(struct radeon_device *rdev); |
997 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
1001 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
998 | 1002 | ||
999 | /* r600 blit */ |
1003 | /* r600 blit */ |
1000 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
1004 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
1001 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
1005 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
1002 | void r600_kms_blit_copy(struct radeon_device *rdev, |
1006 | void r600_kms_blit_copy(struct radeon_device *rdev, |
1003 | u64 src_gpu_addr, u64 dst_gpu_addr, |
1007 | u64 src_gpu_addr, u64 dst_gpu_addr, |
1004 | int size_bytes); |
1008 | int size_bytes); |
1005 | 1009 | ||
1006 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1010 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1007 | { |
1011 | { |
1008 | if (reg < rdev->rmmio_size) |
1012 | if (reg < rdev->rmmio_size) |
1009 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1013 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1010 | else { |
1014 | else { |
1011 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1015 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1012 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1016 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1013 | } |
1017 | } |
1014 | } |
1018 | } |
1015 | 1019 | ||
1016 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1020 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1017 | { |
1021 | { |
1018 | if (reg < rdev->rmmio_size) |
1022 | if (reg < rdev->rmmio_size) |
1019 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1023 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1020 | else { |
1024 | else { |
1021 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1025 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
1022 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1026 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
1023 | } |
1027 | } |
1024 | } |
1028 | } |
1025 | 1029 | ||
1026 | /* |
1030 | /* |
1027 | * Cast helper |
1031 | * Cast helper |
1028 | */ |
1032 | */ |
1029 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
1033 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
1030 | 1034 | ||
1031 | /* |
1035 | /* |
1032 | * Registers read & write functions. |
1036 | * Registers read & write functions. |
1033 | */ |
1037 | */ |
1034 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
1038 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
1035 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
1039 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
1036 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
1040 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
1037 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1041 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1038 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1042 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1039 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1043 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1040 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
1044 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
1041 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
1045 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
1042 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
1046 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
1043 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
1047 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
1044 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1048 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1045 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
1049 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
1046 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1050 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1047 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
1051 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
1048 | #define WREG32_P(reg, val, mask) \ |
1052 | #define WREG32_P(reg, val, mask) \ |
1049 | do { \ |
1053 | do { \ |
1050 | uint32_t tmp_ = RREG32(reg); \ |
1054 | uint32_t tmp_ = RREG32(reg); \ |
1051 | tmp_ &= (mask); \ |
1055 | tmp_ &= (mask); \ |
1052 | tmp_ |= ((val) & ~(mask)); \ |
1056 | tmp_ |= ((val) & ~(mask)); \ |
1053 | WREG32(reg, tmp_); \ |
1057 | WREG32(reg, tmp_); \ |
1054 | } while (0) |
1058 | } while (0) |
1055 | #define WREG32_PLL_P(reg, val, mask) \ |
1059 | #define WREG32_PLL_P(reg, val, mask) \ |
1056 | do { \ |
1060 | do { \ |
1057 | uint32_t tmp_ = RREG32_PLL(reg); \ |
1061 | uint32_t tmp_ = RREG32_PLL(reg); \ |
1058 | tmp_ &= (mask); \ |
1062 | tmp_ &= (mask); \ |
1059 | tmp_ |= ((val) & ~(mask)); \ |
1063 | tmp_ |= ((val) & ~(mask)); \ |
1060 | WREG32_PLL(reg, tmp_); \ |
1064 | WREG32_PLL(reg, tmp_); \ |
1061 | } while (0) |
1065 | } while (0) |
1062 | 1066 | ||
1063 | /* |
1067 | /* |
1064 | * Indirect registers accessor |
1068 | * Indirect registers accessor |
1065 | */ |
1069 | */ |
1066 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
1070 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
1067 | { |
1071 | { |
1068 | uint32_t r; |
1072 | uint32_t r; |
1069 | 1073 | ||
1070 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1074 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1071 | r = RREG32(RADEON_PCIE_DATA); |
1075 | r = RREG32(RADEON_PCIE_DATA); |
1072 | return r; |
1076 | return r; |
1073 | } |
1077 | } |
1074 | 1078 | ||
1075 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1079 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1076 | { |
1080 | { |
1077 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1081 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1078 | WREG32(RADEON_PCIE_DATA, (v)); |
1082 | WREG32(RADEON_PCIE_DATA, (v)); |
1079 | } |
1083 | } |
1080 | 1084 | ||
1081 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1085 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1082 | 1086 | ||
1083 | 1087 | ||
1084 | /* |
1088 | /* |
1085 | * ASICs helpers. |
1089 | * ASICs helpers. |
1086 | */ |
1090 | */ |
1087 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1091 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1088 | (rdev->pdev->device == 0x5969)) |
1092 | (rdev->pdev->device == 0x5969)) |
1089 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1093 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1090 | (rdev->family == CHIP_RV200) || \ |
1094 | (rdev->family == CHIP_RV200) || \ |
1091 | (rdev->family == CHIP_RS100) || \ |
1095 | (rdev->family == CHIP_RS100) || \ |
1092 | (rdev->family == CHIP_RS200) || \ |
1096 | (rdev->family == CHIP_RS200) || \ |
1093 | (rdev->family == CHIP_RV250) || \ |
1097 | (rdev->family == CHIP_RV250) || \ |
1094 | (rdev->family == CHIP_RV280) || \ |
1098 | (rdev->family == CHIP_RV280) || \ |
1095 | (rdev->family == CHIP_RS300)) |
1099 | (rdev->family == CHIP_RS300)) |
1096 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
1100 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
1097 | (rdev->family == CHIP_RV350) || \ |
1101 | (rdev->family == CHIP_RV350) || \ |
1098 | (rdev->family == CHIP_R350) || \ |
1102 | (rdev->family == CHIP_R350) || \ |
1099 | (rdev->family == CHIP_RV380) || \ |
1103 | (rdev->family == CHIP_RV380) || \ |
1100 | (rdev->family == CHIP_R420) || \ |
1104 | (rdev->family == CHIP_R420) || \ |
1101 | (rdev->family == CHIP_R423) || \ |
1105 | (rdev->family == CHIP_R423) || \ |
1102 | (rdev->family == CHIP_RV410) || \ |
1106 | (rdev->family == CHIP_RV410) || \ |
1103 | (rdev->family == CHIP_RS400) || \ |
1107 | (rdev->family == CHIP_RS400) || \ |
1104 | (rdev->family == CHIP_RS480)) |
1108 | (rdev->family == CHIP_RS480)) |
1105 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1109 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1106 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1110 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1107 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1111 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
1108 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1112 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1109 | 1113 | ||
1110 | /* |
1114 | /* |
1111 | * BIOS helpers. |
1115 | * BIOS helpers. |
1112 | */ |
1116 | */ |
1113 | #define RBIOS8(i) (rdev->bios[i]) |
1117 | #define RBIOS8(i) (rdev->bios[i]) |
1114 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
1118 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
1115 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
1119 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
1116 | 1120 | ||
1117 | int radeon_combios_init(struct radeon_device *rdev); |
1121 | int radeon_combios_init(struct radeon_device *rdev); |
1118 | void radeon_combios_fini(struct radeon_device *rdev); |
1122 | void radeon_combios_fini(struct radeon_device *rdev); |
1119 | int radeon_atombios_init(struct radeon_device *rdev); |
1123 | int radeon_atombios_init(struct radeon_device *rdev); |
1120 | void radeon_atombios_fini(struct radeon_device *rdev); |
1124 | void radeon_atombios_fini(struct radeon_device *rdev); |
1121 | 1125 | ||
1122 | 1126 | ||
1123 | /* |
1127 | /* |
1124 | * RING helpers. |
1128 | * RING helpers. |
1125 | */ |
1129 | */ |
1126 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1130 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1127 | { |
1131 | { |
1128 | #if DRM_DEBUG_CODE |
1132 | #if DRM_DEBUG_CODE |
1129 | if (rdev->cp.count_dw <= 0) { |
1133 | if (rdev->cp.count_dw <= 0) { |
1130 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
1134 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
1131 | } |
1135 | } |
1132 | #endif |
1136 | #endif |
1133 | rdev->cp.ring[rdev->cp.wptr++] = v; |
1137 | rdev->cp.ring[rdev->cp.wptr++] = v; |
1134 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
1138 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
1135 | rdev->cp.count_dw--; |
1139 | rdev->cp.count_dw--; |
1136 | rdev->cp.ring_free_dw--; |
1140 | rdev->cp.ring_free_dw--; |
1137 | } |
1141 | } |
1138 | 1142 | ||
1139 | 1143 | ||
1140 | /* |
1144 | /* |
1141 | * ASICs macro. |
1145 | * ASICs macro. |
1142 | */ |
1146 | */ |
1143 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
1147 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
1144 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1148 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1145 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
1149 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
1146 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
1150 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
1147 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1151 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1148 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1152 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1149 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1153 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
1150 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1154 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1151 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1155 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1152 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1156 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1153 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1157 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1154 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1158 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1155 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
1159 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
1156 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1160 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1157 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
1161 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
1158 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1162 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1159 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1163 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1160 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
1164 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
1161 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
1165 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
1162 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1166 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
1163 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1167 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1164 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1168 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1165 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1169 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1166 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
1170 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
1167 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
1171 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
1168 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1172 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1169 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1173 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
1170 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1174 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1171 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
1175 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
1172 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
1176 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
1173 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1177 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1174 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
1178 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
1175 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
1179 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
1176 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
1180 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
1177 | 1181 | ||
1178 | /* Common functions */ |
1182 | /* Common functions */ |
1179 | /* AGP */ |
1183 | /* AGP */ |
1180 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1184 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1181 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1185 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1182 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1186 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1183 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1187 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1184 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
1188 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
1185 | extern bool radeon_card_posted(struct radeon_device *rdev); |
1189 | extern bool radeon_card_posted(struct radeon_device *rdev); |
1186 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1190 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1187 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1191 | extern int radeon_clocks_init(struct radeon_device *rdev); |
1188 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
1192 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
1189 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1193 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1190 | extern void radeon_surface_init(struct radeon_device *rdev); |
1194 | extern void radeon_surface_init(struct radeon_device *rdev); |
1191 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1195 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
1192 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1196 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1193 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1197 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
1194 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1198 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1195 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1199 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1196 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1200 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1197 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1201 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1198 | extern int radeon_resume_kms(struct drm_device *dev); |
1202 | extern int radeon_resume_kms(struct drm_device *dev); |
1199 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
1203 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
1200 | 1204 | ||
1201 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1205 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
1202 | struct r100_mc_save { |
1206 | struct r100_mc_save { |
1203 | u32 GENMO_WT; |
1207 | u32 GENMO_WT; |
1204 | u32 CRTC_EXT_CNTL; |
1208 | u32 CRTC_EXT_CNTL; |
1205 | u32 CRTC_GEN_CNTL; |
1209 | u32 CRTC_GEN_CNTL; |
1206 | u32 CRTC2_GEN_CNTL; |
1210 | u32 CRTC2_GEN_CNTL; |
1207 | u32 CUR_OFFSET; |
1211 | u32 CUR_OFFSET; |
1208 | u32 CUR2_OFFSET; |
1212 | u32 CUR2_OFFSET; |
1209 | }; |
1213 | }; |
1210 | extern void r100_cp_disable(struct radeon_device *rdev); |
1214 | extern void r100_cp_disable(struct radeon_device *rdev); |
1211 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
1215 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
1212 | extern void r100_cp_fini(struct radeon_device *rdev); |
1216 | extern void r100_cp_fini(struct radeon_device *rdev); |
1213 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
1217 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
1214 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
1218 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
1215 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
1219 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
1216 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
1220 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
1217 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
1221 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
1218 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
1222 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
1219 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
1223 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
1220 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
1224 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
1221 | extern void r100_ib_fini(struct radeon_device *rdev); |
1225 | extern void r100_ib_fini(struct radeon_device *rdev); |
1222 | extern int r100_ib_init(struct radeon_device *rdev); |
1226 | extern int r100_ib_init(struct radeon_device *rdev); |
1223 | extern void r100_irq_disable(struct radeon_device *rdev); |
1227 | extern void r100_irq_disable(struct radeon_device *rdev); |
1224 | extern int r100_irq_set(struct radeon_device *rdev); |
1228 | extern int r100_irq_set(struct radeon_device *rdev); |
1225 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
1229 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
1226 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
1230 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
1227 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
1231 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
1228 | extern void r100_wb_disable(struct radeon_device *rdev); |
1232 | extern void r100_wb_disable(struct radeon_device *rdev); |
1229 | extern void r100_wb_fini(struct radeon_device *rdev); |
1233 | extern void r100_wb_fini(struct radeon_device *rdev); |
1230 | extern int r100_wb_init(struct radeon_device *rdev); |
1234 | extern int r100_wb_init(struct radeon_device *rdev); |
1231 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1235 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1232 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
1236 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
1233 | extern int r100_cp_reset(struct radeon_device *rdev); |
1237 | extern int r100_cp_reset(struct radeon_device *rdev); |
1234 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
1238 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
1235 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1239 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1236 | struct radeon_cs_packet *pkt, |
1240 | struct radeon_cs_packet *pkt, |
1237 | struct radeon_bo *robj); |
1241 | struct radeon_bo *robj); |
1238 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1242 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1239 | struct radeon_cs_packet *pkt, |
1243 | struct radeon_cs_packet *pkt, |
1240 | const unsigned *auth, unsigned n, |
1244 | const unsigned *auth, unsigned n, |
1241 | radeon_packet0_check_t check); |
1245 | radeon_packet0_check_t check); |
1242 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1246 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
1243 | struct radeon_cs_packet *pkt, |
1247 | struct radeon_cs_packet *pkt, |
1244 | unsigned idx); |
1248 | unsigned idx); |
1245 | extern void r100_enable_bm(struct radeon_device *rdev); |
1249 | extern void r100_enable_bm(struct radeon_device *rdev); |
1246 | extern void r100_set_common_regs(struct radeon_device *rdev); |
1250 | extern void r100_set_common_regs(struct radeon_device *rdev); |
1247 | 1251 | ||
1248 | /* rv200,rv250,rv280 */ |
1252 | /* rv200,rv250,rv280 */ |
1249 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
1253 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
1250 | 1254 | ||
1251 | /* r300,r350,rv350,rv370,rv380 */ |
1255 | /* r300,r350,rv350,rv370,rv380 */ |
1252 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1256 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
1253 | extern void r300_mc_program(struct radeon_device *rdev); |
1257 | extern void r300_mc_program(struct radeon_device *rdev); |
1254 | extern void r300_mc_init(struct radeon_device *rdev); |
1258 | extern void r300_mc_init(struct radeon_device *rdev); |
1255 | extern void r300_clock_startup(struct radeon_device *rdev); |
1259 | extern void r300_clock_startup(struct radeon_device *rdev); |
1256 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1260 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
1257 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1261 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1258 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1262 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
1259 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1263 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
1260 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1264 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
1261 | 1265 | ||
1262 | /* r420,r423,rv410 */ |
1266 | /* r420,r423,rv410 */ |
1263 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1267 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1264 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1268 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
1265 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1269 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1266 | extern void r420_pipes_init(struct radeon_device *rdev); |
1270 | extern void r420_pipes_init(struct radeon_device *rdev); |
1267 | 1271 | ||
1268 | /* rv515 */ |
1272 | /* rv515 */ |
1269 | struct rv515_mc_save { |
1273 | struct rv515_mc_save { |
1270 | u32 d1vga_control; |
1274 | u32 d1vga_control; |
1271 | u32 d2vga_control; |
1275 | u32 d2vga_control; |
1272 | u32 vga_render_control; |
1276 | u32 vga_render_control; |
1273 | u32 vga_hdp_control; |
1277 | u32 vga_hdp_control; |
1274 | u32 d1crtc_control; |
1278 | u32 d1crtc_control; |
1275 | u32 d2crtc_control; |
1279 | u32 d2crtc_control; |
1276 | }; |
1280 | }; |
1277 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1281 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1278 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1282 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1279 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
1283 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
1280 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1284 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1281 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
1285 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
1282 | extern void rv515_clock_startup(struct radeon_device *rdev); |
1286 | extern void rv515_clock_startup(struct radeon_device *rdev); |
1283 | extern void rv515_debugfs(struct radeon_device *rdev); |
1287 | extern void rv515_debugfs(struct radeon_device *rdev); |
1284 | extern int rv515_suspend(struct radeon_device *rdev); |
1288 | extern int rv515_suspend(struct radeon_device *rdev); |
1285 | 1289 | ||
1286 | /* rs400 */ |
1290 | /* rs400 */ |
1287 | extern int rs400_gart_init(struct radeon_device *rdev); |
1291 | extern int rs400_gart_init(struct radeon_device *rdev); |
1288 | extern int rs400_gart_enable(struct radeon_device *rdev); |
1292 | extern int rs400_gart_enable(struct radeon_device *rdev); |
1289 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
1293 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
1290 | extern void rs400_gart_disable(struct radeon_device *rdev); |
1294 | extern void rs400_gart_disable(struct radeon_device *rdev); |
1291 | extern void rs400_gart_fini(struct radeon_device *rdev); |
1295 | extern void rs400_gart_fini(struct radeon_device *rdev); |
1292 | 1296 | ||
1293 | /* rs600 */ |
1297 | /* rs600 */ |
1294 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
1298 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
1295 | extern int rs600_irq_set(struct radeon_device *rdev); |
1299 | extern int rs600_irq_set(struct radeon_device *rdev); |
1296 | extern void rs600_irq_disable(struct radeon_device *rdev); |
1300 | extern void rs600_irq_disable(struct radeon_device *rdev); |
1297 | 1301 | ||
1298 | /* rs690, rs740 */ |
1302 | /* rs690, rs740 */ |
1299 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1303 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
1300 | struct drm_display_mode *mode1, |
1304 | struct drm_display_mode *mode1, |
1301 | struct drm_display_mode *mode2); |
1305 | struct drm_display_mode *mode2); |
1302 | 1306 | ||
1303 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
1307 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
1304 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1308 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
1305 | extern bool r600_card_posted(struct radeon_device *rdev); |
1309 | extern bool r600_card_posted(struct radeon_device *rdev); |
1306 | extern void r600_cp_stop(struct radeon_device *rdev); |
1310 | extern void r600_cp_stop(struct radeon_device *rdev); |
1307 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1311 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1308 | extern int r600_cp_resume(struct radeon_device *rdev); |
1312 | extern int r600_cp_resume(struct radeon_device *rdev); |
1309 | extern void r600_cp_fini(struct radeon_device *rdev); |
1313 | extern void r600_cp_fini(struct radeon_device *rdev); |
1310 | extern int r600_count_pipe_bits(uint32_t val); |
1314 | extern int r600_count_pipe_bits(uint32_t val); |
1311 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1315 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1312 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1316 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
1313 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1317 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1314 | extern int r600_ib_test(struct radeon_device *rdev); |
1318 | extern int r600_ib_test(struct radeon_device *rdev); |
1315 | extern int r600_ring_test(struct radeon_device *rdev); |
1319 | extern int r600_ring_test(struct radeon_device *rdev); |
1316 | extern void r600_wb_fini(struct radeon_device *rdev); |
1320 | extern void r600_wb_fini(struct radeon_device *rdev); |
1317 | extern int r600_wb_enable(struct radeon_device *rdev); |
1321 | extern int r600_wb_enable(struct radeon_device *rdev); |
1318 | extern void r600_wb_disable(struct radeon_device *rdev); |
1322 | extern void r600_wb_disable(struct radeon_device *rdev); |
1319 | extern void r600_scratch_init(struct radeon_device *rdev); |
1323 | extern void r600_scratch_init(struct radeon_device *rdev); |
1320 | extern int r600_blit_init(struct radeon_device *rdev); |
1324 | extern int r600_blit_init(struct radeon_device *rdev); |
1321 | extern void r600_blit_fini(struct radeon_device *rdev); |
1325 | extern void r600_blit_fini(struct radeon_device *rdev); |
1322 | extern int r600_init_microcode(struct radeon_device *rdev); |
1326 | extern int r600_init_microcode(struct radeon_device *rdev); |
1323 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1327 | extern int r600_gpu_reset(struct radeon_device *rdev); |
1324 | /* r600 irq */ |
1328 | /* r600 irq */ |
1325 | extern int r600_irq_init(struct radeon_device *rdev); |
1329 | extern int r600_irq_init(struct radeon_device *rdev); |
1326 | extern void r600_irq_fini(struct radeon_device *rdev); |
1330 | extern void r600_irq_fini(struct radeon_device *rdev); |
1327 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1331 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1328 | extern int r600_irq_set(struct radeon_device *rdev); |
1332 | extern int r600_irq_set(struct radeon_device *rdev); |
1329 | extern void r600_irq_suspend(struct radeon_device *rdev); |
1333 | extern void r600_irq_suspend(struct radeon_device *rdev); |
1330 | /* r600 audio */ |
1334 | /* r600 audio */ |
1331 | extern int r600_audio_init(struct radeon_device *rdev); |
1335 | extern int r600_audio_init(struct radeon_device *rdev); |
1332 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
1336 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
1333 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
1337 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
1334 | extern void r600_audio_fini(struct radeon_device *rdev); |
1338 | extern void r600_audio_fini(struct radeon_device *rdev); |
1335 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
1339 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
1336 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); |
1340 | extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable); |
1337 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1341 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1338 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
1342 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
1339 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
1343 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
1340 | int channels, |
1344 | int channels, |
1341 | int rate, |
1345 | int rate, |
1342 | int bps, |
1346 | int bps, |
1343 | uint8_t status_bits, |
1347 | uint8_t status_bits, |
1344 | uint8_t category_code); |
1348 | uint8_t category_code); |
1345 | 1349 | ||
1346 | /* evergreen */ |
1350 | /* evergreen */ |
1347 | struct evergreen_mc_save { |
1351 | struct evergreen_mc_save { |
1348 | u32 vga_control[6]; |
1352 | u32 vga_control[6]; |
1349 | u32 vga_render_control; |
1353 | u32 vga_render_control; |
1350 | u32 vga_hdp_control; |
1354 | u32 vga_hdp_control; |
1351 | u32 crtc_control[6]; |
1355 | u32 crtc_control[6]; |
1352 | }; |
1356 | }; |
1353 | 1357 | ||
1354 | #include "radeon_object.h" |
1358 | #include "radeon_object.h" |
1355 | 1359 | ||
1356 | #define DRM_UDELAY(d) udelay(d) |
1360 | #define DRM_UDELAY(d) udelay(d) |
1357 | 1361 | ||
1358 | resource_size_t |
1362 | resource_size_t |
1359 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1363 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
1360 | resource_size_t |
1364 | resource_size_t |
1361 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1365 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
1362 | 1366 | ||
1363 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1367 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1364 | videomode_t *mode, bool strict); |
1368 | videomode_t *mode, bool strict); |
1365 | 1369 | ||
1366 | 1370 | ||
1367 | #endif=>><>><>><>><>>>>=> |
1371 | #endif=>><>><>><>><>>>>=> |