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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include "drmP.h" |
28 | #include "drmP.h" |
29 | #include "radeon.h" |
29 | #include "radeon.h" |
30 | #include "atom.h" |
30 | #include "atom.h" |
31 | #include "r520d.h" |
31 | #include "r520d.h" |
32 | 32 | ||
33 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
33 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
34 | 34 | ||
35 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
35 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
36 | { |
36 | { |
37 | unsigned i; |
37 | unsigned i; |
38 | uint32_t tmp; |
38 | uint32_t tmp; |
39 | 39 | ||
40 | for (i = 0; i < rdev->usec_timeout; i++) { |
40 | for (i = 0; i < rdev->usec_timeout; i++) { |
41 | /* read MC_STATUS */ |
41 | /* read MC_STATUS */ |
42 | tmp = RREG32_MC(R520_MC_STATUS); |
42 | tmp = RREG32_MC(R520_MC_STATUS); |
43 | if (tmp & R520_MC_STATUS_IDLE) { |
43 | if (tmp & R520_MC_STATUS_IDLE) { |
44 | return 0; |
44 | return 0; |
45 | } |
45 | } |
46 | DRM_UDELAY(1); |
46 | DRM_UDELAY(1); |
47 | } |
47 | } |
48 | return -1; |
48 | return -1; |
49 | } |
49 | } |
50 | 50 | ||
51 | static void r520_gpu_init(struct radeon_device *rdev) |
51 | static void r520_gpu_init(struct radeon_device *rdev) |
52 | { |
52 | { |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
54 | ENTER(); |
54 | ENTER(); |
55 | 55 | ||
56 | r100_hdp_reset(rdev); |
56 | r100_hdp_reset(rdev); |
57 | rv515_vga_render_disable(rdev); |
57 | rv515_vga_render_disable(rdev); |
58 | /* |
58 | /* |
59 | * DST_PIPE_CONFIG 0x170C |
59 | * DST_PIPE_CONFIG 0x170C |
60 | * GB_TILE_CONFIG 0x4018 |
60 | * GB_TILE_CONFIG 0x4018 |
61 | * GB_FIFO_SIZE 0x4024 |
61 | * GB_FIFO_SIZE 0x4024 |
62 | * GB_PIPE_SELECT 0x402C |
62 | * GB_PIPE_SELECT 0x402C |
63 | * GB_PIPE_SELECT2 0x4124 |
63 | * GB_PIPE_SELECT2 0x4124 |
64 | * Z_PIPE_SHIFT 0 |
64 | * Z_PIPE_SHIFT 0 |
65 | * Z_PIPE_MASK 0x000000003 |
65 | * Z_PIPE_MASK 0x000000003 |
66 | * GB_FIFO_SIZE2 0x4128 |
66 | * GB_FIFO_SIZE2 0x4128 |
67 | * SC_SFIFO_SIZE_SHIFT 0 |
67 | * SC_SFIFO_SIZE_SHIFT 0 |
68 | * SC_SFIFO_SIZE_MASK 0x000000003 |
68 | * SC_SFIFO_SIZE_MASK 0x000000003 |
69 | * SC_MFIFO_SIZE_SHIFT 2 |
69 | * SC_MFIFO_SIZE_SHIFT 2 |
70 | * SC_MFIFO_SIZE_MASK 0x00000000C |
70 | * SC_MFIFO_SIZE_MASK 0x00000000C |
71 | * FG_SFIFO_SIZE_SHIFT 4 |
71 | * FG_SFIFO_SIZE_SHIFT 4 |
72 | * FG_SFIFO_SIZE_MASK 0x000000030 |
72 | * FG_SFIFO_SIZE_MASK 0x000000030 |
73 | * ZB_MFIFO_SIZE_SHIFT 6 |
73 | * ZB_MFIFO_SIZE_SHIFT 6 |
74 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
74 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
75 | * GA_ENHANCE 0x4274 |
75 | * GA_ENHANCE 0x4274 |
76 | * SU_REG_DEST 0x42C8 |
76 | * SU_REG_DEST 0x42C8 |
77 | */ |
77 | */ |
78 | /* workaround for RV530 */ |
78 | /* workaround for RV530 */ |
79 | if (rdev->family == CHIP_RV530) { |
79 | if (rdev->family == CHIP_RV530) { |
80 | WREG32(0x4128, 0xFF); |
80 | WREG32(0x4128, 0xFF); |
81 | } |
81 | } |
82 | r420_pipes_init(rdev); |
82 | r420_pipes_init(rdev); |
83 | gb_pipe_select = RREG32(0x402C); |
83 | gb_pipe_select = RREG32(0x402C); |
84 | tmp = RREG32(0x170C); |
84 | tmp = RREG32(0x170C); |
85 | pipe_select_current = (tmp >> 2) & 3; |
85 | pipe_select_current = (tmp >> 2) & 3; |
86 | tmp = (1 << pipe_select_current) | |
86 | tmp = (1 << pipe_select_current) | |
87 | (((gb_pipe_select >> 8) & 0xF) << 4); |
87 | (((gb_pipe_select >> 8) & 0xF) << 4); |
88 | WREG32_PLL(0x000D, tmp); |
88 | WREG32_PLL(0x000D, tmp); |
89 | if (r520_mc_wait_for_idle(rdev)) { |
89 | if (r520_mc_wait_for_idle(rdev)) { |
90 | printk(KERN_WARNING "Failed to wait MC idle while " |
90 | printk(KERN_WARNING "Failed to wait MC idle while " |
91 | "programming pipes. Bad things might happen.\n"); |
91 | "programming pipes. Bad things might happen.\n"); |
92 | } |
92 | } |
93 | } |
93 | } |
94 | 94 | ||
95 | static void r520_vram_get_type(struct radeon_device *rdev) |
95 | static void r520_vram_get_type(struct radeon_device *rdev) |
96 | { |
96 | { |
97 | uint32_t tmp; |
97 | uint32_t tmp; |
98 | ENTER(); |
98 | ENTER(); |
99 | 99 | ||
100 | rdev->mc.vram_width = 128; |
100 | rdev->mc.vram_width = 128; |
101 | rdev->mc.vram_is_ddr = true; |
101 | rdev->mc.vram_is_ddr = true; |
102 | tmp = RREG32_MC(R520_MC_CNTL0); |
102 | tmp = RREG32_MC(R520_MC_CNTL0); |
103 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
103 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
104 | case 0: |
104 | case 0: |
105 | rdev->mc.vram_width = 32; |
105 | rdev->mc.vram_width = 32; |
106 | break; |
106 | break; |
107 | case 1: |
107 | case 1: |
108 | rdev->mc.vram_width = 64; |
108 | rdev->mc.vram_width = 64; |
109 | break; |
109 | break; |
110 | case 2: |
110 | case 2: |
111 | rdev->mc.vram_width = 128; |
111 | rdev->mc.vram_width = 128; |
112 | break; |
112 | break; |
113 | case 3: |
113 | case 3: |
114 | rdev->mc.vram_width = 256; |
114 | rdev->mc.vram_width = 256; |
115 | break; |
115 | break; |
116 | default: |
116 | default: |
117 | rdev->mc.vram_width = 128; |
117 | rdev->mc.vram_width = 128; |
118 | break; |
118 | break; |
119 | } |
119 | } |
120 | if (tmp & R520_MC_CHANNEL_SIZE) |
120 | if (tmp & R520_MC_CHANNEL_SIZE) |
121 | rdev->mc.vram_width *= 2; |
121 | rdev->mc.vram_width *= 2; |
122 | } |
122 | } |
123 | 123 | ||
124 | void r520_vram_info(struct radeon_device *rdev) |
124 | void r520_vram_info(struct radeon_device *rdev) |
125 | { |
125 | { |
126 | fixed20_12 a; |
126 | fixed20_12 a; |
127 | 127 | ||
128 | r520_vram_get_type(rdev); |
128 | r520_vram_get_type(rdev); |
129 | 129 | ||
130 | r100_vram_init_sizes(rdev); |
130 | r100_vram_init_sizes(rdev); |
131 | /* FIXME: we should enforce default clock in case GPU is not in |
131 | /* FIXME: we should enforce default clock in case GPU is not in |
132 | * default setup |
132 | * default setup |
133 | */ |
133 | */ |
134 | a.full = rfixed_const(100); |
134 | a.full = rfixed_const(100); |
135 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
135 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
136 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
136 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
137 | } |
137 | } |
138 | 138 | ||
139 | void r520_mc_program(struct radeon_device *rdev) |
139 | void r520_mc_program(struct radeon_device *rdev) |
140 | { |
140 | { |
141 | struct rv515_mc_save save; |
141 | struct rv515_mc_save save; |
142 | 142 | ||
143 | /* Stops all mc clients */ |
143 | /* Stops all mc clients */ |
144 | rv515_mc_stop(rdev, &save); |
144 | rv515_mc_stop(rdev, &save); |
145 | 145 | ||
146 | /* Wait for mc idle */ |
146 | /* Wait for mc idle */ |
147 | if (r520_mc_wait_for_idle(rdev)) |
147 | if (r520_mc_wait_for_idle(rdev)) |
148 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
148 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
149 | /* Write VRAM size in case we are limiting it */ |
149 | /* Write VRAM size in case we are limiting it */ |
150 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
150 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
151 | /* Program MC, should be a 32bits limited address space */ |
151 | /* Program MC, should be a 32bits limited address space */ |
152 | WREG32_MC(R_000004_MC_FB_LOCATION, |
152 | WREG32_MC(R_000004_MC_FB_LOCATION, |
153 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
153 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
154 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
154 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
155 | WREG32(R_000134_HDP_FB_LOCATION, |
155 | WREG32(R_000134_HDP_FB_LOCATION, |
156 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
156 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
157 | if (rdev->flags & RADEON_IS_AGP) { |
157 | if (rdev->flags & RADEON_IS_AGP) { |
158 | WREG32_MC(R_000005_MC_AGP_LOCATION, |
158 | WREG32_MC(R_000005_MC_AGP_LOCATION, |
159 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
159 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
160 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
160 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
161 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
161 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
162 | WREG32_MC(R_000007_AGP_BASE_2, |
162 | WREG32_MC(R_000007_AGP_BASE_2, |
163 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
163 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
164 | } else { |
164 | } else { |
165 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); |
165 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); |
166 | WREG32_MC(R_000006_AGP_BASE, 0); |
166 | WREG32_MC(R_000006_AGP_BASE, 0); |
167 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
167 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
168 | } |
168 | } |
169 | 169 | ||
170 | rv515_mc_resume(rdev, &save); |
170 | rv515_mc_resume(rdev, &save); |
171 | } |
171 | } |
172 | 172 | ||
173 | static int r520_startup(struct radeon_device *rdev) |
173 | static int r520_startup(struct radeon_device *rdev) |
174 | { |
174 | { |
175 | int r; |
175 | int r; |
176 | 176 | ||
177 | r520_mc_program(rdev); |
177 | r520_mc_program(rdev); |
178 | /* Resume clock */ |
178 | /* Resume clock */ |
179 | rv515_clock_startup(rdev); |
179 | rv515_clock_startup(rdev); |
180 | /* Initialize GPU configuration (# pipes, ...) */ |
180 | /* Initialize GPU configuration (# pipes, ...) */ |
181 | r520_gpu_init(rdev); |
181 | r520_gpu_init(rdev); |
182 | /* Initialize GART (initialize after TTM so we can allocate |
182 | /* Initialize GART (initialize after TTM so we can allocate |
183 | * memory through TTM but finalize after TTM) */ |
183 | * memory through TTM but finalize after TTM) */ |
184 | if (rdev->flags & RADEON_IS_PCIE) { |
184 | if (rdev->flags & RADEON_IS_PCIE) { |
185 | r = rv370_pcie_gart_enable(rdev); |
185 | r = rv370_pcie_gart_enable(rdev); |
186 | if (r) |
186 | if (r) |
187 | return r; |
187 | return r; |
188 | } |
188 | } |
189 | /* Enable IRQ */ |
189 | /* Enable IRQ */ |
190 | // rdev->irq.sw_int = true; |
190 | // rdev->irq.sw_int = true; |
191 | // rs600_irq_set(rdev); |
191 | // rs600_irq_set(rdev); |
192 | /* 1M ring buffer */ |
192 | /* 1M ring buffer */ |
193 | // r = r100_cp_init(rdev, 1024 * 1024); |
193 | // r = r100_cp_init(rdev, 1024 * 1024); |
194 | // if (r) { |
194 | // if (r) { |
195 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
195 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
196 | // return r; |
196 | // return r; |
197 | // } |
197 | // } |
198 | // r = r100_wb_init(rdev); |
198 | // r = r100_wb_init(rdev); |
199 | // if (r) |
199 | // if (r) |
200 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
200 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
201 | // r = r100_ib_init(rdev); |
201 | // r = r100_ib_init(rdev); |
202 | // if (r) { |
202 | // if (r) { |
203 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
203 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
204 | // return r; |
204 | // return r; |
205 | // } |
205 | // } |
206 | return 0; |
206 | return 0; |
207 | } |
207 | } |
208 | 208 | ||
209 | 209 | ||
210 | 210 | ||
211 | int r520_init(struct radeon_device *rdev) |
211 | int r520_init(struct radeon_device *rdev) |
212 | { |
212 | { |
213 | int r; |
213 | int r; |
214 | 214 | ||
215 | ENTER(); |
215 | ENTER(); |
216 | 216 | ||
217 | /* Initialize scratch registers */ |
217 | /* Initialize scratch registers */ |
218 | radeon_scratch_init(rdev); |
218 | radeon_scratch_init(rdev); |
219 | /* Initialize surface registers */ |
219 | /* Initialize surface registers */ |
220 | radeon_surface_init(rdev); |
220 | radeon_surface_init(rdev); |
221 | /* TODO: disable VGA need to use VGA request */ |
221 | /* TODO: disable VGA need to use VGA request */ |
222 | /* BIOS*/ |
222 | /* BIOS*/ |
223 | if (!radeon_get_bios(rdev)) { |
223 | if (!radeon_get_bios(rdev)) { |
224 | if (ASIC_IS_AVIVO(rdev)) |
224 | if (ASIC_IS_AVIVO(rdev)) |
225 | return -EINVAL; |
225 | return -EINVAL; |
226 | } |
226 | } |
227 | if (rdev->is_atom_bios) { |
227 | if (rdev->is_atom_bios) { |
228 | r = radeon_atombios_init(rdev); |
228 | r = radeon_atombios_init(rdev); |
229 | if (r) |
229 | if (r) |
230 | return r; |
230 | return r; |
231 | } else { |
231 | } else { |
232 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
232 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
233 | return -EINVAL; |
233 | return -EINVAL; |
234 | } |
234 | } |
235 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
235 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
236 | if (radeon_gpu_reset(rdev)) { |
236 | if (radeon_gpu_reset(rdev)) { |
237 | dev_warn(rdev->dev, |
237 | dev_warn(rdev->dev, |
238 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
238 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
239 | RREG32(R_000E40_RBBM_STATUS), |
239 | RREG32(R_000E40_RBBM_STATUS), |
240 | RREG32(R_0007C0_CP_STAT)); |
240 | RREG32(R_0007C0_CP_STAT)); |
241 | } |
241 | } |
242 | /* check if cards are posted or not */ |
242 | /* check if cards are posted or not */ |
243 | if (!radeon_card_posted(rdev) && rdev->bios) { |
243 | if (!radeon_card_posted(rdev) && rdev->bios) { |
244 | DRM_INFO("GPU not posted. posting now...\n"); |
244 | DRM_INFO("GPU not posted. posting now...\n"); |
245 | atom_asic_init(rdev->mode_info.atom_context); |
245 | atom_asic_init(rdev->mode_info.atom_context); |
246 | } |
246 | } |
247 | /* Initialize clocks */ |
247 | /* Initialize clocks */ |
248 | radeon_get_clock_info(rdev->ddev); |
248 | radeon_get_clock_info(rdev->ddev); |
249 | /* Get vram informations */ |
249 | /* Get vram informations */ |
250 | r520_vram_info(rdev); |
250 | r520_vram_info(rdev); |
251 | /* Initialize memory controller (also test AGP) */ |
251 | /* Initialize memory controller (also test AGP) */ |
252 | r = r420_mc_init(rdev); |
252 | r = r420_mc_init(rdev); |
- | 253 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
|
253 | if (r) |
254 | if (r) |
254 | return r; |
255 | return r; |
255 | rv515_debugfs(rdev); |
256 | rv515_debugfs(rdev); |
256 | /* Fence driver */ |
257 | /* Fence driver */ |
257 | // r = radeon_fence_driver_init(rdev); |
258 | // r = radeon_fence_driver_init(rdev); |
258 | // if (r) |
259 | // if (r) |
259 | // return r; |
260 | // return r; |
260 | // r = radeon_irq_kms_init(rdev); |
261 | // r = radeon_irq_kms_init(rdev); |
261 | // if (r) |
262 | // if (r) |
262 | // return r; |
263 | // return r; |
263 | /* Memory manager */ |
264 | /* Memory manager */ |
264 | r = radeon_object_init(rdev); |
265 | r = radeon_object_init(rdev); |
265 | if (r) |
266 | if (r) |
266 | return r; |
267 | return r; |
267 | r = rv370_pcie_gart_init(rdev); |
268 | r = rv370_pcie_gart_init(rdev); |
268 | if (r) |
269 | if (r) |
269 | return r; |
270 | return r; |
270 | rv515_set_safe_registers(rdev); |
271 | rv515_set_safe_registers(rdev); |
271 | rdev->accel_working = true; |
272 | rdev->accel_working = true; |
272 | r = r520_startup(rdev); |
273 | r = r520_startup(rdev); |
273 | if (r) { |
274 | if (r) { |
274 | /* Somethings want wront with the accel init stop accel */ |
275 | /* Somethings want wront with the accel init stop accel */ |
275 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
276 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
276 | // rv515_suspend(rdev); |
277 | // rv515_suspend(rdev); |
277 | // r100_cp_fini(rdev); |
278 | // r100_cp_fini(rdev); |
278 | // r100_wb_fini(rdev); |
279 | // r100_wb_fini(rdev); |
279 | // r100_ib_fini(rdev); |
280 | // r100_ib_fini(rdev); |
280 | rv370_pcie_gart_fini(rdev); |
281 | rv370_pcie_gart_fini(rdev); |
281 | // radeon_agp_fini(rdev); |
282 | // radeon_agp_fini(rdev); |
282 | // radeon_irq_kms_fini(rdev); |
283 | // radeon_irq_kms_fini(rdev); |
283 | rdev->accel_working = false; |
284 | rdev->accel_working = false; |
284 | } |
285 | } |
285 | 286 | ||
286 | LEAVE(); |
287 | LEAVE(); |
287 | 288 | ||
288 | return 0; |
289 | return 0; |
289 | }><>><>> |
290 | }><>><>> |