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1 | /* |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
14 | * all copies or substantial portions of the Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: Dave Airlie |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
25 | * Alex Deucher |
26 | * Jerome Glisse |
26 | * Jerome Glisse |
27 | */ |
27 | */ |
28 | #include |
28 | #include |
29 | #include "drmP.h" |
29 | #include "drmP.h" |
30 | #include "radeon_reg.h" |
30 | #include "radeon_reg.h" |
31 | #include "radeon.h" |
31 | #include "radeon.h" |
32 | #include "atom.h" |
32 | #include "atom.h" |
33 | #include "r100d.h" |
33 | #include "r100d.h" |
34 | #include "r420d.h" |
34 | #include "r420d.h" |
35 | #include "r420_reg_safe.h" |
35 | #include "r420_reg_safe.h" |
36 | 36 | ||
37 | static void r420_set_reg_safe(struct radeon_device *rdev) |
37 | static void r420_set_reg_safe(struct radeon_device *rdev) |
38 | { |
38 | { |
39 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
39 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
40 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
40 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); |
41 | } |
41 | } |
42 | 42 | ||
43 | int r420_mc_init(struct radeon_device *rdev) |
43 | int r420_mc_init(struct radeon_device *rdev) |
44 | { |
44 | { |
45 | int r; |
45 | int r; |
46 | 46 | ||
47 | /* Setup GPU memory space */ |
47 | /* Setup GPU memory space */ |
48 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
48 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
49 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
49 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
50 | if (rdev->flags & RADEON_IS_AGP) { |
50 | if (rdev->flags & RADEON_IS_AGP) { |
51 | r = radeon_agp_init(rdev); |
51 | r = radeon_agp_init(rdev); |
52 | if (r) { |
52 | if (r) { |
53 | radeon_agp_disable(rdev); |
53 | radeon_agp_disable(rdev); |
54 | } else { |
54 | } else { |
55 | rdev->mc.gtt_location = rdev->mc.agp_base; |
55 | rdev->mc.gtt_location = rdev->mc.agp_base; |
56 | } |
56 | } |
57 | } |
57 | } |
58 | r = radeon_mc_setup(rdev); |
58 | r = radeon_mc_setup(rdev); |
59 | if (r) { |
59 | if (r) { |
60 | return r; |
60 | return r; |
61 | } |
61 | } |
62 | return 0; |
62 | return 0; |
63 | } |
63 | } |
64 | 64 | ||
65 | void r420_pipes_init(struct radeon_device *rdev) |
65 | void r420_pipes_init(struct radeon_device *rdev) |
66 | { |
66 | { |
67 | unsigned tmp; |
67 | unsigned tmp; |
68 | unsigned gb_pipe_select; |
68 | unsigned gb_pipe_select; |
69 | unsigned num_pipes; |
69 | unsigned num_pipes; |
70 | 70 | ||
71 | /* GA_ENHANCE workaround TCL deadlock issue */ |
71 | /* GA_ENHANCE workaround TCL deadlock issue */ |
72 | WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); |
72 | WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)); |
73 | /* add idle wait as per freedesktop.org bug 24041 */ |
73 | /* add idle wait as per freedesktop.org bug 24041 */ |
74 | if (r100_gui_wait_for_idle(rdev)) { |
74 | if (r100_gui_wait_for_idle(rdev)) { |
75 | printk(KERN_WARNING "Failed to wait GUI idle while " |
75 | printk(KERN_WARNING "Failed to wait GUI idle while " |
76 | "programming pipes. Bad things might happen.\n"); |
76 | "programming pipes. Bad things might happen.\n"); |
77 | } |
77 | } |
78 | /* get max number of pipes */ |
78 | /* get max number of pipes */ |
79 | gb_pipe_select = RREG32(0x402C); |
79 | gb_pipe_select = RREG32(0x402C); |
80 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
80 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
81 | rdev->num_gb_pipes = num_pipes; |
81 | rdev->num_gb_pipes = num_pipes; |
82 | tmp = 0; |
82 | tmp = 0; |
83 | switch (num_pipes) { |
83 | switch (num_pipes) { |
84 | default: |
84 | default: |
85 | /* force to 1 pipe */ |
85 | /* force to 1 pipe */ |
86 | num_pipes = 1; |
86 | num_pipes = 1; |
87 | case 1: |
87 | case 1: |
88 | tmp = (0 << 1); |
88 | tmp = (0 << 1); |
89 | break; |
89 | break; |
90 | case 2: |
90 | case 2: |
91 | tmp = (3 << 1); |
91 | tmp = (3 << 1); |
92 | break; |
92 | break; |
93 | case 3: |
93 | case 3: |
94 | tmp = (6 << 1); |
94 | tmp = (6 << 1); |
95 | break; |
95 | break; |
96 | case 4: |
96 | case 4: |
97 | tmp = (7 << 1); |
97 | tmp = (7 << 1); |
98 | break; |
98 | break; |
99 | } |
99 | } |
100 | WREG32(0x42C8, (1 << num_pipes) - 1); |
100 | WREG32(0x42C8, (1 << num_pipes) - 1); |
101 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
101 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
102 | tmp |= (1 << 4) | (1 << 0); |
102 | tmp |= (1 << 4) | (1 << 0); |
103 | WREG32(0x4018, tmp); |
103 | WREG32(0x4018, tmp); |
104 | if (r100_gui_wait_for_idle(rdev)) { |
104 | if (r100_gui_wait_for_idle(rdev)) { |
105 | printk(KERN_WARNING "Failed to wait GUI idle while " |
105 | printk(KERN_WARNING "Failed to wait GUI idle while " |
106 | "programming pipes. Bad things might happen.\n"); |
106 | "programming pipes. Bad things might happen.\n"); |
107 | } |
107 | } |
108 | 108 | ||
109 | tmp = RREG32(0x170C); |
109 | tmp = RREG32(0x170C); |
110 | WREG32(0x170C, tmp | (1 << 31)); |
110 | WREG32(0x170C, tmp | (1 << 31)); |
111 | 111 | ||
112 | WREG32(R300_RB2D_DSTCACHE_MODE, |
112 | WREG32(R300_RB2D_DSTCACHE_MODE, |
113 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
113 | RREG32(R300_RB2D_DSTCACHE_MODE) | |
114 | R300_DC_AUTOFLUSH_ENABLE | |
114 | R300_DC_AUTOFLUSH_ENABLE | |
115 | R300_DC_DC_DISABLE_IGNORE_PE); |
115 | R300_DC_DC_DISABLE_IGNORE_PE); |
116 | 116 | ||
117 | if (r100_gui_wait_for_idle(rdev)) { |
117 | if (r100_gui_wait_for_idle(rdev)) { |
118 | printk(KERN_WARNING "Failed to wait GUI idle while " |
118 | printk(KERN_WARNING "Failed to wait GUI idle while " |
119 | "programming pipes. Bad things might happen.\n"); |
119 | "programming pipes. Bad things might happen.\n"); |
120 | } |
120 | } |
121 | 121 | ||
122 | if (rdev->family == CHIP_RV530) { |
122 | if (rdev->family == CHIP_RV530) { |
123 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
123 | tmp = RREG32(RV530_GB_PIPE_SELECT2); |
124 | if ((tmp & 3) == 3) |
124 | if ((tmp & 3) == 3) |
125 | rdev->num_z_pipes = 2; |
125 | rdev->num_z_pipes = 2; |
126 | else |
126 | else |
127 | rdev->num_z_pipes = 1; |
127 | rdev->num_z_pipes = 1; |
128 | } else |
128 | } else |
129 | rdev->num_z_pipes = 1; |
129 | rdev->num_z_pipes = 1; |
130 | 130 | ||
131 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
131 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", |
132 | rdev->num_gb_pipes, rdev->num_z_pipes); |
132 | rdev->num_gb_pipes, rdev->num_z_pipes); |
133 | } |
133 | } |
134 | 134 | ||
135 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
135 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
136 | { |
136 | { |
137 | u32 r; |
137 | u32 r; |
138 | 138 | ||
139 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
139 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); |
140 | r = RREG32(R_0001FC_MC_IND_DATA); |
140 | r = RREG32(R_0001FC_MC_IND_DATA); |
141 | return r; |
141 | return r; |
142 | } |
142 | } |
143 | 143 | ||
144 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
144 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
145 | { |
145 | { |
146 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
146 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | |
147 | S_0001F8_MC_IND_WR_EN(1)); |
147 | S_0001F8_MC_IND_WR_EN(1)); |
148 | WREG32(R_0001FC_MC_IND_DATA, v); |
148 | WREG32(R_0001FC_MC_IND_DATA, v); |
149 | } |
149 | } |
150 | 150 | ||
151 | static void r420_debugfs(struct radeon_device *rdev) |
151 | static void r420_debugfs(struct radeon_device *rdev) |
152 | { |
152 | { |
153 | if (r100_debugfs_rbbm_init(rdev)) { |
153 | if (r100_debugfs_rbbm_init(rdev)) { |
154 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
154 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
155 | } |
155 | } |
156 | if (r420_debugfs_pipes_info_init(rdev)) { |
156 | if (r420_debugfs_pipes_info_init(rdev)) { |
157 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
157 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
158 | } |
158 | } |
159 | } |
159 | } |
160 | 160 | ||
161 | static void r420_clock_resume(struct radeon_device *rdev) |
161 | static void r420_clock_resume(struct radeon_device *rdev) |
162 | { |
162 | { |
163 | u32 sclk_cntl; |
163 | u32 sclk_cntl; |
164 | 164 | ||
165 | if (radeon_dynclks != -1 && radeon_dynclks) |
165 | if (radeon_dynclks != -1 && radeon_dynclks) |
166 | radeon_atom_set_clock_gating(rdev, 1); |
166 | radeon_atom_set_clock_gating(rdev, 1); |
167 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
167 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
168 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
168 | sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
169 | if (rdev->family == CHIP_R420) |
169 | if (rdev->family == CHIP_R420) |
170 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
170 | sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); |
171 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
171 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); |
172 | } |
172 | } |
173 | 173 | ||
174 | static void r420_cp_errata_init(struct radeon_device *rdev) |
174 | static void r420_cp_errata_init(struct radeon_device *rdev) |
175 | { |
175 | { |
176 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
176 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
177 | * while the 2D engine is busy. |
177 | * while the 2D engine is busy. |
178 | * |
178 | * |
179 | * The proper workaround is to queue a RESYNC at the beginning |
179 | * The proper workaround is to queue a RESYNC at the beginning |
180 | * of the CP init, apparently. |
180 | * of the CP init, apparently. |
181 | */ |
181 | */ |
182 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
182 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
183 | radeon_ring_lock(rdev, 8); |
183 | radeon_ring_lock(rdev, 8); |
184 | radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
184 | radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1)); |
185 | radeon_ring_write(rdev, rdev->config.r300.resync_scratch); |
185 | radeon_ring_write(rdev, rdev->config.r300.resync_scratch); |
186 | radeon_ring_write(rdev, 0xDEADBEEF); |
186 | radeon_ring_write(rdev, 0xDEADBEEF); |
187 | radeon_ring_unlock_commit(rdev); |
187 | radeon_ring_unlock_commit(rdev); |
188 | } |
188 | } |
189 | 189 | ||
190 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
190 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
191 | { |
191 | { |
192 | /* Catch the RESYNC we dispatched all the way back, |
192 | /* Catch the RESYNC we dispatched all the way back, |
193 | * at the very beginning of the CP init. |
193 | * at the very beginning of the CP init. |
194 | */ |
194 | */ |
195 | radeon_ring_lock(rdev, 8); |
195 | radeon_ring_lock(rdev, 8); |
196 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
196 | radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
197 | radeon_ring_write(rdev, R300_RB3D_DC_FINISH); |
197 | radeon_ring_write(rdev, R300_RB3D_DC_FINISH); |
198 | radeon_ring_unlock_commit(rdev); |
198 | radeon_ring_unlock_commit(rdev); |
199 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
199 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
200 | } |
200 | } |
201 | 201 | ||
202 | static int r420_startup(struct radeon_device *rdev) |
202 | static int r420_startup(struct radeon_device *rdev) |
203 | { |
203 | { |
204 | int r; |
204 | int r; |
205 | 205 | ||
206 | /* set common regs */ |
206 | /* set common regs */ |
207 | r100_set_common_regs(rdev); |
207 | r100_set_common_regs(rdev); |
208 | /* program mc */ |
208 | /* program mc */ |
209 | r300_mc_program(rdev); |
209 | r300_mc_program(rdev); |
210 | /* Resume clock */ |
210 | /* Resume clock */ |
211 | r420_clock_resume(rdev); |
211 | r420_clock_resume(rdev); |
212 | /* Initialize GART (initialize after TTM so we can allocate |
212 | /* Initialize GART (initialize after TTM so we can allocate |
213 | * memory through TTM but finalize after TTM) */ |
213 | * memory through TTM but finalize after TTM) */ |
214 | if (rdev->flags & RADEON_IS_PCIE) { |
214 | if (rdev->flags & RADEON_IS_PCIE) { |
215 | r = rv370_pcie_gart_enable(rdev); |
215 | r = rv370_pcie_gart_enable(rdev); |
216 | if (r) |
216 | if (r) |
217 | return r; |
217 | return r; |
218 | } |
218 | } |
219 | if (rdev->flags & RADEON_IS_PCI) { |
219 | if (rdev->flags & RADEON_IS_PCI) { |
220 | r = r100_pci_gart_enable(rdev); |
220 | r = r100_pci_gart_enable(rdev); |
221 | if (r) |
221 | if (r) |
222 | return r; |
222 | return r; |
223 | } |
223 | } |
224 | r420_pipes_init(rdev); |
224 | r420_pipes_init(rdev); |
225 | /* Enable IRQ */ |
225 | /* Enable IRQ */ |
226 | // r100_irq_set(rdev); |
226 | // r100_irq_set(rdev); |
227 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
227 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
228 | /* 1M ring buffer */ |
228 | /* 1M ring buffer */ |
229 | r = r100_cp_init(rdev, 1024 * 1024); |
229 | r = r100_cp_init(rdev, 1024 * 1024); |
230 | if (r) { |
230 | if (r) { |
231 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
231 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
232 | return r; |
232 | return r; |
233 | } |
233 | } |
234 | r420_cp_errata_init(rdev); |
234 | r420_cp_errata_init(rdev); |
235 | // r = r100_wb_init(rdev); |
235 | // r = r100_wb_init(rdev); |
236 | // if (r) { |
236 | // if (r) { |
237 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
237 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
238 | // } |
238 | // } |
239 | // r = r100_ib_init(rdev); |
239 | // r = r100_ib_init(rdev); |
240 | // if (r) { |
240 | // if (r) { |
241 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
241 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
242 | // return r; |
242 | // return r; |
243 | // } |
243 | // } |
244 | return 0; |
244 | return 0; |
245 | } |
245 | } |
246 | 246 | ||
247 | int r420_resume(struct radeon_device *rdev) |
247 | int r420_resume(struct radeon_device *rdev) |
248 | { |
248 | { |
249 | /* Make sur GART are not working */ |
249 | /* Make sur GART are not working */ |
250 | if (rdev->flags & RADEON_IS_PCIE) |
250 | if (rdev->flags & RADEON_IS_PCIE) |
251 | rv370_pcie_gart_disable(rdev); |
251 | rv370_pcie_gart_disable(rdev); |
252 | if (rdev->flags & RADEON_IS_PCI) |
252 | if (rdev->flags & RADEON_IS_PCI) |
253 | r100_pci_gart_disable(rdev); |
253 | r100_pci_gart_disable(rdev); |
254 | /* Resume clock before doing reset */ |
254 | /* Resume clock before doing reset */ |
255 | r420_clock_resume(rdev); |
255 | r420_clock_resume(rdev); |
256 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
256 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
257 | if (radeon_gpu_reset(rdev)) { |
257 | if (radeon_gpu_reset(rdev)) { |
258 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
258 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
259 | RREG32(R_000E40_RBBM_STATUS), |
259 | RREG32(R_000E40_RBBM_STATUS), |
260 | RREG32(R_0007C0_CP_STAT)); |
260 | RREG32(R_0007C0_CP_STAT)); |
261 | } |
261 | } |
262 | /* check if cards are posted or not */ |
262 | /* check if cards are posted or not */ |
263 | if (rdev->is_atom_bios) { |
263 | if (rdev->is_atom_bios) { |
264 | atom_asic_init(rdev->mode_info.atom_context); |
264 | atom_asic_init(rdev->mode_info.atom_context); |
265 | } else { |
265 | } else { |
266 | radeon_combios_asic_init(rdev->ddev); |
266 | radeon_combios_asic_init(rdev->ddev); |
267 | } |
267 | } |
268 | /* Resume clock after posting */ |
268 | /* Resume clock after posting */ |
269 | r420_clock_resume(rdev); |
269 | r420_clock_resume(rdev); |
270 | /* Initialize surface registers */ |
270 | /* Initialize surface registers */ |
271 | radeon_surface_init(rdev); |
271 | radeon_surface_init(rdev); |
272 | return r420_startup(rdev); |
272 | return r420_startup(rdev); |
273 | } |
273 | } |
274 | 274 | ||
275 | 275 | ||
276 | 276 | ||
277 | int r420_init(struct radeon_device *rdev) |
277 | int r420_init(struct radeon_device *rdev) |
278 | { |
278 | { |
279 | int r; |
279 | int r; |
280 | 280 | ||
281 | /* Initialize scratch registers */ |
281 | /* Initialize scratch registers */ |
282 | radeon_scratch_init(rdev); |
282 | radeon_scratch_init(rdev); |
283 | /* Initialize surface registers */ |
283 | /* Initialize surface registers */ |
284 | radeon_surface_init(rdev); |
284 | radeon_surface_init(rdev); |
285 | /* TODO: disable VGA need to use VGA request */ |
285 | /* TODO: disable VGA need to use VGA request */ |
286 | /* BIOS*/ |
286 | /* BIOS*/ |
287 | if (!radeon_get_bios(rdev)) { |
287 | if (!radeon_get_bios(rdev)) { |
288 | if (ASIC_IS_AVIVO(rdev)) |
288 | if (ASIC_IS_AVIVO(rdev)) |
289 | return -EINVAL; |
289 | return -EINVAL; |
290 | } |
290 | } |
291 | if (rdev->is_atom_bios) { |
291 | if (rdev->is_atom_bios) { |
292 | r = radeon_atombios_init(rdev); |
292 | r = radeon_atombios_init(rdev); |
293 | if (r) { |
293 | if (r) { |
294 | return r; |
294 | return r; |
295 | } |
295 | } |
296 | } else { |
296 | } else { |
297 | r = radeon_combios_init(rdev); |
297 | r = radeon_combios_init(rdev); |
298 | if (r) { |
298 | if (r) { |
299 | return r; |
299 | return r; |
300 | } |
300 | } |
301 | } |
301 | } |
302 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
302 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
303 | if (radeon_gpu_reset(rdev)) { |
303 | if (radeon_gpu_reset(rdev)) { |
304 | dev_warn(rdev->dev, |
304 | dev_warn(rdev->dev, |
305 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
305 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
306 | RREG32(R_000E40_RBBM_STATUS), |
306 | RREG32(R_000E40_RBBM_STATUS), |
307 | RREG32(R_0007C0_CP_STAT)); |
307 | RREG32(R_0007C0_CP_STAT)); |
308 | } |
308 | } |
309 | /* check if cards are posted or not */ |
309 | /* check if cards are posted or not */ |
310 | if (radeon_boot_test_post_card(rdev) == false) |
310 | if (radeon_boot_test_post_card(rdev) == false) |
311 | return -EINVAL; |
311 | return -EINVAL; |
312 | 312 | ||
313 | /* Initialize clocks */ |
313 | /* Initialize clocks */ |
314 | radeon_get_clock_info(rdev->ddev); |
314 | radeon_get_clock_info(rdev->ddev); |
315 | /* Initialize power management */ |
315 | /* Initialize power management */ |
316 | radeon_pm_init(rdev); |
316 | radeon_pm_init(rdev); |
317 | /* Get vram informations */ |
317 | /* Get vram informations */ |
318 | r300_vram_info(rdev); |
318 | r300_vram_info(rdev); |
319 | /* Initialize memory controller (also test AGP) */ |
319 | /* Initialize memory controller (also test AGP) */ |
320 | r = r420_mc_init(rdev); |
320 | r = r420_mc_init(rdev); |
321 | if (r) { |
321 | if (r) { |
322 | return r; |
322 | return r; |
323 | } |
323 | } |
324 | r420_debugfs(rdev); |
324 | r420_debugfs(rdev); |
325 | /* Fence driver */ |
325 | /* Fence driver */ |
326 | // r = radeon_fence_driver_init(rdev); |
326 | // r = radeon_fence_driver_init(rdev); |
327 | // if (r) { |
327 | // if (r) { |
328 | // return r; |
328 | // return r; |
329 | // } |
329 | // } |
330 | // r = radeon_irq_kms_init(rdev); |
330 | // r = radeon_irq_kms_init(rdev); |
331 | // if (r) { |
331 | // if (r) { |
332 | // return r; |
332 | // return r; |
333 | // } |
333 | // } |
334 | /* Memory manager */ |
334 | /* Memory manager */ |
335 | r = radeon_bo_init(rdev); |
335 | r = radeon_bo_init(rdev); |
336 | if (r) { |
336 | if (r) { |
337 | return r; |
337 | return r; |
338 | } |
338 | } |
339 | if (rdev->family == CHIP_R420) |
339 | if (rdev->family == CHIP_R420) |
340 | r100_enable_bm(rdev); |
340 | r100_enable_bm(rdev); |
341 | 341 | ||
342 | if (rdev->flags & RADEON_IS_PCIE) { |
342 | if (rdev->flags & RADEON_IS_PCIE) { |
343 | r = rv370_pcie_gart_init(rdev); |
343 | r = rv370_pcie_gart_init(rdev); |
344 | if (r) |
344 | if (r) |
345 | return r; |
345 | return r; |
346 | } |
346 | } |
347 | if (rdev->flags & RADEON_IS_PCI) { |
347 | if (rdev->flags & RADEON_IS_PCI) { |
348 | r = r100_pci_gart_init(rdev); |
348 | r = r100_pci_gart_init(rdev); |
349 | if (r) |
349 | if (r) |
350 | return r; |
350 | return r; |
351 | } |
351 | } |
352 | r420_set_reg_safe(rdev); |
352 | r420_set_reg_safe(rdev); |
353 | rdev->accel_working = true; |
353 | rdev->accel_working = true; |
354 | r = r420_startup(rdev); |
354 | r = r420_startup(rdev); |
355 | if (r) { |
355 | if (r) { |
356 | /* Somethings want wront with the accel init stop accel */ |
356 | /* Somethings want wront with the accel init stop accel */ |
357 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
357 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
358 | // r420_suspend(rdev); |
- | |
359 | // r100_cp_fini(rdev); |
358 | // r100_cp_fini(rdev); |
360 | // r100_wb_fini(rdev); |
359 | // r100_wb_fini(rdev); |
361 | // r100_ib_fini(rdev); |
360 | // r100_ib_fini(rdev); |
362 | if (rdev->flags & RADEON_IS_PCIE) |
361 | if (rdev->flags & RADEON_IS_PCIE) |
363 | rv370_pcie_gart_fini(rdev); |
362 | rv370_pcie_gart_fini(rdev); |
364 | if (rdev->flags & RADEON_IS_PCI) |
363 | if (rdev->flags & RADEON_IS_PCI) |
365 | r100_pci_gart_fini(rdev); |
364 | r100_pci_gart_fini(rdev); |
366 | // radeon_agp_fini(rdev); |
365 | // radeon_agp_fini(rdev); |
367 | rdev->accel_working = false; |
366 | rdev->accel_working = false; |
368 | } |
367 | } |
369 | return 0; |
368 | return 0; |
370 | } |
369 | } |
371 | 370 | ||
372 | /* |
371 | /* |
373 | * Debugfs info |
372 | * Debugfs info |
374 | */ |
373 | */ |
375 | #if defined(CONFIG_DEBUG_FS) |
374 | #if defined(CONFIG_DEBUG_FS) |
376 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
375 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
377 | { |
376 | { |
378 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
377 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
379 | struct drm_device *dev = node->minor->dev; |
378 | struct drm_device *dev = node->minor->dev; |
380 | struct radeon_device *rdev = dev->dev_private; |
379 | struct radeon_device *rdev = dev->dev_private; |
381 | uint32_t tmp; |
380 | uint32_t tmp; |
382 | 381 | ||
383 | tmp = RREG32(R400_GB_PIPE_SELECT); |
382 | tmp = RREG32(R400_GB_PIPE_SELECT); |
384 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
383 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
385 | tmp = RREG32(R300_GB_TILE_CONFIG); |
384 | tmp = RREG32(R300_GB_TILE_CONFIG); |
386 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
385 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
387 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
386 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
388 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
387 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
389 | return 0; |
388 | return 0; |
390 | } |
389 | } |
391 | 390 | ||
392 | static struct drm_info_list r420_pipes_info_list[] = { |
391 | static struct drm_info_list r420_pipes_info_list[] = { |
393 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
392 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, |
394 | }; |
393 | }; |
395 | #endif |
394 | #endif |
396 | 395 | ||
397 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
396 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
398 | { |
397 | { |
399 | #if defined(CONFIG_DEBUG_FS) |
398 | #if defined(CONFIG_DEBUG_FS) |
400 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
399 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
401 | #else |
400 | #else |
402 | return 0; |
401 | return 0; |
403 | #endif |
402 | #endif |
404 | }><>><>><>><>><>><>><>><>><>><>><>><> |
403 | }><>><>><>><>><>><>><>><>><>><>><>><> |