WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/pci.c


#include 
#include 
#include 
 
static LIST_HEAD(devices);
 
static dev_t* pci_scan_device(u32_t bus, int devfn);
 
 
/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
#define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
 
#define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
/*
 * Translate the low bits of the PCI base
 * to the resource type
 */
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
    if (flags & PCI_BASE_ADDRESS_SPACE_IO)
        return IORESOURCE_IO;
 
    if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
        return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 
    return IORESOURCE_MEM;
}
 
 
static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
{
    u32_t size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
{
    u64_t size = mask & maxbase;      /* Find the significant bits */
 
    if (!size)
        return 0;
 
    /* Get the lowest of them to find the decode size, and
       from that the extent.  */
    size = (size & ~(size-1)) - 1;
 
    /* base == maxbase can be valid only if the BAR has
       already been programmed with all 1s.  */
    if (base == maxbase && ((base | size) & mask) != mask)
        return 0;
 
    return size;
}
 
static inline int is_64bit_memory(u32_t mask)
{
    if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
        (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
        return 1;
    return 0;
}
 
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    u32_t  pos, reg, next;
    u32_t  l, sz;
    struct resource *res;
 
    for(pos=0; pos < howmany; pos = next)
    {
        u64_t  l64;
        u64_t  sz64;
        u32_t  raw_sz;
 
        next = pos + 1;
 
        res  = &dev->resource[pos];
 
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        l = PciRead32(dev->bus, dev->devfn, reg);
        PciWrite32(dev->bus, dev->devfn, reg, ~0);
        sz = PciRead32(dev->bus, dev->devfn, reg);
        PciWrite32(dev->bus, dev->devfn, reg, l);
 
        if (!sz || sz == 0xffffffff)
            continue;
 
        if (l == 0xffffffff)
            l = 0;
 
        raw_sz = sz;
        if ((l & PCI_BASE_ADDRESS_SPACE) ==
                        PCI_BASE_ADDRESS_SPACE_MEMORY)
        {
            sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
            /*
             * For 64bit prefetchable memory sz could be 0, if the
             * real size is bigger than 4G, so we need to check
             * szhi for that.
             */
            if (!is_64bit_memory(l) && !sz)
                    continue;
            res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
        }
        else {
            sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
            if (!sz)
                continue;
            res->start = l & PCI_BASE_ADDRESS_IO_MASK;
            res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
        }
        res->end = res->start + (unsigned long) sz;
        res->flags |= pci_calc_resource_flags(l);
        if (is_64bit_memory(l))
        {
            u32_t szhi, lhi;
 
            lhi = PciRead32(dev->bus, dev->devfn, reg+4);
            PciWrite32(dev->bus, dev->devfn, reg+4, ~0);
            szhi = PciRead32(dev->bus, dev->devfn, reg+4);
            PciWrite32(dev->bus, dev->devfn, reg+4, lhi);
            sz64 = ((u64_t)szhi << 32) | raw_sz;
            l64 = ((u64_t)lhi << 32) | l;
            sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
            next++;
 
#if BITS_PER_LONG == 64
            if (!sz64) {
                res->start = 0;
                res->end = 0;
                res->flags = 0;
                continue;
            }
            res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
            res->end = res->start + sz64;
#else
            if (sz64 > 0x100000000ULL) {
                printk(KERN_ERR "PCI: Unable to handle 64-bit "
                                "BAR for device %s\n", pci_name(dev));
                res->start = 0;
                res->flags = 0;
            }
            else if (lhi)
            {
                /* 64-bit wide address, treat as disabled */
                PciWrite32(dev->bus, dev->devfn, reg,
                        l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
                PciWrite32(dev->bus, dev->devfn, reg+4, 0);
                res->start = 0;
                res->end = sz;
            }
#endif
        }
    }
 
    if ( rom )
    {
        dev->rom_base_reg = rom;
        res = &dev->resource[PCI_ROM_RESOURCE];
 
        l = PciRead32(dev->bus, dev->devfn, rom);
        PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
        sz = PciRead32(dev->bus, dev->devfn, rom);
        PciWrite32(dev->bus, dev->devfn, rom, l);
 
        if (l == 0xffffffff)
            l = 0;
 
        if (sz && sz != 0xffffffff)
        {
            sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
 
            if (sz)
            {
                res->flags = (l & IORESOURCE_ROM_ENABLE) |
                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
                res->start = l & PCI_ROM_ADDRESS_MASK;
                res->end = res->start + (unsigned long) sz;
            }
        }
    }
}
 
static void pci_read_irq(struct pci_dev *dev)
{
    u8_t irq;
 
    irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);
    dev->pin = irq;
    if (irq)
        PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);
    dev->irq = irq;
};
 
 
static int pci_setup_device(struct pci_dev *dev)
{
    u32_t  class;
 
    class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);
    dev->revision = class & 0xff;
    class >>= 8;                                /* upper 3 bytes */
    dev->class = class;
 
    /* "Unknown power state" */
//    dev->current_state = PCI_UNKNOWN;
 
    /* Early fixups, before probing the BARs */
 //   pci_fixup_device(pci_fixup_early, dev);
    class = dev->class >> 8;
 
    switch (dev->hdr_type)
    {
        case PCI_HEADER_TYPE_NORMAL:                /* standard header */
            if (class == PCI_CLASS_BRIDGE_PCI)
                goto bad;
            pci_read_irq(dev);
            pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
            dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
            dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);
 
            /*
             *      Do the ugly legacy mode stuff here rather than broken chip
             *      quirk code. Legacy mode ATA controllers have fixed
             *      addresses. These are not always echoed in BAR0-3, and
             *      BAR0-3 in a few cases contain junk!
             */
            if (class == PCI_CLASS_STORAGE_IDE)
            {
                u8_t progif;
 
                progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);
                if ((progif & 1) == 0)
                {
                    dev->resource[0].start = 0x1F0;
                    dev->resource[0].end = 0x1F7;
                    dev->resource[0].flags = LEGACY_IO_RESOURCE;
                    dev->resource[1].start = 0x3F6;
                    dev->resource[1].end = 0x3F6;
                    dev->resource[1].flags = LEGACY_IO_RESOURCE;
                }
                if ((progif & 4) == 0)
                {
                    dev->resource[2].start = 0x170;
                    dev->resource[2].end = 0x177;
                    dev->resource[2].flags = LEGACY_IO_RESOURCE;
                    dev->resource[3].start = 0x376;
                    dev->resource[3].end = 0x376;
                    dev->resource[3].flags = LEGACY_IO_RESOURCE;
                };
            }
            break;
 
        case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                if (class != PCI_CLASS_BRIDGE_PCI)
                        goto bad;
                /* The PCI-to-PCI bridge spec requires that subtractive
                   decoding (i.e. transparent) bridge must have programming
                   interface code of 0x01. */
                pci_read_irq(dev);
                dev->transparent = ((dev->class & 0xff) == 1);
                pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
                break;
 
        case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
                if (class != PCI_CLASS_BRIDGE_CARDBUS)
                        goto bad;
                pci_read_irq(dev);
                pci_read_bases(dev, 1, 0);
                dev->subsystem_vendor = PciRead16(dev->bus,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_VENDOR_ID);
 
                dev->subsystem_device = PciRead16(dev->bus,
                                                  dev->devfn,
                                                  PCI_CB_SUBSYSTEM_ID);
                break;
 
        default:                                    /* unknown header */
                printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
                        pci_name(dev), dev->hdr_type);
                return -1;
 
        bad:
                printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
                       pci_name(dev), class, dev->hdr_type);
                dev->class = PCI_CLASS_NOT_DEFINED;
    }
 
    /* We found a fine healthy device, go go go... */
 
    return 0;
};
 
static dev_t* pci_scan_device(u32_t bus, int devfn)
{
    dev_t  *dev;
 
    u32_t   id;
    u8_t    hdr;
 
    int     timeout = 10;
 
    id = PciRead32(bus,devfn, PCI_VENDOR_ID);
 
    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (id == 0xffffffff || id == 0x00000000 ||
        id == 0x0000ffff || id == 0xffff0000)
        return NULL;
 
    while (id == 0xffff0001)
    {
 
        delay(timeout/10);
        timeout *= 2;
 
        id = PciRead32(bus, devfn, PCI_VENDOR_ID);
 
        /* Card hasn't responded in 60 seconds?  Must be stuck. */
        if (timeout > 60 * 100)
        {
            printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
                   "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn));
            return NULL;
        }
    };
 
    hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE);
 
    dev = (dev_t*)malloc(sizeof(dev_t));
 
    INIT_LIST_HEAD(&dev->link);
 
    if(unlikely(dev == NULL))
        return NULL;
 
    dev->pci_dev.bus      = bus;
    dev->pci_dev.devfn    = devfn;
    dev->pci_dev.hdr_type = hdr & 0x7f;
    dev->pci_dev.multifunction    = !!(hdr & 0x80);
    dev->pci_dev.vendor   = id & 0xffff;
    dev->pci_dev.device   = (id >> 16) & 0xffff;
 
    pci_setup_device(&dev->pci_dev);
 
    return dev;
 
};
 
int pci_scan_slot(u32_t bus, int devfn)
{
    int  func, nr = 0;
 
    for (func = 0; func < 8; func++, devfn++)
    {
        dev_t  *dev;
 
        dev = pci_scan_device(bus, devfn);
        if( dev )
        {
            list_add(&dev->link, &devices);
 
            nr++;
 
            /*
             * If this is a single function device,
             * don't scan past the first function.
             */
            if (!dev->pci_dev.multifunction)
            {
                if (func > 0) {
                    dev->pci_dev.multifunction = 1;
                }
                else {
                    break;
                }
             }
        }
        else {
            if (func == 0)
                break;
        }
    };
 
    return nr;
};
 
 
void pci_scan_bus(u32_t bus)
{
    u32_t devfn;
    dev_t *dev;
 
 
    for (devfn = 0; devfn < 0x100; devfn += 8)
        pci_scan_slot(bus, devfn);
 
}
 
int enum_pci_devices()
{
    dev_t  *dev;
    u32_t   last_bus;
    u32_t   bus = 0 , devfn = 0;
 
  //  list_initialize(&devices);
 
    last_bus = PciApi(1);
 
 
    if( unlikely(last_bus == -1))
        return -1;
 
    for(;bus <= last_bus; bus++)
        pci_scan_bus(bus);
 
//    for(dev = (dev_t*)devices.next;
//        &dev->link != &devices;
//        dev = (dev_t*)dev->link.next)
//    {
//        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
//                dev->pci_dev.vendor,
//                dev->pci_dev.device,
//                dev->pci_dev.bus,
//                dev->pci_dev.devfn);
//
//    }
    return 0;
}
 
#if 0
/**
 * pci_set_power_state - Set the power state of a PCI device
 * @dev: PCI device to be suspended
 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
 *
 * Transition a device to a new power state, using the Power Management
 * Capabilities in the device's config space.
 *
 * RETURN VALUE:
 * -EINVAL if trying to enter a lower state than we're already in.
 * 0 if we're already in the requested state.
 * -EIO if device does not support PCI PM.
 * 0 if we can successfully change the power state.
 */
int
pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
        int pm, need_restore = 0;
        u16 pmcsr, pmc;
 
        /* bound the state we're entering */
        if (state > PCI_D3hot)
                state = PCI_D3hot;
 
        /*
         * If the device or the parent bridge can't support PCI PM, ignore
         * the request if we're doing anything besides putting it into D0
         * (which would only happen on boot).
         */
        if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
                return 0;
 
        /* find PCI PM capability in list */
        pm = pci_find_capability(dev, PCI_CAP_ID_PM);
 
        /* abort if the device doesn't support PM capabilities */
        if (!pm)
                return -EIO;
 
        /* Validate current state:
         * Can enter D0 from any state, but if we can only go deeper
         * to sleep if we're already in a low power state
         */
        if (state != PCI_D0 && dev->current_state > state) {
                printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
                        __FUNCTION__, pci_name(dev), state, dev->current_state);
                return -EINVAL;
        } else if (dev->current_state == state)
                return 0;        /* we're already there */
 
 
        pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
        if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
                printk(KERN_DEBUG
                       "PCI: %s has unsupported PM cap regs version (%u)\n",
                       pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
                return -EIO;
        }
 
        /* check if this device supports the desired state */
        if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
                return -EIO;
        else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
                return -EIO;
 
        pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
 
        /* If we're (effectively) in D3, force entire word to 0.
         * This doesn't affect PME_Status, disables PME_En, and
         * sets PowerState to 0.
         */
        switch (dev->current_state) {
        case PCI_D0:
        case PCI_D1:
        case PCI_D2:
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                pmcsr |= state;
                break;
        case PCI_UNKNOWN: /* Boot-up */
                if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
                 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
                        need_restore = 1;
                /* Fall-through: force to D0 */
        default:
                pmcsr = 0;
                break;
        }
 
        /* enter specified state */
        pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
 
        /* Mandatory power management transition delays */
        /* see PCI PM 1.1 5.6.1 table 18 */
        if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
                msleep(pci_pm_d3_delay);
        else if (state == PCI_D2 || dev->current_state == PCI_D2)
                udelay(200);
 
        /*
         * Give firmware a chance to be called, such as ACPI _PRx, _PSx
         * Firmware method after native method ?
         */
        if (platform_pci_set_power_state)
                platform_pci_set_power_state(dev, state);
 
        dev->current_state = state;
 
        /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
         * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
         * from D3hot to D0 _may_ perform an internal reset, thereby
         * going to "D0 Uninitialized" rather than "D0 Initialized".
         * For example, at least some versions of the 3c905B and the
         * 3c556B exhibit this behaviour.
         *
         * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
         * devices in a D3hot state at boot.  Consequently, we need to
         * restore at least the BARs so that the device will be
         * accessible to its driver.
         */
        if (need_restore)
                pci_restore_bars(dev);
 
        return 0;
}
#endif
 
int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
    u16_t cmd, old_cmd;
    int  idx;
    struct resource *r;
 
    cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND);
    old_cmd = cmd;
    for (idx = 0; idx < PCI_NUM_RESOURCES; idx++)
    {
        /* Only set up the requested stuff */
        if (!(mask & (1 << idx)))
                continue;
 
        r = &dev->resource[idx];
        if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
                continue;
        if ((idx == PCI_ROM_RESOURCE) &&
                        (!(r->flags & IORESOURCE_ROM_ENABLE)))
                continue;
        if (!r->start && r->end) {
                printk(KERN_ERR "PCI: Device %s not available "
                        "because of resource %d collisions\n",
                        pci_name(dev), idx);
                return -EINVAL;
        }
        if (r->flags & IORESOURCE_IO)
                cmd |= PCI_COMMAND_IO;
        if (r->flags & IORESOURCE_MEM)
                cmd |= PCI_COMMAND_MEMORY;
    }
    if (cmd != old_cmd) {
        printk("PCI: Enabling device %s (%04x -> %04x)\n",
                pci_name(dev), old_cmd, cmd);
        PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd);
    }
    return 0;
}
 
 
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
        int err;
 
        if ((err = pcibios_enable_resources(dev, mask)) < 0)
                return err;
 
//        if (!dev->msi_enabled)
//                return pcibios_enable_irq(dev);
        return 0;
}
 
 
static int do_pci_enable_device(struct pci_dev *dev, int bars)
{
        int err;
 
//        err = pci_set_power_state(dev, PCI_D0);
//        if (err < 0 && err != -EIO)
//                return err;
        err = pcibios_enable_device(dev, bars);
//        if (err < 0)
//                return err;
//        pci_fixup_device(pci_fixup_enable, dev);
 
        return 0;
}
 
 
static int __pci_enable_device_flags(struct pci_dev *dev,
                                     resource_size_t flags)
{
        int err;
        int i, bars = 0;
 
//        if (atomic_add_return(1, &dev->enable_cnt) > 1)
//                return 0;               /* already enabled */
 
        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
                if (dev->resource[i].flags & flags)
                        bars |= (1 << i);
 
        err = do_pci_enable_device(dev, bars);
//        if (err < 0)
//                atomic_dec(&dev->enable_cnt);
        return err;
}
 
 
/**
 * pci_enable_device - Initialize device before it's used by a driver.
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O and memory. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 *
 *  Note we don't actually enable the device many times if we call
 *  this function repeatedly (we just increment the count).
 */
int pci_enable_device(struct pci_dev *dev)
{
        return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
}
 
 
 
struct pci_device_id* find_pci_device(dev_t* pdev, struct pci_device_id *idlist)
{
    dev_t *dev;
    struct pci_device_id *ent;
 
    for(dev = (dev_t*)devices.next;
        &dev->link != &devices;
        dev = (dev_t*)dev->link.next)
    {
        if( dev->pci_dev.vendor != idlist->vendor )
            continue;
 
        for(ent = idlist; ent->vendor != 0; ent++)
        {
            if(unlikely(ent->device == dev->pci_dev.device))
            {
                pdev->pci_dev = dev->pci_dev;
                return  ent;
            }
        };
    }
 
    return NULL;
};
 
 
 
/**
 * pci_map_rom - map a PCI ROM to kernel space
 * @pdev: pointer to pci device struct
 * @size: pointer to receive size of pci window over ROM
 * @return: kernel virtual pointer to image of ROM
 *
 * Map a PCI ROM into kernel space. If ROM is boot video ROM,
 * the shadow BIOS copy will be returned instead of the
 * actual ROM.
 */
 
#define legacyBIOSLocation 0xC0000
#define OS_BASE   0x80000000
 
void *pci_map_rom(struct pci_dev *pdev, size_t *size)
{
    struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
    u32_t start;
    void  *rom;
 
#if 0
    /*
     * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
     * memory map if the VGA enable bit of the Bridge Control register is
     * set for embedded VGA.
     */
    if (res->flags & IORESOURCE_ROM_SHADOW) {
        /* primary video rom always starts here */
        start = (u32_t)0xC0000;
        *size = 0x20000; /* cover C000:0 through E000:0 */
    } else {
        if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
            *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             return (void *)(unsigned long)
                     pci_resource_start(pdev, PCI_ROM_RESOURCE);
        } else {
                /* assign the ROM an address if it doesn't have one */
            //if (res->parent == NULL &&
            //     pci_assign_resource(pdev,PCI_ROM_RESOURCE))
            //         return NULL;
             start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
             *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
             if (*size == 0)
                     return NULL;
 
             /* Enable ROM space decodes */
             if (pci_enable_rom(pdev))
                     return NULL;
        }
    }
 
    rom = ioremap(start, *size);
    if (!rom) {
            /* restore enable if ioremap fails */
            if (!(res->flags & (IORESOURCE_ROM_ENABLE |
                                IORESOURCE_ROM_SHADOW |
                                IORESOURCE_ROM_COPY)))
                    pci_disable_rom(pdev);
            return NULL;
    }
 
    /*
     * Try to find the true size of the ROM since sometimes the PCI window
     * size is much larger than the actual size of the ROM.
     * True size is important if the ROM is going to be copied.
     */
    *size = pci_get_rom_size(rom, *size);
 
#endif
 
    unsigned char tmp[32];
    rom = NULL;
 
    dbgprintf("Getting BIOS copy from legacy VBIOS location\n");
    memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32);
    *size = tmp[2] * 512;
    if (*size > 0x10000 )
    {
        *size = 0;
        dbgprintf("Invalid BIOS length field\n");
    }
    else
        rom = (void*)( OS_BASE+legacyBIOSLocation);
 
    return rom;
}
 
 
int
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
{
//        if (!pci_dma_supported(dev, mask))
//                return -EIO;
 
        dev->dma_mask = mask;
 
        return 0;
}

Rev 1119	Rev 1120
1	#include	1	#include
2	#include	2	#include
3	#include	3	#include
4		4
5	link_t devices;	5	static LIST_HEAD(devices);
6		6
7	static dev_t* pci_scan_device(u32_t bus, int devfn);	7	static dev_t* pci_scan_device(u32_t bus, int devfn);
8		8
9		9
10	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */	10	/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
11	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */	11	#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
12		12
13	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)	13	#define LEGACY_IO_RESOURCE (IORESOURCE_IO \| IORESOURCE_PCI_FIXED)
14		14
15	/*	15	/*
16	* Translate the low bits of the PCI base	16	* Translate the low bits of the PCI base
17	* to the resource type	17	* to the resource type
18	*/	18	*/
19	static inline unsigned int pci_calc_resource_flags(unsigned int flags)	19	static inline unsigned int pci_calc_resource_flags(unsigned int flags)
20	{	20	{
21	if (flags & PCI_BASE_ADDRESS_SPACE_IO)	21	if (flags & PCI_BASE_ADDRESS_SPACE_IO)
22	return IORESOURCE_IO;	22	return IORESOURCE_IO;
23		23
24	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)	24	if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
25	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;	25	return IORESOURCE_MEM \| IORESOURCE_PREFETCH;
26		26
27	return IORESOURCE_MEM;	27	return IORESOURCE_MEM;
28	}	28	}
29		29
30		30
31	static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)	31	static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
32	{	32	{
33	u32_t size = mask & maxbase; /* Find the significant bits */	33	u32_t size = mask & maxbase; /* Find the significant bits */
34		34
35	if (!size)	35	if (!size)
36	return 0;	36	return 0;
37		37
38	/* Get the lowest of them to find the decode size, and	38	/* Get the lowest of them to find the decode size, and
39	from that the extent. */	39	from that the extent. */
40	size = (size & ~(size-1)) - 1;	40	size = (size & ~(size-1)) - 1;
41		41
42	/* base == maxbase can be valid only if the BAR has	42	/* base == maxbase can be valid only if the BAR has
43	already been programmed with all 1s. */	43	already been programmed with all 1s. */
44	if (base == maxbase && ((base \| size) & mask) != mask)	44	if (base == maxbase && ((base \| size) & mask) != mask)
45	return 0;	45	return 0;
46		46
47	return size;	47	return size;
48	}	48	}
49		49
50	static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)	50	static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
51	{	51	{
52	u64_t size = mask & maxbase; /* Find the significant bits */	52	u64_t size = mask & maxbase; /* Find the significant bits */
53		53
54	if (!size)	54	if (!size)
55	return 0;	55	return 0;
56		56
57	/* Get the lowest of them to find the decode size, and	57	/* Get the lowest of them to find the decode size, and
58	from that the extent. */	58	from that the extent. */
59	size = (size & ~(size-1)) - 1;	59	size = (size & ~(size-1)) - 1;
60		60
61	/* base == maxbase can be valid only if the BAR has	61	/* base == maxbase can be valid only if the BAR has
62	already been programmed with all 1s. */	62	already been programmed with all 1s. */
63	if (base == maxbase && ((base \| size) & mask) != mask)	63	if (base == maxbase && ((base \| size) & mask) != mask)
64	return 0;	64	return 0;
65		65
66	return size;	66	return size;
67	}	67	}
68		68
69	static inline int is_64bit_memory(u32_t mask)	69	static inline int is_64bit_memory(u32_t mask)
70	{	70	{
71	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==	71	if ((mask & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
72	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))	72	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64))
73	return 1;	73	return 1;
74	return 0;	74	return 0;
75	}	75	}
76		76
77	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)	77	static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
78	{	78	{
79	u32_t pos, reg, next;	79	u32_t pos, reg, next;
80	u32_t l, sz;	80	u32_t l, sz;
81	struct resource *res;	81	struct resource *res;
82		82
83	for(pos=0; pos < howmany; pos = next)	83	for(pos=0; pos < howmany; pos = next)
84	{	84	{
85	u64_t l64;	85	u64_t l64;
86	u64_t sz64;	86	u64_t sz64;
87	u32_t raw_sz;	87	u32_t raw_sz;
88		88
89	next = pos + 1;	89	next = pos + 1;
90		90
91	res = &dev->resource[pos];	91	res = &dev->resource[pos];
92		92
93	reg = PCI_BASE_ADDRESS_0 + (pos << 2);	93	reg = PCI_BASE_ADDRESS_0 + (pos << 2);
94	l = PciRead32(dev->bus, dev->devfn, reg);	94	l = PciRead32(dev->bus, dev->devfn, reg);
95	PciWrite32(dev->bus, dev->devfn, reg, ~0);	95	PciWrite32(dev->bus, dev->devfn, reg, ~0);
96	sz = PciRead32(dev->bus, dev->devfn, reg);	96	sz = PciRead32(dev->bus, dev->devfn, reg);
97	PciWrite32(dev->bus, dev->devfn, reg, l);	97	PciWrite32(dev->bus, dev->devfn, reg, l);
98		98
99	if (!sz \|\| sz == 0xffffffff)	99	if (!sz \|\| sz == 0xffffffff)
100	continue;	100	continue;
101		101
102	if (l == 0xffffffff)	102	if (l == 0xffffffff)
103	l = 0;	103	l = 0;
104		104
105	raw_sz = sz;	105	raw_sz = sz;
106	if ((l & PCI_BASE_ADDRESS_SPACE) ==	106	if ((l & PCI_BASE_ADDRESS_SPACE) ==
107	PCI_BASE_ADDRESS_SPACE_MEMORY)	107	PCI_BASE_ADDRESS_SPACE_MEMORY)
108	{	108	{
109	sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);	109	sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
110	/*	110	/*
111	* For 64bit prefetchable memory sz could be 0, if the	111	* For 64bit prefetchable memory sz could be 0, if the
112	* real size is bigger than 4G, so we need to check	112	* real size is bigger than 4G, so we need to check
113	* szhi for that.	113	* szhi for that.
114	*/	114	*/
115	if (!is_64bit_memory(l) && !sz)	115	if (!is_64bit_memory(l) && !sz)
116	continue;	116	continue;
117	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;	117	res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
118	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;	118	res->flags \|= l & ~PCI_BASE_ADDRESS_MEM_MASK;
119	}	119	}
120	else {	120	else {
121	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);	121	sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
122	if (!sz)	122	if (!sz)
123	continue;	123	continue;
124	res->start = l & PCI_BASE_ADDRESS_IO_MASK;	124	res->start = l & PCI_BASE_ADDRESS_IO_MASK;
125	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;	125	res->flags \|= l & ~PCI_BASE_ADDRESS_IO_MASK;
126	}	126	}
127	res->end = res->start + (unsigned long) sz;	127	res->end = res->start + (unsigned long) sz;
128	res->flags \|= pci_calc_resource_flags(l);	128	res->flags \|= pci_calc_resource_flags(l);
129	if (is_64bit_memory(l))	129	if (is_64bit_memory(l))
130	{	130	{
131	u32_t szhi, lhi;	131	u32_t szhi, lhi;
132		132
133	lhi = PciRead32(dev->bus, dev->devfn, reg+4);	133	lhi = PciRead32(dev->bus, dev->devfn, reg+4);
134	PciWrite32(dev->bus, dev->devfn, reg+4, ~0);	134	PciWrite32(dev->bus, dev->devfn, reg+4, ~0);
135	szhi = PciRead32(dev->bus, dev->devfn, reg+4);	135	szhi = PciRead32(dev->bus, dev->devfn, reg+4);
136	PciWrite32(dev->bus, dev->devfn, reg+4, lhi);	136	PciWrite32(dev->bus, dev->devfn, reg+4, lhi);
137	sz64 = ((u64_t)szhi << 32) \| raw_sz;	137	sz64 = ((u64_t)szhi << 32) \| raw_sz;
138	l64 = ((u64_t)lhi << 32) \| l;	138	l64 = ((u64_t)lhi << 32) \| l;
139	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);	139	sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
140	next++;	140	next++;
141		141
142	#if BITS_PER_LONG == 64	142	#if BITS_PER_LONG == 64
143	if (!sz64) {	143	if (!sz64) {
144	res->start = 0;	144	res->start = 0;
145	res->end = 0;	145	res->end = 0;
146	res->flags = 0;	146	res->flags = 0;
147	continue;	147	continue;
148	}	148	}
149	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;	149	res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
150	res->end = res->start + sz64;	150	res->end = res->start + sz64;
151	#else	151	#else
152	if (sz64 > 0x100000000ULL) {	152	if (sz64 > 0x100000000ULL) {
153	printk(KERN_ERR "PCI: Unable to handle 64-bit "	153	printk(KERN_ERR "PCI: Unable to handle 64-bit "
154	"BAR for device %s\n", pci_name(dev));	154	"BAR for device %s\n", pci_name(dev));
155	res->start = 0;	155	res->start = 0;
156	res->flags = 0;	156	res->flags = 0;
157	}	157	}
158	else if (lhi)	158	else if (lhi)
159	{	159	{
160	/* 64-bit wide address, treat as disabled */	160	/* 64-bit wide address, treat as disabled */
161	PciWrite32(dev->bus, dev->devfn, reg,	161	PciWrite32(dev->bus, dev->devfn, reg,
162	l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);	162	l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
163	PciWrite32(dev->bus, dev->devfn, reg+4, 0);	163	PciWrite32(dev->bus, dev->devfn, reg+4, 0);
164	res->start = 0;	164	res->start = 0;
165	res->end = sz;	165	res->end = sz;
166	}	166	}
167	#endif	167	#endif
168	}	168	}
169	}	169	}
170		170
171	if ( rom )	171	if ( rom )
172	{	172	{
173	dev->rom_base_reg = rom;	173	dev->rom_base_reg = rom;
174	res = &dev->resource[PCI_ROM_RESOURCE];	174	res = &dev->resource[PCI_ROM_RESOURCE];
175		175
176	l = PciRead32(dev->bus, dev->devfn, rom);	176	l = PciRead32(dev->bus, dev->devfn, rom);
177	PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);	177	PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
178	sz = PciRead32(dev->bus, dev->devfn, rom);	178	sz = PciRead32(dev->bus, dev->devfn, rom);
179	PciWrite32(dev->bus, dev->devfn, rom, l);	179	PciWrite32(dev->bus, dev->devfn, rom, l);
180		180
181	if (l == 0xffffffff)	181	if (l == 0xffffffff)
182	l = 0;	182	l = 0;
183		183
184	if (sz && sz != 0xffffffff)	184	if (sz && sz != 0xffffffff)
185	{	185	{
186	sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);	186	sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
187		187
188	if (sz)	188	if (sz)
189	{	189	{
190	res->flags = (l & IORESOURCE_ROM_ENABLE) \|	190	res->flags = (l & IORESOURCE_ROM_ENABLE) \|
191	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|	191	IORESOURCE_MEM \| IORESOURCE_PREFETCH \|
192	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;	192	IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
193	res->start = l & PCI_ROM_ADDRESS_MASK;	193	res->start = l & PCI_ROM_ADDRESS_MASK;
194	res->end = res->start + (unsigned long) sz;	194	res->end = res->start + (unsigned long) sz;
195	}	195	}
196	}	196	}
197	}	197	}
198	}	198	}
199		199
200	static void pci_read_irq(struct pci_dev *dev)	200	static void pci_read_irq(struct pci_dev *dev)
201	{	201	{
202	u8_t irq;	202	u8_t irq;
203		203
204	irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);	204	irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);
205	dev->pin = irq;	205	dev->pin = irq;
206	if (irq)	206	if (irq)
207	PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);	207	PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);
208	dev->irq = irq;	208	dev->irq = irq;
209	};	209	};
210		210
211		211
212	static int pci_setup_device(struct pci_dev *dev)	212	static int pci_setup_device(struct pci_dev *dev)
213	{	213	{
214	u32_t class;	214	u32_t class;
215		215
216	class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);	216	class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);
217	dev->revision = class & 0xff;	217	dev->revision = class & 0xff;
218	class >>= 8; /* upper 3 bytes */	218	class >>= 8; /* upper 3 bytes */
219	dev->class = class;	219	dev->class = class;
220		220
221	/* "Unknown power state" */	221	/* "Unknown power state" */
222	// dev->current_state = PCI_UNKNOWN;	222	// dev->current_state = PCI_UNKNOWN;
223		223
224	/* Early fixups, before probing the BARs */	224	/* Early fixups, before probing the BARs */
225	// pci_fixup_device(pci_fixup_early, dev);	225	// pci_fixup_device(pci_fixup_early, dev);
226	class = dev->class >> 8;	226	class = dev->class >> 8;
227		227
228	switch (dev->hdr_type)	228	switch (dev->hdr_type)
229	{	229	{
230	case PCI_HEADER_TYPE_NORMAL: /* standard header */	230	case PCI_HEADER_TYPE_NORMAL: /* standard header */
231	if (class == PCI_CLASS_BRIDGE_PCI)	231	if (class == PCI_CLASS_BRIDGE_PCI)
232	goto bad;	232	goto bad;
233	pci_read_irq(dev);	233	pci_read_irq(dev);
234	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);	234	pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
235	dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);	235	dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
236	dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);	236	dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);
237		237
238	/*	238	/*
239	* Do the ugly legacy mode stuff here rather than broken chip	239	* Do the ugly legacy mode stuff here rather than broken chip
240	* quirk code. Legacy mode ATA controllers have fixed	240	* quirk code. Legacy mode ATA controllers have fixed
241	* addresses. These are not always echoed in BAR0-3, and	241	* addresses. These are not always echoed in BAR0-3, and
242	* BAR0-3 in a few cases contain junk!	242	* BAR0-3 in a few cases contain junk!
243	*/	243	*/
244	if (class == PCI_CLASS_STORAGE_IDE)	244	if (class == PCI_CLASS_STORAGE_IDE)
245	{	245	{
246	u8_t progif;	246	u8_t progif;
247		247
248	progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);	248	progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);
249	if ((progif & 1) == 0)	249	if ((progif & 1) == 0)
250	{	250	{
251	dev->resource[0].start = 0x1F0;	251	dev->resource[0].start = 0x1F0;
252	dev->resource[0].end = 0x1F7;	252	dev->resource[0].end = 0x1F7;
253	dev->resource[0].flags = LEGACY_IO_RESOURCE;	253	dev->resource[0].flags = LEGACY_IO_RESOURCE;
254	dev->resource[1].start = 0x3F6;	254	dev->resource[1].start = 0x3F6;
255	dev->resource[1].end = 0x3F6;	255	dev->resource[1].end = 0x3F6;
256	dev->resource[1].flags = LEGACY_IO_RESOURCE;	256	dev->resource[1].flags = LEGACY_IO_RESOURCE;
257	}	257	}
258	if ((progif & 4) == 0)	258	if ((progif & 4) == 0)
259	{	259	{
260	dev->resource[2].start = 0x170;	260	dev->resource[2].start = 0x170;
261	dev->resource[2].end = 0x177;	261	dev->resource[2].end = 0x177;
262	dev->resource[2].flags = LEGACY_IO_RESOURCE;	262	dev->resource[2].flags = LEGACY_IO_RESOURCE;
263	dev->resource[3].start = 0x376;	263	dev->resource[3].start = 0x376;
264	dev->resource[3].end = 0x376;	264	dev->resource[3].end = 0x376;
265	dev->resource[3].flags = LEGACY_IO_RESOURCE;	265	dev->resource[3].flags = LEGACY_IO_RESOURCE;
266	};	266	};
267	}	267	}
268	break;	268	break;
269		269
270	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */	270	case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
271	if (class != PCI_CLASS_BRIDGE_PCI)	271	if (class != PCI_CLASS_BRIDGE_PCI)
272	goto bad;	272	goto bad;
273	/* The PCI-to-PCI bridge spec requires that subtractive	273	/* The PCI-to-PCI bridge spec requires that subtractive
274	decoding (i.e. transparent) bridge must have programming	274	decoding (i.e. transparent) bridge must have programming
275	interface code of 0x01. */	275	interface code of 0x01. */
276	pci_read_irq(dev);	276	pci_read_irq(dev);
277	dev->transparent = ((dev->class & 0xff) == 1);	277	dev->transparent = ((dev->class & 0xff) == 1);
278	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);	278	pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
279	break;	279	break;
280		280
281	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */	281	case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
282	if (class != PCI_CLASS_BRIDGE_CARDBUS)	282	if (class != PCI_CLASS_BRIDGE_CARDBUS)
283	goto bad;	283	goto bad;
284	pci_read_irq(dev);	284	pci_read_irq(dev);
285	pci_read_bases(dev, 1, 0);	285	pci_read_bases(dev, 1, 0);
286	dev->subsystem_vendor = PciRead16(dev->bus,	286	dev->subsystem_vendor = PciRead16(dev->bus,
287	dev->devfn,	287	dev->devfn,
288	PCI_CB_SUBSYSTEM_VENDOR_ID);	288	PCI_CB_SUBSYSTEM_VENDOR_ID);
289		289
290	dev->subsystem_device = PciRead16(dev->bus,	290	dev->subsystem_device = PciRead16(dev->bus,
291	dev->devfn,	291	dev->devfn,
292	PCI_CB_SUBSYSTEM_ID);	292	PCI_CB_SUBSYSTEM_ID);
293	break;	293	break;
294		294
295	default: /* unknown header */	295	default: /* unknown header */
296	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",	296	printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
297	pci_name(dev), dev->hdr_type);	297	pci_name(dev), dev->hdr_type);
298	return -1;	298	return -1;
299		299
300	bad:	300	bad:
301	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",	301	printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
302	pci_name(dev), class, dev->hdr_type);	302	pci_name(dev), class, dev->hdr_type);
303	dev->class = PCI_CLASS_NOT_DEFINED;	303	dev->class = PCI_CLASS_NOT_DEFINED;
304	}	304	}
305		305
306	/* We found a fine healthy device, go go go... */	306	/* We found a fine healthy device, go go go... */
307		307
308	return 0;	308	return 0;
309	};	309	};
310		310
311	static dev_t* pci_scan_device(u32_t bus, int devfn)	311	static dev_t* pci_scan_device(u32_t bus, int devfn)
312	{	312	{
313	dev_t *dev;	313	dev_t *dev;
314		314
315	u32_t id;	315	u32_t id;
316	u8_t hdr;	316	u8_t hdr;
317		317
318	int timeout = 10;	318	int timeout = 10;
319		319
320	id = PciRead32(bus,devfn, PCI_VENDOR_ID);	320	id = PciRead32(bus,devfn, PCI_VENDOR_ID);
321		321
322	/* some broken boards return 0 or ~0 if a slot is empty: */	322	/* some broken boards return 0 or ~0 if a slot is empty: */
323	if (id == 0xffffffff \|\| id == 0x00000000 \|\|	323	if (id == 0xffffffff \|\| id == 0x00000000 \|\|
324	id == 0x0000ffff \|\| id == 0xffff0000)	324	id == 0x0000ffff \|\| id == 0xffff0000)
325	return NULL;	325	return NULL;
326		326
327	while (id == 0xffff0001)	327	while (id == 0xffff0001)
328	{	328	{
329		329
330	delay(timeout/10);	330	delay(timeout/10);
331	timeout *= 2;	331	timeout *= 2;
332		332
333	id = PciRead32(bus, devfn, PCI_VENDOR_ID);	333	id = PciRead32(bus, devfn, PCI_VENDOR_ID);
334		334
335	/* Card hasn't responded in 60 seconds? Must be stuck. */	335	/* Card hasn't responded in 60 seconds? Must be stuck. */
336	if (timeout > 60 * 100)	336	if (timeout > 60 * 100)
337	{	337	{
338	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "	338	printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
339	"responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn));	339	"responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn));
340	return NULL;	340	return NULL;
341	}	341	}
342	};	342	};
343		343
344	hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE);	344	hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE);
345		345
346	dev = (dev_t*)malloc(sizeof(dev_t));	346	dev = (dev_t*)malloc(sizeof(dev_t));
347		347
348	link_initialize(&dev->link);	348	INIT_LIST_HEAD(&dev->link);
349		349
350	if(unlikely(dev == NULL))	350	if(unlikely(dev == NULL))
351	return NULL;	351	return NULL;
352		352
353	dev->pci_dev.bus = bus;	353	dev->pci_dev.bus = bus;
354	dev->pci_dev.devfn = devfn;	354	dev->pci_dev.devfn = devfn;
355	dev->pci_dev.hdr_type = hdr & 0x7f;	355	dev->pci_dev.hdr_type = hdr & 0x7f;
356	dev->pci_dev.multifunction = !!(hdr & 0x80);	356	dev->pci_dev.multifunction = !!(hdr & 0x80);
357	dev->pci_dev.vendor = id & 0xffff;	357	dev->pci_dev.vendor = id & 0xffff;
358	dev->pci_dev.device = (id >> 16) & 0xffff;	358	dev->pci_dev.device = (id >> 16) & 0xffff;
359		359
360	pci_setup_device(&dev->pci_dev);	360	pci_setup_device(&dev->pci_dev);
361		361
362	return dev;	362	return dev;
363		363
364	};	364	};
365		365
366	int pci_scan_slot(u32_t bus, int devfn)	366	int pci_scan_slot(u32_t bus, int devfn)
367	{	367	{
368	int func, nr = 0;	368	int func, nr = 0;
369		369
370	for (func = 0; func < 8; func++, devfn++)	370	for (func = 0; func < 8; func++, devfn++)
371	{	371	{
372	dev_t *dev;	372	dev_t *dev;
373		373
374	dev = pci_scan_device(bus, devfn);	374	dev = pci_scan_device(bus, devfn);
375	if( dev )	375	if( dev )
376	{	376	{
377	list_append(&dev->link, &devices);	377	list_add(&dev->link, &devices);
378		378
379	nr++;	379	nr++;
380		380
381	/*	381	/*
382	* If this is a single function device,	382	* If this is a single function device,
383	* don't scan past the first function.	383	* don't scan past the first function.
384	*/	384	*/
385	if (!dev->pci_dev.multifunction)	385	if (!dev->pci_dev.multifunction)
386	{	386	{
387	if (func > 0) {	387	if (func > 0) {
388	dev->pci_dev.multifunction = 1;	388	dev->pci_dev.multifunction = 1;
389	}	389	}
390	else {	390	else {
391	break;	391	break;
392	}	392	}
393	}	393	}
394	}	394	}
395	else {	395	else {
396	if (func == 0)	396	if (func == 0)
397	break;	397	break;
398	}	398	}
399	};	399	};
400		400
401	return nr;	401	return nr;
402	};	402	};
403		403
404		404
405	void pci_scan_bus(u32_t bus)	405	void pci_scan_bus(u32_t bus)
406	{	406	{
407	u32_t devfn;	407	u32_t devfn;
408	dev_t *dev;	408	dev_t *dev;
409		409
410		410
411	for (devfn = 0; devfn < 0x100; devfn += 8)	411	for (devfn = 0; devfn < 0x100; devfn += 8)
412	pci_scan_slot(bus, devfn);	412	pci_scan_slot(bus, devfn);
413		413
414	}	414	}
415		415
416	int enum_pci_devices()	416	int enum_pci_devices()
417	{	417	{
418	dev_t *dev;	418	dev_t *dev;
419	u32_t last_bus;	419	u32_t last_bus;
420	u32_t bus = 0 , devfn = 0;	420	u32_t bus = 0 , devfn = 0;
421		421
422	list_initialize(&devices);	422	// list_initialize(&devices);
423		423
424	last_bus = PciApi(1);	424	last_bus = PciApi(1);
425		425
426		426
427	if( unlikely(last_bus == -1))	427	if( unlikely(last_bus == -1))
428	return -1;	428	return -1;
429		429
430	for(;bus <= last_bus; bus++)	430	for(;bus <= last_bus; bus++)
431	pci_scan_bus(bus);	431	pci_scan_bus(bus);
432		432
433	// for(dev = (dev_t*)devices.next;	433	// for(dev = (dev_t*)devices.next;
434	// &dev->link != &devices;	434	// &dev->link != &devices;
435	// dev = (dev_t*)dev->link.next)	435	// dev = (dev_t*)dev->link.next)
436	// {	436	// {
437	// dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",	437	// dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
438	// dev->pci_dev.vendor,	438	// dev->pci_dev.vendor,
439	// dev->pci_dev.device,	439	// dev->pci_dev.device,
440	// dev->pci_dev.bus,	440	// dev->pci_dev.bus,
441	// dev->pci_dev.devfn);	441	// dev->pci_dev.devfn);
442	//	442	//
443	// }	443	// }
444	return 0;	444	return 0;
445	}	445	}
446		446
447	#if 0	447	#if 0
448	/**	448	/**
449	* pci_set_power_state - Set the power state of a PCI device	449	* pci_set_power_state - Set the power state of a PCI device
450	* @dev: PCI device to be suspended	450	* @dev: PCI device to be suspended
451	* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering	451	* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
452	*	452	*
453	* Transition a device to a new power state, using the Power Management	453	* Transition a device to a new power state, using the Power Management
454	* Capabilities in the device's config space.	454	* Capabilities in the device's config space.
455	*	455	*
456	* RETURN VALUE:	456	* RETURN VALUE:
457	* -EINVAL if trying to enter a lower state than we're already in.	457	* -EINVAL if trying to enter a lower state than we're already in.
458	* 0 if we're already in the requested state.	458	* 0 if we're already in the requested state.
459	* -EIO if device does not support PCI PM.	459	* -EIO if device does not support PCI PM.
460	* 0 if we can successfully change the power state.	460	* 0 if we can successfully change the power state.
461	*/	461	*/
462	int	462	int
463	pci_set_power_state(struct pci_dev *dev, pci_power_t state)	463	pci_set_power_state(struct pci_dev *dev, pci_power_t state)
464	{	464	{
465	int pm, need_restore = 0;	465	int pm, need_restore = 0;
466	u16 pmcsr, pmc;	466	u16 pmcsr, pmc;
467		467
468	/* bound the state we're entering */	468	/* bound the state we're entering */
469	if (state > PCI_D3hot)	469	if (state > PCI_D3hot)
470	state = PCI_D3hot;	470	state = PCI_D3hot;
471		471
472	/*	472	/*
473	* If the device or the parent bridge can't support PCI PM, ignore	473	* If the device or the parent bridge can't support PCI PM, ignore
474	* the request if we're doing anything besides putting it into D0	474	* the request if we're doing anything besides putting it into D0
475	* (which would only happen on boot).	475	* (which would only happen on boot).
476	*/	476	*/
477	if ((state == PCI_D1 \|\| state == PCI_D2) && pci_no_d1d2(dev))	477	if ((state == PCI_D1 \|\| state == PCI_D2) && pci_no_d1d2(dev))
478	return 0;	478	return 0;
479		479
480	/* find PCI PM capability in list */	480	/* find PCI PM capability in list */
481	pm = pci_find_capability(dev, PCI_CAP_ID_PM);	481	pm = pci_find_capability(dev, PCI_CAP_ID_PM);
482		482
483	/* abort if the device doesn't support PM capabilities */	483	/* abort if the device doesn't support PM capabilities */
484	if (!pm)	484	if (!pm)
485	return -EIO;	485	return -EIO;
486		486
487	/* Validate current state:	487	/* Validate current state:
488	* Can enter D0 from any state, but if we can only go deeper	488	* Can enter D0 from any state, but if we can only go deeper
489	* to sleep if we're already in a low power state	489	* to sleep if we're already in a low power state
490	*/	490	*/
491	if (state != PCI_D0 && dev->current_state > state) {	491	if (state != PCI_D0 && dev->current_state > state) {
492	printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",	492	printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
493	__FUNCTION__, pci_name(dev), state, dev->current_state);	493	__FUNCTION__, pci_name(dev), state, dev->current_state);
494	return -EINVAL;	494	return -EINVAL;
495	} else if (dev->current_state == state)	495	} else if (dev->current_state == state)
496	return 0; /* we're already there */	496	return 0; /* we're already there */
497		497
498		498
499	pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);	499	pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
500	if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {	500	if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {

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(root)/drivers/video/drm/radeon/pci.c – Rev 1119 → 1120