WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/evergreen_dma.c


/*
 * Copyright 2010 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Alex Deucher
 */
#include 
#include "radeon.h"
#include "radeon_asic.h"
#include "evergreend.h"
 
u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);
 
/**
 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
 *
 * @rdev: radeon_device pointer
 * @fence: radeon fence object
 *
 * Add a DMA fence packet to the ring to write
 * the fence seq number and DMA trap packet to generate
 * an interrupt if needed (evergreen-SI).
 */
void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
				   struct radeon_fence *fence)
{
	struct radeon_ring *ring = &rdev->ring[fence->ring];
	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
	/* write the fence */
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
	radeon_ring_write(ring, addr & 0xfffffffc);
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
	radeon_ring_write(ring, fence->seq);
	/* generate an interrupt */
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
	/* flush HDP */
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
	radeon_ring_write(ring, 1);
}
 
/**
 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
 *
 * @rdev: radeon_device pointer
 * @ib: IB object to schedule
 *
 * Schedule an IB in the DMA ring (evergreen).
 */
void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
				   struct radeon_ib *ib)
{
	struct radeon_ring *ring = &rdev->ring[ib->ring];
 
	if (rdev->wb.enabled) {
		u32 next_rptr = ring->wptr + 4;
		while ((next_rptr & 7) != 5)
			next_rptr++;
		next_rptr += 3;
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
		radeon_ring_write(ring, next_rptr);
	}
 
	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
	 * Pad as necessary with NOPs.
	 */
	while ((ring->wptr & 7) != 5)
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
 
}
 
/**
 * evergreen_copy_dma - copy pages using the DMA engine
 *
 * @rdev: radeon_device pointer
 * @src_offset: src GPU address
 * @dst_offset: dst GPU address
 * @num_gpu_pages: number of GPU pages to xfer
 * @fence: radeon fence object
 *
 * Copy GPU paging using the DMA engine (evergreen-cayman).
 * Used by the radeon ttm implementation to move pages if
 * registered as the asic copy callback.
 */
struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
					uint64_t src_offset,
					uint64_t dst_offset,
		       unsigned num_gpu_pages,
					struct reservation_object *resv)
{
	struct radeon_fence *fence;
	struct radeon_sync sync;
	int ring_index = rdev->asic->copy.dma_ring_index;
	struct radeon_ring *ring = &rdev->ring[ring_index];
	u32 size_in_dw, cur_size_in_dw;
	int i, num_loops;
	int r = 0;
 
 
 
 
 
	radeon_sync_create(&sync);
 
	size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
	num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
	if (r) {
		DRM_ERROR("radeon: moving bo (%d).\n", r);
		radeon_sync_free(rdev, &sync, NULL);
		return ERR_PTR(r);
	}
 
	radeon_sync_resv(rdev, &sync, resv, false);
	radeon_sync_rings(rdev, &sync, ring->idx);
 
	for (i = 0; i < num_loops; i++) {
		cur_size_in_dw = size_in_dw;
		if (cur_size_in_dw > 0xFFFFF)
			cur_size_in_dw = 0xFFFFF;
		size_in_dw -= cur_size_in_dw;
		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
		radeon_ring_write(ring, dst_offset & 0xfffffffc);
		radeon_ring_write(ring, src_offset & 0xfffffffc);
		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
		src_offset += cur_size_in_dw * 4;
		dst_offset += cur_size_in_dw * 4;
	}
 
	r = radeon_fence_emit(rdev, &fence, ring->idx);
	if (r) {
		radeon_ring_unlock_undo(rdev, ring);
		radeon_sync_free(rdev, &sync, NULL);
		return ERR_PTR(r);
	}
 
	radeon_ring_unlock_commit(rdev, ring, false);
	radeon_sync_free(rdev, &sync, fence);
 
	return fence;
}
 
/**
 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
 *
 * @rdev: radeon_device pointer
 * @ring: radeon_ring structure holding ring information
 *
 * Check if the async DMA engine is locked up.
 * Returns true if the engine appears to be locked up, false if not.
 */
bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{
	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
	if (!(reset_mask & RADEON_RESET_DMA)) {
		radeon_ring_lockup_update(rdev, ring);
		return false;
	}
	return radeon_ring_test_lockup(rdev, ring);
}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/evergreen_dma.c – Rev 5078 → 5271

Rev 5078		Rev 5271
1	/*	1	/*
2	* Copyright 2010 Advanced Micro Devices, Inc.	2	* Copyright 2010 Advanced Micro Devices, Inc.
3	*	3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a	4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),	5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation	6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the	8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:	9	* Software is furnished to do so, subject to the following conditions:
10	*	10	*
11	* The above copyright notice and this permission notice shall be included in	11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.	12	* all copies or substantial portions of the Software.
13	*	13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.	20	* OTHER DEALINGS IN THE SOFTWARE.
21	*	21	*
22	* Authors: Alex Deucher	22	* Authors: Alex Deucher
23	*/	23	*/
24	#include	24	#include
25	#include "radeon.h"	25	#include "radeon.h"
26	#include "radeon_asic.h"	26	#include "radeon_asic.h"
27	#include "evergreend.h"	27	#include "evergreend.h"
28		28
29	u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);	29	u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev);
30		30
31	/**	31	/**
32	* evergreen_dma_fence_ring_emit - emit a fence on the DMA ring	32	* evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
33	*	33	*
34	* @rdev: radeon_device pointer	34	* @rdev: radeon_device pointer
35	* @fence: radeon fence object	35	* @fence: radeon fence object
36	*	36	*
37	* Add a DMA fence packet to the ring to write	37	* Add a DMA fence packet to the ring to write
38	* the fence seq number and DMA trap packet to generate	38	* the fence seq number and DMA trap packet to generate
39	* an interrupt if needed (evergreen-SI).	39	* an interrupt if needed (evergreen-SI).
40	*/	40	*/
41	void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,	41	void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
42	struct radeon_fence *fence)	42	struct radeon_fence *fence)
43	{	43	{
44	struct radeon_ring *ring = &rdev->ring[fence->ring];	44	struct radeon_ring *ring = &rdev->ring[fence->ring];
45	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;	45	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
46	/* write the fence */	46	/* write the fence */
47	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));	47	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
48	radeon_ring_write(ring, addr & 0xfffffffc);	48	radeon_ring_write(ring, addr & 0xfffffffc);
49	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));	49	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
50	radeon_ring_write(ring, fence->seq);	50	radeon_ring_write(ring, fence->seq);
51	/* generate an interrupt */	51	/* generate an interrupt */
52	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));	52	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
53	/* flush HDP */	53	/* flush HDP */
54	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));	54	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
55	radeon_ring_write(ring, (0xf << 16) \| (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));	55	radeon_ring_write(ring, (0xf << 16) \| (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
56	radeon_ring_write(ring, 1);	56	radeon_ring_write(ring, 1);
57	}	57	}
58		58
59	/**	59	/**
60	* evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine	60	* evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
61	*	61	*
62	* @rdev: radeon_device pointer	62	* @rdev: radeon_device pointer
63	* @ib: IB object to schedule	63	* @ib: IB object to schedule
64	*	64	*
65	* Schedule an IB in the DMA ring (evergreen).	65	* Schedule an IB in the DMA ring (evergreen).
66	*/	66	*/
67	void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,	67	void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
68	struct radeon_ib *ib)	68	struct radeon_ib *ib)
69	{	69	{
70	struct radeon_ring *ring = &rdev->ring[ib->ring];	70	struct radeon_ring *ring = &rdev->ring[ib->ring];
71		71
72	if (rdev->wb.enabled) {	72	if (rdev->wb.enabled) {
73	u32 next_rptr = ring->wptr + 4;	73	u32 next_rptr = ring->wptr + 4;
74	while ((next_rptr & 7) != 5)	74	while ((next_rptr & 7) != 5)
75	next_rptr++;	75	next_rptr++;
76	next_rptr += 3;	76	next_rptr += 3;
77	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));	77	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
78	radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);	78	radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
79	radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);	79	radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
80	radeon_ring_write(ring, next_rptr);	80	radeon_ring_write(ring, next_rptr);
81	}	81	}
82		82
83	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.	83	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
84	* Pad as necessary with NOPs.	84	* Pad as necessary with NOPs.
85	*/	85	*/
86	while ((ring->wptr & 7) != 5)	86	while ((ring->wptr & 7) != 5)
87	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));	87	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
88	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));	88	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
89	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));	89	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
90	radeon_ring_write(ring, (ib->length_dw << 12) \| (upper_32_bits(ib->gpu_addr) & 0xFF));	90	radeon_ring_write(ring, (ib->length_dw << 12) \| (upper_32_bits(ib->gpu_addr) & 0xFF));
91		91
92	}	92	}
93		93
94	/**	94	/**
95	* evergreen_copy_dma - copy pages using the DMA engine	95	* evergreen_copy_dma - copy pages using the DMA engine
96	*	96	*
97	* @rdev: radeon_device pointer	97	* @rdev: radeon_device pointer
98	* @src_offset: src GPU address	98	* @src_offset: src GPU address
99	* @dst_offset: dst GPU address	99	* @dst_offset: dst GPU address
100	* @num_gpu_pages: number of GPU pages to xfer	100	* @num_gpu_pages: number of GPU pages to xfer
101	* @fence: radeon fence object	101	* @fence: radeon fence object
102	*	102	*
103	* Copy GPU paging using the DMA engine (evergreen-cayman).	103	* Copy GPU paging using the DMA engine (evergreen-cayman).
104	* Used by the radeon ttm implementation to move pages if	104	* Used by the radeon ttm implementation to move pages if
105	* registered as the asic copy callback.	105	* registered as the asic copy callback.
106	*/	106	*/
107	int evergreen_copy_dma(struct radeon_device *rdev,	107	struct radeon_fence evergreen_copy_dma(struct radeon_device rdev,
108	uint64_t src_offset, uint64_t dst_offset,	108	uint64_t src_offset,
-		109	uint64_t dst_offset,
109	unsigned num_gpu_pages,	110	unsigned num_gpu_pages,
110	struct radeon_fence **fence)	111	struct reservation_object *resv)
111	{	112	{
112	struct radeon_semaphore *sem = NULL;	113	struct radeon_fence *fence;
-		114	struct radeon_sync sync;
113	int ring_index = rdev->asic->copy.dma_ring_index;	115	int ring_index = rdev->asic->copy.dma_ring_index;
114	struct radeon_ring *ring = &rdev->ring[ring_index];	116	struct radeon_ring *ring = &rdev->ring[ring_index];
115	u32 size_in_dw, cur_size_in_dw;	117	u32 size_in_dw, cur_size_in_dw;
116	int i, num_loops;	118	int i, num_loops;
117	int r = 0;	119	int r = 0;
118		120
119	r = radeon_semaphore_create(rdev, &sem);	-
120	if (r) {	-
121	DRM_ERROR("radeon: moving bo (%d).\n", r);	-
122	return r;	-
123	}	121	radeon_sync_create(&sync);
124		122
125	size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;	123	size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
126	num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);	124	num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
127	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);	125	r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
128	if (r) {	126	if (r) {
129	DRM_ERROR("radeon: moving bo (%d).\n", r);	127	DRM_ERROR("radeon: moving bo (%d).\n", r);
130	radeon_semaphore_free(rdev, &sem, NULL);	128	radeon_sync_free(rdev, &sync, NULL);
131	return r;	129	return ERR_PTR(r);
132	}	130	}
133		131
134	radeon_semaphore_sync_to(sem, *fence);	132	radeon_sync_resv(rdev, &sync, resv, false);
135	radeon_semaphore_sync_rings(rdev, sem, ring->idx);	133	radeon_sync_rings(rdev, &sync, ring->idx);
136		134
137	for (i = 0; i < num_loops; i++) {	135	for (i = 0; i < num_loops; i++) {
138	cur_size_in_dw = size_in_dw;	136	cur_size_in_dw = size_in_dw;
139	if (cur_size_in_dw > 0xFFFFF)	137	if (cur_size_in_dw > 0xFFFFF)
140	cur_size_in_dw = 0xFFFFF;	138	cur_size_in_dw = 0xFFFFF;
141	size_in_dw -= cur_size_in_dw;	139	size_in_dw -= cur_size_in_dw;
142	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));	140	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
143	radeon_ring_write(ring, dst_offset & 0xfffffffc);	141	radeon_ring_write(ring, dst_offset & 0xfffffffc);
144	radeon_ring_write(ring, src_offset & 0xfffffffc);	142	radeon_ring_write(ring, src_offset & 0xfffffffc);
145	radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);	143	radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
146	radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);	144	radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
147	src_offset += cur_size_in_dw * 4;	145	src_offset += cur_size_in_dw * 4;
148	dst_offset += cur_size_in_dw * 4;	146	dst_offset += cur_size_in_dw * 4;
149	}	147	}
150		148
151	r = radeon_fence_emit(rdev, fence, ring->idx);	149	r = radeon_fence_emit(rdev, &fence, ring->idx);
152	if (r) {	150	if (r) {
153	radeon_ring_unlock_undo(rdev, ring);	151	radeon_ring_unlock_undo(rdev, ring);
154	radeon_semaphore_free(rdev, &sem, NULL);	152	radeon_sync_free(rdev, &sync, NULL);
155	return r;	153	return ERR_PTR(r);
156	}	154	}
157		155
158	radeon_ring_unlock_commit(rdev, ring, false);	156	radeon_ring_unlock_commit(rdev, ring, false);
159	radeon_semaphore_free(rdev, &sem, *fence);	157	radeon_sync_free(rdev, &sync, fence);
160		158
161	return r;	159	return fence;
162	}	160	}
163		161
164	/**	162	/**
165	* evergreen_dma_is_lockup - Check if the DMA engine is locked up	163	* evergreen_dma_is_lockup - Check if the DMA engine is locked up
166	*	164	*
167	* @rdev: radeon_device pointer	165	* @rdev: radeon_device pointer
168	* @ring: radeon_ring structure holding ring information	166	* @ring: radeon_ring structure holding ring information
169	*	167	*
170	* Check if the async DMA engine is locked up.	168	* Check if the async DMA engine is locked up.
171	* Returns true if the engine appears to be locked up, false if not.	169	* Returns true if the engine appears to be locked up, false if not.
172	*/	170	*/
173	bool evergreen_dma_is_lockup(struct radeon_device rdev, struct radeon_ring ring)	171	bool evergreen_dma_is_lockup(struct radeon_device rdev, struct radeon_ring ring)
174	{	172	{
175	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);	173	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
176		174
177	if (!(reset_mask & RADEON_RESET_DMA)) {	175	if (!(reset_mask & RADEON_RESET_DMA)) {
178	radeon_ring_lockup_update(rdev, ring);	176	radeon_ring_lockup_update(rdev, ring);
179	return false;	177	return false;
180	}	178	}
181	return radeon_ring_test_lockup(rdev, ring);	179	return radeon_ring_test_lockup(rdev, ring);
182	}	180	}