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1 | /* |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation |
2 | * Copyright © 2008-2010 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * Zou Nan hai |
25 | * Zou Nan hai |
26 | * Xiang Hai hao |
26 | * Xiang Hai hao |
27 | * |
27 | * |
28 | */ |
28 | */ |
29 | #define iowrite32(v, addr) writel((v), (addr)) |
29 | #define iowrite32(v, addr) writel((v), (addr)) |
30 | #define ioread32(addr) readl(addr) |
30 | #define ioread32(addr) readl(addr) |
31 | 31 | ||
32 | #include "drmP.h" |
32 | #include "drmP.h" |
33 | #include "drm.h" |
33 | #include "drm.h" |
34 | #include "i915_drv.h" |
34 | #include "i915_drv.h" |
35 | #include "i915_drm.h" |
35 | #include "i915_drm.h" |
36 | //#include "i915_trace.h" |
36 | //#include "i915_trace.h" |
37 | #include "intel_drv.h" |
37 | #include "intel_drv.h" |
- | 38 | ||
- | 39 | /* |
|
- | 40 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
|
- | 41 | * over cache flushing. |
|
- | 42 | */ |
|
- | 43 | struct pipe_control { |
|
- | 44 | struct drm_i915_gem_object *obj; |
|
- | 45 | volatile u32 *cpu_page; |
|
- | 46 | u32 gtt_offset; |
|
- | 47 | }; |
|
38 | 48 | ||
39 | static inline int ring_space(struct intel_ring_buffer *ring) |
49 | static inline int ring_space(struct intel_ring_buffer *ring) |
40 | { |
50 | { |
41 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
51 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
42 | if (space < 0) |
52 | if (space < 0) |
43 | space += ring->size; |
53 | space += ring->size; |
44 | return space; |
54 | return space; |
45 | } |
55 | } |
46 | 56 | ||
47 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
57 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
48 | { |
58 | { |
49 | drm_i915_private_t *dev_priv = dev->dev_private; |
59 | drm_i915_private_t *dev_priv = dev->dev_private; |
50 | u32 seqno; |
60 | u32 seqno; |
51 | 61 | ||
52 | seqno = dev_priv->next_seqno; |
62 | seqno = dev_priv->next_seqno; |
53 | 63 | ||
54 | /* reserve 0 for non-seqno */ |
64 | /* reserve 0 for non-seqno */ |
55 | if (++dev_priv->next_seqno == 0) |
65 | if (++dev_priv->next_seqno == 0) |
56 | dev_priv->next_seqno = 1; |
66 | dev_priv->next_seqno = 1; |
57 | 67 | ||
58 | return seqno; |
68 | return seqno; |
59 | } |
69 | } |
60 | 70 | ||
61 | static int |
71 | static int |
62 | render_ring_flush(struct intel_ring_buffer *ring, |
72 | render_ring_flush(struct intel_ring_buffer *ring, |
63 | u32 invalidate_domains, |
73 | u32 invalidate_domains, |
64 | u32 flush_domains) |
74 | u32 flush_domains) |
65 | { |
75 | { |
66 | struct drm_device *dev = ring->dev; |
76 | struct drm_device *dev = ring->dev; |
67 | u32 cmd; |
77 | u32 cmd; |
68 | int ret; |
78 | int ret; |
69 | 79 | ||
70 | /* |
80 | /* |
71 | * read/write caches: |
81 | * read/write caches: |
72 | * |
82 | * |
73 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
83 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
74 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
84 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
75 | * also flushed at 2d versus 3d pipeline switches. |
85 | * also flushed at 2d versus 3d pipeline switches. |
76 | * |
86 | * |
77 | * read-only caches: |
87 | * read-only caches: |
78 | * |
88 | * |
79 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
89 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
80 | * MI_READ_FLUSH is set, and is always flushed on 965. |
90 | * MI_READ_FLUSH is set, and is always flushed on 965. |
81 | * |
91 | * |
82 | * I915_GEM_DOMAIN_COMMAND may not exist? |
92 | * I915_GEM_DOMAIN_COMMAND may not exist? |
83 | * |
93 | * |
84 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
94 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
85 | * invalidated when MI_EXE_FLUSH is set. |
95 | * invalidated when MI_EXE_FLUSH is set. |
86 | * |
96 | * |
87 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
97 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
88 | * invalidated with every MI_FLUSH. |
98 | * invalidated with every MI_FLUSH. |
89 | * |
99 | * |
90 | * TLBs: |
100 | * TLBs: |
91 | * |
101 | * |
92 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
102 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
93 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
103 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
94 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
104 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
95 | * are flushed at any MI_FLUSH. |
105 | * are flushed at any MI_FLUSH. |
96 | */ |
106 | */ |
97 | 107 | ||
98 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
108 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
99 | if ((invalidate_domains|flush_domains) & |
109 | if ((invalidate_domains|flush_domains) & |
100 | I915_GEM_DOMAIN_RENDER) |
110 | I915_GEM_DOMAIN_RENDER) |
101 | cmd &= ~MI_NO_WRITE_FLUSH; |
111 | cmd &= ~MI_NO_WRITE_FLUSH; |
102 | if (INTEL_INFO(dev)->gen < 4) { |
112 | if (INTEL_INFO(dev)->gen < 4) { |
103 | /* |
113 | /* |
104 | * On the 965, the sampler cache always gets flushed |
114 | * On the 965, the sampler cache always gets flushed |
105 | * and this bit is reserved. |
115 | * and this bit is reserved. |
106 | */ |
116 | */ |
107 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
117 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
108 | cmd |= MI_READ_FLUSH; |
118 | cmd |= MI_READ_FLUSH; |
109 | } |
119 | } |
110 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
111 | cmd |= MI_EXE_FLUSH; |
121 | cmd |= MI_EXE_FLUSH; |
112 | 122 | ||
113 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
114 | (IS_G4X(dev) || IS_GEN5(dev))) |
124 | (IS_G4X(dev) || IS_GEN5(dev))) |
115 | cmd |= MI_INVALIDATE_ISP; |
125 | cmd |= MI_INVALIDATE_ISP; |
116 | 126 | ||
117 | ret = intel_ring_begin(ring, 2); |
127 | ret = intel_ring_begin(ring, 2); |
118 | if (ret) |
128 | if (ret) |
119 | return ret; |
129 | return ret; |
120 | 130 | ||
121 | intel_ring_emit(ring, cmd); |
131 | intel_ring_emit(ring, cmd); |
122 | intel_ring_emit(ring, MI_NOOP); |
132 | intel_ring_emit(ring, MI_NOOP); |
123 | intel_ring_advance(ring); |
133 | intel_ring_advance(ring); |
124 | 134 | ||
125 | return 0; |
135 | return 0; |
126 | } |
136 | } |
- | 137 | ||
- | 138 | /** |
|
- | 139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
|
- | 140 | * implementing two workarounds on gen6. From section 1.4.7.1 |
|
- | 141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
|
- | 142 | * |
|
- | 143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
|
- | 144 | * produced by non-pipelined state commands), software needs to first |
|
- | 145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
|
- | 146 | * 0. |
|
- | 147 | * |
|
- | 148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
|
- | 149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
|
- | 150 | * |
|
- | 151 | * And the workaround for these two requires this workaround first: |
|
- | 152 | * |
|
- | 153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
|
- | 154 | * BEFORE the pipe-control with a post-sync op and no write-cache |
|
- | 155 | * flushes. |
|
- | 156 | * |
|
- | 157 | * And this last workaround is tricky because of the requirements on |
|
- | 158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
|
- | 159 | * volume 2 part 1: |
|
- | 160 | * |
|
- | 161 | * "1 of the following must also be set: |
|
- | 162 | * - Render Target Cache Flush Enable ([12] of DW1) |
|
- | 163 | * - Depth Cache Flush Enable ([0] of DW1) |
|
- | 164 | * - Stall at Pixel Scoreboard ([1] of DW1) |
|
- | 165 | * - Depth Stall ([13] of DW1) |
|
- | 166 | * - Post-Sync Operation ([13] of DW1) |
|
- | 167 | * - Notify Enable ([8] of DW1)" |
|
- | 168 | * |
|
- | 169 | * The cache flushes require the workaround flush that triggered this |
|
- | 170 | * one, so we can't use it. Depth stall would trigger the same. |
|
- | 171 | * Post-sync nonzero is what triggered this second workaround, so we |
|
- | 172 | * can't use that one either. Notify enable is IRQs, which aren't |
|
- | 173 | * really our business. That leaves only stall at scoreboard. |
|
- | 174 | */ |
|
- | 175 | static int |
|
- | 176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
|
- | 177 | { |
|
- | 178 | struct pipe_control *pc = ring->private; |
|
- | 179 | u32 scratch_addr = pc->gtt_offset + 128; |
|
- | 180 | int ret; |
|
- | 181 | ||
- | 182 | ||
- | 183 | ret = intel_ring_begin(ring, 6); |
|
- | 184 | if (ret) |
|
- | 185 | return ret; |
|
- | 186 | ||
- | 187 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
|
- | 188 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
|
- | 189 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
|
- | 190 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
|
- | 191 | intel_ring_emit(ring, 0); /* low dword */ |
|
- | 192 | intel_ring_emit(ring, 0); /* high dword */ |
|
- | 193 | intel_ring_emit(ring, MI_NOOP); |
|
- | 194 | intel_ring_advance(ring); |
|
- | 195 | ||
- | 196 | ret = intel_ring_begin(ring, 6); |
|
- | 197 | if (ret) |
|
- | 198 | return ret; |
|
- | 199 | ||
- | 200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
|
- | 201 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
|
- | 202 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
|
- | 203 | intel_ring_emit(ring, 0); |
|
- | 204 | intel_ring_emit(ring, 0); |
|
- | 205 | intel_ring_emit(ring, MI_NOOP); |
|
- | 206 | intel_ring_advance(ring); |
|
- | 207 | ||
- | 208 | return 0; |
|
- | 209 | } |
|
- | 210 | ||
- | 211 | static int |
|
- | 212 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
|
- | 213 | u32 invalidate_domains, u32 flush_domains) |
|
- | 214 | { |
|
- | 215 | u32 flags = 0; |
|
- | 216 | struct pipe_control *pc = ring->private; |
|
- | 217 | u32 scratch_addr = pc->gtt_offset + 128; |
|
- | 218 | int ret; |
|
- | 219 | ||
- | 220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
|
- | 221 | intel_emit_post_sync_nonzero_flush(ring); |
|
- | 222 | ||
- | 223 | /* Just flush everything. Experiments have shown that reducing the |
|
- | 224 | * number of bits based on the write domains has little performance |
|
- | 225 | * impact. |
|
- | 226 | */ |
|
- | 227 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
|
- | 228 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
|
- | 229 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
|
- | 230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
|
- | 231 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
|
- | 232 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
|
- | 233 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
|
- | 234 | ||
- | 235 | ret = intel_ring_begin(ring, 6); |
|
- | 236 | if (ret) |
|
- | 237 | return ret; |
|
- | 238 | ||
- | 239 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
|
- | 240 | intel_ring_emit(ring, flags); |
|
- | 241 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
|
- | 242 | intel_ring_emit(ring, 0); /* lower dword */ |
|
- | 243 | intel_ring_emit(ring, 0); /* uppwer dword */ |
|
- | 244 | intel_ring_emit(ring, MI_NOOP); |
|
- | 245 | intel_ring_advance(ring); |
|
- | 246 | ||
- | 247 | return 0; |
|
- | 248 | } |
|
127 | 249 | ||
128 | static void ring_write_tail(struct intel_ring_buffer *ring, |
250 | static void ring_write_tail(struct intel_ring_buffer *ring, |
129 | u32 value) |
251 | u32 value) |
130 | { |
252 | { |
131 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
253 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
132 | I915_WRITE_TAIL(ring, value); |
254 | I915_WRITE_TAIL(ring, value); |
133 | } |
255 | } |
134 | 256 | ||
135 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
257 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
136 | { |
258 | { |
137 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
259 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
138 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
260 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
139 | RING_ACTHD(ring->mmio_base) : ACTHD; |
261 | RING_ACTHD(ring->mmio_base) : ACTHD; |
140 | 262 | ||
141 | return I915_READ(acthd_reg); |
263 | return I915_READ(acthd_reg); |
142 | } |
264 | } |
143 | 265 | ||
144 | static int init_ring_common(struct intel_ring_buffer *ring) |
266 | static int init_ring_common(struct intel_ring_buffer *ring) |
145 | { |
267 | { |
146 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
268 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
147 | struct drm_i915_gem_object *obj = ring->obj; |
269 | struct drm_i915_gem_object *obj = ring->obj; |
148 | u32 head; |
270 | u32 head; |
149 | 271 | ||
150 | /* Stop the ring if it's running. */ |
272 | /* Stop the ring if it's running. */ |
151 | I915_WRITE_CTL(ring, 0); |
273 | I915_WRITE_CTL(ring, 0); |
152 | I915_WRITE_HEAD(ring, 0); |
274 | I915_WRITE_HEAD(ring, 0); |
153 | ring->write_tail(ring, 0); |
275 | ring->write_tail(ring, 0); |
154 | 276 | ||
155 | /* Initialize the ring. */ |
277 | /* Initialize the ring. */ |
156 | I915_WRITE_START(ring, obj->gtt_offset); |
278 | I915_WRITE_START(ring, obj->gtt_offset); |
157 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
279 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
158 | 280 | ||
159 | /* G45 ring initialization fails to reset head to zero */ |
281 | /* G45 ring initialization fails to reset head to zero */ |
160 | if (head != 0) { |
282 | if (head != 0) { |
161 | DRM_DEBUG_KMS("%s head not reset to zero " |
283 | DRM_DEBUG_KMS("%s head not reset to zero " |
162 | "ctl %08x head %08x tail %08x start %08x\n", |
284 | "ctl %08x head %08x tail %08x start %08x\n", |
163 | ring->name, |
285 | ring->name, |
164 | I915_READ_CTL(ring), |
286 | I915_READ_CTL(ring), |
165 | I915_READ_HEAD(ring), |
287 | I915_READ_HEAD(ring), |
166 | I915_READ_TAIL(ring), |
288 | I915_READ_TAIL(ring), |
167 | I915_READ_START(ring)); |
289 | I915_READ_START(ring)); |
168 | 290 | ||
169 | I915_WRITE_HEAD(ring, 0); |
291 | I915_WRITE_HEAD(ring, 0); |
170 | 292 | ||
171 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
293 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
172 | DRM_ERROR("failed to set %s head to zero " |
294 | DRM_ERROR("failed to set %s head to zero " |
173 | "ctl %08x head %08x tail %08x start %08x\n", |
295 | "ctl %08x head %08x tail %08x start %08x\n", |
174 | ring->name, |
296 | ring->name, |
175 | I915_READ_CTL(ring), |
297 | I915_READ_CTL(ring), |
176 | I915_READ_HEAD(ring), |
298 | I915_READ_HEAD(ring), |
177 | I915_READ_TAIL(ring), |
299 | I915_READ_TAIL(ring), |
178 | I915_READ_START(ring)); |
300 | I915_READ_START(ring)); |
179 | } |
301 | } |
180 | } |
302 | } |
181 | 303 | ||
182 | I915_WRITE_CTL(ring, |
304 | I915_WRITE_CTL(ring, |
183 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
305 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
184 | | RING_REPORT_64K | RING_VALID); |
306 | | RING_REPORT_64K | RING_VALID); |
185 | 307 | ||
186 | /* If the head is still not zero, the ring is dead */ |
308 | /* If the head is still not zero, the ring is dead */ |
187 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
309 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
188 | I915_READ_START(ring) != obj->gtt_offset || |
310 | I915_READ_START(ring) != obj->gtt_offset || |
189 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
311 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
190 | DRM_ERROR("%s initialization failed " |
312 | DRM_ERROR("%s initialization failed " |
191 | "ctl %08x head %08x tail %08x start %08x\n", |
313 | "ctl %08x head %08x tail %08x start %08x\n", |
192 | ring->name, |
314 | ring->name, |
193 | I915_READ_CTL(ring), |
315 | I915_READ_CTL(ring), |
194 | I915_READ_HEAD(ring), |
316 | I915_READ_HEAD(ring), |
195 | I915_READ_TAIL(ring), |
317 | I915_READ_TAIL(ring), |
196 | I915_READ_START(ring)); |
318 | I915_READ_START(ring)); |
197 | return -EIO; |
319 | return -EIO; |
198 | } |
320 | } |
199 | 321 | ||
200 | ring->head = I915_READ_HEAD(ring); |
322 | ring->head = I915_READ_HEAD(ring); |
201 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
323 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
202 | ring->space = ring_space(ring); |
324 | ring->space = ring_space(ring); |
203 | 325 | ||
204 | 326 | ||
205 | return 0; |
327 | return 0; |
206 | } |
328 | } |
207 | - | ||
208 | /* |
- | |
209 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
- | |
210 | * over cache flushing. |
- | |
211 | */ |
- | |
212 | struct pipe_control { |
- | |
213 | struct drm_i915_gem_object *obj; |
- | |
214 | volatile u32 *cpu_page; |
- | |
215 | u32 gtt_offset; |
- | |
216 | }; |
- | |
217 | 329 | ||
218 | static int |
330 | static int |
219 | init_pipe_control(struct intel_ring_buffer *ring) |
331 | init_pipe_control(struct intel_ring_buffer *ring) |
220 | { |
332 | { |
221 | struct pipe_control *pc; |
333 | struct pipe_control *pc; |
222 | struct drm_i915_gem_object *obj; |
334 | struct drm_i915_gem_object *obj; |
223 | int ret; |
335 | int ret; |
224 | 336 | ||
225 | if (ring->private) |
337 | if (ring->private) |
226 | return 0; |
338 | return 0; |
227 | 339 | ||
228 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
340 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
229 | if (!pc) |
341 | if (!pc) |
230 | return -ENOMEM; |
342 | return -ENOMEM; |
231 | 343 | ||
232 | obj = i915_gem_alloc_object(ring->dev, 4096); |
344 | obj = i915_gem_alloc_object(ring->dev, 4096); |
233 | if (obj == NULL) { |
345 | if (obj == NULL) { |
234 | DRM_ERROR("Failed to allocate seqno page\n"); |
346 | DRM_ERROR("Failed to allocate seqno page\n"); |
235 | ret = -ENOMEM; |
347 | ret = -ENOMEM; |
236 | goto err; |
348 | goto err; |
237 | } |
349 | } |
238 | 350 | ||
239 | // i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
351 | // i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
240 | 352 | ||
241 | ret = i915_gem_object_pin(obj, 4096, true); |
353 | ret = i915_gem_object_pin(obj, 4096, true); |
242 | if (ret) |
354 | if (ret) |
243 | goto err_unref; |
355 | goto err_unref; |
244 | 356 | ||
245 | pc->gtt_offset = obj->gtt_offset; |
357 | pc->gtt_offset = obj->gtt_offset; |
246 | pc->cpu_page = (void*)MapIoMem(obj->pages[0], 4096, PG_SW); |
358 | pc->cpu_page = (void*)MapIoMem(obj->pages[0], 4096, PG_SW); |
247 | if (pc->cpu_page == NULL) |
359 | if (pc->cpu_page == NULL) |
248 | goto err_unpin; |
360 | goto err_unpin; |
249 | 361 | ||
250 | pc->obj = obj; |
362 | pc->obj = obj; |
251 | ring->private = pc; |
363 | ring->private = pc; |
252 | return 0; |
364 | return 0; |
253 | 365 | ||
254 | err_unpin: |
366 | err_unpin: |
255 | // i915_gem_object_unpin(obj); |
367 | // i915_gem_object_unpin(obj); |
256 | err_unref: |
368 | err_unref: |
257 | // drm_gem_object_unreference(&obj->base); |
369 | // drm_gem_object_unreference(&obj->base); |
258 | err: |
370 | err: |
259 | kfree(pc); |
371 | kfree(pc); |
260 | return ret; |
372 | return ret; |
261 | } |
373 | } |
262 | 374 | ||
263 | static void |
375 | static void |
264 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
376 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
265 | { |
377 | { |
266 | struct pipe_control *pc = ring->private; |
378 | struct pipe_control *pc = ring->private; |
267 | struct drm_i915_gem_object *obj; |
379 | struct drm_i915_gem_object *obj; |
268 | 380 | ||
269 | if (!ring->private) |
381 | if (!ring->private) |
270 | return; |
382 | return; |
271 | 383 | ||
272 | obj = pc->obj; |
384 | obj = pc->obj; |
273 | // kunmap(obj->pages[0]); |
385 | // kunmap(obj->pages[0]); |
274 | // i915_gem_object_unpin(obj); |
386 | // i915_gem_object_unpin(obj); |
275 | // drm_gem_object_unreference(&obj->base); |
387 | // drm_gem_object_unreference(&obj->base); |
276 | 388 | ||
277 | kfree(pc); |
389 | kfree(pc); |
278 | ring->private = NULL; |
390 | ring->private = NULL; |
279 | } |
391 | } |
280 | 392 | ||
281 | static int init_render_ring(struct intel_ring_buffer *ring) |
393 | static int init_render_ring(struct intel_ring_buffer *ring) |
282 | { |
394 | { |
283 | struct drm_device *dev = ring->dev; |
395 | struct drm_device *dev = ring->dev; |
284 | struct drm_i915_private *dev_priv = dev->dev_private; |
396 | struct drm_i915_private *dev_priv = dev->dev_private; |
285 | int ret = init_ring_common(ring); |
397 | int ret = init_ring_common(ring); |
286 | 398 | ||
287 | if (INTEL_INFO(dev)->gen > 3) { |
399 | if (INTEL_INFO(dev)->gen > 3) { |
288 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
400 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
289 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
401 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
290 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
402 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
291 | I915_WRITE(MI_MODE, mode); |
403 | I915_WRITE(MI_MODE, mode); |
292 | if (IS_GEN7(dev)) |
404 | if (IS_GEN7(dev)) |
293 | I915_WRITE(GFX_MODE_GEN7, |
405 | I915_WRITE(GFX_MODE_GEN7, |
294 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
406 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
295 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
407 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
296 | } |
408 | } |
297 | 409 | ||
298 | if (INTEL_INFO(dev)->gen >= 6) { |
- | |
299 | } else if (IS_GEN5(dev)) { |
410 | if (INTEL_INFO(dev)->gen >= 5) { |
300 | ret = init_pipe_control(ring); |
411 | ret = init_pipe_control(ring); |
301 | if (ret) |
412 | if (ret) |
302 | return ret; |
413 | return ret; |
303 | } |
414 | } |
- | 415 | ||
- | 416 | if (INTEL_INFO(dev)->gen >= 6) { |
|
- | 417 | I915_WRITE(INSTPM, |
|
- | 418 | INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); |
|
- | 419 | } |
|
304 | 420 | ||
305 | return ret; |
421 | return ret; |
306 | } |
422 | } |
307 | 423 | ||
308 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
424 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
309 | { |
425 | { |
310 | if (!ring->private) |
426 | if (!ring->private) |
311 | return; |
427 | return; |
312 | 428 | ||
313 | cleanup_pipe_control(ring); |
429 | cleanup_pipe_control(ring); |
314 | } |
430 | } |
315 | 431 | ||
316 | static void |
432 | static void |
317 | update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) |
433 | update_mboxes(struct intel_ring_buffer *ring, |
- | 434 | u32 seqno, |
|
- | 435 | u32 mmio_offset) |
|
318 | { |
436 | { |
319 | struct drm_device *dev = ring->dev; |
- | |
320 | struct drm_i915_private *dev_priv = dev->dev_private; |
- | |
321 | int id; |
- | |
322 | - | ||
323 | /* |
- | |
324 | * cs -> 1 = vcs, 0 = bcs |
- | |
325 | * vcs -> 1 = bcs, 0 = cs, |
- | |
326 | * bcs -> 1 = cs, 0 = vcs. |
- | |
327 | */ |
- | |
328 | id = ring - dev_priv->ring; |
- | |
329 | id += 2 - i; |
- | |
330 | id %= 3; |
- | |
331 | - | ||
332 | intel_ring_emit(ring, |
437 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
333 | MI_SEMAPHORE_MBOX | |
438 | MI_SEMAPHORE_GLOBAL_GTT | |
334 | MI_SEMAPHORE_REGISTER | |
439 | MI_SEMAPHORE_REGISTER | |
335 | MI_SEMAPHORE_UPDATE); |
440 | MI_SEMAPHORE_UPDATE); |
336 | intel_ring_emit(ring, seqno); |
441 | intel_ring_emit(ring, seqno); |
337 | intel_ring_emit(ring, |
442 | intel_ring_emit(ring, mmio_offset); |
338 | RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); |
- | |
339 | } |
443 | } |
- | 444 | ||
- | 445 | /** |
|
- | 446 | * gen6_add_request - Update the semaphore mailbox registers |
|
- | 447 | * |
|
- | 448 | * @ring - ring that is adding a request |
|
- | 449 | * @seqno - return seqno stuck into the ring |
|
- | 450 | * |
|
- | 451 | * Update the mailbox registers in the *other* rings with the current seqno. |
|
- | 452 | * This acts like a signal in the canonical semaphore. |
|
340 | 453 | */ |
|
341 | static int |
454 | static int |
342 | gen6_add_request(struct intel_ring_buffer *ring, |
455 | gen6_add_request(struct intel_ring_buffer *ring, |
343 | u32 *result) |
456 | u32 *seqno) |
- | 457 | { |
|
344 | { |
458 | u32 mbox1_reg; |
345 | u32 seqno; |
459 | u32 mbox2_reg; |
346 | int ret; |
460 | int ret; |
347 | 461 | ||
348 | ret = intel_ring_begin(ring, 10); |
462 | ret = intel_ring_begin(ring, 10); |
349 | if (ret) |
463 | if (ret) |
350 | return ret; |
464 | return ret; |
351 | 465 | ||
352 | seqno = i915_gem_get_seqno(ring->dev); |
466 | mbox1_reg = ring->signal_mbox[0]; |
- | 467 | mbox2_reg = ring->signal_mbox[1]; |
|
353 | update_semaphore(ring, 0, seqno); |
468 | |
- | 469 | *seqno = i915_gem_get_seqno(ring->dev); |
|
- | 470 | ||
354 | update_semaphore(ring, 1, seqno); |
471 | update_mboxes(ring, *seqno, mbox1_reg); |
355 | 472 | update_mboxes(ring, *seqno, mbox2_reg); |
|
356 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
473 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
357 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
474 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
358 | intel_ring_emit(ring, seqno); |
475 | intel_ring_emit(ring, *seqno); |
359 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
476 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
360 | intel_ring_advance(ring); |
477 | intel_ring_advance(ring); |
361 | - | ||
362 | *result = seqno; |
478 | |
363 | return 0; |
479 | return 0; |
364 | } |
480 | } |
- | 481 | ||
- | 482 | /** |
|
- | 483 | * intel_ring_sync - sync the waiter to the signaller on seqno |
|
- | 484 | * |
|
- | 485 | * @waiter - ring that is waiting |
|
- | 486 | * @signaller - ring which has, or will signal |
|
365 | 487 | * @seqno - seqno which the waiter will block on |
|
- | 488 | */ |
|
366 | int |
489 | static int |
367 | intel_ring_sync(struct intel_ring_buffer *ring, |
490 | intel_ring_sync(struct intel_ring_buffer *waiter, |
- | 491 | struct intel_ring_buffer *signaller, |
|
368 | struct intel_ring_buffer *to, |
492 | int ring, |
369 | u32 seqno) |
493 | u32 seqno) |
370 | { |
494 | { |
371 | int ret; |
495 | int ret; |
- | 496 | u32 dw1 = MI_SEMAPHORE_MBOX | |
|
- | 497 | MI_SEMAPHORE_COMPARE | |
|
- | 498 | MI_SEMAPHORE_REGISTER; |
|
372 | 499 | ||
373 | ret = intel_ring_begin(ring, 4); |
500 | ret = intel_ring_begin(waiter, 4); |
374 | if (ret) |
501 | if (ret) |
375 | return ret; |
502 | return ret; |
376 | - | ||
377 | intel_ring_emit(ring, |
- | |
378 | MI_SEMAPHORE_MBOX | |
- | |
379 | MI_SEMAPHORE_REGISTER | |
503 | |
380 | intel_ring_sync_index(ring, to) << 17 | |
- | |
381 | MI_SEMAPHORE_COMPARE); |
504 | intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]); |
382 | intel_ring_emit(ring, seqno); |
505 | intel_ring_emit(waiter, seqno); |
383 | intel_ring_emit(ring, 0); |
506 | intel_ring_emit(waiter, 0); |
384 | intel_ring_emit(ring, MI_NOOP); |
507 | intel_ring_emit(waiter, MI_NOOP); |
385 | intel_ring_advance(ring); |
508 | intel_ring_advance(waiter); |
386 | 509 | ||
387 | return 0; |
510 | return 0; |
388 | } |
511 | } |
- | 512 | ||
- | 513 | /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */ |
|
- | 514 | int |
|
- | 515 | render_ring_sync_to(struct intel_ring_buffer *waiter, |
|
- | 516 | struct intel_ring_buffer *signaller, |
|
- | 517 | u32 seqno) |
|
- | 518 | { |
|
- | 519 | // WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID); |
|
- | 520 | return intel_ring_sync(waiter, |
|
- | 521 | signaller, |
|
- | 522 | RCS, |
|
- | 523 | seqno); |
|
- | 524 | } |
|
- | 525 | ||
- | 526 | /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */ |
|
- | 527 | int |
|
- | 528 | gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter, |
|
- | 529 | struct intel_ring_buffer *signaller, |
|
- | 530 | u32 seqno) |
|
- | 531 | { |
|
- | 532 | // WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID); |
|
- | 533 | return intel_ring_sync(waiter, |
|
- | 534 | signaller, |
|
- | 535 | VCS, |
|
- | 536 | seqno); |
|
- | 537 | } |
|
- | 538 | ||
- | 539 | /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */ |
|
- | 540 | int |
|
- | 541 | gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, |
|
- | 542 | struct intel_ring_buffer *signaller, |
|
- | 543 | u32 seqno) |
|
- | 544 | { |
|
- | 545 | // WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID); |
|
- | 546 | return intel_ring_sync(waiter, |
|
- | 547 | signaller, |
|
- | 548 | BCS, |
|
- | 549 | seqno); |
|
- | 550 | } |
|
- | 551 | ||
- | 552 | ||
389 | 553 | ||
390 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
554 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
391 | do { \ |
555 | do { \ |
392 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
556 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
393 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
557 | PIPE_CONTROL_DEPTH_STALL); \ |
394 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
558 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
395 | intel_ring_emit(ring__, 0); \ |
559 | intel_ring_emit(ring__, 0); \ |
396 | intel_ring_emit(ring__, 0); \ |
560 | intel_ring_emit(ring__, 0); \ |
397 | } while (0) |
561 | } while (0) |
398 | 562 | ||
399 | static int |
563 | static int |
400 | pc_render_add_request(struct intel_ring_buffer *ring, |
564 | pc_render_add_request(struct intel_ring_buffer *ring, |
401 | u32 *result) |
565 | u32 *result) |
402 | { |
566 | { |
403 | struct drm_device *dev = ring->dev; |
567 | struct drm_device *dev = ring->dev; |
404 | u32 seqno = i915_gem_get_seqno(dev); |
568 | u32 seqno = i915_gem_get_seqno(dev); |
405 | struct pipe_control *pc = ring->private; |
569 | struct pipe_control *pc = ring->private; |
406 | u32 scratch_addr = pc->gtt_offset + 128; |
570 | u32 scratch_addr = pc->gtt_offset + 128; |
407 | int ret; |
571 | int ret; |
408 | 572 | ||
409 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
573 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
410 | * incoherent with writes to memory, i.e. completely fubar, |
574 | * incoherent with writes to memory, i.e. completely fubar, |
411 | * so we need to use PIPE_NOTIFY instead. |
575 | * so we need to use PIPE_NOTIFY instead. |
412 | * |
576 | * |
413 | * However, we also need to workaround the qword write |
577 | * However, we also need to workaround the qword write |
414 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
578 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
415 | * memory before requesting an interrupt. |
579 | * memory before requesting an interrupt. |
416 | */ |
580 | */ |
417 | ret = intel_ring_begin(ring, 32); |
581 | ret = intel_ring_begin(ring, 32); |
418 | if (ret) |
582 | if (ret) |
419 | return ret; |
583 | return ret; |
420 | 584 | ||
- | 585 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
|
421 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
586 | PIPE_CONTROL_WRITE_FLUSH | |
422 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
587 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
423 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
588 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
424 | intel_ring_emit(ring, seqno); |
589 | intel_ring_emit(ring, seqno); |
425 | intel_ring_emit(ring, 0); |
590 | intel_ring_emit(ring, 0); |
426 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
591 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
427 | scratch_addr += 128; /* write to separate cachelines */ |
592 | scratch_addr += 128; /* write to separate cachelines */ |
428 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
593 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
429 | scratch_addr += 128; |
594 | scratch_addr += 128; |
430 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
595 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
431 | scratch_addr += 128; |
596 | scratch_addr += 128; |
432 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
597 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
433 | scratch_addr += 128; |
598 | scratch_addr += 128; |
434 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
599 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
435 | scratch_addr += 128; |
600 | scratch_addr += 128; |
436 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
601 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
437 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
602 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
438 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
603 | PIPE_CONTROL_WRITE_FLUSH | |
- | 604 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
|
439 | PIPE_CONTROL_NOTIFY); |
605 | PIPE_CONTROL_NOTIFY); |
440 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
606 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
441 | intel_ring_emit(ring, seqno); |
607 | intel_ring_emit(ring, seqno); |
442 | intel_ring_emit(ring, 0); |
608 | intel_ring_emit(ring, 0); |
443 | intel_ring_advance(ring); |
609 | intel_ring_advance(ring); |
444 | 610 | ||
445 | *result = seqno; |
611 | *result = seqno; |
446 | return 0; |
612 | return 0; |
447 | } |
613 | } |
448 | 614 | ||
449 | static int |
615 | static int |
450 | render_ring_add_request(struct intel_ring_buffer *ring, |
616 | render_ring_add_request(struct intel_ring_buffer *ring, |
451 | u32 *result) |
617 | u32 *result) |
452 | { |
618 | { |
453 | struct drm_device *dev = ring->dev; |
619 | struct drm_device *dev = ring->dev; |
454 | u32 seqno = i915_gem_get_seqno(dev); |
620 | u32 seqno = i915_gem_get_seqno(dev); |
455 | int ret; |
621 | int ret; |
456 | 622 | ||
457 | ret = intel_ring_begin(ring, 4); |
623 | ret = intel_ring_begin(ring, 4); |
458 | if (ret) |
624 | if (ret) |
459 | return ret; |
625 | return ret; |
460 | 626 | ||
461 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
627 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
462 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
628 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
463 | intel_ring_emit(ring, seqno); |
629 | intel_ring_emit(ring, seqno); |
464 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
630 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
465 | intel_ring_advance(ring); |
631 | intel_ring_advance(ring); |
466 | 632 | ||
467 | *result = seqno; |
633 | *result = seqno; |
468 | return 0; |
634 | return 0; |
469 | } |
635 | } |
470 | 636 | ||
471 | static u32 |
637 | static u32 |
- | 638 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) |
|
- | 639 | { |
|
- | 640 | struct drm_device *dev = ring->dev; |
|
- | 641 | ||
- | 642 | /* Workaround to force correct ordering between irq and seqno writes on |
|
- | 643 | * ivb (and maybe also on snb) by reading from a CS register (like |
|
- | 644 | * ACTHD) before reading the status page. */ |
|
- | 645 | if (IS_GEN7(dev)) |
|
- | 646 | intel_ring_get_active_head(ring); |
|
- | 647 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
|
- | 648 | } |
|
- | 649 | ||
- | 650 | static u32 |
|
472 | ring_get_seqno(struct intel_ring_buffer *ring) |
651 | ring_get_seqno(struct intel_ring_buffer *ring) |
473 | { |
652 | { |
474 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
653 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
475 | } |
654 | } |
476 | 655 | ||
477 | static u32 |
656 | static u32 |
478 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
657 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
479 | { |
658 | { |
480 | struct pipe_control *pc = ring->private; |
659 | struct pipe_control *pc = ring->private; |
481 | return pc->cpu_page[0]; |
660 | return pc->cpu_page[0]; |
482 | } |
661 | } |
483 | 662 | ||
484 | static void |
663 | static void |
485 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
664 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
486 | { |
665 | { |
487 | dev_priv->gt_irq_mask &= ~mask; |
666 | dev_priv->gt_irq_mask &= ~mask; |
488 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
667 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
489 | POSTING_READ(GTIMR); |
668 | POSTING_READ(GTIMR); |
490 | } |
669 | } |
491 | 670 | ||
492 | static void |
671 | static void |
493 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
672 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
494 | { |
673 | { |
495 | dev_priv->gt_irq_mask |= mask; |
674 | dev_priv->gt_irq_mask |= mask; |
496 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
675 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
497 | POSTING_READ(GTIMR); |
676 | POSTING_READ(GTIMR); |
498 | } |
677 | } |
499 | 678 | ||
500 | static void |
679 | static void |
501 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
680 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
502 | { |
681 | { |
503 | dev_priv->irq_mask &= ~mask; |
682 | dev_priv->irq_mask &= ~mask; |
504 | I915_WRITE(IMR, dev_priv->irq_mask); |
683 | I915_WRITE(IMR, dev_priv->irq_mask); |
505 | POSTING_READ(IMR); |
684 | POSTING_READ(IMR); |
506 | } |
685 | } |
507 | 686 | ||
508 | static void |
687 | static void |
509 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
688 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
510 | { |
689 | { |
511 | dev_priv->irq_mask |= mask; |
690 | dev_priv->irq_mask |= mask; |
512 | I915_WRITE(IMR, dev_priv->irq_mask); |
691 | I915_WRITE(IMR, dev_priv->irq_mask); |
513 | POSTING_READ(IMR); |
692 | POSTING_READ(IMR); |
514 | } |
693 | } |
515 | - | ||
516 | #if 0 |
694 | |
517 | static bool |
695 | static bool |
518 | render_ring_get_irq(struct intel_ring_buffer *ring) |
696 | render_ring_get_irq(struct intel_ring_buffer *ring) |
519 | { |
697 | { |
520 | struct drm_device *dev = ring->dev; |
698 | struct drm_device *dev = ring->dev; |
521 | drm_i915_private_t *dev_priv = dev->dev_private; |
699 | drm_i915_private_t *dev_priv = dev->dev_private; |
522 | 700 | ||
523 | if (!dev->irq_enabled) |
701 | if (!dev->irq_enabled) |
524 | return false; |
702 | return false; |
525 | 703 | ||
526 | spin_lock(&ring->irq_lock); |
704 | spin_lock(&ring->irq_lock); |
527 | if (ring->irq_refcount++ == 0) { |
705 | if (ring->irq_refcount++ == 0) { |
528 | if (HAS_PCH_SPLIT(dev)) |
706 | if (HAS_PCH_SPLIT(dev)) |
529 | ironlake_enable_irq(dev_priv, |
707 | ironlake_enable_irq(dev_priv, |
530 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
708 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
531 | else |
709 | else |
532 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
710 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
533 | } |
711 | } |
534 | spin_unlock(&ring->irq_lock); |
712 | spin_unlock(&ring->irq_lock); |
535 | 713 | ||
536 | return true; |
714 | return true; |
537 | } |
715 | } |
538 | 716 | ||
539 | static void |
717 | static void |
540 | render_ring_put_irq(struct intel_ring_buffer *ring) |
718 | render_ring_put_irq(struct intel_ring_buffer *ring) |
541 | { |
719 | { |
542 | struct drm_device *dev = ring->dev; |
720 | struct drm_device *dev = ring->dev; |
543 | drm_i915_private_t *dev_priv = dev->dev_private; |
721 | drm_i915_private_t *dev_priv = dev->dev_private; |
544 | 722 | ||
545 | spin_lock(&ring->irq_lock); |
723 | spin_lock(&ring->irq_lock); |
546 | if (--ring->irq_refcount == 0) { |
724 | if (--ring->irq_refcount == 0) { |
547 | if (HAS_PCH_SPLIT(dev)) |
725 | if (HAS_PCH_SPLIT(dev)) |
548 | ironlake_disable_irq(dev_priv, |
726 | ironlake_disable_irq(dev_priv, |
549 | GT_USER_INTERRUPT | |
727 | GT_USER_INTERRUPT | |
550 | GT_PIPE_NOTIFY); |
728 | GT_PIPE_NOTIFY); |
551 | else |
729 | else |
552 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
730 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
553 | } |
731 | } |
554 | spin_unlock(&ring->irq_lock); |
732 | spin_unlock(&ring->irq_lock); |
555 | } |
733 | } |
556 | #endif |
- | |
557 | 734 | ||
558 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
735 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
559 | { |
736 | { |
560 | struct drm_device *dev = ring->dev; |
737 | struct drm_device *dev = ring->dev; |
561 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
738 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
562 | u32 mmio = 0; |
739 | u32 mmio = 0; |
563 | 740 | ||
564 | /* The ring status page addresses are no longer next to the rest of |
741 | /* The ring status page addresses are no longer next to the rest of |
565 | * the ring registers as of gen7. |
742 | * the ring registers as of gen7. |
566 | */ |
743 | */ |
567 | if (IS_GEN7(dev)) { |
744 | if (IS_GEN7(dev)) { |
568 | switch (ring->id) { |
745 | switch (ring->id) { |
569 | case RING_RENDER: |
746 | case RING_RENDER: |
570 | mmio = RENDER_HWS_PGA_GEN7; |
747 | mmio = RENDER_HWS_PGA_GEN7; |
571 | break; |
748 | break; |
572 | case RING_BLT: |
749 | case RING_BLT: |
573 | mmio = BLT_HWS_PGA_GEN7; |
750 | mmio = BLT_HWS_PGA_GEN7; |
574 | break; |
751 | break; |
575 | case RING_BSD: |
752 | case RING_BSD: |
576 | mmio = BSD_HWS_PGA_GEN7; |
753 | mmio = BSD_HWS_PGA_GEN7; |
577 | break; |
754 | break; |
578 | } |
755 | } |
579 | } else if (IS_GEN6(ring->dev)) { |
756 | } else if (IS_GEN6(ring->dev)) { |
580 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
757 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
581 | } else { |
758 | } else { |
582 | mmio = RING_HWS_PGA(ring->mmio_base); |
759 | mmio = RING_HWS_PGA(ring->mmio_base); |
583 | } |
760 | } |
584 | 761 | ||
585 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
762 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
586 | POSTING_READ(mmio); |
763 | POSTING_READ(mmio); |
587 | } |
764 | } |
588 | 765 | ||
589 | static int |
766 | static int |
590 | bsd_ring_flush(struct intel_ring_buffer *ring, |
767 | bsd_ring_flush(struct intel_ring_buffer *ring, |
591 | u32 invalidate_domains, |
768 | u32 invalidate_domains, |
592 | u32 flush_domains) |
769 | u32 flush_domains) |
593 | { |
770 | { |
594 | int ret; |
771 | int ret; |
595 | 772 | ||
596 | ret = intel_ring_begin(ring, 2); |
773 | ret = intel_ring_begin(ring, 2); |
597 | if (ret) |
774 | if (ret) |
598 | return ret; |
775 | return ret; |
599 | 776 | ||
600 | intel_ring_emit(ring, MI_FLUSH); |
777 | intel_ring_emit(ring, MI_FLUSH); |
601 | intel_ring_emit(ring, MI_NOOP); |
778 | intel_ring_emit(ring, MI_NOOP); |
602 | intel_ring_advance(ring); |
779 | intel_ring_advance(ring); |
603 | return 0; |
780 | return 0; |
604 | } |
781 | } |
605 | 782 | ||
606 | static int |
783 | static int |
607 | ring_add_request(struct intel_ring_buffer *ring, |
784 | ring_add_request(struct intel_ring_buffer *ring, |
608 | u32 *result) |
785 | u32 *result) |
609 | { |
786 | { |
610 | u32 seqno; |
787 | u32 seqno; |
611 | int ret; |
788 | int ret; |
612 | 789 | ||
613 | ret = intel_ring_begin(ring, 4); |
790 | ret = intel_ring_begin(ring, 4); |
614 | if (ret) |
791 | if (ret) |
615 | return ret; |
792 | return ret; |
616 | 793 | ||
617 | seqno = i915_gem_get_seqno(ring->dev); |
794 | seqno = i915_gem_get_seqno(ring->dev); |
618 | 795 | ||
619 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
796 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
620 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
797 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
621 | intel_ring_emit(ring, seqno); |
798 | intel_ring_emit(ring, seqno); |
622 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
799 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
623 | intel_ring_advance(ring); |
800 | intel_ring_advance(ring); |
624 | 801 | ||
625 | *result = seqno; |
802 | *result = seqno; |
626 | return 0; |
803 | return 0; |
627 | } |
804 | } |
628 | - | ||
629 | #if 0 |
- | |
630 | 805 | ||
631 | static bool |
806 | static bool |
632 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
807 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
633 | { |
808 | { |
634 | struct drm_device *dev = ring->dev; |
809 | struct drm_device *dev = ring->dev; |
635 | drm_i915_private_t *dev_priv = dev->dev_private; |
810 | drm_i915_private_t *dev_priv = dev->dev_private; |
636 | 811 | ||
637 | if (!dev->irq_enabled) |
812 | if (!dev->irq_enabled) |
638 | return false; |
813 | return false; |
- | 814 | ||
- | 815 | /* It looks like we need to prevent the gt from suspending while waiting |
|
- | 816 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
|
- | 817 | * blt/bsd rings on ivb. */ |
|
- | 818 | if (IS_GEN7(dev)) |
|
- | 819 | gen6_gt_force_wake_get(dev_priv); |
|
639 | 820 | ||
640 | spin_lock(&ring->irq_lock); |
821 | spin_lock(&ring->irq_lock); |
641 | if (ring->irq_refcount++ == 0) { |
822 | if (ring->irq_refcount++ == 0) { |
642 | ring->irq_mask &= ~rflag; |
823 | ring->irq_mask &= ~rflag; |
643 | I915_WRITE_IMR(ring, ring->irq_mask); |
824 | I915_WRITE_IMR(ring, ring->irq_mask); |
644 | ironlake_enable_irq(dev_priv, gflag); |
825 | ironlake_enable_irq(dev_priv, gflag); |
645 | } |
826 | } |
646 | spin_unlock(&ring->irq_lock); |
827 | spin_unlock(&ring->irq_lock); |
647 | 828 | ||
648 | return true; |
829 | return true; |
649 | } |
830 | } |
650 | 831 | ||
651 | static void |
832 | static void |
652 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
833 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
653 | { |
834 | { |
654 | struct drm_device *dev = ring->dev; |
835 | struct drm_device *dev = ring->dev; |
655 | drm_i915_private_t *dev_priv = dev->dev_private; |
836 | drm_i915_private_t *dev_priv = dev->dev_private; |
656 | 837 | ||
657 | spin_lock(&ring->irq_lock); |
838 | spin_lock(&ring->irq_lock); |
658 | if (--ring->irq_refcount == 0) { |
839 | if (--ring->irq_refcount == 0) { |
659 | ring->irq_mask |= rflag; |
840 | ring->irq_mask |= rflag; |
660 | I915_WRITE_IMR(ring, ring->irq_mask); |
841 | I915_WRITE_IMR(ring, ring->irq_mask); |
661 | ironlake_disable_irq(dev_priv, gflag); |
842 | ironlake_disable_irq(dev_priv, gflag); |
662 | } |
843 | } |
663 | spin_unlock(&ring->irq_lock); |
844 | spin_unlock(&ring->irq_lock); |
- | 845 | ||
- | 846 | if (IS_GEN7(dev)) |
|
- | 847 | gen6_gt_force_wake_put(dev_priv); |
|
664 | } |
848 | } |
665 | 849 | ||
666 | static bool |
850 | static bool |
667 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
851 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
668 | { |
852 | { |
669 | struct drm_device *dev = ring->dev; |
853 | struct drm_device *dev = ring->dev; |
670 | drm_i915_private_t *dev_priv = dev->dev_private; |
854 | drm_i915_private_t *dev_priv = dev->dev_private; |
671 | 855 | ||
672 | if (!dev->irq_enabled) |
856 | if (!dev->irq_enabled) |
673 | return false; |
857 | return false; |
674 | 858 | ||
675 | spin_lock(&ring->irq_lock); |
859 | spin_lock(&ring->irq_lock); |
676 | if (ring->irq_refcount++ == 0) { |
860 | if (ring->irq_refcount++ == 0) { |
677 | if (IS_G4X(dev)) |
861 | if (IS_G4X(dev)) |
678 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
862 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
679 | else |
863 | else |
680 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
864 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
681 | } |
865 | } |
682 | spin_unlock(&ring->irq_lock); |
866 | spin_unlock(&ring->irq_lock); |
683 | 867 | ||
684 | return true; |
868 | return true; |
685 | } |
869 | } |
686 | static void |
870 | static void |
687 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
871 | bsd_ring_put_irq(struct intel_ring_buffer *ring) |
688 | { |
872 | { |
689 | struct drm_device *dev = ring->dev; |
873 | struct drm_device *dev = ring->dev; |
690 | drm_i915_private_t *dev_priv = dev->dev_private; |
874 | drm_i915_private_t *dev_priv = dev->dev_private; |
691 | 875 | ||
692 | spin_lock(&ring->irq_lock); |
876 | spin_lock(&ring->irq_lock); |
693 | if (--ring->irq_refcount == 0) { |
877 | if (--ring->irq_refcount == 0) { |
694 | if (IS_G4X(dev)) |
878 | if (IS_G4X(dev)) |
695 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
879 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
696 | else |
880 | else |
697 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
881 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
698 | } |
882 | } |
699 | spin_unlock(&ring->irq_lock); |
883 | spin_unlock(&ring->irq_lock); |
700 | } |
884 | } |
701 | #endif |
- | |
702 | 885 | ||
703 | static int |
886 | static int |
704 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
887 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
705 | { |
888 | { |
706 | int ret; |
889 | int ret; |
707 | 890 | ||
708 | ret = intel_ring_begin(ring, 2); |
891 | ret = intel_ring_begin(ring, 2); |
709 | if (ret) |
892 | if (ret) |
710 | return ret; |
893 | return ret; |
711 | 894 | ||
712 | intel_ring_emit(ring, |
895 | intel_ring_emit(ring, |
713 | MI_BATCH_BUFFER_START | (2 << 6) | |
896 | MI_BATCH_BUFFER_START | (2 << 6) | |
714 | MI_BATCH_NON_SECURE_I965); |
897 | MI_BATCH_NON_SECURE_I965); |
715 | intel_ring_emit(ring, offset); |
898 | intel_ring_emit(ring, offset); |
716 | intel_ring_advance(ring); |
899 | intel_ring_advance(ring); |
717 | 900 | ||
718 | return 0; |
901 | return 0; |
719 | } |
902 | } |
720 | 903 | ||
721 | static int |
904 | static int |
722 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
905 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
723 | u32 offset, u32 len) |
906 | u32 offset, u32 len) |
724 | { |
907 | { |
725 | struct drm_device *dev = ring->dev; |
908 | struct drm_device *dev = ring->dev; |
726 | int ret; |
909 | int ret; |
727 | 910 | ||
728 | if (IS_I830(dev) || IS_845G(dev)) { |
911 | if (IS_I830(dev) || IS_845G(dev)) { |
729 | ret = intel_ring_begin(ring, 4); |
912 | ret = intel_ring_begin(ring, 4); |
730 | if (ret) |
913 | if (ret) |
731 | return ret; |
914 | return ret; |
732 | 915 | ||
733 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
916 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
734 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
917 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
735 | intel_ring_emit(ring, offset + len - 8); |
918 | intel_ring_emit(ring, offset + len - 8); |
736 | intel_ring_emit(ring, 0); |
919 | intel_ring_emit(ring, 0); |
737 | } else { |
920 | } else { |
738 | ret = intel_ring_begin(ring, 2); |
921 | ret = intel_ring_begin(ring, 2); |
739 | if (ret) |
922 | if (ret) |
740 | return ret; |
923 | return ret; |
741 | 924 | ||
742 | if (INTEL_INFO(dev)->gen >= 4) { |
925 | if (INTEL_INFO(dev)->gen >= 4) { |
743 | intel_ring_emit(ring, |
926 | intel_ring_emit(ring, |
744 | MI_BATCH_BUFFER_START | (2 << 6) | |
927 | MI_BATCH_BUFFER_START | (2 << 6) | |
745 | MI_BATCH_NON_SECURE_I965); |
928 | MI_BATCH_NON_SECURE_I965); |
746 | intel_ring_emit(ring, offset); |
929 | intel_ring_emit(ring, offset); |
747 | } else { |
930 | } else { |
748 | intel_ring_emit(ring, |
931 | intel_ring_emit(ring, |
749 | MI_BATCH_BUFFER_START | (2 << 6)); |
932 | MI_BATCH_BUFFER_START | (2 << 6)); |
750 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
933 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
751 | } |
934 | } |
752 | } |
935 | } |
753 | intel_ring_advance(ring); |
936 | intel_ring_advance(ring); |
754 | 937 | ||
755 | return 0; |
938 | return 0; |
756 | } |
939 | } |
757 | 940 | ||
758 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
941 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
759 | { |
942 | { |
760 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
943 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
761 | struct drm_i915_gem_object *obj; |
944 | struct drm_i915_gem_object *obj; |
762 | 945 | ||
763 | obj = ring->status_page.obj; |
946 | obj = ring->status_page.obj; |
764 | if (obj == NULL) |
947 | if (obj == NULL) |
765 | return; |
948 | return; |
766 | 949 | ||
767 | kunmap(obj->pages[0]); |
950 | kunmap(obj->pages[0]); |
768 | // i915_gem_object_unpin(obj); |
951 | // i915_gem_object_unpin(obj); |
769 | // drm_gem_object_unreference(&obj->base); |
952 | // drm_gem_object_unreference(&obj->base); |
770 | ring->status_page.obj = NULL; |
953 | ring->status_page.obj = NULL; |
771 | 954 | ||
772 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
955 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
773 | } |
956 | } |
774 | 957 | ||
775 | static int init_status_page(struct intel_ring_buffer *ring) |
958 | static int init_status_page(struct intel_ring_buffer *ring) |
776 | { |
959 | { |
777 | struct drm_device *dev = ring->dev; |
960 | struct drm_device *dev = ring->dev; |
778 | drm_i915_private_t *dev_priv = dev->dev_private; |
961 | drm_i915_private_t *dev_priv = dev->dev_private; |
779 | struct drm_i915_gem_object *obj; |
962 | struct drm_i915_gem_object *obj; |
780 | int ret; |
963 | int ret; |
781 | 964 | ||
782 | obj = i915_gem_alloc_object(dev, 4096); |
965 | obj = i915_gem_alloc_object(dev, 4096); |
783 | if (obj == NULL) { |
966 | if (obj == NULL) { |
784 | DRM_ERROR("Failed to allocate status page\n"); |
967 | DRM_ERROR("Failed to allocate status page\n"); |
785 | ret = -ENOMEM; |
968 | ret = -ENOMEM; |
786 | goto err; |
969 | goto err; |
787 | } |
970 | } |
788 | 971 | ||
789 | // i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
972 | // i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
790 | 973 | ||
791 | ret = i915_gem_object_pin(obj, 4096, true); |
974 | ret = i915_gem_object_pin(obj, 4096, true); |
792 | if (ret != 0) { |
975 | if (ret != 0) { |
793 | goto err_unref; |
976 | goto err_unref; |
794 | } |
977 | } |
795 | 978 | ||
796 | ring->status_page.gfx_addr = obj->gtt_offset; |
979 | ring->status_page.gfx_addr = obj->gtt_offset; |
797 | ring->status_page.page_addr = MapIoMem(obj->pages[0], 4096, PG_SW); |
980 | ring->status_page.page_addr = MapIoMem(obj->pages[0], 4096, PG_SW); |
798 | if (ring->status_page.page_addr == NULL) { |
981 | if (ring->status_page.page_addr == NULL) { |
799 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
982 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
800 | goto err_unpin; |
983 | goto err_unpin; |
801 | } |
984 | } |
802 | ring->status_page.obj = obj; |
985 | ring->status_page.obj = obj; |
803 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
986 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
804 | 987 | ||
805 | intel_ring_setup_status_page(ring); |
988 | intel_ring_setup_status_page(ring); |
806 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
989 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
807 | ring->name, ring->status_page.gfx_addr); |
990 | ring->name, ring->status_page.gfx_addr); |
808 | 991 | ||
809 | return 0; |
992 | return 0; |
810 | 993 | ||
811 | err_unpin: |
994 | err_unpin: |
812 | // i915_gem_object_unpin(obj); |
995 | // i915_gem_object_unpin(obj); |
813 | err_unref: |
996 | err_unref: |
814 | // drm_gem_object_unreference(&obj->base); |
997 | // drm_gem_object_unreference(&obj->base); |
815 | err: |
998 | err: |
816 | return ret; |
999 | return ret; |
817 | } |
1000 | } |
818 | 1001 | ||
819 | int intel_init_ring_buffer(struct drm_device *dev, |
1002 | int intel_init_ring_buffer(struct drm_device *dev, |
820 | struct intel_ring_buffer *ring) |
1003 | struct intel_ring_buffer *ring) |
821 | { |
1004 | { |
822 | struct drm_i915_gem_object *obj; |
1005 | struct drm_i915_gem_object *obj; |
823 | int ret; |
1006 | int ret; |
824 | 1007 | ||
825 | ring->dev = dev; |
1008 | ring->dev = dev; |
826 | INIT_LIST_HEAD(&ring->active_list); |
1009 | INIT_LIST_HEAD(&ring->active_list); |
827 | INIT_LIST_HEAD(&ring->request_list); |
1010 | INIT_LIST_HEAD(&ring->request_list); |
828 | INIT_LIST_HEAD(&ring->gpu_write_list); |
1011 | INIT_LIST_HEAD(&ring->gpu_write_list); |
829 | 1012 | ||
830 | // init_waitqueue_head(&ring->irq_queue); |
1013 | // init_waitqueue_head(&ring->irq_queue); |
831 | // spin_lock_init(&ring->irq_lock); |
1014 | spin_lock_init(&ring->irq_lock); |
832 | ring->irq_mask = ~0; |
1015 | ring->irq_mask = ~0; |
833 | 1016 | ||
834 | if (I915_NEED_GFX_HWS(dev)) { |
1017 | if (I915_NEED_GFX_HWS(dev)) { |
835 | ret = init_status_page(ring); |
1018 | ret = init_status_page(ring); |
836 | if (ret) |
1019 | if (ret) |
837 | return ret; |
1020 | return ret; |
838 | } |
1021 | } |
839 | 1022 | ||
840 | obj = i915_gem_alloc_object(dev, ring->size); |
1023 | obj = i915_gem_alloc_object(dev, ring->size); |
841 | if (obj == NULL) { |
1024 | if (obj == NULL) { |
842 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
1025 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
843 | ret = -ENOMEM; |
1026 | ret = -ENOMEM; |
844 | goto err_hws; |
1027 | goto err_hws; |
845 | } |
1028 | } |
846 | 1029 | ||
847 | ring->obj = obj; |
1030 | ring->obj = obj; |
848 | 1031 | ||
849 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
1032 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
850 | if (ret) |
1033 | if (ret) |
851 | goto err_unref; |
1034 | goto err_unref; |
852 | 1035 | ||
853 | ring->map.size = ring->size; |
1036 | ring->map.size = ring->size; |
854 | ring->map.offset = get_bus_addr() + obj->gtt_offset; |
1037 | ring->map.offset = get_bus_addr() + obj->gtt_offset; |
855 | ring->map.type = 0; |
1038 | ring->map.type = 0; |
856 | ring->map.flags = 0; |
1039 | ring->map.flags = 0; |
857 | ring->map.mtrr = 0; |
1040 | ring->map.mtrr = 0; |
858 | 1041 | ||
859 | // drm_core_ioremap_wc(&ring->map, dev); |
1042 | // drm_core_ioremap_wc(&ring->map, dev); |
860 | 1043 | ||
861 | ring->map.handle = ioremap(ring->map.offset, ring->map.size); |
1044 | ring->map.handle = ioremap(ring->map.offset, ring->map.size); |
862 | 1045 | ||
863 | if (ring->map.handle == NULL) { |
1046 | if (ring->map.handle == NULL) { |
864 | DRM_ERROR("Failed to map ringbuffer.\n"); |
1047 | DRM_ERROR("Failed to map ringbuffer.\n"); |
865 | ret = -EINVAL; |
1048 | ret = -EINVAL; |
866 | goto err_unpin; |
1049 | goto err_unpin; |
867 | } |
1050 | } |
868 | 1051 | ||
869 | ring->virtual_start = ring->map.handle; |
1052 | ring->virtual_start = ring->map.handle; |
870 | ret = ring->init(ring); |
1053 | ret = ring->init(ring); |
871 | if (ret) |
1054 | if (ret) |
872 | goto err_unmap; |
1055 | goto err_unmap; |
873 | 1056 | ||
874 | /* Workaround an erratum on the i830 which causes a hang if |
1057 | /* Workaround an erratum on the i830 which causes a hang if |
875 | * the TAIL pointer points to within the last 2 cachelines |
1058 | * the TAIL pointer points to within the last 2 cachelines |
876 | * of the buffer. |
1059 | * of the buffer. |
877 | */ |
1060 | */ |
878 | ring->effective_size = ring->size; |
1061 | ring->effective_size = ring->size; |
879 | if (IS_I830(ring->dev)) |
1062 | if (IS_I830(ring->dev)) |
880 | ring->effective_size -= 128; |
1063 | ring->effective_size -= 128; |
881 | 1064 | ||
882 | return 0; |
1065 | return 0; |
883 | 1066 | ||
884 | err_unmap: |
1067 | err_unmap: |
885 | // drm_core_ioremapfree(&ring->map, dev); |
1068 | // drm_core_ioremapfree(&ring->map, dev); |
886 | FreeKernelSpace(ring->virtual_start); |
1069 | FreeKernelSpace(ring->virtual_start); |
887 | err_unpin: |
1070 | err_unpin: |
888 | // i915_gem_object_unpin(obj); |
1071 | // i915_gem_object_unpin(obj); |
889 | err_unref: |
1072 | err_unref: |
890 | // drm_gem_object_unreference(&obj->base); |
1073 | // drm_gem_object_unreference(&obj->base); |
891 | ring->obj = NULL; |
1074 | ring->obj = NULL; |
892 | err_hws: |
1075 | err_hws: |
893 | // cleanup_status_page(ring); |
1076 | // cleanup_status_page(ring); |
894 | return ret; |
1077 | return ret; |
895 | } |
1078 | } |
896 | 1079 | ||
897 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
1080 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
898 | { |
1081 | { |
899 | struct drm_i915_private *dev_priv; |
1082 | struct drm_i915_private *dev_priv; |
900 | int ret; |
1083 | int ret; |
901 | 1084 | ||
902 | if (ring->obj == NULL) |
1085 | if (ring->obj == NULL) |
903 | return; |
1086 | return; |
904 | 1087 | ||
905 | /* Disable the ring buffer. The ring must be idle at this point */ |
1088 | /* Disable the ring buffer. The ring must be idle at this point */ |
906 | dev_priv = ring->dev->dev_private; |
1089 | dev_priv = ring->dev->dev_private; |
907 | ret = intel_wait_ring_idle(ring); |
1090 | ret = intel_wait_ring_idle(ring); |
908 | if (ret) |
1091 | if (ret) |
909 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1092 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
910 | ring->name, ret); |
1093 | ring->name, ret); |
911 | 1094 | ||
912 | I915_WRITE_CTL(ring, 0); |
1095 | I915_WRITE_CTL(ring, 0); |
913 | 1096 | ||
914 | // drm_core_ioremapfree(&ring->map, ring->dev); |
1097 | // drm_core_ioremapfree(&ring->map, ring->dev); |
915 | 1098 | ||
916 | // i915_gem_object_unpin(ring->obj); |
1099 | // i915_gem_object_unpin(ring->obj); |
917 | // drm_gem_object_unreference(&ring->obj->base); |
1100 | // drm_gem_object_unreference(&ring->obj->base); |
918 | ring->obj = NULL; |
1101 | ring->obj = NULL; |
919 | 1102 | ||
920 | if (ring->cleanup) |
1103 | if (ring->cleanup) |
921 | ring->cleanup(ring); |
1104 | ring->cleanup(ring); |
922 | 1105 | ||
923 | // cleanup_status_page(ring); |
1106 | // cleanup_status_page(ring); |
924 | } |
1107 | } |
925 | 1108 | ||
926 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1109 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
927 | { |
1110 | { |
928 | unsigned int *virt; |
1111 | unsigned int *virt; |
929 | int rem = ring->size - ring->tail; |
1112 | int rem = ring->size - ring->tail; |
930 | 1113 | ||
931 | ENTER(); |
1114 | ENTER(); |
932 | 1115 | ||
933 | if (ring->space < rem) { |
1116 | if (ring->space < rem) { |
934 | int ret = intel_wait_ring_buffer(ring, rem); |
1117 | int ret = intel_wait_ring_buffer(ring, rem); |
935 | if (ret) |
1118 | if (ret) |
936 | return ret; |
1119 | return ret; |
937 | } |
1120 | } |
938 | 1121 | ||
939 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1122 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
940 | rem /= 8; |
1123 | rem /= 8; |
941 | while (rem--) { |
1124 | while (rem--) { |
942 | *virt++ = MI_NOOP; |
1125 | *virt++ = MI_NOOP; |
943 | *virt++ = MI_NOOP; |
1126 | *virt++ = MI_NOOP; |
944 | } |
1127 | } |
945 | 1128 | ||
946 | ring->tail = 0; |
1129 | ring->tail = 0; |
947 | ring->space = ring_space(ring); |
1130 | ring->space = ring_space(ring); |
948 | 1131 | ||
949 | LEAVE(); |
1132 | LEAVE(); |
950 | return 0; |
1133 | return 0; |
951 | } |
1134 | } |
952 | 1135 | ||
953 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
1136 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
954 | { |
1137 | { |
955 | struct drm_device *dev = ring->dev; |
1138 | struct drm_device *dev = ring->dev; |
956 | struct drm_i915_private *dev_priv = dev->dev_private; |
1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
957 | unsigned long end; |
1140 | unsigned long end; |
958 | u32 head; |
1141 | u32 head; |
959 | 1142 | ||
960 | ENTER(); |
1143 | ENTER(); |
961 | 1144 | ||
962 | /* If the reported head position has wrapped or hasn't advanced, |
1145 | /* If the reported head position has wrapped or hasn't advanced, |
963 | * fallback to the slow and accurate path. |
1146 | * fallback to the slow and accurate path. |
964 | */ |
1147 | */ |
965 | head = intel_read_status_page(ring, 4); |
1148 | head = intel_read_status_page(ring, 4); |
966 | if (head > ring->head) { |
1149 | if (head > ring->head) { |
967 | ring->head = head; |
1150 | ring->head = head; |
968 | ring->space = ring_space(ring); |
1151 | ring->space = ring_space(ring); |
969 | if (ring->space >= n) |
1152 | if (ring->space >= n) |
970 | { |
1153 | { |
971 | LEAVE(); |
1154 | LEAVE(); |
972 | return 0; |
1155 | return 0; |
973 | }; |
1156 | }; |
974 | } |
1157 | } |
975 | 1158 | ||
976 | // trace_i915_ring_wait_begin(ring); |
1159 | // trace_i915_ring_wait_begin(ring); |
977 | end = jiffies + 3 * HZ; |
1160 | end = jiffies + 3 * HZ; |
978 | do { |
1161 | do { |
979 | ring->head = I915_READ_HEAD(ring); |
1162 | ring->head = I915_READ_HEAD(ring); |
980 | ring->space = ring_space(ring); |
1163 | ring->space = ring_space(ring); |
981 | if (ring->space >= n) { |
1164 | if (ring->space >= n) { |
982 | // trace_i915_ring_wait_end(ring); |
1165 | // trace_i915_ring_wait_end(ring); |
983 | LEAVE(); |
1166 | LEAVE(); |
984 | return 0; |
1167 | return 0; |
985 | } |
1168 | } |
986 | 1169 | ||
987 | msleep(1); |
1170 | msleep(1); |
988 | if (atomic_read(&dev_priv->mm.wedged)) |
1171 | if (atomic_read(&dev_priv->mm.wedged)) |
989 | { |
1172 | { |
990 | LEAVE(); |
1173 | LEAVE(); |
991 | return -EAGAIN; |
1174 | return -EAGAIN; |
992 | }; |
1175 | }; |
993 | } while (!time_after(jiffies, end)); |
1176 | } while (!time_after(jiffies, end)); |
994 | // trace_i915_ring_wait_end(ring); |
1177 | // trace_i915_ring_wait_end(ring); |
995 | LEAVE(); |
1178 | LEAVE(); |
996 | 1179 | ||
997 | return -EBUSY; |
1180 | return -EBUSY; |
998 | } |
1181 | } |
999 | 1182 | ||
1000 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1183 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1001 | int num_dwords) |
1184 | int num_dwords) |
1002 | { |
1185 | { |
1003 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1186 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1004 | int n = 4*num_dwords; |
1187 | int n = 4*num_dwords; |
1005 | int ret; |
1188 | int ret; |
1006 | 1189 | ||
1007 | // if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
1190 | // if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
1008 | // return -EIO; |
1191 | // return -EIO; |
1009 | 1192 | ||
1010 | if (unlikely(ring->tail + n > ring->effective_size)) { |
1193 | if (unlikely(ring->tail + n > ring->effective_size)) { |
1011 | ret = intel_wrap_ring_buffer(ring); |
1194 | ret = intel_wrap_ring_buffer(ring); |
1012 | if (unlikely(ret)) |
1195 | if (unlikely(ret)) |
1013 | return ret; |
1196 | return ret; |
1014 | } |
1197 | } |
1015 | 1198 | ||
1016 | if (unlikely(ring->space < n)) { |
1199 | if (unlikely(ring->space < n)) { |
1017 | ret = intel_wait_ring_buffer(ring, n); |
1200 | ret = intel_wait_ring_buffer(ring, n); |
1018 | if (unlikely(ret)) |
1201 | if (unlikely(ret)) |
1019 | return ret; |
1202 | return ret; |
1020 | } |
1203 | } |
1021 | 1204 | ||
1022 | ring->space -= n; |
1205 | ring->space -= n; |
1023 | return 0; |
1206 | return 0; |
1024 | } |
1207 | } |
1025 | 1208 | ||
1026 | void intel_ring_advance(struct intel_ring_buffer *ring) |
1209 | void intel_ring_advance(struct intel_ring_buffer *ring) |
1027 | { |
1210 | { |
1028 | ring->tail &= ring->size - 1; |
1211 | ring->tail &= ring->size - 1; |
1029 | ring->write_tail(ring, ring->tail); |
1212 | ring->write_tail(ring, ring->tail); |
1030 | } |
1213 | } |
1031 | 1214 | ||
1032 | static const struct intel_ring_buffer render_ring = { |
1215 | static const struct intel_ring_buffer render_ring = { |
1033 | .name = "render ring", |
1216 | .name = "render ring", |
1034 | .id = RING_RENDER, |
1217 | .id = RING_RENDER, |
1035 | .mmio_base = RENDER_RING_BASE, |
1218 | .mmio_base = RENDER_RING_BASE, |
1036 | .size = 32 * PAGE_SIZE, |
1219 | .size = 32 * PAGE_SIZE, |
1037 | .init = init_render_ring, |
1220 | .init = init_render_ring, |
1038 | .write_tail = ring_write_tail, |
1221 | .write_tail = ring_write_tail, |
1039 | .flush = render_ring_flush, |
1222 | .flush = render_ring_flush, |
1040 | .add_request = render_ring_add_request, |
1223 | .add_request = render_ring_add_request, |
1041 | // .get_seqno = ring_get_seqno, |
1224 | .get_seqno = ring_get_seqno, |
1042 | // .irq_get = render_ring_get_irq, |
1225 | .irq_get = render_ring_get_irq, |
1043 | // .irq_put = render_ring_put_irq, |
1226 | .irq_put = render_ring_put_irq, |
1044 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
1227 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
1045 | // .cleanup = render_ring_cleanup, |
1228 | // .cleanup = render_ring_cleanup, |
- | 1229 | .sync_to = render_ring_sync_to, |
|
- | 1230 | .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID, |
|
- | 1231 | MI_SEMAPHORE_SYNC_RV, |
|
- | 1232 | MI_SEMAPHORE_SYNC_RB}, |
|
- | 1233 | .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC}, |
|
1046 | }; |
1234 | }; |
1047 | 1235 | ||
1048 | /* ring buffer for bit-stream decoder */ |
1236 | /* ring buffer for bit-stream decoder */ |
1049 | 1237 | ||
1050 | static const struct intel_ring_buffer bsd_ring = { |
1238 | static const struct intel_ring_buffer bsd_ring = { |
1051 | .name = "bsd ring", |
1239 | .name = "bsd ring", |
1052 | .id = RING_BSD, |
1240 | .id = RING_BSD, |
1053 | .mmio_base = BSD_RING_BASE, |
1241 | .mmio_base = BSD_RING_BASE, |
1054 | .size = 32 * PAGE_SIZE, |
1242 | .size = 32 * PAGE_SIZE, |
1055 | .init = init_ring_common, |
1243 | .init = init_ring_common, |
1056 | .write_tail = ring_write_tail, |
1244 | .write_tail = ring_write_tail, |
1057 | .flush = bsd_ring_flush, |
1245 | .flush = bsd_ring_flush, |
1058 | .add_request = ring_add_request, |
1246 | .add_request = ring_add_request, |
1059 | // .get_seqno = ring_get_seqno, |
1247 | .get_seqno = ring_get_seqno, |
1060 | // .irq_get = bsd_ring_get_irq, |
1248 | .irq_get = bsd_ring_get_irq, |
1061 | // .irq_put = bsd_ring_put_irq, |
1249 | .irq_put = bsd_ring_put_irq, |
1062 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
1250 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
1063 | }; |
1251 | }; |
1064 | 1252 | ||
1065 | 1253 | ||
1066 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
1254 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
1067 | u32 value) |
1255 | u32 value) |
1068 | { |
1256 | { |
1069 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1257 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
1070 | 1258 | ||
1071 | /* Every tail move must follow the sequence below */ |
1259 | /* Every tail move must follow the sequence below */ |
1072 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1260 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1073 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
1261 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
1074 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
1262 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
1075 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
1263 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
1076 | 1264 | ||
1077 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
1265 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
1078 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
1266 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
1079 | 50)) |
1267 | 50)) |
1080 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
1268 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
1081 | 1269 | ||
1082 | I915_WRITE_TAIL(ring, value); |
1270 | I915_WRITE_TAIL(ring, value); |
1083 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1271 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1084 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
1272 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
1085 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
1273 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
1086 | } |
1274 | } |
1087 | 1275 | ||
1088 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1276 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1089 | u32 invalidate, u32 flush) |
1277 | u32 invalidate, u32 flush) |
1090 | { |
1278 | { |
1091 | uint32_t cmd; |
1279 | uint32_t cmd; |
1092 | int ret; |
1280 | int ret; |
1093 | 1281 | ||
1094 | ret = intel_ring_begin(ring, 4); |
1282 | ret = intel_ring_begin(ring, 4); |
1095 | if (ret) |
1283 | if (ret) |
1096 | return ret; |
1284 | return ret; |
1097 | 1285 | ||
1098 | cmd = MI_FLUSH_DW; |
1286 | cmd = MI_FLUSH_DW; |
1099 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1287 | if (invalidate & I915_GEM_GPU_DOMAINS) |
1100 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1288 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1101 | intel_ring_emit(ring, cmd); |
1289 | intel_ring_emit(ring, cmd); |
1102 | intel_ring_emit(ring, 0); |
1290 | intel_ring_emit(ring, 0); |
1103 | intel_ring_emit(ring, 0); |
1291 | intel_ring_emit(ring, 0); |
1104 | intel_ring_emit(ring, MI_NOOP); |
1292 | intel_ring_emit(ring, MI_NOOP); |
1105 | intel_ring_advance(ring); |
1293 | intel_ring_advance(ring); |
1106 | return 0; |
1294 | return 0; |
1107 | } |
1295 | } |
1108 | 1296 | ||
1109 | static int |
1297 | static int |
1110 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1298 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1111 | u32 offset, u32 len) |
1299 | u32 offset, u32 len) |
1112 | { |
1300 | { |
1113 | int ret; |
1301 | int ret; |
1114 | 1302 | ||
1115 | ret = intel_ring_begin(ring, 2); |
1303 | ret = intel_ring_begin(ring, 2); |
1116 | if (ret) |
1304 | if (ret) |
1117 | return ret; |
1305 | return ret; |
1118 | 1306 | ||
1119 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1307 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1120 | /* bit0-7 is the length on GEN6+ */ |
1308 | /* bit0-7 is the length on GEN6+ */ |
1121 | intel_ring_emit(ring, offset); |
1309 | intel_ring_emit(ring, offset); |
1122 | intel_ring_advance(ring); |
1310 | intel_ring_advance(ring); |
1123 | 1311 | ||
1124 | return 0; |
1312 | return 0; |
1125 | } |
1313 | } |
1126 | - | ||
1127 | #if 0 |
- | |
1128 | 1314 | ||
1129 | static bool |
1315 | static bool |
1130 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
1316 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
1131 | { |
1317 | { |
1132 | return gen6_ring_get_irq(ring, |
1318 | return gen6_ring_get_irq(ring, |
1133 | GT_USER_INTERRUPT, |
1319 | GT_USER_INTERRUPT, |
1134 | GEN6_RENDER_USER_INTERRUPT); |
1320 | GEN6_RENDER_USER_INTERRUPT); |
1135 | } |
1321 | } |
1136 | 1322 | ||
1137 | static void |
1323 | static void |
1138 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
1324 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
1139 | { |
1325 | { |
1140 | return gen6_ring_put_irq(ring, |
1326 | return gen6_ring_put_irq(ring, |
1141 | GT_USER_INTERRUPT, |
1327 | GT_USER_INTERRUPT, |
1142 | GEN6_RENDER_USER_INTERRUPT); |
1328 | GEN6_RENDER_USER_INTERRUPT); |
1143 | } |
1329 | } |
1144 | 1330 | ||
1145 | static bool |
1331 | static bool |
1146 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
1332 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
1147 | { |
1333 | { |
1148 | return gen6_ring_get_irq(ring, |
1334 | return gen6_ring_get_irq(ring, |
1149 | GT_GEN6_BSD_USER_INTERRUPT, |
1335 | GT_GEN6_BSD_USER_INTERRUPT, |
1150 | GEN6_BSD_USER_INTERRUPT); |
1336 | GEN6_BSD_USER_INTERRUPT); |
1151 | } |
1337 | } |
1152 | 1338 | ||
1153 | static void |
1339 | static void |
1154 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
1340 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
1155 | { |
1341 | { |
1156 | return gen6_ring_put_irq(ring, |
1342 | return gen6_ring_put_irq(ring, |
1157 | GT_GEN6_BSD_USER_INTERRUPT, |
1343 | GT_GEN6_BSD_USER_INTERRUPT, |
1158 | GEN6_BSD_USER_INTERRUPT); |
1344 | GEN6_BSD_USER_INTERRUPT); |
1159 | } |
1345 | } |
1160 | - | ||
1161 | #endif |
- | |
1162 | 1346 | ||
1163 | /* ring buffer for Video Codec for Gen6+ */ |
1347 | /* ring buffer for Video Codec for Gen6+ */ |
1164 | static const struct intel_ring_buffer gen6_bsd_ring = { |
1348 | static const struct intel_ring_buffer gen6_bsd_ring = { |
1165 | .name = "gen6 bsd ring", |
1349 | .name = "gen6 bsd ring", |
1166 | .id = RING_BSD, |
1350 | .id = RING_BSD, |
1167 | .mmio_base = GEN6_BSD_RING_BASE, |
1351 | .mmio_base = GEN6_BSD_RING_BASE, |
1168 | .size = 32 * PAGE_SIZE, |
1352 | .size = 32 * PAGE_SIZE, |
1169 | .init = init_ring_common, |
1353 | .init = init_ring_common, |
1170 | .write_tail = gen6_bsd_ring_write_tail, |
1354 | .write_tail = gen6_bsd_ring_write_tail, |
1171 | .flush = gen6_ring_flush, |
1355 | .flush = gen6_ring_flush, |
1172 | .add_request = gen6_add_request, |
1356 | .add_request = gen6_add_request, |
1173 | // .get_seqno = ring_get_seqno, |
1357 | .get_seqno = gen6_ring_get_seqno, |
1174 | // .irq_get = gen6_bsd_ring_get_irq, |
1358 | .irq_get = gen6_bsd_ring_get_irq, |
1175 | // .irq_put = gen6_bsd_ring_put_irq, |
1359 | .irq_put = gen6_bsd_ring_put_irq, |
1176 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
1360 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
- | 1361 | .sync_to = gen6_bsd_ring_sync_to, |
|
- | 1362 | .semaphore_register = {MI_SEMAPHORE_SYNC_VR, |
|
- | 1363 | MI_SEMAPHORE_SYNC_INVALID, |
|
- | 1364 | MI_SEMAPHORE_SYNC_VB}, |
|
- | 1365 | .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC}, |
|
1177 | }; |
1366 | }; |
1178 | - | ||
1179 | #if 0 |
1367 | |
1180 | /* Blitter support (SandyBridge+) */ |
1368 | /* Blitter support (SandyBridge+) */ |
1181 | 1369 | ||
1182 | static bool |
1370 | static bool |
1183 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
1371 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
1184 | { |
1372 | { |
1185 | return gen6_ring_get_irq(ring, |
1373 | return gen6_ring_get_irq(ring, |
1186 | GT_BLT_USER_INTERRUPT, |
1374 | GT_BLT_USER_INTERRUPT, |
1187 | GEN6_BLITTER_USER_INTERRUPT); |
1375 | GEN6_BLITTER_USER_INTERRUPT); |
1188 | } |
1376 | } |
1189 | 1377 | ||
1190 | static void |
1378 | static void |
1191 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
1379 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
1192 | { |
1380 | { |
1193 | gen6_ring_put_irq(ring, |
1381 | gen6_ring_put_irq(ring, |
1194 | GT_BLT_USER_INTERRUPT, |
1382 | GT_BLT_USER_INTERRUPT, |
1195 | GEN6_BLITTER_USER_INTERRUPT); |
1383 | GEN6_BLITTER_USER_INTERRUPT); |
1196 | } |
1384 | } |
1197 | #endif |
- | |
1198 | 1385 | ||
1199 | 1386 | ||
1200 | /* Workaround for some stepping of SNB, |
1387 | /* Workaround for some stepping of SNB, |
1201 | * each time when BLT engine ring tail moved, |
1388 | * each time when BLT engine ring tail moved, |
1202 | * the first command in the ring to be parsed |
1389 | * the first command in the ring to be parsed |
1203 | * should be MI_BATCH_BUFFER_START |
1390 | * should be MI_BATCH_BUFFER_START |
1204 | */ |
1391 | */ |
1205 | #define NEED_BLT_WORKAROUND(dev) \ |
1392 | #define NEED_BLT_WORKAROUND(dev) \ |
1206 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
1393 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) |
1207 | 1394 | ||
1208 | static inline struct drm_i915_gem_object * |
1395 | static inline struct drm_i915_gem_object * |
1209 | to_blt_workaround(struct intel_ring_buffer *ring) |
1396 | to_blt_workaround(struct intel_ring_buffer *ring) |
1210 | { |
1397 | { |
1211 | return ring->private; |
1398 | return ring->private; |
1212 | } |
1399 | } |
1213 | 1400 | ||
1214 | static int blt_ring_init(struct intel_ring_buffer *ring) |
1401 | static int blt_ring_init(struct intel_ring_buffer *ring) |
1215 | { |
1402 | { |
1216 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
1403 | if (NEED_BLT_WORKAROUND(ring->dev)) { |
1217 | struct drm_i915_gem_object *obj; |
1404 | struct drm_i915_gem_object *obj; |
1218 | u32 *ptr; |
1405 | u32 *ptr; |
1219 | int ret; |
1406 | int ret; |
1220 | 1407 | ||
1221 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1408 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1222 | if (obj == NULL) |
1409 | if (obj == NULL) |
1223 | return -ENOMEM; |
1410 | return -ENOMEM; |
1224 | 1411 | ||
1225 | ret = i915_gem_object_pin(obj, 4096, true); |
1412 | ret = i915_gem_object_pin(obj, 4096, true); |
1226 | if (ret) { |
1413 | if (ret) { |
1227 | // drm_gem_object_unreference(&obj->base); |
1414 | // drm_gem_object_unreference(&obj->base); |
1228 | return ret; |
1415 | return ret; |
1229 | } |
1416 | } |
1230 | 1417 | ||
1231 | ptr = ioremap(obj->pages[0], 4096); |
1418 | ptr = ioremap(obj->pages[0], 4096); |
1232 | *ptr++ = MI_BATCH_BUFFER_END; |
1419 | *ptr++ = MI_BATCH_BUFFER_END; |
1233 | *ptr++ = MI_NOOP; |
1420 | *ptr++ = MI_NOOP; |
1234 | // iounmap(obj->pages[0]); |
1421 | // iounmap(obj->pages[0]); |
1235 | 1422 | ||
1236 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
1423 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
1237 | if (ret) { |
1424 | if (ret) { |
1238 | // i915_gem_object_unpin(obj); |
1425 | // i915_gem_object_unpin(obj); |
1239 | // drm_gem_object_unreference(&obj->base); |
1426 | // drm_gem_object_unreference(&obj->base); |
1240 | return ret; |
1427 | return ret; |
1241 | } |
1428 | } |
1242 | 1429 | ||
1243 | ring->private = obj; |
1430 | ring->private = obj; |
1244 | } |
1431 | } |
1245 | 1432 | ||
1246 | return init_ring_common(ring); |
1433 | return init_ring_common(ring); |
1247 | } |
1434 | } |
1248 | 1435 | ||
1249 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
1436 | static int blt_ring_begin(struct intel_ring_buffer *ring, |
1250 | int num_dwords) |
1437 | int num_dwords) |
1251 | { |
1438 | { |
1252 | if (ring->private) { |
1439 | if (ring->private) { |
1253 | int ret = intel_ring_begin(ring, num_dwords+2); |
1440 | int ret = intel_ring_begin(ring, num_dwords+2); |
1254 | if (ret) |
1441 | if (ret) |
1255 | return ret; |
1442 | return ret; |
1256 | 1443 | ||
1257 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
1444 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
1258 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
1445 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
1259 | 1446 | ||
1260 | return 0; |
1447 | return 0; |
1261 | } else |
1448 | } else |
1262 | return intel_ring_begin(ring, 4); |
1449 | return intel_ring_begin(ring, 4); |
1263 | } |
1450 | } |
1264 | 1451 | ||
1265 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
1452 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
1266 | u32 invalidate, u32 flush) |
1453 | u32 invalidate, u32 flush) |
1267 | { |
1454 | { |
1268 | uint32_t cmd; |
1455 | uint32_t cmd; |
1269 | int ret; |
1456 | int ret; |
1270 | 1457 | ||
1271 | ret = blt_ring_begin(ring, 4); |
1458 | ret = blt_ring_begin(ring, 4); |
1272 | if (ret) |
1459 | if (ret) |
1273 | return ret; |
1460 | return ret; |
1274 | 1461 | ||
1275 | cmd = MI_FLUSH_DW; |
1462 | cmd = MI_FLUSH_DW; |
1276 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1463 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
1277 | cmd |= MI_INVALIDATE_TLB; |
1464 | cmd |= MI_INVALIDATE_TLB; |
1278 | intel_ring_emit(ring, cmd); |
1465 | intel_ring_emit(ring, cmd); |
1279 | intel_ring_emit(ring, 0); |
1466 | intel_ring_emit(ring, 0); |
1280 | intel_ring_emit(ring, 0); |
1467 | intel_ring_emit(ring, 0); |
1281 | intel_ring_emit(ring, MI_NOOP); |
1468 | intel_ring_emit(ring, MI_NOOP); |
1282 | intel_ring_advance(ring); |
1469 | intel_ring_advance(ring); |
1283 | return 0; |
1470 | return 0; |
1284 | } |
1471 | } |
1285 | 1472 | ||
1286 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
1473 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
1287 | { |
1474 | { |
1288 | if (!ring->private) |
1475 | if (!ring->private) |
1289 | return; |
1476 | return; |
1290 | 1477 | ||
1291 | i915_gem_object_unpin(ring->private); |
1478 | i915_gem_object_unpin(ring->private); |
1292 | drm_gem_object_unreference(ring->private); |
1479 | drm_gem_object_unreference(ring->private); |
1293 | ring->private = NULL; |
1480 | ring->private = NULL; |
1294 | } |
1481 | } |
1295 | 1482 | ||
1296 | static const struct intel_ring_buffer gen6_blt_ring = { |
1483 | static const struct intel_ring_buffer gen6_blt_ring = { |
1297 | .name = "blt ring", |
1484 | .name = "blt ring", |
1298 | .id = RING_BLT, |
1485 | .id = RING_BLT, |
1299 | .mmio_base = BLT_RING_BASE, |
1486 | .mmio_base = BLT_RING_BASE, |
1300 | .size = 32 * PAGE_SIZE, |
1487 | .size = 32 * PAGE_SIZE, |
1301 | .init = blt_ring_init, |
1488 | .init = blt_ring_init, |
1302 | .write_tail = ring_write_tail, |
1489 | .write_tail = ring_write_tail, |
1303 | .flush = blt_ring_flush, |
1490 | .flush = blt_ring_flush, |
1304 | .add_request = gen6_add_request, |
1491 | .add_request = gen6_add_request, |
1305 | // .get_seqno = ring_get_seqno, |
1492 | .get_seqno = gen6_ring_get_seqno, |
1306 | // .irq_get = blt_ring_get_irq, |
1493 | .irq_get = blt_ring_get_irq, |
1307 | // .irq_put = blt_ring_put_irq, |
1494 | .irq_put = blt_ring_put_irq, |
1308 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
1495 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
1309 | // .cleanup = blt_ring_cleanup, |
1496 | // .cleanup = blt_ring_cleanup, |
- | 1497 | .sync_to = gen6_blt_ring_sync_to, |
|
- | 1498 | .semaphore_register = {MI_SEMAPHORE_SYNC_BR, |
|
- | 1499 | MI_SEMAPHORE_SYNC_BV, |
|
- | 1500 | MI_SEMAPHORE_SYNC_INVALID}, |
|
- | 1501 | .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC}, |
|
1310 | }; |
1502 | }; |
1311 | 1503 | ||
1312 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1504 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1313 | { |
1505 | { |
1314 | drm_i915_private_t *dev_priv = dev->dev_private; |
1506 | drm_i915_private_t *dev_priv = dev->dev_private; |
1315 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
1507 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
1316 | 1508 | ||
1317 | *ring = render_ring; |
1509 | *ring = render_ring; |
1318 | if (INTEL_INFO(dev)->gen >= 6) { |
1510 | if (INTEL_INFO(dev)->gen >= 6) { |
1319 | ring->add_request = gen6_add_request; |
1511 | ring->add_request = gen6_add_request; |
- | 1512 | ring->flush = gen6_render_ring_flush; |
|
1320 | // ring->irq_get = gen6_render_ring_get_irq; |
1513 | ring->irq_get = gen6_render_ring_get_irq; |
1321 | // ring->irq_put = gen6_render_ring_put_irq; |
1514 | ring->irq_put = gen6_render_ring_put_irq; |
- | 1515 | ring->get_seqno = gen6_ring_get_seqno; |
|
1322 | } else if (IS_GEN5(dev)) { |
1516 | } else if (IS_GEN5(dev)) { |
1323 | ring->add_request = pc_render_add_request; |
1517 | ring->add_request = pc_render_add_request; |
1324 | // ring->get_seqno = pc_render_get_seqno; |
1518 | ring->get_seqno = pc_render_get_seqno; |
1325 | } |
1519 | } |
1326 | 1520 | ||
1327 | if (!I915_NEED_GFX_HWS(dev)) { |
1521 | if (!I915_NEED_GFX_HWS(dev)) { |
1328 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1522 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1329 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
1523 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
1330 | } |
1524 | } |
1331 | 1525 | ||
1332 | return intel_init_ring_buffer(dev, ring); |
1526 | return intel_init_ring_buffer(dev, ring); |
1333 | } |
1527 | } |
1334 | 1528 | ||
1335 | 1529 | ||
1336 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1530 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1337 | { |
1531 | { |
1338 | drm_i915_private_t *dev_priv = dev->dev_private; |
1532 | drm_i915_private_t *dev_priv = dev->dev_private; |
1339 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
1533 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
1340 | 1534 | ||
1341 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
1535 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
1342 | *ring = gen6_bsd_ring; |
1536 | *ring = gen6_bsd_ring; |
1343 | else |
1537 | else |
1344 | *ring = bsd_ring; |
1538 | *ring = bsd_ring; |
1345 | 1539 | ||
1346 | return intel_init_ring_buffer(dev, ring); |
1540 | return intel_init_ring_buffer(dev, ring); |
1347 | } |
1541 | } |
1348 | 1542 | ||
1349 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
1543 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
1350 | { |
1544 | { |
1351 | drm_i915_private_t *dev_priv = dev->dev_private; |
1545 | drm_i915_private_t *dev_priv = dev->dev_private; |
1352 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
1546 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
1353 | 1547 | ||
1354 | *ring = gen6_blt_ring; |
1548 | *ring = gen6_blt_ring; |
1355 | 1549 | ||
1356 | return intel_init_ring_buffer(dev, ring); |
1550 | return intel_init_ring_buffer(dev, ring); |
1357 | }>>>><>><>><>><>><>><>><>><>><>>> |
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