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1 | /* |
1 | /* |
2 | * Copyright 2006 Dave Airlie |
2 | * Copyright 2006 Dave Airlie |
3 | * Copyright © 2006-2009 Intel Corporation |
3 | * Copyright © 2006-2009 Intel Corporation |
4 | * |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
11 | * |
12 | * The above copyright notice and this permission notice (including the next |
12 | * The above copyright notice and this permission notice (including the next |
13 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * Software. |
14 | * Software. |
15 | * |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. |
22 | * DEALINGS IN THE SOFTWARE. |
23 | * |
23 | * |
24 | * Authors: |
24 | * Authors: |
25 | * Eric Anholt |
25 | * Eric Anholt |
26 | * Jesse Barnes |
26 | * Jesse Barnes |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include |
36 | #include |
37 | #include "intel_drv.h" |
37 | #include "intel_drv.h" |
38 | #include |
38 | #include |
39 | #include "i915_drv.h" |
39 | #include "i915_drv.h" |
40 | 40 | ||
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { |
42 | { |
43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
44 | } |
44 | } |
45 | 45 | ||
46 | static void |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
48 | { |
48 | { |
49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; |
51 | uint32_t enabled_bits; |
52 | 52 | ||
53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
54 | 54 | ||
55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
56 | "HDMI port enabled, expecting disabled\n"); |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } |
57 | } |
58 | 58 | ||
59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
60 | { |
60 | { |
61 | struct intel_digital_port *intel_dig_port = |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); |
62 | container_of(encoder, struct intel_digital_port, base.base); |
63 | return &intel_dig_port->hdmi; |
63 | return &intel_dig_port->hdmi; |
64 | } |
64 | } |
65 | 65 | ||
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { |
67 | { |
68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
69 | } |
69 | } |
70 | 70 | ||
71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
72 | { |
72 | { |
73 | switch (type) { |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: |
74 | case HDMI_INFOFRAME_TYPE_AVI: |
75 | return VIDEO_DIP_SELECT_AVI; |
75 | return VIDEO_DIP_SELECT_AVI; |
76 | case HDMI_INFOFRAME_TYPE_SPD: |
76 | case HDMI_INFOFRAME_TYPE_SPD: |
77 | return VIDEO_DIP_SELECT_SPD; |
77 | return VIDEO_DIP_SELECT_SPD; |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; |
79 | return VIDEO_DIP_SELECT_VENDOR; |
80 | default: |
80 | default: |
81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
82 | return 0; |
82 | return 0; |
83 | } |
83 | } |
84 | } |
84 | } |
85 | 85 | ||
86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
87 | { |
87 | { |
88 | switch (type) { |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: |
89 | case HDMI_INFOFRAME_TYPE_AVI: |
90 | return VIDEO_DIP_ENABLE_AVI; |
90 | return VIDEO_DIP_ENABLE_AVI; |
91 | case HDMI_INFOFRAME_TYPE_SPD: |
91 | case HDMI_INFOFRAME_TYPE_SPD: |
92 | return VIDEO_DIP_ENABLE_SPD; |
92 | return VIDEO_DIP_ENABLE_SPD; |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; |
94 | return VIDEO_DIP_ENABLE_VENDOR; |
95 | default: |
95 | default: |
96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
97 | return 0; |
97 | return 0; |
98 | } |
98 | } |
99 | } |
99 | } |
100 | 100 | ||
101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
102 | { |
102 | { |
103 | switch (type) { |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: |
104 | case HDMI_INFOFRAME_TYPE_AVI: |
105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
106 | case HDMI_INFOFRAME_TYPE_SPD: |
106 | case HDMI_INFOFRAME_TYPE_SPD: |
107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; |
109 | return VIDEO_DIP_ENABLE_VS_HSW; |
110 | default: |
110 | default: |
111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
112 | return 0; |
112 | return 0; |
113 | } |
113 | } |
114 | } |
114 | } |
115 | 115 | ||
116 | static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, |
116 | static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv, |
117 | enum transcoder cpu_transcoder, |
117 | enum transcoder cpu_transcoder, |
118 | enum hdmi_infoframe_type type, |
118 | enum hdmi_infoframe_type type, |
119 | int i) |
119 | int i) |
120 | { |
120 | { |
121 | switch (type) { |
121 | switch (type) { |
122 | case HDMI_INFOFRAME_TYPE_AVI: |
122 | case HDMI_INFOFRAME_TYPE_AVI: |
123 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
123 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
124 | case HDMI_INFOFRAME_TYPE_SPD: |
124 | case HDMI_INFOFRAME_TYPE_SPD: |
125 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
125 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
126 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | case HDMI_INFOFRAME_TYPE_VENDOR: |
127 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
127 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
128 | default: |
128 | default: |
129 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
129 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
130 | return 0; |
130 | return 0; |
131 | } |
131 | } |
132 | } |
132 | } |
133 | 133 | ||
134 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
134 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
135 | enum hdmi_infoframe_type type, |
135 | enum hdmi_infoframe_type type, |
136 | const void *frame, ssize_t len) |
136 | const void *frame, ssize_t len) |
137 | { |
137 | { |
138 | const uint32_t *data = frame; |
138 | const uint32_t *data = frame; |
139 | struct drm_device *dev = encoder->dev; |
139 | struct drm_device *dev = encoder->dev; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
140 | struct drm_i915_private *dev_priv = dev->dev_private; |
141 | u32 val = I915_READ(VIDEO_DIP_CTL); |
141 | u32 val = I915_READ(VIDEO_DIP_CTL); |
142 | int i; |
142 | int i; |
143 | 143 | ||
144 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
145 | 145 | ||
146 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
146 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
147 | val |= g4x_infoframe_index(type); |
147 | val |= g4x_infoframe_index(type); |
148 | 148 | ||
149 | val &= ~g4x_infoframe_enable(type); |
149 | val &= ~g4x_infoframe_enable(type); |
150 | 150 | ||
151 | I915_WRITE(VIDEO_DIP_CTL, val); |
151 | I915_WRITE(VIDEO_DIP_CTL, val); |
152 | 152 | ||
153 | mmiowb(); |
153 | mmiowb(); |
154 | for (i = 0; i < len; i += 4) { |
154 | for (i = 0; i < len; i += 4) { |
155 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | I915_WRITE(VIDEO_DIP_DATA, *data); |
156 | data++; |
156 | data++; |
157 | } |
157 | } |
158 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | /* Write every possible data byte to force correct ECC calculation. */ |
159 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
159 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
160 | I915_WRITE(VIDEO_DIP_DATA, 0); |
160 | I915_WRITE(VIDEO_DIP_DATA, 0); |
161 | mmiowb(); |
161 | mmiowb(); |
162 | 162 | ||
163 | val |= g4x_infoframe_enable(type); |
163 | val |= g4x_infoframe_enable(type); |
164 | val &= ~VIDEO_DIP_FREQ_MASK; |
164 | val &= ~VIDEO_DIP_FREQ_MASK; |
165 | val |= VIDEO_DIP_FREQ_VSYNC; |
165 | val |= VIDEO_DIP_FREQ_VSYNC; |
166 | 166 | ||
167 | I915_WRITE(VIDEO_DIP_CTL, val); |
167 | I915_WRITE(VIDEO_DIP_CTL, val); |
168 | POSTING_READ(VIDEO_DIP_CTL); |
168 | POSTING_READ(VIDEO_DIP_CTL); |
169 | } |
169 | } |
170 | 170 | ||
171 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
172 | { |
172 | { |
173 | struct drm_device *dev = encoder->dev; |
173 | struct drm_device *dev = encoder->dev; |
174 | struct drm_i915_private *dev_priv = dev->dev_private; |
174 | struct drm_i915_private *dev_priv = dev->dev_private; |
175 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
175 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
176 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | u32 val = I915_READ(VIDEO_DIP_CTL); |
177 | 177 | ||
178 | if ((val & VIDEO_DIP_ENABLE) == 0) |
178 | if ((val & VIDEO_DIP_ENABLE) == 0) |
179 | return false; |
179 | return false; |
180 | 180 | ||
181 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
181 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
182 | return false; |
182 | return false; |
183 | 183 | ||
184 | return val & (VIDEO_DIP_ENABLE_AVI | |
184 | return val & (VIDEO_DIP_ENABLE_AVI | |
185 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
185 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
186 | } |
186 | } |
187 | 187 | ||
188 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
188 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
189 | enum hdmi_infoframe_type type, |
189 | enum hdmi_infoframe_type type, |
190 | const void *frame, ssize_t len) |
190 | const void *frame, ssize_t len) |
191 | { |
191 | { |
192 | const uint32_t *data = frame; |
192 | const uint32_t *data = frame; |
193 | struct drm_device *dev = encoder->dev; |
193 | struct drm_device *dev = encoder->dev; |
194 | struct drm_i915_private *dev_priv = dev->dev_private; |
194 | struct drm_i915_private *dev_priv = dev->dev_private; |
195 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
195 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
196 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
196 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
197 | u32 val = I915_READ(reg); |
197 | u32 val = I915_READ(reg); |
198 | 198 | ||
199 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
199 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
200 | 200 | ||
201 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
201 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
202 | val |= g4x_infoframe_index(type); |
202 | val |= g4x_infoframe_index(type); |
203 | 203 | ||
204 | val &= ~g4x_infoframe_enable(type); |
204 | val &= ~g4x_infoframe_enable(type); |
205 | 205 | ||
206 | I915_WRITE(reg, val); |
206 | I915_WRITE(reg, val); |
207 | 207 | ||
208 | mmiowb(); |
208 | mmiowb(); |
209 | for (i = 0; i < len; i += 4) { |
209 | for (i = 0; i < len; i += 4) { |
210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
211 | data++; |
211 | data++; |
212 | } |
212 | } |
213 | /* Write every possible data byte to force correct ECC calculation. */ |
213 | /* Write every possible data byte to force correct ECC calculation. */ |
214 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
214 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
215 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
215 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
216 | mmiowb(); |
216 | mmiowb(); |
217 | 217 | ||
218 | val |= g4x_infoframe_enable(type); |
218 | val |= g4x_infoframe_enable(type); |
219 | val &= ~VIDEO_DIP_FREQ_MASK; |
219 | val &= ~VIDEO_DIP_FREQ_MASK; |
220 | val |= VIDEO_DIP_FREQ_VSYNC; |
220 | val |= VIDEO_DIP_FREQ_VSYNC; |
221 | 221 | ||
222 | I915_WRITE(reg, val); |
222 | I915_WRITE(reg, val); |
223 | POSTING_READ(reg); |
223 | POSTING_READ(reg); |
224 | } |
224 | } |
225 | 225 | ||
226 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
226 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
227 | { |
227 | { |
228 | struct drm_device *dev = encoder->dev; |
228 | struct drm_device *dev = encoder->dev; |
229 | struct drm_i915_private *dev_priv = dev->dev_private; |
229 | struct drm_i915_private *dev_priv = dev->dev_private; |
230 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
230 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
231 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
231 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
232 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
232 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
233 | u32 val = I915_READ(reg); |
233 | u32 val = I915_READ(reg); |
234 | 234 | ||
235 | if ((val & VIDEO_DIP_ENABLE) == 0) |
235 | if ((val & VIDEO_DIP_ENABLE) == 0) |
236 | return false; |
236 | return false; |
237 | 237 | ||
238 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
238 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
239 | return false; |
239 | return false; |
240 | 240 | ||
241 | return val & (VIDEO_DIP_ENABLE_AVI | |
241 | return val & (VIDEO_DIP_ENABLE_AVI | |
242 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
242 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
243 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
243 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
244 | } |
244 | } |
245 | 245 | ||
246 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
246 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
247 | enum hdmi_infoframe_type type, |
247 | enum hdmi_infoframe_type type, |
248 | const void *frame, ssize_t len) |
248 | const void *frame, ssize_t len) |
249 | { |
249 | { |
250 | const uint32_t *data = frame; |
250 | const uint32_t *data = frame; |
251 | struct drm_device *dev = encoder->dev; |
251 | struct drm_device *dev = encoder->dev; |
252 | struct drm_i915_private *dev_priv = dev->dev_private; |
252 | struct drm_i915_private *dev_priv = dev->dev_private; |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
254 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
254 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
255 | u32 val = I915_READ(reg); |
255 | u32 val = I915_READ(reg); |
256 | 256 | ||
257 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
257 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
258 | 258 | ||
259 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
259 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
260 | val |= g4x_infoframe_index(type); |
260 | val |= g4x_infoframe_index(type); |
261 | 261 | ||
262 | /* The DIP control register spec says that we need to update the AVI |
262 | /* The DIP control register spec says that we need to update the AVI |
263 | * infoframe without clearing its enable bit */ |
263 | * infoframe without clearing its enable bit */ |
264 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
264 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
265 | val &= ~g4x_infoframe_enable(type); |
265 | val &= ~g4x_infoframe_enable(type); |
266 | 266 | ||
267 | I915_WRITE(reg, val); |
267 | I915_WRITE(reg, val); |
268 | 268 | ||
269 | mmiowb(); |
269 | mmiowb(); |
270 | for (i = 0; i < len; i += 4) { |
270 | for (i = 0; i < len; i += 4) { |
271 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
271 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
272 | data++; |
272 | data++; |
273 | } |
273 | } |
274 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | /* Write every possible data byte to force correct ECC calculation. */ |
275 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
275 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
276 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
276 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
277 | mmiowb(); |
277 | mmiowb(); |
278 | 278 | ||
279 | val |= g4x_infoframe_enable(type); |
279 | val |= g4x_infoframe_enable(type); |
280 | val &= ~VIDEO_DIP_FREQ_MASK; |
280 | val &= ~VIDEO_DIP_FREQ_MASK; |
281 | val |= VIDEO_DIP_FREQ_VSYNC; |
281 | val |= VIDEO_DIP_FREQ_VSYNC; |
282 | 282 | ||
283 | I915_WRITE(reg, val); |
283 | I915_WRITE(reg, val); |
284 | POSTING_READ(reg); |
284 | POSTING_READ(reg); |
285 | } |
285 | } |
286 | 286 | ||
287 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
287 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
288 | { |
288 | { |
289 | struct drm_device *dev = encoder->dev; |
289 | struct drm_device *dev = encoder->dev; |
290 | struct drm_i915_private *dev_priv = dev->dev_private; |
290 | struct drm_i915_private *dev_priv = dev->dev_private; |
291 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
291 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
292 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
292 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
293 | u32 val = I915_READ(reg); |
293 | u32 val = I915_READ(reg); |
294 | 294 | ||
295 | if ((val & VIDEO_DIP_ENABLE) == 0) |
295 | if ((val & VIDEO_DIP_ENABLE) == 0) |
296 | return false; |
296 | return false; |
297 | 297 | ||
298 | return val & (VIDEO_DIP_ENABLE_AVI | |
298 | return val & (VIDEO_DIP_ENABLE_AVI | |
299 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
299 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
300 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
300 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
301 | } |
301 | } |
302 | 302 | ||
303 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
303 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
304 | enum hdmi_infoframe_type type, |
304 | enum hdmi_infoframe_type type, |
305 | const void *frame, ssize_t len) |
305 | const void *frame, ssize_t len) |
306 | { |
306 | { |
307 | const uint32_t *data = frame; |
307 | const uint32_t *data = frame; |
308 | struct drm_device *dev = encoder->dev; |
308 | struct drm_device *dev = encoder->dev; |
309 | struct drm_i915_private *dev_priv = dev->dev_private; |
309 | struct drm_i915_private *dev_priv = dev->dev_private; |
310 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
310 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
311 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
311 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
312 | u32 val = I915_READ(reg); |
312 | u32 val = I915_READ(reg); |
313 | 313 | ||
314 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
314 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
315 | 315 | ||
316 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
316 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
317 | val |= g4x_infoframe_index(type); |
317 | val |= g4x_infoframe_index(type); |
318 | 318 | ||
319 | val &= ~g4x_infoframe_enable(type); |
319 | val &= ~g4x_infoframe_enable(type); |
320 | 320 | ||
321 | I915_WRITE(reg, val); |
321 | I915_WRITE(reg, val); |
322 | 322 | ||
323 | mmiowb(); |
323 | mmiowb(); |
324 | for (i = 0; i < len; i += 4) { |
324 | for (i = 0; i < len; i += 4) { |
325 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
325 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
326 | data++; |
326 | data++; |
327 | } |
327 | } |
328 | /* Write every possible data byte to force correct ECC calculation. */ |
328 | /* Write every possible data byte to force correct ECC calculation. */ |
329 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
329 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
330 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
330 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
331 | mmiowb(); |
331 | mmiowb(); |
332 | 332 | ||
333 | val |= g4x_infoframe_enable(type); |
333 | val |= g4x_infoframe_enable(type); |
334 | val &= ~VIDEO_DIP_FREQ_MASK; |
334 | val &= ~VIDEO_DIP_FREQ_MASK; |
335 | val |= VIDEO_DIP_FREQ_VSYNC; |
335 | val |= VIDEO_DIP_FREQ_VSYNC; |
336 | 336 | ||
337 | I915_WRITE(reg, val); |
337 | I915_WRITE(reg, val); |
338 | POSTING_READ(reg); |
338 | POSTING_READ(reg); |
339 | } |
339 | } |
340 | 340 | ||
341 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
341 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
342 | { |
342 | { |
343 | struct drm_device *dev = encoder->dev; |
343 | struct drm_device *dev = encoder->dev; |
344 | struct drm_i915_private *dev_priv = dev->dev_private; |
344 | struct drm_i915_private *dev_priv = dev->dev_private; |
345 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
345 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
346 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
346 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
347 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
347 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
348 | u32 val = I915_READ(reg); |
348 | u32 val = I915_READ(reg); |
349 | 349 | ||
350 | if ((val & VIDEO_DIP_ENABLE) == 0) |
350 | if ((val & VIDEO_DIP_ENABLE) == 0) |
351 | return false; |
351 | return false; |
352 | 352 | ||
353 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
353 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
354 | return false; |
354 | return false; |
355 | 355 | ||
356 | return val & (VIDEO_DIP_ENABLE_AVI | |
356 | return val & (VIDEO_DIP_ENABLE_AVI | |
357 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
357 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
358 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
358 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
359 | } |
359 | } |
360 | 360 | ||
361 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
361 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
362 | enum hdmi_infoframe_type type, |
362 | enum hdmi_infoframe_type type, |
363 | const void *frame, ssize_t len) |
363 | const void *frame, ssize_t len) |
364 | { |
364 | { |
365 | const uint32_t *data = frame; |
365 | const uint32_t *data = frame; |
366 | struct drm_device *dev = encoder->dev; |
366 | struct drm_device *dev = encoder->dev; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; |
368 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
368 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
369 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
369 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
370 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
370 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
371 | u32 data_reg; |
371 | u32 data_reg; |
372 | int i; |
372 | int i; |
373 | u32 val = I915_READ(ctl_reg); |
373 | u32 val = I915_READ(ctl_reg); |
374 | 374 | ||
375 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
375 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
376 | if (data_reg == 0) |
376 | if (data_reg == 0) |
377 | return; |
377 | return; |
378 | 378 | ||
379 | val &= ~hsw_infoframe_enable(type); |
379 | val &= ~hsw_infoframe_enable(type); |
380 | I915_WRITE(ctl_reg, val); |
380 | I915_WRITE(ctl_reg, val); |
381 | 381 | ||
382 | mmiowb(); |
382 | mmiowb(); |
383 | for (i = 0; i < len; i += 4) { |
383 | for (i = 0; i < len; i += 4) { |
384 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
384 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
385 | type, i >> 2), *data); |
385 | type, i >> 2), *data); |
386 | data++; |
386 | data++; |
387 | } |
387 | } |
388 | /* Write every possible data byte to force correct ECC calculation. */ |
388 | /* Write every possible data byte to force correct ECC calculation. */ |
389 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
389 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), 0); |
391 | type, i >> 2), 0); |
392 | mmiowb(); |
392 | mmiowb(); |
393 | 393 | ||
394 | val |= hsw_infoframe_enable(type); |
394 | val |= hsw_infoframe_enable(type); |
395 | I915_WRITE(ctl_reg, val); |
395 | I915_WRITE(ctl_reg, val); |
396 | POSTING_READ(ctl_reg); |
396 | POSTING_READ(ctl_reg); |
397 | } |
397 | } |
398 | 398 | ||
399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
400 | { |
400 | { |
401 | struct drm_device *dev = encoder->dev; |
401 | struct drm_device *dev = encoder->dev; |
402 | struct drm_i915_private *dev_priv = dev->dev_private; |
402 | struct drm_i915_private *dev_priv = dev->dev_private; |
403 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
403 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
404 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
404 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
405 | u32 val = I915_READ(ctl_reg); |
405 | u32 val = I915_READ(ctl_reg); |
406 | 406 | ||
407 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
407 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
408 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
408 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
409 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
409 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
410 | } |
410 | } |
411 | 411 | ||
412 | /* |
412 | /* |
413 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
413 | * The data we write to the DIP data buffer registers is 1 byte bigger than the |
414 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
414 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting |
415 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
415 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be |
416 | * used for both technologies. |
416 | * used for both technologies. |
417 | * |
417 | * |
418 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 |
418 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 |
419 | * DW1: DB3 | DB2 | DB1 | DB0 |
419 | * DW1: DB3 | DB2 | DB1 | DB0 |
420 | * DW2: DB7 | DB6 | DB5 | DB4 |
420 | * DW2: DB7 | DB6 | DB5 | DB4 |
421 | * DW3: ... |
421 | * DW3: ... |
422 | * |
422 | * |
423 | * (HB is Header Byte, DB is Data Byte) |
423 | * (HB is Header Byte, DB is Data Byte) |
424 | * |
424 | * |
425 | * The hdmi pack() functions don't know about that hardware specific hole so we |
425 | * The hdmi pack() functions don't know about that hardware specific hole so we |
426 | * trick them by giving an offset into the buffer and moving back the header |
426 | * trick them by giving an offset into the buffer and moving back the header |
427 | * bytes by one. |
427 | * bytes by one. |
428 | */ |
428 | */ |
429 | static void intel_write_infoframe(struct drm_encoder *encoder, |
429 | static void intel_write_infoframe(struct drm_encoder *encoder, |
430 | union hdmi_infoframe *frame) |
430 | union hdmi_infoframe *frame) |
431 | { |
431 | { |
432 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
432 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
433 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
433 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
434 | ssize_t len; |
434 | ssize_t len; |
435 | 435 | ||
436 | /* see comment above for the reason for this offset */ |
436 | /* see comment above for the reason for this offset */ |
437 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); |
437 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); |
438 | if (len < 0) |
438 | if (len < 0) |
439 | return; |
439 | return; |
440 | 440 | ||
441 | /* Insert the 'hole' (see big comment above) at position 3 */ |
441 | /* Insert the 'hole' (see big comment above) at position 3 */ |
442 | buffer[0] = buffer[1]; |
442 | buffer[0] = buffer[1]; |
443 | buffer[1] = buffer[2]; |
443 | buffer[1] = buffer[2]; |
444 | buffer[2] = buffer[3]; |
444 | buffer[2] = buffer[3]; |
445 | buffer[3] = 0; |
445 | buffer[3] = 0; |
446 | len++; |
446 | len++; |
447 | 447 | ||
448 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
448 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
449 | } |
449 | } |
450 | 450 | ||
451 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
451 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
452 | const struct drm_display_mode *adjusted_mode) |
452 | const struct drm_display_mode *adjusted_mode) |
453 | { |
453 | { |
454 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
454 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
455 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
455 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
456 | union hdmi_infoframe frame; |
456 | union hdmi_infoframe frame; |
457 | int ret; |
457 | int ret; |
458 | 458 | ||
459 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
459 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
460 | adjusted_mode); |
460 | adjusted_mode); |
461 | if (ret < 0) { |
461 | if (ret < 0) { |
462 | DRM_ERROR("couldn't fill AVI infoframe\n"); |
462 | DRM_ERROR("couldn't fill AVI infoframe\n"); |
463 | return; |
463 | return; |
464 | } |
464 | } |
465 | 465 | ||
466 | if (intel_hdmi->rgb_quant_range_selectable) { |
466 | if (intel_hdmi->rgb_quant_range_selectable) { |
467 | if (intel_crtc->config->limited_color_range) |
467 | if (intel_crtc->config->limited_color_range) |
468 | frame.avi.quantization_range = |
468 | frame.avi.quantization_range = |
469 | HDMI_QUANTIZATION_RANGE_LIMITED; |
469 | HDMI_QUANTIZATION_RANGE_LIMITED; |
470 | else |
470 | else |
471 | frame.avi.quantization_range = |
471 | frame.avi.quantization_range = |
472 | HDMI_QUANTIZATION_RANGE_FULL; |
472 | HDMI_QUANTIZATION_RANGE_FULL; |
473 | } |
473 | } |
474 | 474 | ||
475 | intel_write_infoframe(encoder, &frame); |
475 | intel_write_infoframe(encoder, &frame); |
476 | } |
476 | } |
477 | 477 | ||
478 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
478 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
479 | { |
479 | { |
480 | union hdmi_infoframe frame; |
480 | union hdmi_infoframe frame; |
481 | int ret; |
481 | int ret; |
482 | 482 | ||
483 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); |
483 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); |
484 | if (ret < 0) { |
484 | if (ret < 0) { |
485 | DRM_ERROR("couldn't fill SPD infoframe\n"); |
485 | DRM_ERROR("couldn't fill SPD infoframe\n"); |
486 | return; |
486 | return; |
487 | } |
487 | } |
488 | 488 | ||
489 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
489 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
490 | 490 | ||
491 | intel_write_infoframe(encoder, &frame); |
491 | intel_write_infoframe(encoder, &frame); |
492 | } |
492 | } |
493 | 493 | ||
494 | static void |
494 | static void |
495 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, |
495 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, |
496 | const struct drm_display_mode *adjusted_mode) |
496 | const struct drm_display_mode *adjusted_mode) |
497 | { |
497 | { |
498 | union hdmi_infoframe frame; |
498 | union hdmi_infoframe frame; |
499 | int ret; |
499 | int ret; |
500 | 500 | ||
501 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, |
501 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, |
502 | adjusted_mode); |
502 | adjusted_mode); |
503 | if (ret < 0) |
503 | if (ret < 0) |
504 | return; |
504 | return; |
505 | 505 | ||
506 | intel_write_infoframe(encoder, &frame); |
506 | intel_write_infoframe(encoder, &frame); |
507 | } |
507 | } |
508 | 508 | ||
509 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
509 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
510 | bool enable, |
510 | bool enable, |
511 | const struct drm_display_mode *adjusted_mode) |
511 | const struct drm_display_mode *adjusted_mode) |
512 | { |
512 | { |
513 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
513 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
514 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
514 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
515 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
515 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
516 | u32 reg = VIDEO_DIP_CTL; |
516 | u32 reg = VIDEO_DIP_CTL; |
517 | u32 val = I915_READ(reg); |
517 | u32 val = I915_READ(reg); |
518 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
518 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
519 | 519 | ||
520 | assert_hdmi_port_disabled(intel_hdmi); |
520 | assert_hdmi_port_disabled(intel_hdmi); |
521 | 521 | ||
522 | /* If the registers were not initialized yet, they might be zeroes, |
522 | /* If the registers were not initialized yet, they might be zeroes, |
523 | * which means we're selecting the AVI DIP and we're setting its |
523 | * which means we're selecting the AVI DIP and we're setting its |
524 | * frequency to once. This seems to really confuse the HW and make |
524 | * frequency to once. This seems to really confuse the HW and make |
525 | * things stop working (the register spec says the AVI always needs to |
525 | * things stop working (the register spec says the AVI always needs to |
526 | * be sent every VSync). So here we avoid writing to the register more |
526 | * be sent every VSync). So here we avoid writing to the register more |
527 | * than we need and also explicitly select the AVI DIP and explicitly |
527 | * than we need and also explicitly select the AVI DIP and explicitly |
528 | * set its frequency to every VSync. Avoiding to write it twice seems to |
528 | * set its frequency to every VSync. Avoiding to write it twice seems to |
529 | * be enough to solve the problem, but being defensive shouldn't hurt us |
529 | * be enough to solve the problem, but being defensive shouldn't hurt us |
530 | * either. */ |
530 | * either. */ |
531 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
531 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
532 | 532 | ||
533 | if (!enable) { |
533 | if (!enable) { |
534 | if (!(val & VIDEO_DIP_ENABLE)) |
534 | if (!(val & VIDEO_DIP_ENABLE)) |
535 | return; |
535 | return; |
536 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
536 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
537 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", |
537 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", |
538 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
538 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
539 | return; |
539 | return; |
540 | } |
540 | } |
541 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
541 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
542 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
542 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
543 | I915_WRITE(reg, val); |
543 | I915_WRITE(reg, val); |
544 | POSTING_READ(reg); |
544 | POSTING_READ(reg); |
545 | return; |
545 | return; |
546 | } |
546 | } |
547 | 547 | ||
548 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
548 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
549 | if (val & VIDEO_DIP_ENABLE) { |
549 | if (val & VIDEO_DIP_ENABLE) { |
550 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
550 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
551 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
551 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
552 | return; |
552 | return; |
553 | } |
553 | } |
554 | val &= ~VIDEO_DIP_PORT_MASK; |
554 | val &= ~VIDEO_DIP_PORT_MASK; |
555 | val |= port; |
555 | val |= port; |
556 | } |
556 | } |
557 | 557 | ||
558 | val |= VIDEO_DIP_ENABLE; |
558 | val |= VIDEO_DIP_ENABLE; |
559 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
559 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
560 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
560 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); |
561 | 561 | ||
562 | I915_WRITE(reg, val); |
562 | I915_WRITE(reg, val); |
563 | POSTING_READ(reg); |
563 | POSTING_READ(reg); |
564 | 564 | ||
565 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
565 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
566 | intel_hdmi_set_spd_infoframe(encoder); |
566 | intel_hdmi_set_spd_infoframe(encoder); |
567 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
567 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
568 | } |
568 | } |
569 | 569 | ||
570 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
570 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
571 | { |
571 | { |
572 | struct drm_device *dev = encoder->dev; |
572 | struct drm_device *dev = encoder->dev; |
573 | struct drm_connector *connector; |
573 | struct drm_connector *connector; |
574 | 574 | ||
575 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
575 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
576 | 576 | ||
577 | /* |
577 | /* |
578 | * HDMI cloning is only supported on g4x which doesn't |
578 | * HDMI cloning is only supported on g4x which doesn't |
579 | * support deep color or GCP infoframes anyway so no |
579 | * support deep color or GCP infoframes anyway so no |
580 | * need to worry about multiple HDMI sinks here. |
580 | * need to worry about multiple HDMI sinks here. |
581 | */ |
581 | */ |
582 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
582 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
583 | if (connector->encoder == encoder) |
583 | if (connector->encoder == encoder) |
584 | return connector->display_info.bpc > 8; |
584 | return connector->display_info.bpc > 8; |
585 | 585 | ||
586 | return false; |
586 | return false; |
587 | } |
587 | } |
588 | 588 | ||
589 | /* |
589 | /* |
590 | * Determine if default_phase=1 can be indicated in the GCP infoframe. |
590 | * Determine if default_phase=1 can be indicated in the GCP infoframe. |
591 | * |
591 | * |
592 | * From HDMI specification 1.4a: |
592 | * From HDMI specification 1.4a: |
593 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 |
593 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 |
594 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 |
594 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 |
595 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase |
595 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase |
596 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing |
596 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing |
597 | * phase of 0 |
597 | * phase of 0 |
598 | */ |
598 | */ |
599 | static bool gcp_default_phase_possible(int pipe_bpp, |
599 | static bool gcp_default_phase_possible(int pipe_bpp, |
600 | const struct drm_display_mode *mode) |
600 | const struct drm_display_mode *mode) |
601 | { |
601 | { |
602 | unsigned int pixels_per_group; |
602 | unsigned int pixels_per_group; |
603 | 603 | ||
604 | switch (pipe_bpp) { |
604 | switch (pipe_bpp) { |
605 | case 30: |
605 | case 30: |
606 | /* 4 pixels in 5 clocks */ |
606 | /* 4 pixels in 5 clocks */ |
607 | pixels_per_group = 4; |
607 | pixels_per_group = 4; |
608 | break; |
608 | break; |
609 | case 36: |
609 | case 36: |
610 | /* 2 pixels in 3 clocks */ |
610 | /* 2 pixels in 3 clocks */ |
611 | pixels_per_group = 2; |
611 | pixels_per_group = 2; |
612 | break; |
612 | break; |
613 | case 48: |
613 | case 48: |
614 | /* 1 pixel in 2 clocks */ |
614 | /* 1 pixel in 2 clocks */ |
615 | pixels_per_group = 1; |
615 | pixels_per_group = 1; |
616 | break; |
616 | break; |
617 | default: |
617 | default: |
618 | /* phase information not relevant for 8bpc */ |
618 | /* phase information not relevant for 8bpc */ |
619 | return false; |
619 | return false; |
620 | } |
620 | } |
621 | 621 | ||
622 | return mode->crtc_hdisplay % pixels_per_group == 0 && |
622 | return mode->crtc_hdisplay % pixels_per_group == 0 && |
623 | mode->crtc_htotal % pixels_per_group == 0 && |
623 | mode->crtc_htotal % pixels_per_group == 0 && |
624 | mode->crtc_hblank_start % pixels_per_group == 0 && |
624 | mode->crtc_hblank_start % pixels_per_group == 0 && |
625 | mode->crtc_hblank_end % pixels_per_group == 0 && |
625 | mode->crtc_hblank_end % pixels_per_group == 0 && |
626 | mode->crtc_hsync_start % pixels_per_group == 0 && |
626 | mode->crtc_hsync_start % pixels_per_group == 0 && |
627 | mode->crtc_hsync_end % pixels_per_group == 0 && |
627 | mode->crtc_hsync_end % pixels_per_group == 0 && |
628 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || |
628 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || |
629 | mode->crtc_htotal/2 % pixels_per_group == 0); |
629 | mode->crtc_htotal/2 % pixels_per_group == 0); |
630 | } |
630 | } |
631 | 631 | ||
632 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
632 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
633 | { |
633 | { |
634 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
634 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
635 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
635 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
636 | u32 reg, val = 0; |
636 | u32 reg, val = 0; |
637 | 637 | ||
638 | if (HAS_DDI(dev_priv)) |
638 | if (HAS_DDI(dev_priv)) |
639 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); |
639 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); |
640 | else if (IS_VALLEYVIEW(dev_priv)) |
640 | else if (IS_VALLEYVIEW(dev_priv)) |
641 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
641 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
642 | else if (HAS_PCH_SPLIT(dev_priv->dev)) |
642 | else if (HAS_PCH_SPLIT(dev_priv->dev)) |
643 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
643 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
644 | else |
644 | else |
645 | return false; |
645 | return false; |
646 | 646 | ||
647 | /* Indicate color depth whenever the sink supports deep color */ |
647 | /* Indicate color depth whenever the sink supports deep color */ |
648 | if (hdmi_sink_is_deep_color(encoder)) |
648 | if (hdmi_sink_is_deep_color(encoder)) |
649 | val |= GCP_COLOR_INDICATION; |
649 | val |= GCP_COLOR_INDICATION; |
650 | 650 | ||
651 | /* Enable default_phase whenever the display mode is suitably aligned */ |
651 | /* Enable default_phase whenever the display mode is suitably aligned */ |
652 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, |
652 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, |
653 | &crtc->config->base.adjusted_mode)) |
653 | &crtc->config->base.adjusted_mode)) |
654 | val |= GCP_DEFAULT_PHASE_ENABLE; |
654 | val |= GCP_DEFAULT_PHASE_ENABLE; |
655 | 655 | ||
656 | I915_WRITE(reg, val); |
656 | I915_WRITE(reg, val); |
657 | 657 | ||
658 | return val != 0; |
658 | return val != 0; |
659 | } |
659 | } |
660 | 660 | ||
661 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
661 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
662 | bool enable, |
662 | bool enable, |
663 | const struct drm_display_mode *adjusted_mode) |
663 | const struct drm_display_mode *adjusted_mode) |
664 | { |
664 | { |
665 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
665 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
666 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
666 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
667 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
667 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
668 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
668 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
669 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
669 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
670 | u32 val = I915_READ(reg); |
670 | u32 val = I915_READ(reg); |
671 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
671 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
672 | 672 | ||
673 | assert_hdmi_port_disabled(intel_hdmi); |
673 | assert_hdmi_port_disabled(intel_hdmi); |
674 | 674 | ||
675 | /* See the big comment in g4x_set_infoframes() */ |
675 | /* See the big comment in g4x_set_infoframes() */ |
676 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
676 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
677 | 677 | ||
678 | if (!enable) { |
678 | if (!enable) { |
679 | if (!(val & VIDEO_DIP_ENABLE)) |
679 | if (!(val & VIDEO_DIP_ENABLE)) |
680 | return; |
680 | return; |
681 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
681 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
682 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
682 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
683 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
683 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
684 | I915_WRITE(reg, val); |
684 | I915_WRITE(reg, val); |
685 | POSTING_READ(reg); |
685 | POSTING_READ(reg); |
686 | return; |
686 | return; |
687 | } |
687 | } |
688 | 688 | ||
689 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
689 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
690 | WARN(val & VIDEO_DIP_ENABLE, |
690 | WARN(val & VIDEO_DIP_ENABLE, |
691 | "DIP already enabled on port %c\n", |
691 | "DIP already enabled on port %c\n", |
692 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
692 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
693 | val &= ~VIDEO_DIP_PORT_MASK; |
693 | val &= ~VIDEO_DIP_PORT_MASK; |
694 | val |= port; |
694 | val |= port; |
695 | } |
695 | } |
696 | 696 | ||
697 | val |= VIDEO_DIP_ENABLE; |
697 | val |= VIDEO_DIP_ENABLE; |
698 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
698 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
699 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
699 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
700 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
700 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
701 | 701 | ||
702 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
702 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
703 | val |= VIDEO_DIP_ENABLE_GCP; |
703 | val |= VIDEO_DIP_ENABLE_GCP; |
704 | 704 | ||
705 | I915_WRITE(reg, val); |
705 | I915_WRITE(reg, val); |
706 | POSTING_READ(reg); |
706 | POSTING_READ(reg); |
707 | 707 | ||
708 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
708 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
709 | intel_hdmi_set_spd_infoframe(encoder); |
709 | intel_hdmi_set_spd_infoframe(encoder); |
710 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
710 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
711 | } |
711 | } |
712 | 712 | ||
713 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
713 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
714 | bool enable, |
714 | bool enable, |
715 | const struct drm_display_mode *adjusted_mode) |
715 | const struct drm_display_mode *adjusted_mode) |
716 | { |
716 | { |
717 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
717 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
718 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
718 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
719 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
719 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
720 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
720 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
721 | u32 val = I915_READ(reg); |
721 | u32 val = I915_READ(reg); |
722 | 722 | ||
723 | assert_hdmi_port_disabled(intel_hdmi); |
723 | assert_hdmi_port_disabled(intel_hdmi); |
724 | 724 | ||
725 | /* See the big comment in g4x_set_infoframes() */ |
725 | /* See the big comment in g4x_set_infoframes() */ |
726 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
726 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
727 | 727 | ||
728 | if (!enable) { |
728 | if (!enable) { |
729 | if (!(val & VIDEO_DIP_ENABLE)) |
729 | if (!(val & VIDEO_DIP_ENABLE)) |
730 | return; |
730 | return; |
731 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
731 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
732 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
732 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
733 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
733 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
734 | I915_WRITE(reg, val); |
734 | I915_WRITE(reg, val); |
735 | POSTING_READ(reg); |
735 | POSTING_READ(reg); |
736 | return; |
736 | return; |
737 | } |
737 | } |
738 | 738 | ||
739 | /* Set both together, unset both together: see the spec. */ |
739 | /* Set both together, unset both together: see the spec. */ |
740 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
740 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
741 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
741 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
742 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
742 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
743 | 743 | ||
744 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
744 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
745 | val |= VIDEO_DIP_ENABLE_GCP; |
745 | val |= VIDEO_DIP_ENABLE_GCP; |
746 | 746 | ||
747 | I915_WRITE(reg, val); |
747 | I915_WRITE(reg, val); |
748 | POSTING_READ(reg); |
748 | POSTING_READ(reg); |
749 | 749 | ||
750 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
750 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
751 | intel_hdmi_set_spd_infoframe(encoder); |
751 | intel_hdmi_set_spd_infoframe(encoder); |
752 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
752 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
753 | } |
753 | } |
754 | 754 | ||
755 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
755 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
756 | bool enable, |
756 | bool enable, |
757 | const struct drm_display_mode *adjusted_mode) |
757 | const struct drm_display_mode *adjusted_mode) |
758 | { |
758 | { |
759 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
759 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
760 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
760 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
761 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
762 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
762 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
763 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
763 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
764 | u32 val = I915_READ(reg); |
764 | u32 val = I915_READ(reg); |
765 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
765 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
766 | 766 | ||
767 | assert_hdmi_port_disabled(intel_hdmi); |
767 | assert_hdmi_port_disabled(intel_hdmi); |
768 | 768 | ||
769 | /* See the big comment in g4x_set_infoframes() */ |
769 | /* See the big comment in g4x_set_infoframes() */ |
770 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
770 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
771 | 771 | ||
772 | if (!enable) { |
772 | if (!enable) { |
773 | if (!(val & VIDEO_DIP_ENABLE)) |
773 | if (!(val & VIDEO_DIP_ENABLE)) |
774 | return; |
774 | return; |
775 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
775 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
776 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
776 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
777 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
777 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
778 | I915_WRITE(reg, val); |
778 | I915_WRITE(reg, val); |
779 | POSTING_READ(reg); |
779 | POSTING_READ(reg); |
780 | return; |
780 | return; |
781 | } |
781 | } |
782 | 782 | ||
783 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
783 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
784 | WARN(val & VIDEO_DIP_ENABLE, |
784 | WARN(val & VIDEO_DIP_ENABLE, |
785 | "DIP already enabled on port %c\n", |
785 | "DIP already enabled on port %c\n", |
786 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
786 | (val & VIDEO_DIP_PORT_MASK) >> 29); |
787 | val &= ~VIDEO_DIP_PORT_MASK; |
787 | val &= ~VIDEO_DIP_PORT_MASK; |
788 | val |= port; |
788 | val |= port; |
789 | } |
789 | } |
790 | 790 | ||
791 | val |= VIDEO_DIP_ENABLE; |
791 | val |= VIDEO_DIP_ENABLE; |
792 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
792 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
793 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
793 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
794 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
794 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
795 | 795 | ||
796 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
796 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
797 | val |= VIDEO_DIP_ENABLE_GCP; |
797 | val |= VIDEO_DIP_ENABLE_GCP; |
798 | 798 | ||
799 | I915_WRITE(reg, val); |
799 | I915_WRITE(reg, val); |
800 | POSTING_READ(reg); |
800 | POSTING_READ(reg); |
801 | 801 | ||
802 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
802 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
803 | intel_hdmi_set_spd_infoframe(encoder); |
803 | intel_hdmi_set_spd_infoframe(encoder); |
804 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
804 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
805 | } |
805 | } |
806 | 806 | ||
807 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
807 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
808 | bool enable, |
808 | bool enable, |
809 | const struct drm_display_mode *adjusted_mode) |
809 | const struct drm_display_mode *adjusted_mode) |
810 | { |
810 | { |
811 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
811 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
813 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
814 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
814 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
815 | u32 val = I915_READ(reg); |
815 | u32 val = I915_READ(reg); |
816 | 816 | ||
817 | assert_hdmi_port_disabled(intel_hdmi); |
817 | assert_hdmi_port_disabled(intel_hdmi); |
818 | 818 | ||
819 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
819 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
820 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
820 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | |
821 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
821 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); |
822 | 822 | ||
823 | if (!enable) { |
823 | if (!enable) { |
824 | I915_WRITE(reg, val); |
824 | I915_WRITE(reg, val); |
825 | POSTING_READ(reg); |
825 | POSTING_READ(reg); |
826 | return; |
826 | return; |
827 | } |
827 | } |
828 | 828 | ||
829 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
829 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
830 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
830 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
831 | 831 | ||
832 | I915_WRITE(reg, val); |
832 | I915_WRITE(reg, val); |
833 | POSTING_READ(reg); |
833 | POSTING_READ(reg); |
834 | 834 | ||
835 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
835 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
836 | intel_hdmi_set_spd_infoframe(encoder); |
836 | intel_hdmi_set_spd_infoframe(encoder); |
837 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
837 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
838 | } |
838 | } |
839 | 839 | ||
840 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
840 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
841 | { |
841 | { |
842 | struct drm_device *dev = encoder->base.dev; |
842 | struct drm_device *dev = encoder->base.dev; |
843 | struct drm_i915_private *dev_priv = dev->dev_private; |
843 | struct drm_i915_private *dev_priv = dev->dev_private; |
844 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
844 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
845 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
845 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
846 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
846 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
847 | u32 hdmi_val; |
847 | u32 hdmi_val; |
848 | 848 | ||
849 | hdmi_val = SDVO_ENCODING_HDMI; |
849 | hdmi_val = SDVO_ENCODING_HDMI; |
850 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
850 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
851 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
851 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
853 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
853 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
854 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
854 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
855 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
855 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
856 | 856 | ||
857 | if (crtc->config->pipe_bpp > 24) |
857 | if (crtc->config->pipe_bpp > 24) |
858 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
858 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
859 | else |
859 | else |
860 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
860 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
861 | 861 | ||
862 | if (crtc->config->has_hdmi_sink) |
862 | if (crtc->config->has_hdmi_sink) |
863 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
863 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
864 | 864 | ||
865 | if (HAS_PCH_CPT(dev)) |
865 | if (HAS_PCH_CPT(dev)) |
866 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
866 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
867 | else if (IS_CHERRYVIEW(dev)) |
867 | else if (IS_CHERRYVIEW(dev)) |
868 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
868 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
869 | else |
869 | else |
870 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
870 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
871 | 871 | ||
872 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
872 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
873 | POSTING_READ(intel_hdmi->hdmi_reg); |
873 | POSTING_READ(intel_hdmi->hdmi_reg); |
874 | } |
874 | } |
875 | 875 | ||
876 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
876 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
877 | enum pipe *pipe) |
877 | enum pipe *pipe) |
878 | { |
878 | { |
879 | struct drm_device *dev = encoder->base.dev; |
879 | struct drm_device *dev = encoder->base.dev; |
880 | struct drm_i915_private *dev_priv = dev->dev_private; |
880 | struct drm_i915_private *dev_priv = dev->dev_private; |
881 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
881 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
882 | enum intel_display_power_domain power_domain; |
882 | enum intel_display_power_domain power_domain; |
883 | u32 tmp; |
883 | u32 tmp; |
884 | 884 | ||
885 | power_domain = intel_display_port_power_domain(encoder); |
885 | power_domain = intel_display_port_power_domain(encoder); |
886 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
886 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
887 | return false; |
887 | return false; |
888 | 888 | ||
889 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
889 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
890 | 890 | ||
891 | if (!(tmp & SDVO_ENABLE)) |
891 | if (!(tmp & SDVO_ENABLE)) |
892 | return false; |
892 | return false; |
893 | 893 | ||
894 | if (HAS_PCH_CPT(dev)) |
894 | if (HAS_PCH_CPT(dev)) |
895 | *pipe = PORT_TO_PIPE_CPT(tmp); |
895 | *pipe = PORT_TO_PIPE_CPT(tmp); |
896 | else if (IS_CHERRYVIEW(dev)) |
896 | else if (IS_CHERRYVIEW(dev)) |
897 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
897 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
898 | else |
898 | else |
899 | *pipe = PORT_TO_PIPE(tmp); |
899 | *pipe = PORT_TO_PIPE(tmp); |
900 | 900 | ||
901 | return true; |
901 | return true; |
902 | } |
902 | } |
903 | 903 | ||
904 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
904 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
905 | struct intel_crtc_state *pipe_config) |
905 | struct intel_crtc_state *pipe_config) |
906 | { |
906 | { |
907 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
907 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
908 | struct drm_device *dev = encoder->base.dev; |
908 | struct drm_device *dev = encoder->base.dev; |
909 | struct drm_i915_private *dev_priv = dev->dev_private; |
909 | struct drm_i915_private *dev_priv = dev->dev_private; |
910 | u32 tmp, flags = 0; |
910 | u32 tmp, flags = 0; |
911 | int dotclock; |
911 | int dotclock; |
912 | 912 | ||
913 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
913 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
914 | 914 | ||
915 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) |
915 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) |
916 | flags |= DRM_MODE_FLAG_PHSYNC; |
916 | flags |= DRM_MODE_FLAG_PHSYNC; |
917 | else |
917 | else |
918 | flags |= DRM_MODE_FLAG_NHSYNC; |
918 | flags |= DRM_MODE_FLAG_NHSYNC; |
919 | 919 | ||
920 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) |
920 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) |
921 | flags |= DRM_MODE_FLAG_PVSYNC; |
921 | flags |= DRM_MODE_FLAG_PVSYNC; |
922 | else |
922 | else |
923 | flags |= DRM_MODE_FLAG_NVSYNC; |
923 | flags |= DRM_MODE_FLAG_NVSYNC; |
924 | 924 | ||
925 | if (tmp & HDMI_MODE_SELECT_HDMI) |
925 | if (tmp & HDMI_MODE_SELECT_HDMI) |
926 | pipe_config->has_hdmi_sink = true; |
926 | pipe_config->has_hdmi_sink = true; |
927 | 927 | ||
928 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
928 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
929 | pipe_config->has_infoframe = true; |
929 | pipe_config->has_infoframe = true; |
930 | 930 | ||
931 | if (tmp & SDVO_AUDIO_ENABLE) |
931 | if (tmp & SDVO_AUDIO_ENABLE) |
932 | pipe_config->has_audio = true; |
932 | pipe_config->has_audio = true; |
933 | 933 | ||
934 | if (!HAS_PCH_SPLIT(dev) && |
934 | if (!HAS_PCH_SPLIT(dev) && |
935 | tmp & HDMI_COLOR_RANGE_16_235) |
935 | tmp & HDMI_COLOR_RANGE_16_235) |
936 | pipe_config->limited_color_range = true; |
936 | pipe_config->limited_color_range = true; |
937 | 937 | ||
938 | pipe_config->base.adjusted_mode.flags |= flags; |
938 | pipe_config->base.adjusted_mode.flags |= flags; |
939 | 939 | ||
940 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) |
940 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) |
941 | dotclock = pipe_config->port_clock * 2 / 3; |
941 | dotclock = pipe_config->port_clock * 2 / 3; |
942 | else |
942 | else |
943 | dotclock = pipe_config->port_clock; |
943 | dotclock = pipe_config->port_clock; |
944 | 944 | ||
945 | if (pipe_config->pixel_multiplier) |
945 | if (pipe_config->pixel_multiplier) |
946 | dotclock /= pipe_config->pixel_multiplier; |
946 | dotclock /= pipe_config->pixel_multiplier; |
947 | 947 | ||
948 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
948 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
949 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
949 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
950 | 950 | ||
951 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
951 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
952 | } |
952 | } |
953 | 953 | ||
954 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
954 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
955 | { |
955 | { |
956 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
956 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
957 | 957 | ||
958 | WARN_ON(!crtc->config->has_hdmi_sink); |
958 | WARN_ON(!crtc->config->has_hdmi_sink); |
959 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
959 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
960 | pipe_name(crtc->pipe)); |
960 | pipe_name(crtc->pipe)); |
961 | intel_audio_codec_enable(encoder); |
961 | intel_audio_codec_enable(encoder); |
962 | } |
962 | } |
963 | 963 | ||
964 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
964 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
965 | { |
965 | { |
966 | struct drm_device *dev = encoder->base.dev; |
966 | struct drm_device *dev = encoder->base.dev; |
967 | struct drm_i915_private *dev_priv = dev->dev_private; |
967 | struct drm_i915_private *dev_priv = dev->dev_private; |
968 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
968 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
969 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
969 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
970 | u32 temp; |
970 | u32 temp; |
971 | 971 | ||
972 | temp = I915_READ(intel_hdmi->hdmi_reg); |
972 | temp = I915_READ(intel_hdmi->hdmi_reg); |
973 | 973 | ||
974 | temp |= SDVO_ENABLE; |
974 | temp |= SDVO_ENABLE; |
975 | if (crtc->config->has_audio) |
975 | if (crtc->config->has_audio) |
976 | temp |= SDVO_AUDIO_ENABLE; |
976 | temp |= SDVO_AUDIO_ENABLE; |
977 | 977 | ||
978 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
978 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
979 | POSTING_READ(intel_hdmi->hdmi_reg); |
979 | POSTING_READ(intel_hdmi->hdmi_reg); |
980 | 980 | ||
981 | if (crtc->config->has_audio) |
981 | if (crtc->config->has_audio) |
982 | intel_enable_hdmi_audio(encoder); |
982 | intel_enable_hdmi_audio(encoder); |
983 | } |
983 | } |
984 | 984 | ||
985 | static void ibx_enable_hdmi(struct intel_encoder *encoder) |
985 | static void ibx_enable_hdmi(struct intel_encoder *encoder) |
986 | { |
986 | { |
987 | struct drm_device *dev = encoder->base.dev; |
987 | struct drm_device *dev = encoder->base.dev; |
988 | struct drm_i915_private *dev_priv = dev->dev_private; |
988 | struct drm_i915_private *dev_priv = dev->dev_private; |
989 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
989 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
990 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
990 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
991 | u32 temp; |
991 | u32 temp; |
992 | 992 | ||
993 | temp = I915_READ(intel_hdmi->hdmi_reg); |
993 | temp = I915_READ(intel_hdmi->hdmi_reg); |
994 | 994 | ||
995 | temp |= SDVO_ENABLE; |
995 | temp |= SDVO_ENABLE; |
996 | if (crtc->config->has_audio) |
996 | if (crtc->config->has_audio) |
997 | temp |= SDVO_AUDIO_ENABLE; |
997 | temp |= SDVO_AUDIO_ENABLE; |
998 | 998 | ||
999 | /* |
999 | /* |
1000 | * HW workaround, need to write this twice for issue |
1000 | * HW workaround, need to write this twice for issue |
1001 | * that may result in first write getting masked. |
1001 | * that may result in first write getting masked. |
1002 | */ |
1002 | */ |
1003 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1003 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1004 | POSTING_READ(intel_hdmi->hdmi_reg); |
1004 | POSTING_READ(intel_hdmi->hdmi_reg); |
1005 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1005 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1006 | POSTING_READ(intel_hdmi->hdmi_reg); |
1006 | POSTING_READ(intel_hdmi->hdmi_reg); |
1007 | 1007 | ||
1008 | /* |
1008 | /* |
1009 | * HW workaround, need to toggle enable bit off and on |
1009 | * HW workaround, need to toggle enable bit off and on |
1010 | * for 12bpc with pixel repeat. |
1010 | * for 12bpc with pixel repeat. |
1011 | * |
1011 | * |
1012 | * FIXME: BSpec says this should be done at the end of |
1012 | * FIXME: BSpec says this should be done at the end of |
1013 | * of the modeset sequence, so not sure if this isn't too soon. |
1013 | * of the modeset sequence, so not sure if this isn't too soon. |
1014 | */ |
1014 | */ |
1015 | if (crtc->config->pipe_bpp > 24 && |
1015 | if (crtc->config->pipe_bpp > 24 && |
1016 | crtc->config->pixel_multiplier > 1) { |
1016 | crtc->config->pixel_multiplier > 1) { |
1017 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1017 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1018 | POSTING_READ(intel_hdmi->hdmi_reg); |
1018 | POSTING_READ(intel_hdmi->hdmi_reg); |
1019 | 1019 | ||
1020 | /* |
1020 | /* |
1021 | * HW workaround, need to write this twice for issue |
1021 | * HW workaround, need to write this twice for issue |
1022 | * that may result in first write getting masked. |
1022 | * that may result in first write getting masked. |
1023 | */ |
1023 | */ |
1024 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1024 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1025 | POSTING_READ(intel_hdmi->hdmi_reg); |
1025 | POSTING_READ(intel_hdmi->hdmi_reg); |
1026 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1026 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1027 | POSTING_READ(intel_hdmi->hdmi_reg); |
1027 | POSTING_READ(intel_hdmi->hdmi_reg); |
1028 | } |
1028 | } |
1029 | 1029 | ||
1030 | if (crtc->config->has_audio) |
1030 | if (crtc->config->has_audio) |
1031 | intel_enable_hdmi_audio(encoder); |
1031 | intel_enable_hdmi_audio(encoder); |
1032 | } |
1032 | } |
1033 | 1033 | ||
1034 | static void cpt_enable_hdmi(struct intel_encoder *encoder) |
1034 | static void cpt_enable_hdmi(struct intel_encoder *encoder) |
1035 | { |
1035 | { |
1036 | struct drm_device *dev = encoder->base.dev; |
1036 | struct drm_device *dev = encoder->base.dev; |
1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
1037 | struct drm_i915_private *dev_priv = dev->dev_private; |
1038 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1038 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1039 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1039 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1040 | enum pipe pipe = crtc->pipe; |
1040 | enum pipe pipe = crtc->pipe; |
1041 | u32 temp; |
1041 | u32 temp; |
1042 | 1042 | ||
1043 | temp = I915_READ(intel_hdmi->hdmi_reg); |
1043 | temp = I915_READ(intel_hdmi->hdmi_reg); |
1044 | 1044 | ||
1045 | temp |= SDVO_ENABLE; |
1045 | temp |= SDVO_ENABLE; |
1046 | if (crtc->config->has_audio) |
1046 | if (crtc->config->has_audio) |
1047 | temp |= SDVO_AUDIO_ENABLE; |
1047 | temp |= SDVO_AUDIO_ENABLE; |
1048 | 1048 | ||
1049 | /* |
1049 | /* |
1050 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb |
1050 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb |
1051 | * |
1051 | * |
1052 | * The procedure for 12bpc is as follows: |
1052 | * The procedure for 12bpc is as follows: |
1053 | * 1. disable HDMI clock gating |
1053 | * 1. disable HDMI clock gating |
1054 | * 2. enable HDMI with 8bpc |
1054 | * 2. enable HDMI with 8bpc |
1055 | * 3. enable HDMI with 12bpc |
1055 | * 3. enable HDMI with 12bpc |
1056 | * 4. enable HDMI clock gating |
1056 | * 4. enable HDMI clock gating |
1057 | */ |
1057 | */ |
1058 | 1058 | ||
1059 | if (crtc->config->pipe_bpp > 24) { |
1059 | if (crtc->config->pipe_bpp > 24) { |
1060 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1060 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1061 | I915_READ(TRANS_CHICKEN1(pipe)) | |
1061 | I915_READ(TRANS_CHICKEN1(pipe)) | |
1062 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
1062 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
1063 | 1063 | ||
1064 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1064 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1065 | temp |= SDVO_COLOR_FORMAT_8bpc; |
1065 | temp |= SDVO_COLOR_FORMAT_8bpc; |
1066 | } |
1066 | } |
1067 | 1067 | ||
1068 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1068 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1069 | POSTING_READ(intel_hdmi->hdmi_reg); |
1069 | POSTING_READ(intel_hdmi->hdmi_reg); |
1070 | 1070 | ||
1071 | if (crtc->config->pipe_bpp > 24) { |
1071 | if (crtc->config->pipe_bpp > 24) { |
1072 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1072 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1073 | temp |= HDMI_COLOR_FORMAT_12bpc; |
1073 | temp |= HDMI_COLOR_FORMAT_12bpc; |
1074 | 1074 | ||
1075 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1075 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1076 | POSTING_READ(intel_hdmi->hdmi_reg); |
1076 | POSTING_READ(intel_hdmi->hdmi_reg); |
1077 | 1077 | ||
1078 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1078 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1079 | I915_READ(TRANS_CHICKEN1(pipe)) & |
1079 | I915_READ(TRANS_CHICKEN1(pipe)) & |
1080 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
1080 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); |
1081 | } |
1081 | } |
1082 | 1082 | ||
1083 | if (crtc->config->has_audio) |
1083 | if (crtc->config->has_audio) |
1084 | intel_enable_hdmi_audio(encoder); |
1084 | intel_enable_hdmi_audio(encoder); |
1085 | } |
1085 | } |
1086 | 1086 | ||
1087 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1087 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1088 | { |
1088 | { |
1089 | } |
1089 | } |
1090 | 1090 | ||
1091 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
1091 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
1092 | { |
1092 | { |
1093 | struct drm_device *dev = encoder->base.dev; |
1093 | struct drm_device *dev = encoder->base.dev; |
1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
1094 | struct drm_i915_private *dev_priv = dev->dev_private; |
1095 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1095 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1096 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1096 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1097 | u32 temp; |
1097 | u32 temp; |
1098 | 1098 | ||
1099 | temp = I915_READ(intel_hdmi->hdmi_reg); |
1099 | temp = I915_READ(intel_hdmi->hdmi_reg); |
1100 | 1100 | ||
1101 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
1101 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
1102 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1102 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1103 | POSTING_READ(intel_hdmi->hdmi_reg); |
1103 | POSTING_READ(intel_hdmi->hdmi_reg); |
1104 | 1104 | ||
1105 | /* |
1105 | /* |
1106 | * HW workaround for IBX, we need to move the port |
1106 | * HW workaround for IBX, we need to move the port |
1107 | * to transcoder A after disabling it to allow the |
1107 | * to transcoder A after disabling it to allow the |
1108 | * matching DP port to be enabled on transcoder A. |
1108 | * matching DP port to be enabled on transcoder A. |
1109 | */ |
1109 | */ |
1110 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { |
1110 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { |
1111 | temp &= ~SDVO_PIPE_B_SELECT; |
1111 | temp &= ~SDVO_PIPE_B_SELECT; |
1112 | temp |= SDVO_ENABLE; |
1112 | temp |= SDVO_ENABLE; |
1113 | /* |
1113 | /* |
1114 | * HW workaround, need to write this twice for issue |
1114 | * HW workaround, need to write this twice for issue |
1115 | * that may result in first write getting masked. |
1115 | * that may result in first write getting masked. |
1116 | */ |
1116 | */ |
1117 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1117 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1118 | POSTING_READ(intel_hdmi->hdmi_reg); |
1118 | POSTING_READ(intel_hdmi->hdmi_reg); |
1119 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1119 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1120 | POSTING_READ(intel_hdmi->hdmi_reg); |
1120 | POSTING_READ(intel_hdmi->hdmi_reg); |
1121 | 1121 | ||
1122 | temp &= ~SDVO_ENABLE; |
1122 | temp &= ~SDVO_ENABLE; |
1123 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1123 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1124 | POSTING_READ(intel_hdmi->hdmi_reg); |
1124 | POSTING_READ(intel_hdmi->hdmi_reg); |
1125 | } |
1125 | } |
1126 | 1126 | ||
1127 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
1127 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
1128 | } |
1128 | } |
1129 | 1129 | ||
1130 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1130 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1131 | { |
1131 | { |
1132 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1132 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1133 | 1133 | ||
1134 | if (crtc->config->has_audio) |
1134 | if (crtc->config->has_audio) |
1135 | intel_audio_codec_disable(encoder); |
1135 | intel_audio_codec_disable(encoder); |
1136 | 1136 | ||
1137 | intel_disable_hdmi(encoder); |
1137 | intel_disable_hdmi(encoder); |
1138 | } |
1138 | } |
1139 | 1139 | ||
1140 | static void pch_disable_hdmi(struct intel_encoder *encoder) |
1140 | static void pch_disable_hdmi(struct intel_encoder *encoder) |
1141 | { |
1141 | { |
1142 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1142 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1143 | 1143 | ||
1144 | if (crtc->config->has_audio) |
1144 | if (crtc->config->has_audio) |
1145 | intel_audio_codec_disable(encoder); |
1145 | intel_audio_codec_disable(encoder); |
1146 | } |
1146 | } |
1147 | 1147 | ||
1148 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) |
1148 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) |
1149 | { |
1149 | { |
1150 | intel_disable_hdmi(encoder); |
1150 | intel_disable_hdmi(encoder); |
1151 | } |
1151 | } |
1152 | 1152 | ||
1153 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
1153 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
1154 | { |
1154 | { |
1155 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1155 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1156 | 1156 | ||
1157 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
1157 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
1158 | return 165000; |
1158 | return 165000; |
1159 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
1159 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
1160 | return 300000; |
1160 | return 300000; |
1161 | else |
1161 | else |
1162 | return 225000; |
1162 | return 225000; |
1163 | } |
1163 | } |
1164 | 1164 | ||
1165 | static enum drm_mode_status |
1165 | static enum drm_mode_status |
1166 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, |
1166 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, |
1167 | int clock, bool respect_dvi_limit) |
1167 | int clock, bool respect_dvi_limit) |
1168 | { |
1168 | { |
1169 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1169 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1170 | 1170 | ||
1171 | if (clock < 25000) |
1171 | if (clock < 25000) |
1172 | return MODE_CLOCK_LOW; |
1172 | return MODE_CLOCK_LOW; |
1173 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) |
1173 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) |
1174 | return MODE_CLOCK_HIGH; |
1174 | return MODE_CLOCK_HIGH; |
1175 | 1175 | ||
1176 | /* BXT DPLL can't generate 223-240 MHz */ |
1176 | /* BXT DPLL can't generate 223-240 MHz */ |
1177 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) |
1177 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) |
1178 | return MODE_CLOCK_RANGE; |
1178 | return MODE_CLOCK_RANGE; |
1179 | 1179 | ||
1180 | /* CHV DPLL can't generate 216-240 MHz */ |
1180 | /* CHV DPLL can't generate 216-240 MHz */ |
1181 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) |
1181 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) |
1182 | return MODE_CLOCK_RANGE; |
1182 | return MODE_CLOCK_RANGE; |
1183 | 1183 | ||
1184 | return MODE_OK; |
1184 | return MODE_OK; |
1185 | } |
1185 | } |
1186 | 1186 | ||
1187 | static enum drm_mode_status |
1187 | static enum drm_mode_status |
1188 | intel_hdmi_mode_valid(struct drm_connector *connector, |
1188 | intel_hdmi_mode_valid(struct drm_connector *connector, |
1189 | struct drm_display_mode *mode) |
1189 | struct drm_display_mode *mode) |
1190 | { |
1190 | { |
1191 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1191 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1192 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1192 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
1193 | enum drm_mode_status status; |
1193 | enum drm_mode_status status; |
1194 | int clock; |
1194 | int clock; |
1195 | 1195 | ||
1196 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1196 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1197 | return MODE_NO_DBLESCAN; |
1197 | return MODE_NO_DBLESCAN; |
1198 | 1198 | ||
1199 | clock = mode->clock; |
1199 | clock = mode->clock; |
1200 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1200 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1201 | clock *= 2; |
1201 | clock *= 2; |
1202 | 1202 | ||
1203 | /* check if we can do 8bpc */ |
1203 | /* check if we can do 8bpc */ |
1204 | status = hdmi_port_clock_valid(hdmi, clock, true); |
1204 | status = hdmi_port_clock_valid(hdmi, clock, true); |
1205 | 1205 | ||
1206 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1206 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1207 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) |
1207 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) |
1208 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); |
1208 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); |
1209 | 1209 | ||
1210 | return status; |
1210 | return status; |
1211 | } |
1211 | } |
1212 | 1212 | ||
1213 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
1213 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
1214 | { |
1214 | { |
1215 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1215 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1216 | struct drm_atomic_state *state; |
1216 | struct drm_atomic_state *state; |
1217 | struct intel_encoder *encoder; |
1217 | struct intel_encoder *encoder; |
1218 | struct drm_connector *connector; |
1218 | struct drm_connector *connector; |
1219 | struct drm_connector_state *connector_state; |
1219 | struct drm_connector_state *connector_state; |
1220 | int count = 0, count_hdmi = 0; |
1220 | int count = 0, count_hdmi = 0; |
1221 | int i; |
1221 | int i; |
1222 | 1222 | ||
1223 | if (HAS_GMCH_DISPLAY(dev)) |
1223 | if (HAS_GMCH_DISPLAY(dev)) |
1224 | return false; |
1224 | return false; |
1225 | 1225 | ||
1226 | state = crtc_state->base.state; |
1226 | state = crtc_state->base.state; |
1227 | 1227 | ||
1228 | for_each_connector_in_state(state, connector, connector_state, i) { |
1228 | for_each_connector_in_state(state, connector, connector_state, i) { |
1229 | if (connector_state->crtc != crtc_state->base.crtc) |
1229 | if (connector_state->crtc != crtc_state->base.crtc) |
1230 | continue; |
1230 | continue; |
1231 | 1231 | ||
1232 | encoder = to_intel_encoder(connector_state->best_encoder); |
1232 | encoder = to_intel_encoder(connector_state->best_encoder); |
1233 | 1233 | ||
1234 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1234 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1235 | count++; |
1235 | count++; |
1236 | } |
1236 | } |
1237 | 1237 | ||
1238 | /* |
1238 | /* |
1239 | * HDMI 12bpc affects the clocks, so it's only possible |
1239 | * HDMI 12bpc affects the clocks, so it's only possible |
1240 | * when not cloning with other encoder types. |
1240 | * when not cloning with other encoder types. |
1241 | */ |
1241 | */ |
1242 | return count_hdmi > 0 && count_hdmi == count; |
1242 | return count_hdmi > 0 && count_hdmi == count; |
1243 | } |
1243 | } |
1244 | 1244 | ||
1245 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
1245 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
1246 | struct intel_crtc_state *pipe_config) |
1246 | struct intel_crtc_state *pipe_config) |
1247 | { |
1247 | { |
1248 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1248 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1249 | struct drm_device *dev = encoder->base.dev; |
1249 | struct drm_device *dev = encoder->base.dev; |
1250 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1250 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1251 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1251 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1252 | int clock_12bpc = clock_8bpc * 3 / 2; |
1252 | int clock_12bpc = clock_8bpc * 3 / 2; |
1253 | int desired_bpp; |
1253 | int desired_bpp; |
1254 | 1254 | ||
1255 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1255 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1256 | 1256 | ||
1257 | if (pipe_config->has_hdmi_sink) |
1257 | if (pipe_config->has_hdmi_sink) |
1258 | pipe_config->has_infoframe = true; |
1258 | pipe_config->has_infoframe = true; |
1259 | 1259 | ||
1260 | if (intel_hdmi->color_range_auto) { |
1260 | if (intel_hdmi->color_range_auto) { |
1261 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
1261 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
1262 | pipe_config->limited_color_range = |
1262 | pipe_config->limited_color_range = |
1263 | pipe_config->has_hdmi_sink && |
1263 | pipe_config->has_hdmi_sink && |
1264 | drm_match_cea_mode(adjusted_mode) > 1; |
1264 | drm_match_cea_mode(adjusted_mode) > 1; |
1265 | } else { |
1265 | } else { |
1266 | pipe_config->limited_color_range = |
1266 | pipe_config->limited_color_range = |
1267 | intel_hdmi->limited_color_range; |
1267 | intel_hdmi->limited_color_range; |
1268 | } |
1268 | } |
1269 | 1269 | ||
1270 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1270 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1271 | pipe_config->pixel_multiplier = 2; |
1271 | pipe_config->pixel_multiplier = 2; |
1272 | clock_8bpc *= 2; |
1272 | clock_8bpc *= 2; |
1273 | clock_12bpc *= 2; |
1273 | clock_12bpc *= 2; |
1274 | } |
1274 | } |
1275 | 1275 | ||
1276 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1276 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1277 | pipe_config->has_pch_encoder = true; |
1277 | pipe_config->has_pch_encoder = true; |
1278 | 1278 | ||
1279 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1279 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1280 | pipe_config->has_audio = true; |
1280 | pipe_config->has_audio = true; |
1281 | 1281 | ||
1282 | /* |
1282 | /* |
1283 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
1283 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak |
1284 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi |
1284 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi |
1285 | * outputs. We also need to check that the higher clock still fits |
1285 | * outputs. We also need to check that the higher clock still fits |
1286 | * within limits. |
1286 | * within limits. |
1287 | */ |
1287 | */ |
1288 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
1288 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
1289 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
1289 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
1290 | hdmi_12bpc_possible(pipe_config)) { |
1290 | hdmi_12bpc_possible(pipe_config)) { |
1291 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1291 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1292 | desired_bpp = 12*3; |
1292 | desired_bpp = 12*3; |
1293 | 1293 | ||
1294 | /* Need to adjust the port link by 1.5x for 12bpc. */ |
1294 | /* Need to adjust the port link by 1.5x for 12bpc. */ |
1295 | pipe_config->port_clock = clock_12bpc; |
1295 | pipe_config->port_clock = clock_12bpc; |
1296 | } else { |
1296 | } else { |
1297 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1297 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1298 | desired_bpp = 8*3; |
1298 | desired_bpp = 8*3; |
1299 | 1299 | ||
1300 | pipe_config->port_clock = clock_8bpc; |
1300 | pipe_config->port_clock = clock_8bpc; |
1301 | } |
1301 | } |
1302 | 1302 | ||
1303 | if (!pipe_config->bw_constrained) { |
1303 | if (!pipe_config->bw_constrained) { |
1304 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); |
1304 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); |
1305 | pipe_config->pipe_bpp = desired_bpp; |
1305 | pipe_config->pipe_bpp = desired_bpp; |
1306 | } |
1306 | } |
1307 | 1307 | ||
1308 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1308 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1309 | false) != MODE_OK) { |
1309 | false) != MODE_OK) { |
1310 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
1310 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
1311 | return false; |
1311 | return false; |
1312 | } |
1312 | } |
1313 | 1313 | ||
1314 | /* Set user selected PAR to incoming mode's member */ |
1314 | /* Set user selected PAR to incoming mode's member */ |
1315 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; |
1315 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; |
1316 | 1316 | ||
1317 | return true; |
1317 | return true; |
1318 | } |
1318 | } |
1319 | 1319 | ||
1320 | static void |
1320 | static void |
1321 | intel_hdmi_unset_edid(struct drm_connector *connector) |
1321 | intel_hdmi_unset_edid(struct drm_connector *connector) |
1322 | { |
1322 | { |
1323 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1323 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1324 | 1324 | ||
1325 | intel_hdmi->has_hdmi_sink = false; |
1325 | intel_hdmi->has_hdmi_sink = false; |
1326 | intel_hdmi->has_audio = false; |
1326 | intel_hdmi->has_audio = false; |
1327 | intel_hdmi->rgb_quant_range_selectable = false; |
1327 | intel_hdmi->rgb_quant_range_selectable = false; |
1328 | 1328 | ||
1329 | kfree(to_intel_connector(connector)->detect_edid); |
1329 | kfree(to_intel_connector(connector)->detect_edid); |
1330 | to_intel_connector(connector)->detect_edid = NULL; |
1330 | to_intel_connector(connector)->detect_edid = NULL; |
1331 | } |
1331 | } |
1332 | 1332 | ||
1333 | static bool |
1333 | static bool |
1334 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
1334 | intel_hdmi_set_edid(struct drm_connector *connector) |
1335 | { |
1335 | { |
1336 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1336 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1337 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1337 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1338 | struct edid *edid = NULL; |
1338 | struct edid *edid; |
1339 | bool connected = false; |
1339 | bool connected = false; |
1340 | 1340 | ||
1341 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1341 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1342 | - | ||
1343 | if (force) |
1342 | |
1344 | edid = drm_get_edid(connector, |
1343 | edid = drm_get_edid(connector, |
1345 | intel_gmbus_get_adapter(dev_priv, |
1344 | intel_gmbus_get_adapter(dev_priv, |
1346 | intel_hdmi->ddc_bus)); |
1345 | intel_hdmi->ddc_bus)); |
1347 | 1346 | ||
1348 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1347 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1349 | 1348 | ||
1350 | to_intel_connector(connector)->detect_edid = edid; |
1349 | to_intel_connector(connector)->detect_edid = edid; |
1351 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { |
1350 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { |
1352 | intel_hdmi->rgb_quant_range_selectable = |
1351 | intel_hdmi->rgb_quant_range_selectable = |
1353 | drm_rgb_quant_range_selectable(edid); |
1352 | drm_rgb_quant_range_selectable(edid); |
1354 | 1353 | ||
1355 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
1354 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
1356 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1355 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1357 | intel_hdmi->has_audio = |
1356 | intel_hdmi->has_audio = |
1358 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1357 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1359 | 1358 | ||
1360 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
1359 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
1361 | intel_hdmi->has_hdmi_sink = |
1360 | intel_hdmi->has_hdmi_sink = |
1362 | drm_detect_hdmi_monitor(edid); |
1361 | drm_detect_hdmi_monitor(edid); |
1363 | 1362 | ||
1364 | connected = true; |
1363 | connected = true; |
1365 | } |
1364 | } |
1366 | 1365 | ||
1367 | return connected; |
1366 | return connected; |
1368 | } |
1367 | } |
1369 | 1368 | ||
1370 | static enum drm_connector_status |
1369 | static enum drm_connector_status |
1371 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
1370 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
1372 | { |
1371 | { |
1373 | enum drm_connector_status status; |
1372 | enum drm_connector_status status; |
1374 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
- | |
1375 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1373 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1376 | bool live_status = false; |
- | |
1377 | unsigned int try; |
- | |
1378 | 1374 | ||
1379 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1375 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1380 | connector->base.id, connector->name); |
1376 | connector->base.id, connector->name); |
1381 | 1377 | ||
1382 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1378 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1383 | - | ||
1384 | for (try = 0; !live_status && try < 9; try++) { |
- | |
1385 | if (try) |
- | |
1386 | msleep(10); |
- | |
1387 | live_status = intel_digital_port_connected(dev_priv, |
- | |
1388 | hdmi_to_dig_port(intel_hdmi)); |
- | |
1389 | } |
- | |
1390 | - | ||
1391 | if (!live_status) { |
- | |
1392 | DRM_DEBUG_KMS("HDMI live status down\n"); |
- | |
1393 | /* |
- | |
1394 | * Live status register is not reliable on all intel platforms. |
- | |
1395 | * So consider live_status only for certain platforms, for |
- | |
1396 | * others, read EDID to determine presence of sink. |
- | |
1397 | */ |
- | |
1398 | if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) |
- | |
1399 | live_status = true; |
- | |
1400 | } |
- | |
1401 | 1379 | ||
1402 | intel_hdmi_unset_edid(connector); |
1380 | intel_hdmi_unset_edid(connector); |
1403 | 1381 | ||
1404 | if (intel_hdmi_set_edid(connector, live_status)) { |
1382 | if (intel_hdmi_set_edid(connector)) { |
1405 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1383 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1406 | 1384 | ||
1407 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1385 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1408 | status = connector_status_connected; |
1386 | status = connector_status_connected; |
1409 | } else |
1387 | } else |
1410 | status = connector_status_disconnected; |
1388 | status = connector_status_disconnected; |
1411 | 1389 | ||
1412 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1390 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1413 | 1391 | ||
1414 | return status; |
1392 | return status; |
1415 | } |
1393 | } |
1416 | 1394 | ||
1417 | static void |
1395 | static void |
1418 | intel_hdmi_force(struct drm_connector *connector) |
1396 | intel_hdmi_force(struct drm_connector *connector) |
1419 | { |
1397 | { |
1420 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1398 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1421 | 1399 | ||
1422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1400 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1423 | connector->base.id, connector->name); |
1401 | connector->base.id, connector->name); |
1424 | 1402 | ||
1425 | intel_hdmi_unset_edid(connector); |
1403 | intel_hdmi_unset_edid(connector); |
1426 | 1404 | ||
1427 | if (connector->status != connector_status_connected) |
1405 | if (connector->status != connector_status_connected) |
1428 | return; |
1406 | return; |
1429 | 1407 | ||
1430 | intel_hdmi_set_edid(connector, true); |
1408 | intel_hdmi_set_edid(connector); |
1431 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1409 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1432 | } |
1410 | } |
1433 | 1411 | ||
1434 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1412 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1435 | { |
1413 | { |
1436 | struct edid *edid; |
1414 | struct edid *edid; |
1437 | 1415 | ||
1438 | edid = to_intel_connector(connector)->detect_edid; |
1416 | edid = to_intel_connector(connector)->detect_edid; |
1439 | if (edid == NULL) |
1417 | if (edid == NULL) |
1440 | return 0; |
1418 | return 0; |
1441 | 1419 | ||
1442 | return intel_connector_update_modes(connector, edid); |
1420 | return intel_connector_update_modes(connector, edid); |
1443 | } |
1421 | } |
1444 | 1422 | ||
1445 | static bool |
1423 | static bool |
1446 | intel_hdmi_detect_audio(struct drm_connector *connector) |
1424 | intel_hdmi_detect_audio(struct drm_connector *connector) |
1447 | { |
1425 | { |
1448 | bool has_audio = false; |
1426 | bool has_audio = false; |
1449 | struct edid *edid; |
1427 | struct edid *edid; |
1450 | 1428 | ||
1451 | edid = to_intel_connector(connector)->detect_edid; |
1429 | edid = to_intel_connector(connector)->detect_edid; |
1452 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) |
1430 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) |
1453 | has_audio = drm_detect_monitor_audio(edid); |
1431 | has_audio = drm_detect_monitor_audio(edid); |
1454 | 1432 | ||
1455 | return has_audio; |
1433 | return has_audio; |
1456 | } |
1434 | } |
1457 | 1435 | ||
1458 | static int |
1436 | static int |
1459 | intel_hdmi_set_property(struct drm_connector *connector, |
1437 | intel_hdmi_set_property(struct drm_connector *connector, |
1460 | struct drm_property *property, |
1438 | struct drm_property *property, |
1461 | uint64_t val) |
1439 | uint64_t val) |
1462 | { |
1440 | { |
1463 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1441 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1464 | struct intel_digital_port *intel_dig_port = |
1442 | struct intel_digital_port *intel_dig_port = |
1465 | hdmi_to_dig_port(intel_hdmi); |
1443 | hdmi_to_dig_port(intel_hdmi); |
1466 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1444 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
1467 | int ret; |
1445 | int ret; |
1468 | 1446 | ||
1469 | ret = drm_object_property_set_value(&connector->base, property, val); |
1447 | ret = drm_object_property_set_value(&connector->base, property, val); |
1470 | if (ret) |
1448 | if (ret) |
1471 | return ret; |
1449 | return ret; |
1472 | 1450 | ||
1473 | if (property == dev_priv->force_audio_property) { |
1451 | if (property == dev_priv->force_audio_property) { |
1474 | enum hdmi_force_audio i = val; |
1452 | enum hdmi_force_audio i = val; |
1475 | bool has_audio; |
1453 | bool has_audio; |
1476 | 1454 | ||
1477 | if (i == intel_hdmi->force_audio) |
1455 | if (i == intel_hdmi->force_audio) |
1478 | return 0; |
1456 | return 0; |
1479 | 1457 | ||
1480 | intel_hdmi->force_audio = i; |
1458 | intel_hdmi->force_audio = i; |
1481 | 1459 | ||
1482 | if (i == HDMI_AUDIO_AUTO) |
1460 | if (i == HDMI_AUDIO_AUTO) |
1483 | has_audio = intel_hdmi_detect_audio(connector); |
1461 | has_audio = intel_hdmi_detect_audio(connector); |
1484 | else |
1462 | else |
1485 | has_audio = (i == HDMI_AUDIO_ON); |
1463 | has_audio = (i == HDMI_AUDIO_ON); |
1486 | 1464 | ||
1487 | if (i == HDMI_AUDIO_OFF_DVI) |
1465 | if (i == HDMI_AUDIO_OFF_DVI) |
1488 | intel_hdmi->has_hdmi_sink = 0; |
1466 | intel_hdmi->has_hdmi_sink = 0; |
1489 | 1467 | ||
1490 | intel_hdmi->has_audio = has_audio; |
1468 | intel_hdmi->has_audio = has_audio; |
1491 | goto done; |
1469 | goto done; |
1492 | } |
1470 | } |
1493 | 1471 | ||
1494 | if (property == dev_priv->broadcast_rgb_property) { |
1472 | if (property == dev_priv->broadcast_rgb_property) { |
1495 | bool old_auto = intel_hdmi->color_range_auto; |
1473 | bool old_auto = intel_hdmi->color_range_auto; |
1496 | bool old_range = intel_hdmi->limited_color_range; |
1474 | bool old_range = intel_hdmi->limited_color_range; |
1497 | 1475 | ||
1498 | switch (val) { |
1476 | switch (val) { |
1499 | case INTEL_BROADCAST_RGB_AUTO: |
1477 | case INTEL_BROADCAST_RGB_AUTO: |
1500 | intel_hdmi->color_range_auto = true; |
1478 | intel_hdmi->color_range_auto = true; |
1501 | break; |
1479 | break; |
1502 | case INTEL_BROADCAST_RGB_FULL: |
1480 | case INTEL_BROADCAST_RGB_FULL: |
1503 | intel_hdmi->color_range_auto = false; |
1481 | intel_hdmi->color_range_auto = false; |
1504 | intel_hdmi->limited_color_range = false; |
1482 | intel_hdmi->limited_color_range = false; |
1505 | break; |
1483 | break; |
1506 | case INTEL_BROADCAST_RGB_LIMITED: |
1484 | case INTEL_BROADCAST_RGB_LIMITED: |
1507 | intel_hdmi->color_range_auto = false; |
1485 | intel_hdmi->color_range_auto = false; |
1508 | intel_hdmi->limited_color_range = true; |
1486 | intel_hdmi->limited_color_range = true; |
1509 | break; |
1487 | break; |
1510 | default: |
1488 | default: |
1511 | return -EINVAL; |
1489 | return -EINVAL; |
1512 | } |
1490 | } |
1513 | 1491 | ||
1514 | if (old_auto == intel_hdmi->color_range_auto && |
1492 | if (old_auto == intel_hdmi->color_range_auto && |
1515 | old_range == intel_hdmi->limited_color_range) |
1493 | old_range == intel_hdmi->limited_color_range) |
1516 | return 0; |
1494 | return 0; |
1517 | 1495 | ||
1518 | goto done; |
1496 | goto done; |
1519 | } |
1497 | } |
1520 | 1498 | ||
1521 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1499 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1522 | switch (val) { |
1500 | switch (val) { |
1523 | case DRM_MODE_PICTURE_ASPECT_NONE: |
1501 | case DRM_MODE_PICTURE_ASPECT_NONE: |
1524 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
1502 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
1525 | break; |
1503 | break; |
1526 | case DRM_MODE_PICTURE_ASPECT_4_3: |
1504 | case DRM_MODE_PICTURE_ASPECT_4_3: |
1527 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; |
1505 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; |
1528 | break; |
1506 | break; |
1529 | case DRM_MODE_PICTURE_ASPECT_16_9: |
1507 | case DRM_MODE_PICTURE_ASPECT_16_9: |
1530 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; |
1508 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; |
1531 | break; |
1509 | break; |
1532 | default: |
1510 | default: |
1533 | return -EINVAL; |
1511 | return -EINVAL; |
1534 | } |
1512 | } |
1535 | goto done; |
1513 | goto done; |
1536 | } |
1514 | } |
1537 | 1515 | ||
1538 | return -EINVAL; |
1516 | return -EINVAL; |
1539 | 1517 | ||
1540 | done: |
1518 | done: |
1541 | if (intel_dig_port->base.base.crtc) |
1519 | if (intel_dig_port->base.base.crtc) |
1542 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); |
1520 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); |
1543 | 1521 | ||
1544 | return 0; |
1522 | return 0; |
1545 | } |
1523 | } |
1546 | 1524 | ||
1547 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1525 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1548 | { |
1526 | { |
1549 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1527 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1550 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1528 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1551 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1529 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1552 | 1530 | ||
1553 | intel_hdmi_prepare(encoder); |
1531 | intel_hdmi_prepare(encoder); |
1554 | 1532 | ||
1555 | intel_hdmi->set_infoframes(&encoder->base, |
1533 | intel_hdmi->set_infoframes(&encoder->base, |
1556 | intel_crtc->config->has_hdmi_sink, |
1534 | intel_crtc->config->has_hdmi_sink, |
1557 | adjusted_mode); |
1535 | adjusted_mode); |
1558 | } |
1536 | } |
1559 | 1537 | ||
1560 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
1538 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
1561 | { |
1539 | { |
1562 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1540 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1563 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
1541 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
1564 | struct drm_device *dev = encoder->base.dev; |
1542 | struct drm_device *dev = encoder->base.dev; |
1565 | struct drm_i915_private *dev_priv = dev->dev_private; |
1543 | struct drm_i915_private *dev_priv = dev->dev_private; |
1566 | struct intel_crtc *intel_crtc = |
1544 | struct intel_crtc *intel_crtc = |
1567 | to_intel_crtc(encoder->base.crtc); |
1545 | to_intel_crtc(encoder->base.crtc); |
1568 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1546 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1569 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1547 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1570 | int pipe = intel_crtc->pipe; |
1548 | int pipe = intel_crtc->pipe; |
1571 | u32 val; |
1549 | u32 val; |
1572 | 1550 | ||
1573 | /* Enable clock channels for this port */ |
1551 | /* Enable clock channels for this port */ |
1574 | mutex_lock(&dev_priv->sb_lock); |
1552 | mutex_lock(&dev_priv->sb_lock); |
1575 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
1553 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
1576 | val = 0; |
1554 | val = 0; |
1577 | if (pipe) |
1555 | if (pipe) |
1578 | val |= (1<<21); |
1556 | val |= (1<<21); |
1579 | else |
1557 | else |
1580 | val &= ~(1<<21); |
1558 | val &= ~(1<<21); |
1581 | val |= 0x001000c4; |
1559 | val |= 0x001000c4; |
1582 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1560 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1583 | 1561 | ||
1584 | /* HDMI 1.0V-2dB */ |
1562 | /* HDMI 1.0V-2dB */ |
1585 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1563 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1586 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); |
1564 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); |
1587 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); |
1565 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); |
1588 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); |
1566 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); |
1589 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); |
1567 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); |
1590 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
1568 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
1591 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1569 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1592 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
1570 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
1593 | 1571 | ||
1594 | /* Program lane clock */ |
1572 | /* Program lane clock */ |
1595 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1573 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1596 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
1574 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
1597 | mutex_unlock(&dev_priv->sb_lock); |
1575 | mutex_unlock(&dev_priv->sb_lock); |
1598 | 1576 | ||
1599 | intel_hdmi->set_infoframes(&encoder->base, |
1577 | intel_hdmi->set_infoframes(&encoder->base, |
1600 | intel_crtc->config->has_hdmi_sink, |
1578 | intel_crtc->config->has_hdmi_sink, |
1601 | adjusted_mode); |
1579 | adjusted_mode); |
1602 | 1580 | ||
1603 | g4x_enable_hdmi(encoder); |
1581 | g4x_enable_hdmi(encoder); |
1604 | 1582 | ||
1605 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
1583 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
1606 | } |
1584 | } |
1607 | 1585 | ||
1608 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1586 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1609 | { |
1587 | { |
1610 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1588 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1611 | struct drm_device *dev = encoder->base.dev; |
1589 | struct drm_device *dev = encoder->base.dev; |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; |
1590 | struct drm_i915_private *dev_priv = dev->dev_private; |
1613 | struct intel_crtc *intel_crtc = |
1591 | struct intel_crtc *intel_crtc = |
1614 | to_intel_crtc(encoder->base.crtc); |
1592 | to_intel_crtc(encoder->base.crtc); |
1615 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1593 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1616 | int pipe = intel_crtc->pipe; |
1594 | int pipe = intel_crtc->pipe; |
1617 | 1595 | ||
1618 | intel_hdmi_prepare(encoder); |
1596 | intel_hdmi_prepare(encoder); |
1619 | 1597 | ||
1620 | /* Program Tx lane resets to default */ |
1598 | /* Program Tx lane resets to default */ |
1621 | mutex_lock(&dev_priv->sb_lock); |
1599 | mutex_lock(&dev_priv->sb_lock); |
1622 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
1600 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
1623 | DPIO_PCS_TX_LANE2_RESET | |
1601 | DPIO_PCS_TX_LANE2_RESET | |
1624 | DPIO_PCS_TX_LANE1_RESET); |
1602 | DPIO_PCS_TX_LANE1_RESET); |
1625 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
1603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
1626 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1604 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1627 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
1605 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
1628 | (1< |
1606 | (1< |
1629 | DPIO_PCS_CLK_SOFT_RESET); |
1607 | DPIO_PCS_CLK_SOFT_RESET); |
1630 | 1608 | ||
1631 | /* Fix up inter-pair skew failure */ |
1609 | /* Fix up inter-pair skew failure */ |
1632 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1610 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1633 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
1611 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
1634 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
1612 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
1635 | 1613 | ||
1636 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1614 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); |
1637 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
1615 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); |
1638 | mutex_unlock(&dev_priv->sb_lock); |
1616 | mutex_unlock(&dev_priv->sb_lock); |
1639 | } |
1617 | } |
1640 | 1618 | ||
1641 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
1619 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
1642 | bool reset) |
1620 | bool reset) |
1643 | { |
1621 | { |
1644 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1622 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1645 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
1623 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
1646 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1624 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1647 | enum pipe pipe = crtc->pipe; |
1625 | enum pipe pipe = crtc->pipe; |
1648 | uint32_t val; |
1626 | uint32_t val; |
1649 | 1627 | ||
1650 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
1628 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
1651 | if (reset) |
1629 | if (reset) |
1652 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
1630 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
1653 | else |
1631 | else |
1654 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
1632 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
1655 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
1633 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
1656 | 1634 | ||
1657 | if (crtc->config->lane_count > 2) { |
1635 | if (crtc->config->lane_count > 2) { |
1658 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
1636 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
1659 | if (reset) |
1637 | if (reset) |
1660 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
1638 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
1661 | else |
1639 | else |
1662 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
1640 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
1663 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
1641 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
1664 | } |
1642 | } |
1665 | 1643 | ||
1666 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
1644 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
1667 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
1645 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
1668 | if (reset) |
1646 | if (reset) |
1669 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
1647 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
1670 | else |
1648 | else |
1671 | val |= DPIO_PCS_CLK_SOFT_RESET; |
1649 | val |= DPIO_PCS_CLK_SOFT_RESET; |
1672 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1650 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1673 | 1651 | ||
1674 | if (crtc->config->lane_count > 2) { |
1652 | if (crtc->config->lane_count > 2) { |
1675 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1653 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1676 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
1654 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
1677 | if (reset) |
1655 | if (reset) |
1678 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
1656 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
1679 | else |
1657 | else |
1680 | val |= DPIO_PCS_CLK_SOFT_RESET; |
1658 | val |= DPIO_PCS_CLK_SOFT_RESET; |
1681 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
1659 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
1682 | } |
1660 | } |
1683 | } |
1661 | } |
1684 | 1662 | ||
1685 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1663 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1686 | { |
1664 | { |
1687 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1665 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1688 | struct drm_device *dev = encoder->base.dev; |
1666 | struct drm_device *dev = encoder->base.dev; |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
1667 | struct drm_i915_private *dev_priv = dev->dev_private; |
1690 | struct intel_crtc *intel_crtc = |
1668 | struct intel_crtc *intel_crtc = |
1691 | to_intel_crtc(encoder->base.crtc); |
1669 | to_intel_crtc(encoder->base.crtc); |
1692 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1670 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1693 | enum pipe pipe = intel_crtc->pipe; |
1671 | enum pipe pipe = intel_crtc->pipe; |
1694 | u32 val; |
1672 | u32 val; |
1695 | 1673 | ||
1696 | intel_hdmi_prepare(encoder); |
1674 | intel_hdmi_prepare(encoder); |
1697 | 1675 | ||
1698 | /* |
1676 | /* |
1699 | * Must trick the second common lane into life. |
1677 | * Must trick the second common lane into life. |
1700 | * Otherwise we can't even access the PLL. |
1678 | * Otherwise we can't even access the PLL. |
1701 | */ |
1679 | */ |
1702 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
1680 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
1703 | dport->release_cl2_override = |
1681 | dport->release_cl2_override = |
1704 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
1682 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
1705 | 1683 | ||
1706 | chv_phy_powergate_lanes(encoder, true, 0x0); |
1684 | chv_phy_powergate_lanes(encoder, true, 0x0); |
1707 | 1685 | ||
1708 | mutex_lock(&dev_priv->sb_lock); |
1686 | mutex_lock(&dev_priv->sb_lock); |
1709 | 1687 | ||
1710 | /* Assert data lane reset */ |
1688 | /* Assert data lane reset */ |
1711 | chv_data_lane_soft_reset(encoder, true); |
1689 | chv_data_lane_soft_reset(encoder, true); |
1712 | 1690 | ||
1713 | /* program left/right clock distribution */ |
1691 | /* program left/right clock distribution */ |
1714 | if (pipe != PIPE_B) { |
1692 | if (pipe != PIPE_B) { |
1715 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
1693 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
1716 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
1694 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
1717 | if (ch == DPIO_CH0) |
1695 | if (ch == DPIO_CH0) |
1718 | val |= CHV_BUFLEFTENA1_FORCE; |
1696 | val |= CHV_BUFLEFTENA1_FORCE; |
1719 | if (ch == DPIO_CH1) |
1697 | if (ch == DPIO_CH1) |
1720 | val |= CHV_BUFRIGHTENA1_FORCE; |
1698 | val |= CHV_BUFRIGHTENA1_FORCE; |
1721 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
1699 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
1722 | } else { |
1700 | } else { |
1723 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
1701 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
1724 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
1702 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
1725 | if (ch == DPIO_CH0) |
1703 | if (ch == DPIO_CH0) |
1726 | val |= CHV_BUFLEFTENA2_FORCE; |
1704 | val |= CHV_BUFLEFTENA2_FORCE; |
1727 | if (ch == DPIO_CH1) |
1705 | if (ch == DPIO_CH1) |
1728 | val |= CHV_BUFRIGHTENA2_FORCE; |
1706 | val |= CHV_BUFRIGHTENA2_FORCE; |
1729 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
1707 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
1730 | } |
1708 | } |
1731 | 1709 | ||
1732 | /* program clock channel usage */ |
1710 | /* program clock channel usage */ |
1733 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
1711 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
1734 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
1712 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
1735 | if (pipe != PIPE_B) |
1713 | if (pipe != PIPE_B) |
1736 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
1714 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
1737 | else |
1715 | else |
1738 | val |= CHV_PCS_USEDCLKCHANNEL; |
1716 | val |= CHV_PCS_USEDCLKCHANNEL; |
1739 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
1717 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
1740 | 1718 | ||
1741 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
1719 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
1742 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
1720 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
1743 | if (pipe != PIPE_B) |
1721 | if (pipe != PIPE_B) |
1744 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
1722 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
1745 | else |
1723 | else |
1746 | val |= CHV_PCS_USEDCLKCHANNEL; |
1724 | val |= CHV_PCS_USEDCLKCHANNEL; |
1747 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
1725 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
1748 | 1726 | ||
1749 | /* |
1727 | /* |
1750 | * This a a bit weird since generally CL |
1728 | * This a a bit weird since generally CL |
1751 | * matches the pipe, but here we need to |
1729 | * matches the pipe, but here we need to |
1752 | * pick the CL based on the port. |
1730 | * pick the CL based on the port. |
1753 | */ |
1731 | */ |
1754 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
1732 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
1755 | if (pipe != PIPE_B) |
1733 | if (pipe != PIPE_B) |
1756 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
1734 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
1757 | else |
1735 | else |
1758 | val |= CHV_CMN_USEDCLKCHANNEL; |
1736 | val |= CHV_CMN_USEDCLKCHANNEL; |
1759 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
1737 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
1760 | 1738 | ||
1761 | mutex_unlock(&dev_priv->sb_lock); |
1739 | mutex_unlock(&dev_priv->sb_lock); |
1762 | } |
1740 | } |
1763 | 1741 | ||
1764 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1742 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1765 | { |
1743 | { |
1766 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1744 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1767 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
1745 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
1768 | u32 val; |
1746 | u32 val; |
1769 | 1747 | ||
1770 | mutex_lock(&dev_priv->sb_lock); |
1748 | mutex_lock(&dev_priv->sb_lock); |
1771 | 1749 | ||
1772 | /* disable left/right clock distribution */ |
1750 | /* disable left/right clock distribution */ |
1773 | if (pipe != PIPE_B) { |
1751 | if (pipe != PIPE_B) { |
1774 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
1752 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
1775 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
1753 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
1776 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
1754 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
1777 | } else { |
1755 | } else { |
1778 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
1756 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
1779 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
1757 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
1780 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
1758 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
1781 | } |
1759 | } |
1782 | 1760 | ||
1783 | mutex_unlock(&dev_priv->sb_lock); |
1761 | mutex_unlock(&dev_priv->sb_lock); |
1784 | 1762 | ||
1785 | /* |
1763 | /* |
1786 | * Leave the power down bit cleared for at least one |
1764 | * Leave the power down bit cleared for at least one |
1787 | * lane so that chv_powergate_phy_ch() will power |
1765 | * lane so that chv_powergate_phy_ch() will power |
1788 | * on something when the channel is otherwise unused. |
1766 | * on something when the channel is otherwise unused. |
1789 | * When the port is off and the override is removed |
1767 | * When the port is off and the override is removed |
1790 | * the lanes power down anyway, so otherwise it doesn't |
1768 | * the lanes power down anyway, so otherwise it doesn't |
1791 | * really matter what the state of power down bits is |
1769 | * really matter what the state of power down bits is |
1792 | * after this. |
1770 | * after this. |
1793 | */ |
1771 | */ |
1794 | chv_phy_powergate_lanes(encoder, false, 0x0); |
1772 | chv_phy_powergate_lanes(encoder, false, 0x0); |
1795 | } |
1773 | } |
1796 | 1774 | ||
1797 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
1775 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
1798 | { |
1776 | { |
1799 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1777 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1800 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1778 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1801 | struct intel_crtc *intel_crtc = |
1779 | struct intel_crtc *intel_crtc = |
1802 | to_intel_crtc(encoder->base.crtc); |
1780 | to_intel_crtc(encoder->base.crtc); |
1803 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1781 | enum dpio_channel port = vlv_dport_to_channel(dport); |
1804 | int pipe = intel_crtc->pipe; |
1782 | int pipe = intel_crtc->pipe; |
1805 | 1783 | ||
1806 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
1784 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
1807 | mutex_lock(&dev_priv->sb_lock); |
1785 | mutex_lock(&dev_priv->sb_lock); |
1808 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1786 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1809 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); |
1787 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); |
1810 | mutex_unlock(&dev_priv->sb_lock); |
1788 | mutex_unlock(&dev_priv->sb_lock); |
1811 | } |
1789 | } |
1812 | 1790 | ||
1813 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1791 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1814 | { |
1792 | { |
1815 | struct drm_device *dev = encoder->base.dev; |
1793 | struct drm_device *dev = encoder->base.dev; |
1816 | struct drm_i915_private *dev_priv = dev->dev_private; |
1794 | struct drm_i915_private *dev_priv = dev->dev_private; |
1817 | 1795 | ||
1818 | mutex_lock(&dev_priv->sb_lock); |
1796 | mutex_lock(&dev_priv->sb_lock); |
1819 | 1797 | ||
1820 | /* Assert data lane reset */ |
1798 | /* Assert data lane reset */ |
1821 | chv_data_lane_soft_reset(encoder, true); |
1799 | chv_data_lane_soft_reset(encoder, true); |
1822 | 1800 | ||
1823 | mutex_unlock(&dev_priv->sb_lock); |
1801 | mutex_unlock(&dev_priv->sb_lock); |
1824 | } |
1802 | } |
1825 | 1803 | ||
1826 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1804 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1827 | { |
1805 | { |
1828 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1806 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1829 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
1807 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
1830 | struct drm_device *dev = encoder->base.dev; |
1808 | struct drm_device *dev = encoder->base.dev; |
1831 | struct drm_i915_private *dev_priv = dev->dev_private; |
1809 | struct drm_i915_private *dev_priv = dev->dev_private; |
1832 | struct intel_crtc *intel_crtc = |
1810 | struct intel_crtc *intel_crtc = |
1833 | to_intel_crtc(encoder->base.crtc); |
1811 | to_intel_crtc(encoder->base.crtc); |
1834 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1812 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1835 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1813 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1836 | int pipe = intel_crtc->pipe; |
1814 | int pipe = intel_crtc->pipe; |
1837 | int data, i, stagger; |
1815 | int data, i, stagger; |
1838 | u32 val; |
1816 | u32 val; |
1839 | 1817 | ||
1840 | mutex_lock(&dev_priv->sb_lock); |
1818 | mutex_lock(&dev_priv->sb_lock); |
1841 | 1819 | ||
1842 | /* allow hardware to manage TX FIFO reset source */ |
1820 | /* allow hardware to manage TX FIFO reset source */ |
1843 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
1821 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
1844 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
1822 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
1845 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
1823 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
1846 | 1824 | ||
1847 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
1825 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
1848 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
1826 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
1849 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
1827 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
1850 | 1828 | ||
1851 | /* Program Tx latency optimal setting */ |
1829 | /* Program Tx latency optimal setting */ |
1852 | for (i = 0; i < 4; i++) { |
1830 | for (i = 0; i < 4; i++) { |
1853 | /* Set the upar bit */ |
1831 | /* Set the upar bit */ |
1854 | data = (i == 1) ? 0x0 : 0x1; |
1832 | data = (i == 1) ? 0x0 : 0x1; |
1855 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
1833 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
1856 | data << DPIO_UPAR_SHIFT); |
1834 | data << DPIO_UPAR_SHIFT); |
1857 | } |
1835 | } |
1858 | 1836 | ||
1859 | /* Data lane stagger programming */ |
1837 | /* Data lane stagger programming */ |
1860 | if (intel_crtc->config->port_clock > 270000) |
1838 | if (intel_crtc->config->port_clock > 270000) |
1861 | stagger = 0x18; |
1839 | stagger = 0x18; |
1862 | else if (intel_crtc->config->port_clock > 135000) |
1840 | else if (intel_crtc->config->port_clock > 135000) |
1863 | stagger = 0xd; |
1841 | stagger = 0xd; |
1864 | else if (intel_crtc->config->port_clock > 67500) |
1842 | else if (intel_crtc->config->port_clock > 67500) |
1865 | stagger = 0x7; |
1843 | stagger = 0x7; |
1866 | else if (intel_crtc->config->port_clock > 33750) |
1844 | else if (intel_crtc->config->port_clock > 33750) |
1867 | stagger = 0x4; |
1845 | stagger = 0x4; |
1868 | else |
1846 | else |
1869 | stagger = 0x2; |
1847 | stagger = 0x2; |
1870 | 1848 | ||
1871 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
1849 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
1872 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
1850 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
1873 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
1851 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
1874 | 1852 | ||
1875 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
1853 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
1876 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
1854 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
1877 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
1855 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
1878 | 1856 | ||
1879 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
1857 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
1880 | DPIO_LANESTAGGER_STRAP(stagger) | |
1858 | DPIO_LANESTAGGER_STRAP(stagger) | |
1881 | DPIO_LANESTAGGER_STRAP_OVRD | |
1859 | DPIO_LANESTAGGER_STRAP_OVRD | |
1882 | DPIO_TX1_STAGGER_MASK(0x1f) | |
1860 | DPIO_TX1_STAGGER_MASK(0x1f) | |
1883 | DPIO_TX1_STAGGER_MULT(6) | |
1861 | DPIO_TX1_STAGGER_MULT(6) | |
1884 | DPIO_TX2_STAGGER_MULT(0)); |
1862 | DPIO_TX2_STAGGER_MULT(0)); |
1885 | 1863 | ||
1886 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
1864 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
1887 | DPIO_LANESTAGGER_STRAP(stagger) | |
1865 | DPIO_LANESTAGGER_STRAP(stagger) | |
1888 | DPIO_LANESTAGGER_STRAP_OVRD | |
1866 | DPIO_LANESTAGGER_STRAP_OVRD | |
1889 | DPIO_TX1_STAGGER_MASK(0x1f) | |
1867 | DPIO_TX1_STAGGER_MASK(0x1f) | |
1890 | DPIO_TX1_STAGGER_MULT(7) | |
1868 | DPIO_TX1_STAGGER_MULT(7) | |
1891 | DPIO_TX2_STAGGER_MULT(5)); |
1869 | DPIO_TX2_STAGGER_MULT(5)); |
1892 | 1870 | ||
1893 | /* Deassert data lane reset */ |
1871 | /* Deassert data lane reset */ |
1894 | chv_data_lane_soft_reset(encoder, false); |
1872 | chv_data_lane_soft_reset(encoder, false); |
1895 | 1873 | ||
1896 | /* Clear calc init */ |
1874 | /* Clear calc init */ |
1897 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1875 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1898 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1876 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1899 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1877 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1900 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
1878 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
1901 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1879 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1902 | 1880 | ||
1903 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
1881 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
1904 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1882 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
1905 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1883 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1906 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
1884 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
1907 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1885 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1908 | 1886 | ||
1909 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1887 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1910 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
1888 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
1911 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
1889 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
1912 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
1890 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
1913 | 1891 | ||
1914 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
1892 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
1915 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
1893 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
1916 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
1894 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
1917 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
1895 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
1918 | 1896 | ||
1919 | /* FIXME: Program the support xxx V-dB */ |
1897 | /* FIXME: Program the support xxx V-dB */ |
1920 | /* Use 800mV-0dB */ |
1898 | /* Use 800mV-0dB */ |
1921 | for (i = 0; i < 4; i++) { |
1899 | for (i = 0; i < 4; i++) { |
1922 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
1900 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
1923 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
1901 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
1924 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; |
1902 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; |
1925 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
1903 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
1926 | } |
1904 | } |
1927 | 1905 | ||
1928 | for (i = 0; i < 4; i++) { |
1906 | for (i = 0; i < 4; i++) { |
1929 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
1907 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
1930 | 1908 | ||
1931 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1909 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1932 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; |
1910 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; |
1933 | 1911 | ||
1934 | /* |
1912 | /* |
1935 | * Supposedly this value shouldn't matter when unique transition |
1913 | * Supposedly this value shouldn't matter when unique transition |
1936 | * scale is disabled, but in fact it does matter. Let's just |
1914 | * scale is disabled, but in fact it does matter. Let's just |
1937 | * always program the same value and hope it's OK. |
1915 | * always program the same value and hope it's OK. |
1938 | */ |
1916 | */ |
1939 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
1917 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
1940 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
1918 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
1941 | 1919 | ||
1942 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1920 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1943 | } |
1921 | } |
1944 | 1922 | ||
1945 | /* |
1923 | /* |
1946 | * The document said it needs to set bit 27 for ch0 and bit 26 |
1924 | * The document said it needs to set bit 27 for ch0 and bit 26 |
1947 | * for ch1. Might be a typo in the doc. |
1925 | * for ch1. Might be a typo in the doc. |
1948 | * For now, for this unique transition scale selection, set bit |
1926 | * For now, for this unique transition scale selection, set bit |
1949 | * 27 for ch0 and ch1. |
1927 | * 27 for ch0 and ch1. |
1950 | */ |
1928 | */ |
1951 | for (i = 0; i < 4; i++) { |
1929 | for (i = 0; i < 4; i++) { |
1952 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
1930 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
1953 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
1931 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
1954 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
1932 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
1955 | } |
1933 | } |
1956 | 1934 | ||
1957 | /* Start swing calculation */ |
1935 | /* Start swing calculation */ |
1958 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1936 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1959 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
1937 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
1960 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1938 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1961 | 1939 | ||
1962 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
1940 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
1963 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
1941 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
1964 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1942 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
1965 | 1943 | ||
1966 | mutex_unlock(&dev_priv->sb_lock); |
1944 | mutex_unlock(&dev_priv->sb_lock); |
1967 | 1945 | ||
1968 | intel_hdmi->set_infoframes(&encoder->base, |
1946 | intel_hdmi->set_infoframes(&encoder->base, |
1969 | intel_crtc->config->has_hdmi_sink, |
1947 | intel_crtc->config->has_hdmi_sink, |
1970 | adjusted_mode); |
1948 | adjusted_mode); |
1971 | 1949 | ||
1972 | g4x_enable_hdmi(encoder); |
1950 | g4x_enable_hdmi(encoder); |
1973 | 1951 | ||
1974 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
1952 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
1975 | 1953 | ||
1976 | /* Second common lane will stay alive on its own now */ |
1954 | /* Second common lane will stay alive on its own now */ |
1977 | if (dport->release_cl2_override) { |
1955 | if (dport->release_cl2_override) { |
1978 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
1956 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
1979 | dport->release_cl2_override = false; |
1957 | dport->release_cl2_override = false; |
1980 | } |
1958 | } |
1981 | } |
1959 | } |
1982 | 1960 | ||
1983 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1961 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1984 | { |
1962 | { |
1985 | kfree(to_intel_connector(connector)->detect_edid); |
1963 | kfree(to_intel_connector(connector)->detect_edid); |
1986 | drm_connector_cleanup(connector); |
1964 | drm_connector_cleanup(connector); |
1987 | kfree(connector); |
1965 | kfree(connector); |
1988 | } |
1966 | } |
1989 | 1967 | ||
1990 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
1968 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
1991 | .dpms = drm_atomic_helper_connector_dpms, |
1969 | .dpms = drm_atomic_helper_connector_dpms, |
1992 | .detect = intel_hdmi_detect, |
1970 | .detect = intel_hdmi_detect, |
1993 | .force = intel_hdmi_force, |
1971 | .force = intel_hdmi_force, |
1994 | .fill_modes = drm_helper_probe_single_connector_modes, |
1972 | .fill_modes = drm_helper_probe_single_connector_modes, |
1995 | .set_property = intel_hdmi_set_property, |
1973 | .set_property = intel_hdmi_set_property, |
1996 | .atomic_get_property = intel_connector_atomic_get_property, |
1974 | .atomic_get_property = intel_connector_atomic_get_property, |
1997 | .destroy = intel_hdmi_destroy, |
1975 | .destroy = intel_hdmi_destroy, |
1998 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
1976 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
1999 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
1977 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2000 | }; |
1978 | }; |
2001 | 1979 | ||
2002 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
1980 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
2003 | .get_modes = intel_hdmi_get_modes, |
1981 | .get_modes = intel_hdmi_get_modes, |
2004 | .mode_valid = intel_hdmi_mode_valid, |
1982 | .mode_valid = intel_hdmi_mode_valid, |
2005 | .best_encoder = intel_best_encoder, |
1983 | .best_encoder = intel_best_encoder, |
2006 | }; |
1984 | }; |
2007 | 1985 | ||
2008 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
1986 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
2009 | .destroy = intel_encoder_destroy, |
1987 | .destroy = intel_encoder_destroy, |
2010 | }; |
1988 | }; |
2011 | 1989 | ||
2012 | static void |
1990 | static void |
2013 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
1991 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
2014 | { |
1992 | { |
2015 | intel_attach_force_audio_property(connector); |
1993 | intel_attach_force_audio_property(connector); |
2016 | intel_attach_broadcast_rgb_property(connector); |
1994 | intel_attach_broadcast_rgb_property(connector); |
2017 | intel_hdmi->color_range_auto = true; |
1995 | intel_hdmi->color_range_auto = true; |
2018 | intel_attach_aspect_ratio_property(connector); |
1996 | intel_attach_aspect_ratio_property(connector); |
2019 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
1997 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
2020 | } |
1998 | } |
- | 1999 | ||
- | 2000 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, |
|
- | 2001 | enum port port) |
|
- | 2002 | { |
|
- | 2003 | const struct ddi_vbt_port_info *info = |
|
- | 2004 | &dev_priv->vbt.ddi_port_info[port]; |
|
- | 2005 | u8 ddc_pin; |
|
- | 2006 | ||
- | 2007 | if (info->alternate_ddc_pin) { |
|
- | 2008 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", |
|
- | 2009 | info->alternate_ddc_pin, port_name(port)); |
|
- | 2010 | return info->alternate_ddc_pin; |
|
- | 2011 | } |
|
- | 2012 | ||
- | 2013 | switch (port) { |
|
- | 2014 | case PORT_B: |
|
- | 2015 | if (IS_BROXTON(dev_priv)) |
|
- | 2016 | ddc_pin = GMBUS_PIN_1_BXT; |
|
- | 2017 | else |
|
- | 2018 | ddc_pin = GMBUS_PIN_DPB; |
|
- | 2019 | break; |
|
- | 2020 | case PORT_C: |
|
- | 2021 | if (IS_BROXTON(dev_priv)) |
|
- | 2022 | ddc_pin = GMBUS_PIN_2_BXT; |
|
- | 2023 | else |
|
- | 2024 | ddc_pin = GMBUS_PIN_DPC; |
|
- | 2025 | break; |
|
- | 2026 | case PORT_D: |
|
- | 2027 | if (IS_CHERRYVIEW(dev_priv)) |
|
- | 2028 | ddc_pin = GMBUS_PIN_DPD_CHV; |
|
- | 2029 | else |
|
- | 2030 | ddc_pin = GMBUS_PIN_DPD; |
|
- | 2031 | break; |
|
- | 2032 | default: |
|
- | 2033 | MISSING_CASE(port); |
|
- | 2034 | ddc_pin = GMBUS_PIN_DPB; |
|
- | 2035 | break; |
|
- | 2036 | } |
|
- | 2037 | ||
- | 2038 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", |
|
- | 2039 | ddc_pin, port_name(port)); |
|
- | 2040 | ||
- | 2041 | return ddc_pin; |
|
- | 2042 | } |
|
2021 | 2043 | ||
2022 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2044 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2023 | struct intel_connector *intel_connector) |
2045 | struct intel_connector *intel_connector) |
2024 | { |
2046 | { |
2025 | struct drm_connector *connector = &intel_connector->base; |
2047 | struct drm_connector *connector = &intel_connector->base; |
2026 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
2048 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
2027 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2049 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2028 | struct drm_device *dev = intel_encoder->base.dev; |
2050 | struct drm_device *dev = intel_encoder->base.dev; |
2029 | struct drm_i915_private *dev_priv = dev->dev_private; |
2051 | struct drm_i915_private *dev_priv = dev->dev_private; |
2030 | enum port port = intel_dig_port->port; |
2052 | enum port port = intel_dig_port->port; |
2031 | uint8_t alternate_ddc_pin; |
- | |
2032 | 2053 | ||
2033 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2054 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2034 | port_name(port)); |
2055 | port_name(port)); |
2035 | 2056 | ||
2036 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
2057 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
2037 | DRM_MODE_CONNECTOR_HDMIA); |
2058 | DRM_MODE_CONNECTOR_HDMIA); |
2038 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2059 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2039 | 2060 | ||
2040 | connector->interlace_allowed = 1; |
2061 | connector->interlace_allowed = 1; |
2041 | connector->doublescan_allowed = 0; |
2062 | connector->doublescan_allowed = 0; |
2042 | connector->stereo_allowed = 1; |
2063 | connector->stereo_allowed = 1; |
- | 2064 | ||
- | 2065 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
|
2043 | 2066 | ||
2044 | switch (port) { |
2067 | switch (port) { |
2045 | case PORT_B: |
- | |
2046 | if (IS_BROXTON(dev_priv)) |
- | |
2047 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; |
- | |
2048 | else |
- | |
2049 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
2068 | case PORT_B: |
2050 | /* |
2069 | /* |
2051 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
2070 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and |
2052 | * interrupts to check the external panel connection. |
2071 | * interrupts to check the external panel connection. |
2053 | */ |
2072 | */ |
2054 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
2073 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
2055 | intel_encoder->hpd_pin = HPD_PORT_A; |
2074 | intel_encoder->hpd_pin = HPD_PORT_A; |
2056 | else |
2075 | else |
2057 | intel_encoder->hpd_pin = HPD_PORT_B; |
2076 | intel_encoder->hpd_pin = HPD_PORT_B; |
2058 | break; |
2077 | break; |
2059 | case PORT_C: |
2078 | case PORT_C: |
2060 | if (IS_BROXTON(dev_priv)) |
- | |
2061 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; |
- | |
2062 | else |
- | |
2063 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
- | |
2064 | intel_encoder->hpd_pin = HPD_PORT_C; |
2079 | intel_encoder->hpd_pin = HPD_PORT_C; |
2065 | break; |
2080 | break; |
2066 | case PORT_D: |
2081 | case PORT_D: |
2067 | if (WARN_ON(IS_BROXTON(dev_priv))) |
- | |
2068 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; |
- | |
2069 | else if (IS_CHERRYVIEW(dev_priv)) |
- | |
2070 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
- | |
2071 | else |
- | |
2072 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
- | |
2073 | intel_encoder->hpd_pin = HPD_PORT_D; |
2082 | intel_encoder->hpd_pin = HPD_PORT_D; |
2074 | break; |
2083 | break; |
2075 | case PORT_E: |
2084 | case PORT_E: |
2076 | /* On SKL PORT E doesn't have seperate GMBUS pin |
- | |
2077 | * We rely on VBT to set a proper alternate GMBUS pin. */ |
- | |
2078 | alternate_ddc_pin = |
- | |
2079 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; |
- | |
2080 | switch (alternate_ddc_pin) { |
- | |
2081 | case DDC_PIN_B: |
- | |
2082 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; |
- | |
2083 | break; |
- | |
2084 | case DDC_PIN_C: |
- | |
2085 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; |
- | |
2086 | break; |
- | |
2087 | case DDC_PIN_D: |
- | |
2088 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
- | |
2089 | break; |
- | |
2090 | default: |
- | |
2091 | MISSING_CASE(alternate_ddc_pin); |
- | |
2092 | } |
- | |
2093 | intel_encoder->hpd_pin = HPD_PORT_E; |
2085 | intel_encoder->hpd_pin = HPD_PORT_E; |
2094 | break; |
2086 | break; |
2095 | case PORT_A: |
- | |
2096 | intel_encoder->hpd_pin = HPD_PORT_A; |
- | |
2097 | /* Internal port only for eDP. */ |
- | |
2098 | default: |
2087 | default: |
- | 2088 | MISSING_CASE(port); |
|
2099 | BUG(); |
2089 | return; |
2100 | } |
2090 | } |
2101 | 2091 | ||
2102 | if (IS_VALLEYVIEW(dev)) { |
2092 | if (IS_VALLEYVIEW(dev)) { |
2103 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
2093 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
2104 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
2094 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
2105 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
2095 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
2106 | } else if (IS_G4X(dev)) { |
2096 | } else if (IS_G4X(dev)) { |
2107 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2097 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2108 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
2098 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
2109 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
2099 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
2110 | } else if (HAS_DDI(dev)) { |
2100 | } else if (HAS_DDI(dev)) { |
2111 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
2101 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
2112 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
2102 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
2113 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
2103 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
2114 | } else if (HAS_PCH_IBX(dev)) { |
2104 | } else if (HAS_PCH_IBX(dev)) { |
2115 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
2105 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
2116 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
2106 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
2117 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
2107 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
2118 | } else { |
2108 | } else { |
2119 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
2109 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
2120 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
2110 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
2121 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
2111 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
2122 | } |
2112 | } |
2123 | 2113 | ||
2124 | if (HAS_DDI(dev)) |
2114 | if (HAS_DDI(dev)) |
2125 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2115 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2126 | else |
2116 | else |
2127 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2117 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2128 | intel_connector->unregister = intel_connector_unregister; |
2118 | intel_connector->unregister = intel_connector_unregister; |
2129 | 2119 | ||
2130 | intel_hdmi_add_properties(intel_hdmi, connector); |
2120 | intel_hdmi_add_properties(intel_hdmi, connector); |
2131 | 2121 | ||
2132 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
2122 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
2133 | drm_connector_register(connector); |
2123 | drm_connector_register(connector); |
2134 | intel_hdmi->attached_connector = intel_connector; |
2124 | intel_hdmi->attached_connector = intel_connector; |
2135 | 2125 | ||
2136 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2126 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2137 | * 0xd. Failure to do so will result in spurious interrupts being |
2127 | * 0xd. Failure to do so will result in spurious interrupts being |
2138 | * generated on the port when a cable is not attached. |
2128 | * generated on the port when a cable is not attached. |
2139 | */ |
2129 | */ |
2140 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
2130 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
2141 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2131 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2142 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2132 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
2143 | } |
2133 | } |
2144 | } |
2134 | } |
2145 | 2135 | ||
2146 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
2136 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
2147 | { |
2137 | { |
2148 | struct intel_digital_port *intel_dig_port; |
2138 | struct intel_digital_port *intel_dig_port; |
2149 | struct intel_encoder *intel_encoder; |
2139 | struct intel_encoder *intel_encoder; |
2150 | struct intel_connector *intel_connector; |
2140 | struct intel_connector *intel_connector; |
2151 | 2141 | ||
2152 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
2142 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
2153 | if (!intel_dig_port) |
2143 | if (!intel_dig_port) |
2154 | return; |
2144 | return; |
2155 | 2145 | ||
2156 | intel_connector = intel_connector_alloc(); |
2146 | intel_connector = intel_connector_alloc(); |
2157 | if (!intel_connector) { |
2147 | if (!intel_connector) { |
2158 | kfree(intel_dig_port); |
2148 | kfree(intel_dig_port); |
2159 | return; |
2149 | return; |
2160 | } |
2150 | } |
2161 | 2151 | ||
2162 | intel_encoder = &intel_dig_port->base; |
2152 | intel_encoder = &intel_dig_port->base; |
2163 | 2153 | ||
2164 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
2154 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
2165 | DRM_MODE_ENCODER_TMDS); |
2155 | DRM_MODE_ENCODER_TMDS); |
2166 | 2156 | ||
2167 | intel_encoder->compute_config = intel_hdmi_compute_config; |
2157 | intel_encoder->compute_config = intel_hdmi_compute_config; |
2168 | if (HAS_PCH_SPLIT(dev)) { |
2158 | if (HAS_PCH_SPLIT(dev)) { |
2169 | intel_encoder->disable = pch_disable_hdmi; |
2159 | intel_encoder->disable = pch_disable_hdmi; |
2170 | intel_encoder->post_disable = pch_post_disable_hdmi; |
2160 | intel_encoder->post_disable = pch_post_disable_hdmi; |
2171 | } else { |
2161 | } else { |
2172 | intel_encoder->disable = g4x_disable_hdmi; |
2162 | intel_encoder->disable = g4x_disable_hdmi; |
2173 | } |
2163 | } |
2174 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
2164 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
2175 | intel_encoder->get_config = intel_hdmi_get_config; |
2165 | intel_encoder->get_config = intel_hdmi_get_config; |
2176 | if (IS_CHERRYVIEW(dev)) { |
2166 | if (IS_CHERRYVIEW(dev)) { |
2177 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
2167 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
2178 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2168 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2179 | intel_encoder->enable = vlv_enable_hdmi; |
2169 | intel_encoder->enable = vlv_enable_hdmi; |
2180 | intel_encoder->post_disable = chv_hdmi_post_disable; |
2170 | intel_encoder->post_disable = chv_hdmi_post_disable; |
2181 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
2171 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
2182 | } else if (IS_VALLEYVIEW(dev)) { |
2172 | } else if (IS_VALLEYVIEW(dev)) { |
2183 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2173 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2184 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; |
2174 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; |
2185 | intel_encoder->enable = vlv_enable_hdmi; |
2175 | intel_encoder->enable = vlv_enable_hdmi; |
2186 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
2176 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
2187 | } else { |
2177 | } else { |
2188 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
2178 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
2189 | if (HAS_PCH_CPT(dev)) |
2179 | if (HAS_PCH_CPT(dev)) |
2190 | intel_encoder->enable = cpt_enable_hdmi; |
2180 | intel_encoder->enable = cpt_enable_hdmi; |
2191 | else if (HAS_PCH_IBX(dev)) |
2181 | else if (HAS_PCH_IBX(dev)) |
2192 | intel_encoder->enable = ibx_enable_hdmi; |
2182 | intel_encoder->enable = ibx_enable_hdmi; |
2193 | else |
2183 | else |
2194 | intel_encoder->enable = g4x_enable_hdmi; |
2184 | intel_encoder->enable = g4x_enable_hdmi; |
2195 | } |
2185 | } |
2196 | 2186 | ||
2197 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
2187 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
2198 | if (IS_CHERRYVIEW(dev)) { |
2188 | if (IS_CHERRYVIEW(dev)) { |
2199 | if (port == PORT_D) |
2189 | if (port == PORT_D) |
2200 | intel_encoder->crtc_mask = 1 << 2; |
2190 | intel_encoder->crtc_mask = 1 << 2; |
2201 | else |
2191 | else |
2202 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
2192 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
2203 | } else { |
2193 | } else { |
2204 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2194 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
2205 | } |
2195 | } |
2206 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
2196 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
2207 | /* |
2197 | /* |
2208 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems |
2198 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems |
2209 | * to work on real hardware. And since g4x can send infoframes to |
2199 | * to work on real hardware. And since g4x can send infoframes to |
2210 | * only one port anyway, nothing is lost by allowing it. |
2200 | * only one port anyway, nothing is lost by allowing it. |
2211 | */ |
2201 | */ |
2212 | if (IS_G4X(dev)) |
2202 | if (IS_G4X(dev)) |
2213 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
2203 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
2214 | 2204 | ||
2215 | intel_dig_port->port = port; |
2205 | intel_dig_port->port = port; |
2216 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
2206 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
2217 | intel_dig_port->dp.output_reg = 0; |
2207 | intel_dig_port->dp.output_reg = 0; |
2218 | 2208 | ||
2219 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
2209 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
2220 | }><>><>><>><>><>><>><>><>>>><>><>><>>><>>><>> |
2210 | }><>><>><>><>><>><>><>><>>>><>><>><>>><>>><>> |
2221 | ><21); |
2211 | ><21); |
2222 | >21); |
2212 | >21); |
2223 | ><21); |
2213 | ><21); |
2224 | >>>>>>>>>>>>>>>>>>>> |
2214 | >>>>>>>>>>>>>>>>>> |