WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_hdmi.c


/*
 * Copyright 2006 Dave Airlie 
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt 
 *	Jesse Barnes 
 */
 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include "intel_drv.h"
#include 
#include "i915_drv.h"
 
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
}
 
static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t enabled_bits;
 
	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
 
	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
	     "HDMI port enabled, expecting disabled\n");
}
 
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	struct intel_digital_port *intel_dig_port =
		container_of(encoder, struct intel_digital_port, base.base);
	return &intel_dig_port->hdmi;
}
 
static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
}
 
static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_SELECT_AVI;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_SELECT_SPD;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_SELECT_VENDOR;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
		return 0;
	}
}
 
static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VENDOR;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
		return 0;
	}
}
 
static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
	case HDMI_INFOFRAME_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD_HSW;
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VS_HSW;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
		return 0;
	}
}
 
static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
				  enum transcoder cpu_transcoder)
{
	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
	case HDMI_INFOFRAME_TYPE_SPD:
		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
	case HDMI_INFOFRAME_TYPE_VENDOR:
		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
		return 0;
	}
}
 
static void g4x_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 val = I915_READ(VIDEO_DIP_CTL);
	int i;
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);
 
	val &= ~g4x_infoframe_enable(type);
 
	I915_WRITE(VIDEO_DIP_CTL, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VIDEO_DIP_DATA, 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(VIDEO_DIP_CTL, val);
	POSTING_READ(VIDEO_DIP_CTL);
}
 
static void ibx_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);
 
	val &= ~g4x_infoframe_enable(type);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void cpt_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);
 
	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
	if (type != HDMI_INFOFRAME_TYPE_AVI)
		val &= ~g4x_infoframe_enable(type);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void vlv_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 
	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
	val |= g4x_infoframe_index(type);
 
	val &= ~g4x_infoframe_enable(type);
 
	I915_WRITE(reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
	mmiowb();
 
	val |= g4x_infoframe_enable(type);
	val &= ~VIDEO_DIP_FREQ_MASK;
	val |= VIDEO_DIP_FREQ_VSYNC;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
}
 
static void hsw_write_infoframe(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len)
{
	const uint32_t *data = frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
	u32 data_reg;
	int i;
	u32 val = I915_READ(ctl_reg);
 
	data_reg = hsw_infoframe_data_reg(type,
					  intel_crtc->config.cpu_transcoder);
	if (data_reg == 0)
		return;
 
	val &= ~hsw_infoframe_enable(type);
	I915_WRITE(ctl_reg, val);
 
	mmiowb();
	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(data_reg + i, 0);
	mmiowb();
 
	val |= hsw_infoframe_enable(type);
	I915_WRITE(ctl_reg, val);
	POSTING_READ(ctl_reg);
}
 
/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */
static void intel_write_infoframe(struct drm_encoder *encoder,
				  union hdmi_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
	ssize_t len;
 
	/* see comment above for the reason for this offset */
	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
	if (len < 0)
		return;
 
	/* Insert the 'hole' (see big comment above) at position 3 */
	buffer[0] = buffer[1];
	buffer[1] = buffer[2];
	buffer[2] = buffer[3];
	buffer[3] = 0;
	len++;
 
	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
}
 
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
					 struct drm_display_mode *adjusted_mode)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	union hdmi_infoframe frame;
	int ret;
 
	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
						       adjusted_mode);
	if (ret < 0) {
		DRM_ERROR("couldn't fill AVI infoframe\n");
		return;
	}
 
	if (intel_hdmi->rgb_quant_range_selectable) {
		if (intel_crtc->config.limited_color_range)
			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_LIMITED;
		else
			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_FULL;
	}
 
	intel_write_infoframe(encoder, &frame);
}
 
static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
{
	union hdmi_infoframe frame;
	int ret;
 
	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
	if (ret < 0) {
		DRM_ERROR("couldn't fill SPD infoframe\n");
		return;
	}
 
	frame.spd.sdi = HDMI_SPD_SDI_PC;
 
	intel_write_infoframe(encoder, &frame);
}
 
static void
intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
			      struct drm_display_mode *adjusted_mode)
{
	union hdmi_infoframe frame;
	int ret;
 
	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
							  adjusted_mode);
	if (ret < 0)
		return;
 
	intel_write_infoframe(encoder, &frame);
}
 
static void g4x_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	u32 reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
	u32 port;
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	switch (intel_dig_port->port) {
	case PORT_B:
		port = VIDEO_DIP_PORT_B;
		break;
	case PORT_C:
		port = VIDEO_DIP_PORT_C;
		break;
	default:
		BUG();
		return;
	}
 
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
			POSTING_READ(reg);
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~VIDEO_DIP_ENABLE_VENDOR;
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}
 
static void ibx_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
	u32 port;
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	switch (intel_dig_port->port) {
	case PORT_B:
		port = VIDEO_DIP_PORT_B;
		break;
	case PORT_C:
		port = VIDEO_DIP_PORT_C;
		break;
	case PORT_D:
		port = VIDEO_DIP_PORT_D;
		break;
	default:
		BUG();
		return;
	}
 
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
			POSTING_READ(reg);
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}
 
static void cpt_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}
 
static void vlv_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 
	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
		POSTING_READ(reg);
		return;
	}
 
	val |= VIDEO_DIP_ENABLE;
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}
 
static void hsw_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
	u32 val = I915_READ(reg);
 
	assert_hdmi_port_disabled(intel_hdmi);
 
	if (!intel_hdmi->has_hdmi_sink) {
		I915_WRITE(reg, 0);
		POSTING_READ(reg);
		return;
	}
 
	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 
	I915_WRITE(reg, val);
	POSTING_READ(reg);
 
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
}
 
static void intel_hdmi_mode_set(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
	u32 hdmi_val;
 
	hdmi_val = SDVO_ENCODING_HDMI;
	if (!HAS_PCH_SPLIT(dev))
		hdmi_val |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 
	if (crtc->config.pipe_bpp > 24)
		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
	else
		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 
	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 
	if (intel_hdmi->has_audio) {
		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(crtc->pipe));
		hdmi_val |= SDVO_AUDIO_ENABLE;
		hdmi_val |= HDMI_MODE_SELECT_HDMI;
		intel_write_eld(&encoder->base, adjusted_mode);
	}
 
		if (HAS_PCH_CPT(dev))
		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
	else
		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 
	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
	POSTING_READ(intel_hdmi->hdmi_reg);
 
	intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
}
 
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 tmp;
 
	tmp = I915_READ(intel_hdmi->hdmi_reg);
 
	if (!(tmp & SDVO_ENABLE))
		return false;
 
	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);
 
	return true;
}
 
static void intel_hdmi_get_config(struct intel_encoder *encoder,
				  struct intel_crtc_config *pipe_config)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	u32 tmp, flags = 0;
	int dotclock;
 
	tmp = I915_READ(intel_hdmi->hdmi_reg);
 
	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
 
	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;
 
	pipe_config->adjusted_mode.flags |= flags;
 
	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;
 
	if (HAS_PCH_SPLIT(dev_priv->dev))
		ironlake_check_encoder_dotclock(pipe_config, dotclock);
 
	pipe_config->adjusted_mode.crtc_clock = dotclock;
}
 
static void intel_enable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
	u32 enable_bits = SDVO_ENABLE;
 
	if (intel_hdmi->has_audio)
		enable_bits |= SDVO_AUDIO_ENABLE;
 
	temp = I915_READ(intel_hdmi->hdmi_reg);
 
	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it, so restore the transcoder select bit here. */
	if (HAS_PCH_IBX(dev))
		enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}
 
	temp |= enable_bits;
 
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
 
	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}
}
 
static void vlv_enable_hdmi(struct intel_encoder *encoder)
{
}
 
static void intel_disable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 
	temp = I915_READ(intel_hdmi->hdmi_reg);
 
	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
		struct drm_crtc *crtc = encoder->base.crtc;
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 
			if (temp & SDVO_PIPE_B_SELECT) {
				temp &= ~SDVO_PIPE_B_SELECT;
			I915_WRITE(intel_hdmi->hdmi_reg, temp);
			POSTING_READ(intel_hdmi->hdmi_reg);
 
				/* Again we need to write this twice. */
			I915_WRITE(intel_hdmi->hdmi_reg, temp);
			POSTING_READ(intel_hdmi->hdmi_reg);
 
				/* Transcoder selection bits only update
				 * effectively on vblank. */
				if (crtc)
					intel_wait_for_vblank(dev, pipe);
				else
					msleep(50);
			}
	}
 
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}
 
		temp &= ~enable_bits;
 
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
 
	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}
}
 
static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
{
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 
	if (IS_G4X(dev))
		return 165000;
	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
		return 300000;
	else
		return 225000;
}
 
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;
 
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;
 
	return MODE_OK;
}
 
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
			       struct intel_crtc_config *pipe_config)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
	int portclock_limit = hdmi_portclock_limit(intel_hdmi);
	int desired_bpp;
 
	if (intel_hdmi->color_range_auto) {
		/* See CEA-861-E - 5.1 Default Encoding Parameters */
		if (intel_hdmi->has_hdmi_sink &&
		    drm_match_cea_mode(adjusted_mode) > 1)
			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
		else
			intel_hdmi->color_range = 0;
	}
 
	if (intel_hdmi->color_range)
		pipe_config->limited_color_range = true;
 
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
		pipe_config->has_pch_encoder = true;
 
	/*
	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
	 * outputs. We also need to check that the higher clock still fits
	 * within limits.
	 */
	if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
	    && HAS_PCH_SPLIT(dev)) {
		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		desired_bpp = 12*3;
 
		/* Need to adjust the port link by 1.5x for 12bpc. */
		pipe_config->port_clock = clock_12bpc;
	} else {
		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		desired_bpp = 8*3;
	}
 
	if (!pipe_config->bw_constrained) {
		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		pipe_config->pipe_bpp = desired_bpp;
	}
 
	if (adjusted_mode->crtc_clock > portclock_limit) {
		DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
		return false;
	}
 
	return true;
}
 
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;
 
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));
 
	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	intel_hdmi->rgb_quant_range_selectable = false;
	edid = drm_get_edid(connector,
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
 
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
				intel_hdmi->has_hdmi_sink =
						drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
			intel_hdmi->rgb_quant_range_selectable =
				drm_rgb_quant_range_selectable(edid);
		}
		kfree(edid);
	}
 
	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				(intel_hdmi->force_audio == HDMI_AUDIO_ON);
		intel_encoder->type = INTEL_OUTPUT_HDMI;
	}
 
	return status;
}
 
static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 
	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */
 
	return intel_ddc_get_modes(connector,
				   intel_gmbus_get_adapter(dev_priv,
							   intel_hdmi->ddc_bus));
}
 
static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;
 
	edid = drm_get_edid(connector,
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}
 
	return has_audio;
}
 
static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;
 
	ret = drm_object_property_set_value(&connector->base, property, val);
	if (ret)
		return ret;
 
	if (property == dev_priv->force_audio_property) {
		enum hdmi_force_audio i = val;
		bool has_audio;
 
		if (i == intel_hdmi->force_audio)
			return 0;
 
		intel_hdmi->force_audio = i;
 
		if (i == HDMI_AUDIO_AUTO)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = (i == HDMI_AUDIO_ON);
 
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
 
		intel_hdmi->has_audio = has_audio;
		goto done;
	}
 
	if (property == dev_priv->broadcast_rgb_property) {
		bool old_auto = intel_hdmi->color_range_auto;
		uint32_t old_range = intel_hdmi->color_range;
 
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_hdmi->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_hdmi->color_range_auto = false;
			intel_hdmi->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_hdmi->color_range_auto = false;
			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
 
		if (old_auto == intel_hdmi->color_range_auto &&
		    old_range == intel_hdmi->color_range)
			return 0;
 
		goto done;
	}
 
	return -EINVAL;
 
done:
	if (intel_dig_port->base.base.crtc)
		intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
 
	return 0;
}
 
static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel port = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
	u32 val;
 
	if (!IS_VALLEYVIEW(dev))
		return;
 
	/* Enable clock channels for this port */
	mutex_lock(&dev_priv->dpio_lock);
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
 
	/* HDMI 1.0V-2dB */
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
 
 
	/* Program lane clock */
 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
	mutex_unlock(&dev_priv->dpio_lock);
 
	intel_enable_hdmi(encoder);
 
	vlv_wait_port_ready(dev_priv, dport);
}
 
static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel port = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
 
	if (!IS_VALLEYVIEW(dev))
		return;
 
	/* Program Tx lane resets to default */
	mutex_lock(&dev_priv->dpio_lock);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<
			 DPIO_PCS_CLK_SOFT_RESET);
 
	/* Fix up inter-pair skew failure */
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
 
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
 
	mutex_unlock(&dev_priv->dpio_lock);
}
 
static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel port = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
 
	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
	mutex_lock(&dev_priv->dpio_lock);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
	mutex_unlock(&dev_priv->dpio_lock);
}
 
static void intel_hdmi_destroy(struct drm_connector *connector)
{
 
	drm_connector_cleanup(connector);
	kfree(connector);
}
 
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = intel_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};
 
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};
 
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};
 
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
	intel_hdmi->color_range_auto = true;
}
 
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
 
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;
	connector->stereo_allowed = 1;
 
	switch (port) {
	case PORT_B:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		intel_encoder->hpd_pin = HPD_PORT_B;
		break;
	case PORT_C:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		intel_encoder->hpd_pin = HPD_PORT_C;
		break;
	case PORT_D:
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		intel_encoder->hpd_pin = HPD_PORT_D;
		break;
	case PORT_A:
		intel_encoder->hpd_pin = HPD_PORT_A;
		/* Internal port only for eDP. */
	default:
		BUG();
	}
 
	if (IS_VALLEYVIEW(dev)) {
		intel_hdmi->write_infoframe = vlv_write_infoframe;
		intel_hdmi->set_infoframes = vlv_set_infoframes;
	} else if (!HAS_PCH_SPLIT(dev)) {
		intel_hdmi->write_infoframe = g4x_write_infoframe;
		intel_hdmi->set_infoframes = g4x_set_infoframes;
	} else if (HAS_DDI(dev)) {
		intel_hdmi->write_infoframe = hsw_write_infoframe;
		intel_hdmi->set_infoframes = hsw_set_infoframes;
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
		intel_hdmi->set_infoframes = ibx_set_infoframes;
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
		intel_hdmi->set_infoframes = cpt_set_infoframes;
	}
 
	if (HAS_DDI(dev))
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
	intel_hdmi_add_properties(intel_hdmi, connector);
 
	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);
 
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
 
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
 
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;
 
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}
 
	intel_encoder = &intel_dig_port->base;
 
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
 
	intel_encoder->compute_config = intel_hdmi_compute_config;
	intel_encoder->mode_set = intel_hdmi_mode_set;
	intel_encoder->disable = intel_disable_hdmi;
	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
	intel_encoder->get_config = intel_hdmi_get_config;
	if (IS_VALLEYVIEW(dev)) {
		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
		intel_encoder->enable = vlv_enable_hdmi;
		intel_encoder->post_disable = vlv_hdmi_post_disable;
	} else {
		intel_encoder->enable = intel_enable_hdmi;
	}
 
	intel_encoder->type = INTEL_OUTPUT_HDMI;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
 
	intel_dig_port->port = port;
	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
	intel_dig_port->dp.output_reg = 0;
 
	intel_hdmi_init_connector(intel_dig_port, intel_connector);
}
>
>
>
>

Rev 4104	Rev 4560
1	/*	1	/*
2	* Copyright 2006 Dave Airlie	2	* Copyright 2006 Dave Airlie
3	* Copyright © 2006-2009 Intel Corporation	3	* Copyright © 2006-2009 Intel Corporation
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice (including the next	12	* The above copyright notice and this permission notice (including the next
13	* paragraph) shall be included in all copies or substantial portions of the	13	* paragraph) shall be included in all copies or substantial portions of the
14	* Software.	14	* Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22	* DEALINGS IN THE SOFTWARE.	22	* DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors:	24	* Authors:
25	* Eric Anholt	25	* Eric Anholt
26	* Jesse Barnes	26	* Jesse Barnes
27	*/	27	*/
28		28
29	#include	29	#include
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include	33	#include
34	#include	34	#include
35	#include	35	#include
36	#include "intel_drv.h"	36	#include "intel_drv.h"
37	#include	37	#include
38	#include "i915_drv.h"	38	#include "i915_drv.h"
39		39
40	static struct drm_device intel_hdmi_to_dev(struct intel_hdmi intel_hdmi)	40	static struct drm_device intel_hdmi_to_dev(struct intel_hdmi intel_hdmi)
41	{	41	{
42	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;	42	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
43	}	43	}
44		44
45	static void	45	static void
46	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)	46	assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47	{	47	{
48	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);	48	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49	struct drm_i915_private *dev_priv = dev->dev_private;	49	struct drm_i915_private *dev_priv = dev->dev_private;
50	uint32_t enabled_bits;	50	uint32_t enabled_bits;
51		51
52	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;	52	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
53		53
54	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,	54	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
55	"HDMI port enabled, expecting disabled\n");	55	"HDMI port enabled, expecting disabled\n");
56	}	56	}
57		57
58	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)	58	struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
59	{	59	{
60	struct intel_digital_port *intel_dig_port =	60	struct intel_digital_port *intel_dig_port =
61	container_of(encoder, struct intel_digital_port, base.base);	61	container_of(encoder, struct intel_digital_port, base.base);
62	return &intel_dig_port->hdmi;	62	return &intel_dig_port->hdmi;
63	}	63	}
64		64
65	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)	65	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
66	{	66	{
67	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);	67	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
68	}	68	}
69		69
70	static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)	70	static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
71	{	71	{
72	switch (type) {	72	switch (type) {
73	case HDMI_INFOFRAME_TYPE_AVI:	73	case HDMI_INFOFRAME_TYPE_AVI:
74	return VIDEO_DIP_SELECT_AVI;	74	return VIDEO_DIP_SELECT_AVI;
75	case HDMI_INFOFRAME_TYPE_SPD:	75	case HDMI_INFOFRAME_TYPE_SPD:
76	return VIDEO_DIP_SELECT_SPD;	76	return VIDEO_DIP_SELECT_SPD;
77	case HDMI_INFOFRAME_TYPE_VENDOR:	77	case HDMI_INFOFRAME_TYPE_VENDOR:
78	return VIDEO_DIP_SELECT_VENDOR;	78	return VIDEO_DIP_SELECT_VENDOR;
79	default:	79	default:
80	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);	80	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
81	return 0;	81	return 0;
82	}	82	}
83	}	83	}
84		84
85	static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)	85	static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
86	{	86	{
87	switch (type) {	87	switch (type) {
88	case HDMI_INFOFRAME_TYPE_AVI:	88	case HDMI_INFOFRAME_TYPE_AVI:
89	return VIDEO_DIP_ENABLE_AVI;	89	return VIDEO_DIP_ENABLE_AVI;
90	case HDMI_INFOFRAME_TYPE_SPD:	90	case HDMI_INFOFRAME_TYPE_SPD:
91	return VIDEO_DIP_ENABLE_SPD;	91	return VIDEO_DIP_ENABLE_SPD;
92	case HDMI_INFOFRAME_TYPE_VENDOR:	92	case HDMI_INFOFRAME_TYPE_VENDOR:
93	return VIDEO_DIP_ENABLE_VENDOR;	93	return VIDEO_DIP_ENABLE_VENDOR;
94	default:	94	default:
95	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);	95	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
96	return 0;	96	return 0;
97	}	97	}
98	}	98	}
99		99
100	static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)	100	static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
101	{	101	{
102	switch (type) {	102	switch (type) {
103	case HDMI_INFOFRAME_TYPE_AVI:	103	case HDMI_INFOFRAME_TYPE_AVI:
104	return VIDEO_DIP_ENABLE_AVI_HSW;	104	return VIDEO_DIP_ENABLE_AVI_HSW;
105	case HDMI_INFOFRAME_TYPE_SPD:	105	case HDMI_INFOFRAME_TYPE_SPD:
106	return VIDEO_DIP_ENABLE_SPD_HSW;	106	return VIDEO_DIP_ENABLE_SPD_HSW;
107	case HDMI_INFOFRAME_TYPE_VENDOR:	107	case HDMI_INFOFRAME_TYPE_VENDOR:
108	return VIDEO_DIP_ENABLE_VS_HSW;	108	return VIDEO_DIP_ENABLE_VS_HSW;
109	default:	109	default:
110	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);	110	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
111	return 0;	111	return 0;
112	}	112	}
113	}	113	}
114		114
115	static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,	115	static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
116	enum transcoder cpu_transcoder)	116	enum transcoder cpu_transcoder)
117	{	117	{
118	switch (type) {	118	switch (type) {
119	case HDMI_INFOFRAME_TYPE_AVI:	119	case HDMI_INFOFRAME_TYPE_AVI:
120	return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);	120	return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
121	case HDMI_INFOFRAME_TYPE_SPD:	121	case HDMI_INFOFRAME_TYPE_SPD:
122	return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);	122	return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
123	case HDMI_INFOFRAME_TYPE_VENDOR:	123	case HDMI_INFOFRAME_TYPE_VENDOR:
124	return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);	124	return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
125	default:	125	default:
126	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);	126	DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
127	return 0;	127	return 0;
128	}	128	}
129	}	129	}
130		130
131	static void g4x_write_infoframe(struct drm_encoder *encoder,	131	static void g4x_write_infoframe(struct drm_encoder *encoder,
132	enum hdmi_infoframe_type type,	132	enum hdmi_infoframe_type type,
133	const uint8_t *frame, ssize_t len)	133	const void *frame, ssize_t len)
134	{	134	{
135	uint32_t data = (uint32_t )frame;	135	const uint32_t *data = frame;
136	struct drm_device *dev = encoder->dev;	136	struct drm_device *dev = encoder->dev;
137	struct drm_i915_private *dev_priv = dev->dev_private;	137	struct drm_i915_private *dev_priv = dev->dev_private;
138	u32 val = I915_READ(VIDEO_DIP_CTL);	138	u32 val = I915_READ(VIDEO_DIP_CTL);
139	int i;	139	int i;
140		140
141	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	141	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
142		142
143	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	143	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
144	val \|= g4x_infoframe_index(type);	144	val \|= g4x_infoframe_index(type);
145		145
146	val &= ~g4x_infoframe_enable(type);	146	val &= ~g4x_infoframe_enable(type);
147		147
148	I915_WRITE(VIDEO_DIP_CTL, val);	148	I915_WRITE(VIDEO_DIP_CTL, val);
149		149
150	mmiowb();	150	mmiowb();
151	for (i = 0; i < len; i += 4) {	151	for (i = 0; i < len; i += 4) {
152	I915_WRITE(VIDEO_DIP_DATA, *data);	152	I915_WRITE(VIDEO_DIP_DATA, *data);
153	data++;	153	data++;
154	}	154	}
155	/* Write every possible data byte to force correct ECC calculation. */	155	/* Write every possible data byte to force correct ECC calculation. */
156	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	156	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
157	I915_WRITE(VIDEO_DIP_DATA, 0);	157	I915_WRITE(VIDEO_DIP_DATA, 0);
158	mmiowb();	158	mmiowb();
159		159
160	val \|= g4x_infoframe_enable(type);	160	val \|= g4x_infoframe_enable(type);
161	val &= ~VIDEO_DIP_FREQ_MASK;	161	val &= ~VIDEO_DIP_FREQ_MASK;
162	val \|= VIDEO_DIP_FREQ_VSYNC;	162	val \|= VIDEO_DIP_FREQ_VSYNC;
163		163
164	I915_WRITE(VIDEO_DIP_CTL, val);	164	I915_WRITE(VIDEO_DIP_CTL, val);
165	POSTING_READ(VIDEO_DIP_CTL);	165	POSTING_READ(VIDEO_DIP_CTL);
166	}	166	}
167		167
168	static void ibx_write_infoframe(struct drm_encoder *encoder,	168	static void ibx_write_infoframe(struct drm_encoder *encoder,
169	enum hdmi_infoframe_type type,	169	enum hdmi_infoframe_type type,
170	const uint8_t *frame, ssize_t len)	170	const void *frame, ssize_t len)
171	{	171	{
172	uint32_t data = (uint32_t )frame;	172	const uint32_t *data = frame;
173	struct drm_device *dev = encoder->dev;	173	struct drm_device *dev = encoder->dev;
174	struct drm_i915_private *dev_priv = dev->dev_private;	174	struct drm_i915_private *dev_priv = dev->dev_private;
175	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	175	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
176	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	176	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
177	u32 val = I915_READ(reg);	177	u32 val = I915_READ(reg);
178		178
179	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	179	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
180		180
181	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	181	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
182	val \|= g4x_infoframe_index(type);	182	val \|= g4x_infoframe_index(type);
183		183
184	val &= ~g4x_infoframe_enable(type);	184	val &= ~g4x_infoframe_enable(type);
185		185
186	I915_WRITE(reg, val);	186	I915_WRITE(reg, val);
187		187
188	mmiowb();	188	mmiowb();
189	for (i = 0; i < len; i += 4) {	189	for (i = 0; i < len; i += 4) {
190	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	190	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
191	data++;	191	data++;
192	}	192	}
193	/* Write every possible data byte to force correct ECC calculation. */	193	/* Write every possible data byte to force correct ECC calculation. */
194	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	194	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
195	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	195	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
196	mmiowb();	196	mmiowb();
197		197
198	val \|= g4x_infoframe_enable(type);	198	val \|= g4x_infoframe_enable(type);
199	val &= ~VIDEO_DIP_FREQ_MASK;	199	val &= ~VIDEO_DIP_FREQ_MASK;
200	val \|= VIDEO_DIP_FREQ_VSYNC;	200	val \|= VIDEO_DIP_FREQ_VSYNC;
201		201
202	I915_WRITE(reg, val);	202	I915_WRITE(reg, val);
203	POSTING_READ(reg);	203	POSTING_READ(reg);
204	}	204	}
205		205
206	static void cpt_write_infoframe(struct drm_encoder *encoder,	206	static void cpt_write_infoframe(struct drm_encoder *encoder,
207	enum hdmi_infoframe_type type,	207	enum hdmi_infoframe_type type,
208	const uint8_t *frame, ssize_t len)	208	const void *frame, ssize_t len)
209	{	209	{
210	uint32_t data = (uint32_t )frame;	210	const uint32_t *data = frame;
211	struct drm_device *dev = encoder->dev;	211	struct drm_device *dev = encoder->dev;
212	struct drm_i915_private *dev_priv = dev->dev_private;	212	struct drm_i915_private *dev_priv = dev->dev_private;
213	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	213	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
214	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	214	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
215	u32 val = I915_READ(reg);	215	u32 val = I915_READ(reg);
216		216
217	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	217	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
218		218
219	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	219	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
220	val \|= g4x_infoframe_index(type);	220	val \|= g4x_infoframe_index(type);
221		221
222	/* The DIP control register spec says that we need to update the AVI	222	/* The DIP control register spec says that we need to update the AVI
223	* infoframe without clearing its enable bit */	223	* infoframe without clearing its enable bit */
224	if (type != HDMI_INFOFRAME_TYPE_AVI)	224	if (type != HDMI_INFOFRAME_TYPE_AVI)
225	val &= ~g4x_infoframe_enable(type);	225	val &= ~g4x_infoframe_enable(type);
226		226
227	I915_WRITE(reg, val);	227	I915_WRITE(reg, val);
228		228
229	mmiowb();	229	mmiowb();
230	for (i = 0; i < len; i += 4) {	230	for (i = 0; i < len; i += 4) {
231	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	231	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
232	data++;	232	data++;
233	}	233	}
234	/* Write every possible data byte to force correct ECC calculation. */	234	/* Write every possible data byte to force correct ECC calculation. */
235	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	235	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
236	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	236	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
237	mmiowb();	237	mmiowb();
238		238
239	val \|= g4x_infoframe_enable(type);	239	val \|= g4x_infoframe_enable(type);
240	val &= ~VIDEO_DIP_FREQ_MASK;	240	val &= ~VIDEO_DIP_FREQ_MASK;
241	val \|= VIDEO_DIP_FREQ_VSYNC;	241	val \|= VIDEO_DIP_FREQ_VSYNC;
242		242
243	I915_WRITE(reg, val);	243	I915_WRITE(reg, val);
244	POSTING_READ(reg);	244	POSTING_READ(reg);
245	}	245	}
246		246
247	static void vlv_write_infoframe(struct drm_encoder *encoder,	247	static void vlv_write_infoframe(struct drm_encoder *encoder,
248	enum hdmi_infoframe_type type,	248	enum hdmi_infoframe_type type,
249	const uint8_t *frame, ssize_t len)	249	const void *frame, ssize_t len)
250	{	250	{
251	uint32_t data = (uint32_t )frame;	251	const uint32_t *data = frame;
252	struct drm_device *dev = encoder->dev;	252	struct drm_device *dev = encoder->dev;
253	struct drm_i915_private *dev_priv = dev->dev_private;	253	struct drm_i915_private *dev_priv = dev->dev_private;
254	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	254	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
255	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);	255	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
256	u32 val = I915_READ(reg);	256	u32 val = I915_READ(reg);
257		257
258	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");	258	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
259		259
260	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */	260	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
261	val \|= g4x_infoframe_index(type);	261	val \|= g4x_infoframe_index(type);
262		262
263	val &= ~g4x_infoframe_enable(type);	263	val &= ~g4x_infoframe_enable(type);
264		264
265	I915_WRITE(reg, val);	265	I915_WRITE(reg, val);
266		266
267	mmiowb();	267	mmiowb();
268	for (i = 0; i < len; i += 4) {	268	for (i = 0; i < len; i += 4) {
269	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);	269	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
270	data++;	270	data++;
271	}	271	}
272	/* Write every possible data byte to force correct ECC calculation. */	272	/* Write every possible data byte to force correct ECC calculation. */
273	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	273	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
274	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);	274	I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
275	mmiowb();	275	mmiowb();
276		276
277	val \|= g4x_infoframe_enable(type);	277	val \|= g4x_infoframe_enable(type);
278	val &= ~VIDEO_DIP_FREQ_MASK;	278	val &= ~VIDEO_DIP_FREQ_MASK;
279	val \|= VIDEO_DIP_FREQ_VSYNC;	279	val \|= VIDEO_DIP_FREQ_VSYNC;
280		280
281	I915_WRITE(reg, val);	281	I915_WRITE(reg, val);
282	POSTING_READ(reg);	282	POSTING_READ(reg);
283	}	283	}
284		284
285	static void hsw_write_infoframe(struct drm_encoder *encoder,	285	static void hsw_write_infoframe(struct drm_encoder *encoder,
286	enum hdmi_infoframe_type type,	286	enum hdmi_infoframe_type type,
287	const uint8_t *frame, ssize_t len)	287	const void *frame, ssize_t len)
288	{	288	{
289	uint32_t data = (uint32_t )frame;	289	const uint32_t *data = frame;
290	struct drm_device *dev = encoder->dev;	290	struct drm_device *dev = encoder->dev;
291	struct drm_i915_private *dev_priv = dev->dev_private;	291	struct drm_i915_private *dev_priv = dev->dev_private;
292	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	292	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
293	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);	293	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
294	u32 data_reg;	294	u32 data_reg;
295	int i;	295	int i;
296	u32 val = I915_READ(ctl_reg);	296	u32 val = I915_READ(ctl_reg);
297		297
298	data_reg = hsw_infoframe_data_reg(type,	298	data_reg = hsw_infoframe_data_reg(type,
299	intel_crtc->config.cpu_transcoder);	299	intel_crtc->config.cpu_transcoder);
300	if (data_reg == 0)	300	if (data_reg == 0)
301	return;	301	return;
302		302
303	val &= ~hsw_infoframe_enable(type);	303	val &= ~hsw_infoframe_enable(type);
304	I915_WRITE(ctl_reg, val);	304	I915_WRITE(ctl_reg, val);
305		305
306	mmiowb();	306	mmiowb();
307	for (i = 0; i < len; i += 4) {	307	for (i = 0; i < len; i += 4) {
308	I915_WRITE(data_reg + i, *data);	308	I915_WRITE(data_reg + i, *data);
309	data++;	309	data++;
310	}	310	}
311	/* Write every possible data byte to force correct ECC calculation. */	311	/* Write every possible data byte to force correct ECC calculation. */
312	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)	312	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
313	I915_WRITE(data_reg + i, 0);	313	I915_WRITE(data_reg + i, 0);
314	mmiowb();	314	mmiowb();
315		315
316	val \|= hsw_infoframe_enable(type);	316	val \|= hsw_infoframe_enable(type);
317	I915_WRITE(ctl_reg, val);	317	I915_WRITE(ctl_reg, val);
318	POSTING_READ(ctl_reg);	318	POSTING_READ(ctl_reg);
319	}	319	}
320		320
321	/*	321	/*
322	* The data we write to the DIP data buffer registers is 1 byte bigger than the	322	* The data we write to the DIP data buffer registers is 1 byte bigger than the
323	* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting	323	* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
324	* at 0). It's also a byte used by DisplayPort so the same DIP registers can be	324	* at 0). It's also a byte used by DisplayPort so the same DIP registers can be
325	* used for both technologies.	325	* used for both technologies.
326	*	326	*
327	* DW0: Reserved/ECC/DP \| HB2 \| HB1 \| HB0	327	* DW0: Reserved/ECC/DP \| HB2 \| HB1 \| HB0
328	* DW1: DB3 \| DB2 \| DB1 \| DB0	328	* DW1: DB3 \| DB2 \| DB1 \| DB0
329	* DW2: DB7 \| DB6 \| DB5 \| DB4	329	* DW2: DB7 \| DB6 \| DB5 \| DB4
330	* DW3: ...	330	* DW3: ...
331	*	331	*
332	* (HB is Header Byte, DB is Data Byte)	332	* (HB is Header Byte, DB is Data Byte)
333	*	333	*
334	* The hdmi pack() functions don't know about that hardware specific hole so we	334	* The hdmi pack() functions don't know about that hardware specific hole so we
335	* trick them by giving an offset into the buffer and moving back the header	335	* trick them by giving an offset into the buffer and moving back the header
336	* bytes by one.	336	* bytes by one.
337	*/	337	*/
338	static void intel_write_infoframe(struct drm_encoder *encoder,	338	static void intel_write_infoframe(struct drm_encoder *encoder,
339	union hdmi_infoframe *frame)	339	union hdmi_infoframe *frame)
340	{	340	{
341	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	341	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
342	uint8_t buffer[VIDEO_DIP_DATA_SIZE];	342	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
343	ssize_t len;	343	ssize_t len;
344		344
345	/* see comment above for the reason for this offset */	345	/* see comment above for the reason for this offset */
346	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);	346	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
347	if (len < 0)	347	if (len < 0)
348	return;	348	return;
349		349
350	/* Insert the 'hole' (see big comment above) at position 3 */	350	/* Insert the 'hole' (see big comment above) at position 3 */
351	buffer[0] = buffer[1];	351	buffer[0] = buffer[1];
352	buffer[1] = buffer[2];	352	buffer[1] = buffer[2];
353	buffer[2] = buffer[3];	353	buffer[2] = buffer[3];
354	buffer[3] = 0;	354	buffer[3] = 0;
355	len++;	355	len++;
356		356
357	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);	357	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
358	}	358	}
359		359
360	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,	360	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
361	struct drm_display_mode *adjusted_mode)	361	struct drm_display_mode *adjusted_mode)
362	{	362	{
363	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	363	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
364	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	364	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
365	union hdmi_infoframe frame;	365	union hdmi_infoframe frame;
366	int ret;	366	int ret;
367		367
368	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,	368	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
369	adjusted_mode);	369	adjusted_mode);
370	if (ret < 0) {	370	if (ret < 0) {
371	DRM_ERROR("couldn't fill AVI infoframe\n");	371	DRM_ERROR("couldn't fill AVI infoframe\n");
372	return;	372	return;
373	}	373	}
374		374
375	if (intel_hdmi->rgb_quant_range_selectable) {	375	if (intel_hdmi->rgb_quant_range_selectable) {
376	if (intel_crtc->config.limited_color_range)	376	if (intel_crtc->config.limited_color_range)
377	frame.avi.quantization_range =	377	frame.avi.quantization_range =
378	HDMI_QUANTIZATION_RANGE_LIMITED;	378	HDMI_QUANTIZATION_RANGE_LIMITED;
379	else	379	else
380	frame.avi.quantization_range =	380	frame.avi.quantization_range =
381	HDMI_QUANTIZATION_RANGE_FULL;	381	HDMI_QUANTIZATION_RANGE_FULL;
382	}	382	}
383		383
384	intel_write_infoframe(encoder, &frame);	384	intel_write_infoframe(encoder, &frame);
385	}	385	}
386		386
387	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)	387	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
388	{	388	{
389	union hdmi_infoframe frame;	389	union hdmi_infoframe frame;
390	int ret;	390	int ret;
391		391
392	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");	392	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
393	if (ret < 0) {	393	if (ret < 0) {
394	DRM_ERROR("couldn't fill SPD infoframe\n");	394	DRM_ERROR("couldn't fill SPD infoframe\n");
395	return;	395	return;
396	}	396	}
397		397
398	frame.spd.sdi = HDMI_SPD_SDI_PC;	398	frame.spd.sdi = HDMI_SPD_SDI_PC;
399		399
400	intel_write_infoframe(encoder, &frame);	400	intel_write_infoframe(encoder, &frame);
401	}	401	}
402		402
403	static void	403	static void
404	intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,	404	intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
405	struct drm_display_mode *adjusted_mode)	405	struct drm_display_mode *adjusted_mode)
406	{	406	{
407	union hdmi_infoframe frame;	407	union hdmi_infoframe frame;
408	int ret;	408	int ret;
409		409
410	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,	410	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
411	adjusted_mode);	411	adjusted_mode);
412	if (ret < 0)	412	if (ret < 0)
413	return;	413	return;
414		414
415	intel_write_infoframe(encoder, &frame);	415	intel_write_infoframe(encoder, &frame);
416	}	416	}
417		417
418	static void g4x_set_infoframes(struct drm_encoder *encoder,	418	static void g4x_set_infoframes(struct drm_encoder *encoder,
419	struct drm_display_mode *adjusted_mode)	419	struct drm_display_mode *adjusted_mode)
420	{	420	{
421	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	421	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
422	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);	422	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
423	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;	423	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
424	u32 reg = VIDEO_DIP_CTL;	424	u32 reg = VIDEO_DIP_CTL;
425	u32 val = I915_READ(reg);	425	u32 val = I915_READ(reg);
426	u32 port;	426	u32 port;
427		427
428	assert_hdmi_port_disabled(intel_hdmi);	428	assert_hdmi_port_disabled(intel_hdmi);
429		429
430	/* If the registers were not initialized yet, they might be zeroes,	430	/* If the registers were not initialized yet, they might be zeroes,
431	* which means we're selecting the AVI DIP and we're setting its	431	* which means we're selecting the AVI DIP and we're setting its
432	* frequency to once. This seems to really confuse the HW and make	432	* frequency to once. This seems to really confuse the HW and make
433	* things stop working (the register spec says the AVI always needs to	433	* things stop working (the register spec says the AVI always needs to
434	* be sent every VSync). So here we avoid writing to the register more	434	* be sent every VSync). So here we avoid writing to the register more
435	* than we need and also explicitly select the AVI DIP and explicitly	435	* than we need and also explicitly select the AVI DIP and explicitly
436	* set its frequency to every VSync. Avoiding to write it twice seems to	436	* set its frequency to every VSync. Avoiding to write it twice seems to
437	* be enough to solve the problem, but being defensive shouldn't hurt us	437	* be enough to solve the problem, but being defensive shouldn't hurt us
438	* either. */	438	* either. */
439	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;	439	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
440		440
441	if (!intel_hdmi->has_hdmi_sink) {	441	if (!intel_hdmi->has_hdmi_sink) {
442	if (!(val & VIDEO_DIP_ENABLE))	442	if (!(val & VIDEO_DIP_ENABLE))
443	return;	443	return;
444	val &= ~VIDEO_DIP_ENABLE;	444	val &= ~VIDEO_DIP_ENABLE;
445	I915_WRITE(reg, val);	445	I915_WRITE(reg, val);
446	POSTING_READ(reg);	446	POSTING_READ(reg);
447	return;	447	return;
448	}	448	}
449		449
450	switch (intel_dig_port->port) {	450	switch (intel_dig_port->port) {
451	case PORT_B:	451	case PORT_B:
452	port = VIDEO_DIP_PORT_B;	452	port = VIDEO_DIP_PORT_B;
453	break;	453	break;
454	case PORT_C:	454	case PORT_C:
455	port = VIDEO_DIP_PORT_C;	455	port = VIDEO_DIP_PORT_C;
456	break;	456	break;
457	default:	457	default:
458	BUG();	458	BUG();
459	return;	459	return;
460	}	460	}
461		461
462	if (port != (val & VIDEO_DIP_PORT_MASK)) {	462	if (port != (val & VIDEO_DIP_PORT_MASK)) {
463	if (val & VIDEO_DIP_ENABLE) {	463	if (val & VIDEO_DIP_ENABLE) {
464	val &= ~VIDEO_DIP_ENABLE;	464	val &= ~VIDEO_DIP_ENABLE;
465	I915_WRITE(reg, val);	465	I915_WRITE(reg, val);
466	POSTING_READ(reg);	466	POSTING_READ(reg);
467	}	467	}
468	val &= ~VIDEO_DIP_PORT_MASK;	468	val &= ~VIDEO_DIP_PORT_MASK;
469	val \|= port;	469	val \|= port;
470	}	470	}
471		471
472	val \|= VIDEO_DIP_ENABLE;	472	val \|= VIDEO_DIP_ENABLE;
473	val &= ~VIDEO_DIP_ENABLE_VENDOR;	473	val &= ~VIDEO_DIP_ENABLE_VENDOR;
474		474
475	I915_WRITE(reg, val);	475	I915_WRITE(reg, val);
476	POSTING_READ(reg);	476	POSTING_READ(reg);
477		477
478	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	478	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
479	intel_hdmi_set_spd_infoframe(encoder);	479	intel_hdmi_set_spd_infoframe(encoder);
480	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);	480	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
481	}	481	}
482		482
483	static void ibx_set_infoframes(struct drm_encoder *encoder,	483	static void ibx_set_infoframes(struct drm_encoder *encoder,
484	struct drm_display_mode *adjusted_mode)	484	struct drm_display_mode *adjusted_mode)
485	{	485	{
486	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	486	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
487	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	487	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
488	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);	488	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
489	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;	489	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
490	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	490	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
491	u32 val = I915_READ(reg);	491	u32 val = I915_READ(reg);
492	u32 port;	492	u32 port;
493		493
494	assert_hdmi_port_disabled(intel_hdmi);	494	assert_hdmi_port_disabled(intel_hdmi);
495		495
496	/* See the big comment in g4x_set_infoframes() */	496	/* See the big comment in g4x_set_infoframes() */
497	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;	497	val \|= VIDEO_DIP_SELECT_AVI \| VIDEO_DIP_FREQ_VSYNC;
498		498
499	if (!intel_hdmi->has_hdmi_sink) {	499	if (!intel_hdmi->has_hdmi_sink) {
500	if (!(val & VIDEO_DIP_ENABLE))	500	if (!(val & VIDEO_DIP_ENABLE))

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_hdmi.c – Rev 4104 → 4560