WebSVN – Kolibri OS – Diff – /drivers/video/drm/i915/intel_drv.h


/*
 * Copyright (c) 2006 Dave Airlie 
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes 
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__
 
#include 
#include 
#include 
#include 
#include "i915_drv.h"
#include 
#include 
#include 
#include 
#include 
 
 
 
#define DIV_ROUND_CLOSEST_ULL(ll, d)	\
({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
 
/**
 * _wait_for - magic (register) wait macro
 *
 * Does the right thing for modeset paths when run under kdgb or similar atomic
 * contexts. Note that it's important that we check the condition again after
 * having timed out, since the timeout could be due to preemption or similar and
 * we've never had a chance to check the condition before the timeout.
 */
#define _wait_for(COND, MS, W) ({ \
	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;	\
	int ret__ = 0;							\
	while (!(COND)) {						\
		if (time_after(jiffies, timeout__)) {			\
			if (!(COND))					\
			ret__ = -ETIMEDOUT;				\
			break;						\
		}							\
		if (W )  {				\
         msleep(W); \
		} else {						\
			cpu_relax();					\
		}							\
	}								\
	ret__;								\
})
 
#define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
#define wait_for_atomic_us(COND, US) _wait_for((COND), \
					       DIV_ROUND_UP((US), 1000), 0)
 
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
 
/*
 * Display related stuff
 */
 
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */
 
/* Maximum cursor sizes */
#define GEN2_CURSOR_WIDTH 64
#define GEN2_CURSOR_HEIGHT 64
#define MAX_CURSOR_WIDTH 256
#define MAX_CURSOR_HEIGHT 256
 
#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2
 
/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
enum intel_output_type {
	INTEL_OUTPUT_UNUSED = 0,
	INTEL_OUTPUT_ANALOG = 1,
	INTEL_OUTPUT_DVO = 2,
	INTEL_OUTPUT_SDVO = 3,
	INTEL_OUTPUT_LVDS = 4,
	INTEL_OUTPUT_TVOUT = 5,
	INTEL_OUTPUT_HDMI = 6,
	INTEL_OUTPUT_DISPLAYPORT = 7,
	INTEL_OUTPUT_EDP = 8,
	INTEL_OUTPUT_DSI = 9,
	INTEL_OUTPUT_UNKNOWN = 10,
	INTEL_OUTPUT_DP_MST = 11,
};
 
#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4
 
#define INTEL_DSI_VIDEO_MODE	0
#define INTEL_DSI_COMMAND_MODE	1
 
struct intel_framebuffer {
	struct drm_framebuffer base;
	struct drm_i915_gem_object *obj;
};
 
struct intel_fbdev {
	struct drm_fb_helper helper;
	struct intel_framebuffer *fb;
	struct list_head fbdev_list;
	struct drm_display_mode *our_mode;
	int preferred_bpp;
};
 
struct intel_encoder {
	struct drm_encoder base;
	/*
	 * The new crtc this encoder will be driven from. Only differs from
	 * base->crtc while a modeset is in progress.
	 */
	struct intel_crtc *new_crtc;
 
	enum intel_output_type type;
	unsigned int cloneable;
	bool connectors_active;
	void (*hot_plug)(struct intel_encoder *);
	bool (*compute_config)(struct intel_encoder *,
			       struct intel_crtc_config *);
	void (*pre_pll_enable)(struct intel_encoder *);
	void (*pre_enable)(struct intel_encoder *);
	void (*enable)(struct intel_encoder *);
	void (*mode_set)(struct intel_encoder *intel_encoder);
	void (*disable)(struct intel_encoder *);
	void (*post_disable)(struct intel_encoder *);
	/* Read out the current hw state of this connector, returning true if
	 * the encoder is active. If the encoder is enabled it also set the pipe
	 * it is connected to in the pipe parameter. */
	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
	/* Reconstructs the equivalent mode flags for the current hardware
	 * state. This must be called _after_ display->get_pipe_config has
	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
	 * be set correctly before calling this function. */
	void (*get_config)(struct intel_encoder *,
			   struct intel_crtc_config *pipe_config);
	/*
	 * Called during system suspend after all pending requests for the
	 * encoder are flushed (for example for DP AUX transactions) and
	 * device interrupts are disabled.
	 */
	void (*suspend)(struct intel_encoder *);
	int crtc_mask;
	enum hpd_pin hpd_pin;
};
 
struct intel_panel {
	struct drm_display_mode *fixed_mode;
	struct drm_display_mode *downclock_mode;
	int fitting_mode;
 
	/* backlight */
	struct {
		bool present;
		u32 level;
		u32 min;
		u32 max;
		bool enabled;
		bool combination_mode;	/* gen 2/4 only */
		bool active_low_pwm;
		struct backlight_device *device;
	} backlight;
 
	void (*backlight_power)(struct intel_connector *, bool enable);
};
 
struct intel_connector {
	struct drm_connector base;
	/*
	 * The fixed encoder this connector is connected to.
	 */
	struct intel_encoder *encoder;
 
	/*
	 * The new encoder this connector will be driven. Only differs from
	 * encoder while a modeset is in progress.
	 */
	struct intel_encoder *new_encoder;
 
	/* Reads out the current hw, returning true if the connector is enabled
	 * and active (i.e. dpms ON state). */
	bool (*get_hw_state)(struct intel_connector *);
 
	/*
	 * Removes all interfaces through which the connector is accessible
	 * - like sysfs, debugfs entries -, so that no new operations can be
	 * started on the connector. Also makes sure all currently pending
	 * operations finish before returing.
	 */
	void (*unregister)(struct intel_connector *);
 
	/* Panel info for eDP and LVDS */
	struct intel_panel panel;
 
	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
	struct edid *edid;
	struct edid *detect_edid;
 
	/* since POLL and HPD connectors may use the same HPD line keep the native
	   state of connector->polled in case hotplug storm detection changes it */
	u8 polled;
 
	void *port; /* store this opaque as its illegal to dereference it */
 
	struct intel_dp *mst_port;
};
 
typedef struct dpll {
	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
} intel_clock_t;
 
struct intel_plane_state {
	struct drm_crtc *crtc;
	struct drm_framebuffer *fb;
	struct drm_rect src;
	struct drm_rect dst;
	struct drm_rect clip;
	struct drm_rect orig_src;
	struct drm_rect orig_dst;
	bool visible;
};
 
struct intel_plane_config {
	bool tiled;
	int size;
	u32 base;
};
 
struct intel_crtc_config {
	/**
	 * quirks - bitfield with hw state readout quirks
	 *
	 * For various reasons the hw state readout code might not be able to
	 * completely faithfully read out the current state. These cases are
	 * tracked with quirk flags so that fastboot and state checker can act
	 * accordingly.
	 */
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
#define PIPE_CONFIG_QUIRK_INHERITED_MODE	(1<<1) /* mode inherited from firmware */
	unsigned long quirks;
 
	/* User requested mode, only valid as a starting point to
	 * compute adjusted_mode, except in the case of (S)DVO where
	 * it's also for the output timings of the (S)DVO chip.
	 * adjusted_mode will then correspond to the S(DVO) chip's
	 * preferred input timings. */
	struct drm_display_mode requested_mode;
	/* Actual pipe timings ie. what we program into the pipe timing
	 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
	struct drm_display_mode adjusted_mode;
 
	/* Pipe source size (ie. panel fitter input size)
	 * All planes will be positioned inside this space,
	 * and get clipped at the edges. */
	int pipe_src_w, pipe_src_h;
 
	/* Whether to set up the PCH/FDI. Note that we never allow sharing
	 * between pch encoders and cpu encoders. */
	bool has_pch_encoder;
 
	/* Are we sending infoframes on the attached port */
	bool has_infoframe;
 
	/* CPU Transcoder for the pipe. Currently this can only differ from the
	 * pipe on Haswell (where we have a special eDP transcoder). */
	enum transcoder cpu_transcoder;
 
	/*
	 * Use reduced/limited/broadcast rbg range, compressing from the full
	 * range fed into the crtcs.
	 */
	bool limited_color_range;
 
	/* DP has a bunch of special case unfortunately, so mark the pipe
	 * accordingly. */
	bool has_dp_encoder;
 
	/* Whether we should send NULL infoframes. Required for audio. */
	bool has_hdmi_sink;
 
	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
	 * has_dp_encoder is set. */
	bool has_audio;
 
	/*
	 * Enable dithering, used when the selected pipe bpp doesn't match the
	 * plane bpp.
	 */
	bool dither;
 
	/* Controls for the clock computation, to override various stages. */
	bool clock_set;
 
	/* SDVO TV has a bunch of special case. To make multifunction encoders
	 * work correctly, we need to track this at runtime.*/
	bool sdvo_tv_clock;
 
	/*
	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
	 * required. This is set in the 2nd loop of calling encoder's
	 * ->compute_config if the first pick doesn't work out.
	 */
	bool bw_constrained;
 
	/* Settings for the intel dpll used on pretty much everything but
	 * haswell. */
	struct dpll dpll;
 
	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
	enum intel_dpll_id shared_dpll;
 
	/*
	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
	 * - enum skl_dpll on SKL
	 */
	uint32_t ddi_pll_sel;
 
	/* Actual register state of the dpll, for shared dpll cross-checking. */
	struct intel_dpll_hw_state dpll_hw_state;
 
	int pipe_bpp;
	struct intel_link_m_n dp_m_n;
 
	/* m2_n2 for eDP downclock */
	struct intel_link_m_n dp_m2_n2;
	bool has_drrs;
 
	/*
	 * Frequence the dpll for the port should run at. Differs from the
	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
	 * already multiplied by pixel_multiplier.
	 */
	int port_clock;
 
	/* Used by SDVO (and if we ever fix it, HDMI). */
	unsigned pixel_multiplier;
 
	/* Panel fitter controls for gen2-gen4 + VLV */
	struct {
		u32 control;
		u32 pgm_ratios;
		u32 lvds_border_bits;
	} gmch_pfit;
 
	/* Panel fitter placement and size for Ironlake+ */
	struct {
		u32 pos;
		u32 size;
		bool enabled;
		bool force_thru;
	} pch_pfit;
 
	/* FDI configuration, only valid if has_pch_encoder is set. */
	int fdi_lanes;
	struct intel_link_m_n fdi_m_n;
 
	bool ips_enabled;
 
	bool double_wide;
 
	bool dp_encoder_is_mst;
	int pbn;
};
 
struct intel_pipe_wm {
	struct intel_wm_level wm[5];
	uint32_t linetime;
	bool fbc_wm_enabled;
	bool pipe_enabled;
	bool sprites_enabled;
	bool sprites_scaled;
};
 
struct intel_mmio_flip {
	u32 seqno;
	struct intel_engine_cs *ring;
	struct work_struct work;
};
 
struct skl_pipe_wm {
	struct skl_wm_level wm[8];
	struct skl_wm_level trans_wm;
	uint32_t linetime;
};
 
struct intel_crtc {
	struct drm_crtc base;
	enum pipe pipe;
	enum plane plane;
	u8 lut_r[256], lut_g[256], lut_b[256];
	/*
	 * Whether the crtc and the connected output pipeline is active. Implies
	 * that crtc->enabled is set, i.e. the current mode configuration has
	 * some outputs connected to this crtc.
	 */
	bool active;
	unsigned long enabled_power_domains;
	bool primary_enabled; /* is the primary plane (partially) visible? */
	bool lowfreq_avail;
	struct intel_overlay *overlay;
	struct intel_unpin_work *unpin_work;
 
	atomic_t unpin_work_count;
 
	/* Display surface base address adjustement for pageflips. Note that on
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
	 * handled in the hw itself (with the TILEOFF register). */
	unsigned long dspaddr_offset;
 
	struct drm_i915_gem_object *cursor_bo;
	uint32_t cursor_addr;
	int16_t cursor_width, cursor_height;
	uint32_t cursor_cntl;
	uint32_t cursor_size;
	uint32_t cursor_base;
 
	struct intel_plane_config plane_config;
	struct intel_crtc_config config;
	struct intel_crtc_config *new_config;
	bool new_enabled;
 
	/* reset counter value when the last flip was submitted */
	unsigned int reset_counter;
 
	/* Access to these should be protected by dev_priv->irq_lock. */
	bool cpu_fifo_underrun_disabled;
	bool pch_fifo_underrun_disabled;
 
	/* per-pipe watermark state */
	struct {
		/* watermarks currently being used  */
		struct intel_pipe_wm active;
		/* SKL wm values currently in use */
		struct skl_pipe_wm skl_active;
	} wm;
 
 
 
	int scanline_offset;
	struct intel_mmio_flip mmio_flip;
};
 
struct intel_plane_wm_parameters {
	uint32_t horiz_pixels;
	uint32_t vert_pixels;
	uint8_t bytes_per_pixel;
	bool enabled;
	bool scaled;
};
 
struct intel_plane {
	struct drm_plane base;
	int plane;
	enum pipe pipe;
	struct drm_i915_gem_object *obj;
	bool can_scale;
	int max_downscale;
	int crtc_x, crtc_y;
	unsigned int crtc_w, crtc_h;
	uint32_t src_x, src_y;
	uint32_t src_w, src_h;
	unsigned int rotation;
 
	/* Since we need to change the watermarks before/after
	 * enabling/disabling the planes, we need to store the parameters here
	 * as the other pieces of the struct may not reflect the values we want
	 * for the watermark calculations. Currently only Haswell uses this.
	 */
	struct intel_plane_wm_parameters wm;
 
	void (*update_plane)(struct drm_plane *plane,
			     struct drm_crtc *crtc,
			     struct drm_framebuffer *fb,
			     struct drm_i915_gem_object *obj,
			     int crtc_x, int crtc_y,
			     unsigned int crtc_w, unsigned int crtc_h,
			     uint32_t x, uint32_t y,
			     uint32_t src_w, uint32_t src_h);
	void (*disable_plane)(struct drm_plane *plane,
			      struct drm_crtc *crtc);
	int (*update_colorkey)(struct drm_plane *plane,
			       struct drm_intel_sprite_colorkey *key);
	void (*get_colorkey)(struct drm_plane *plane,
			     struct drm_intel_sprite_colorkey *key);
};
 
struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};
 
struct cxsr_latency {
	int is_desktop;
	int is_ddr3;
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};
 
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 
struct intel_hdmi {
	u32 hdmi_reg;
	int ddc_bus;
	uint32_t color_range;
	bool color_range_auto;
	bool has_hdmi_sink;
	bool has_audio;
	enum hdmi_force_audio force_audio;
	bool rgb_quant_range_selectable;
	enum hdmi_picture_aspect aspect_ratio;
	void (*write_infoframe)(struct drm_encoder *encoder,
				enum hdmi_infoframe_type type,
				const void *frame, ssize_t len);
	void (*set_infoframes)(struct drm_encoder *encoder,
			       bool enable,
			       struct drm_display_mode *adjusted_mode);
	bool (*infoframe_enabled)(struct drm_encoder *encoder);
};
 
struct intel_dp_mst_encoder;
#define DP_MAX_DOWNSTREAM_PORTS		0x10
 
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum edp_drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};
 
struct intel_dp {
	uint32_t output_reg;
	uint32_t aux_ch_ctl_reg;
	uint32_t DP;
	bool has_audio;
	enum hdmi_force_audio force_audio;
	uint32_t color_range;
	bool color_range_auto;
	uint8_t link_bw;
	uint8_t lane_count;
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
	struct drm_dp_aux aux;
	uint8_t train_set[4];
	int panel_power_up_delay;
	int panel_power_down_delay;
	int panel_power_cycle_delay;
	int backlight_on_delay;
	int backlight_off_delay;
	struct delayed_work panel_vdd_work;
	bool want_panel_vdd;
	unsigned long last_power_cycle;
	unsigned long last_power_on;
	unsigned long last_backlight_off;
 
	/*
	 * Pipe whose power sequencer is currently locked into
	 * this port. Only relevant on VLV/CHV.
	 */
	enum pipe pps_pipe;
	struct edp_power_seq pps_delays;
 
	bool use_tps3;
	bool can_mst; /* this port supports mst */
	bool is_mst;
	int active_mst_links;
	/* connector directly attached - won't be use for modeset in mst world */
	struct intel_connector *attached_connector;
 
	/* mst connector list */
	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
	struct drm_dp_mst_topology_mgr mst_mgr;
 
	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
	/*
	 * This function returns the value we have to program the AUX_CTL
	 * register with to kick off an AUX transaction.
	 */
	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
				     bool has_aux_irq,
				     int send_bytes,
				     uint32_t aux_clock_divider);
	struct {
		enum drrs_support_type type;
		enum edp_drrs_refresh_rate_type refresh_rate_type;
		struct mutex mutex;
	} drrs_state;
 
};
 
struct intel_digital_port {
	struct intel_encoder base;
	enum port port;
	u32 saved_port_bits;
	struct intel_dp dp;
	struct intel_hdmi hdmi;
	bool (*hpd_pulse)(struct intel_digital_port *, bool);
};
 
struct intel_dp_mst_encoder {
	struct intel_encoder base;
	enum pipe pipe;
	struct intel_digital_port *primary;
	void *port; /* store this opaque as its illegal to dereference it */
};
 
static inline int
vlv_dport_to_channel(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
	case PORT_D:
		return DPIO_CH0;
	case PORT_C:
		return DPIO_CH1;
	default:
		BUG();
	}
}
 
static inline int
vlv_pipe_to_channel(enum pipe pipe)
{
	switch (pipe) {
	case PIPE_A:
	case PIPE_C:
		return DPIO_CH0;
	case PIPE_B:
		return DPIO_CH1;
	default:
		BUG();
	}
}
 
static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->pipe_to_crtc_mapping[pipe];
}
 
static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->plane_to_crtc_mapping[plane];
}
 
struct intel_unpin_work {
	struct work_struct work;
	struct drm_crtc *crtc;
	struct drm_i915_gem_object *old_fb_obj;
	struct drm_i915_gem_object *pending_flip_obj;
	struct drm_pending_vblank_event *event;
	atomic_t pending;
#define INTEL_FLIP_INACTIVE	0
#define INTEL_FLIP_PENDING	1
#define INTEL_FLIP_COMPLETE	2
	u32 flip_count;
	u32 gtt_offset;
	struct intel_engine_cs *flip_queued_ring;
	u32 flip_queued_seqno;
	int flip_queued_vblank;
	int flip_ready_vblank;
	bool enable_stall_check;
};
 
struct intel_set_config {
	struct drm_encoder **save_connector_encoders;
	struct drm_crtc **save_encoder_crtcs;
	bool *save_crtc_enabled;
 
	bool fb_changed;
	bool mode_changed;
};
 
struct intel_load_detect_pipe {
	struct drm_framebuffer *release_fb;
	bool load_detect_temp;
	int dpms_mode;
};
 
static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector *connector)
{
	return to_intel_connector(connector)->encoder;
}
 
static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_digital_port, base.base);
}
 
static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
}
 
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
	return &enc_to_dig_port(encoder)->dp;
}
 
static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp *intel_dp)
{
	return container_of(intel_dp, struct intel_digital_port, dp);
}
 
static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
}
 
/*
 * Returns the number of planes for this pipe, ie the number of sprites + 1
 * (primary plane). This doesn't count the cursor plane then.
 */
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
{
	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
}
 
/* intel_fifo_underrun.c */
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum pipe pipe, bool enable);
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum transcoder pch_transcoder,
					   bool enable);
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe);
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum transcoder pch_transcoder);
void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 
/* i915_irq.c */
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_reset_rps_interrupts(struct drm_device *dev);
void gen6_enable_rps_interrupts(struct drm_device *dev);
void gen6_disable_rps_interrupts(struct drm_device *dev);
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
{
	/*
	 * We only use drm_irq_uninstall() at unload and VT switch, so
	 * this is the only thing we need to check.
	 */
	return dev_priv->pm.irqs_enabled;
}
 
int intel_get_crtc_scanline(struct intel_crtc *crtc);
 
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 
/* intel_crt.c */
void intel_crt_init(struct drm_device *dev);
 
 
/* intel_ddi.c */
void intel_prepare_ddi(struct drm_device *dev);
void hsw_fdi_link_train(struct drm_crtc *crtc);
void intel_ddi_init(struct drm_device *dev, enum port port);
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
void intel_ddi_pll_init(struct drm_device *dev);
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder);
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
bool intel_ddi_pll_select(struct intel_crtc *crtc);
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
void intel_ddi_get_config(struct intel_encoder *encoder,
			  struct intel_crtc_config *pipe_config);
 
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
void intel_ddi_clock_get(struct intel_encoder *encoder,
			 struct intel_crtc_config *pipe_config);
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 
 
 
 
 
/* intel_frontbuffer.c */
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
			struct intel_engine_cs *ring);
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
				    unsigned frontbuffer_bits);
void intel_frontbuffer_flip_complete(struct drm_device *dev,
				     unsigned frontbuffer_bits);
void intel_frontbuffer_flush(struct drm_device *dev,
			     unsigned frontbuffer_bits);
/**
 * intel_frontbuffer_flip - synchronous frontbuffer flip
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
 * This function gets called after scheduling a flip on @obj. This is for
 * synchronous plane updates which will happen on the next vblank and which will
 * not get delayed by pending gpu rendering.
 *
 * Can be called without any locks held.
 */
static inline
void intel_frontbuffer_flip(struct drm_device *dev,
			    unsigned frontbuffer_bits)
{
	intel_frontbuffer_flush(dev, frontbuffer_bits);
}
 
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 
 
/* intel_audio.c */
void intel_init_audio(struct drm_device *dev);
void intel_audio_codec_enable(struct intel_encoder *encoder);
void intel_audio_codec_disable(struct intel_encoder *encoder);
 
/* intel_display.c */
const char *intel_output_name(int output);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
int intel_pch_rawclk(struct drm_device *dev);
void intel_mark_busy(struct drm_device *dev);
void intel_mark_idle(struct drm_device *dev);
void intel_crtc_restore_mode(struct drm_crtc *crtc);
void intel_crtc_control(struct drm_crtc *crtc, bool enable);
void intel_crtc_update_dpms(struct drm_crtc *crtc);
void intel_encoder_destroy(struct drm_encoder *encoder);
void intel_connector_dpms(struct drm_connector *, int mode);
bool intel_connector_get_hw_state(struct intel_connector *connector);
void intel_modeset_check_state(struct drm_device *dev);
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				struct intel_digital_port *port);
void intel_connector_attach_encoder(struct intel_connector *connector,
					   struct intel_encoder *encoder);
struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
						    struct drm_crtc *crtc);
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
			     enum pipe pipe);
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
static inline void
intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
	drm_wait_one_vblank(dev, pipe);
}
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
			 struct intel_digital_port *dport);
bool intel_get_load_detect_pipe(struct drm_connector *connector,
				       struct drm_display_mode *mode,
				struct intel_load_detect_pipe *old,
				struct drm_modeset_acquire_ctx *ctx);
void intel_release_load_detect_pipe(struct drm_connector *connector,
				    struct intel_load_detect_pipe *old);
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
			       struct drm_framebuffer *fb,
			       struct intel_engine_cs *pipelined);
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
				  struct drm_mode_fb_cmd2 *mode_cmd,
				  struct drm_i915_gem_object *obj);
void intel_prepare_page_flip(struct drm_device *dev, int plane);
void intel_finish_page_flip(struct drm_device *dev, int pipe);
void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
void intel_check_page_flip(struct drm_device *dev, int pipe);
 
/* shared dpll functions */
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll,
			bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
void intel_put_shared_dpll(struct intel_crtc *crtc);
 
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
		      const struct dpll *dpll);
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
 
/* modesetting asserts */
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
			   enum pipe pipe);
void assert_pll(struct drm_i915_private *dev_priv,
		enum pipe pipe, bool state);
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 
 
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
						    unsigned int tiling_mode,
						      unsigned int bpp,
						      unsigned int pitch);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
		      struct intel_crtc_config *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
void
ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
				int dotclock);
bool intel_crtc_active(struct drm_crtc *crtc);
void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
 
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
				 struct intel_crtc_config *pipe_config);
int intel_format_to_fourcc(int format);
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			     struct intel_connector *intel_connector);
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_complete_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
void intel_dp_check_link_status(struct intel_dp *intel_dp);
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
bool intel_dp_compute_config(struct intel_encoder *encoder,
			     struct intel_crtc_config *pipe_config);
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
			bool long_hpd);
void intel_edp_backlight_on(struct intel_dp *intel_dp);
void intel_edp_backlight_off(struct intel_dp *intel_dp);
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 
void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp);
 
 
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
 
 
 
 
 
 
 
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
int intel_dp_max_link_bw(struct intel_dp *intel_dp);
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
 
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
/* intel_dsi.c */
void intel_dsi_init(struct drm_device *dev);
 
 
/* intel_dvo.c */
void intel_dvo_init(struct drm_device *dev);
 
 
/* legacy fbdev emulation in intel_fbdev.c */
#ifdef CONFIG_DRM_I915_FBDEV
extern int intel_fbdev_init(struct drm_device *dev);
extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
extern void intel_fbdev_fini(struct drm_device *dev);
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
extern void intel_fbdev_restore_mode(struct drm_device *dev);
#else
static inline int intel_fbdev_init(struct drm_device *dev)
{
	return 0;
}
 
static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
{
}
 
static inline void intel_fbdev_fini(struct drm_device *dev)
{
}
 
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
{
}
 
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
{
}
#endif
 
/* intel_hdmi.c */
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector);
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
			       struct intel_crtc_config *pipe_config);
 
 
/* intel_lvds.c */
void intel_lvds_init(struct drm_device *dev);
bool intel_is_dual_link_lvds(struct drm_device *dev);
 
 
/* intel_modes.c */
int intel_connector_update_modes(struct drm_connector *connector,
				 struct edid *edid);
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 
 
/* intel_overlay.c */
void intel_setup_overlay(struct drm_device *dev);
void intel_cleanup_overlay(struct drm_device *dev);
int intel_overlay_switch_off(struct intel_overlay *overlay);
int intel_overlay_put_image(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);
int intel_overlay_attrs(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);
 
 
/* intel_panel.c */
int intel_panel_init(struct intel_panel *panel,
		     struct drm_display_mode *fixed_mode,
		     struct drm_display_mode *downclock_mode);
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
			    struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc *crtc,
			     struct intel_crtc_config *pipe_config,
			     int fitting_mode);
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
			      struct intel_crtc_config *pipe_config,
			      int fitting_mode);
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
				    u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector);
void intel_panel_destroy_backlight(struct drm_connector *connector);
void intel_panel_init_backlight_funcs(struct drm_device *dev);
enum drm_connector_status intel_panel_detect(struct drm_device *dev);
extern struct drm_display_mode *intel_find_panel_downclock(
				struct drm_device *dev,
				struct drm_display_mode *fixed_mode,
				struct drm_connector *connector);
void intel_backlight_register(struct drm_device *dev);
void intel_backlight_unregister(struct drm_device *dev);
 
 
/* intel_psr.c */
bool intel_psr_is_enabled(struct drm_device *dev);
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
			      unsigned frontbuffer_bits);
void intel_psr_flush(struct drm_device *dev,
			 unsigned frontbuffer_bits);
void intel_psr_init(struct drm_device *dev);
 
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
void intel_power_domains_fini(struct drm_i915_private *);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				    enum intel_display_power_domain domain);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				      enum intel_display_power_domain domain);
void intel_display_power_get(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 
/* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_device *dev);
void intel_update_watermarks(struct drm_crtc *crtc);
void intel_update_sprite_watermarks(struct drm_plane *plane,
				    struct drm_crtc *crtc,
				    uint32_t sprite_width,
				    uint32_t sprite_height,
				    int pixel_size,
				    bool enabled, bool scaled);
void intel_init_pm(struct drm_device *dev);
void intel_pm_setup(struct drm_device *dev);
bool intel_fbc_enabled(struct drm_device *dev);
void intel_update_fbc(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
 
 
 
 
 
 
 
 
 
 
 
void intel_init_gt_powersave(struct drm_device *dev);
void intel_cleanup_gt_powersave(struct drm_device *dev);
void intel_enable_gt_powersave(struct drm_device *dev);
void intel_disable_gt_powersave(struct drm_device *dev);
void intel_suspend_gt_powersave(struct drm_device *dev);
void intel_reset_gt_powersave(struct drm_device *dev);
void ironlake_teardown_rc6(struct drm_device *dev);
void gen6_update_ring_freq(struct drm_device *dev);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
void gen6_rps_boost(struct drm_i915_private *dev_priv);
 
 
 
 
 
 
 
void ilk_wm_get_hw_state(struct drm_device *dev);
void skl_wm_get_hw_state(struct drm_device *dev);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
			  struct skl_ddb_allocation *ddb /* out */);
 
 
/* intel_sdvo.c */
bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 
 
/* intel_sprite.c */
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
			       enum plane plane);
int intel_plane_set_property(struct drm_plane *plane,
			     struct drm_property *prop,
			     uint64_t val);
int intel_plane_restore(struct drm_plane *plane);
void intel_plane_disable(struct drm_plane *plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
 
bool intel_pipe_update_start(struct intel_crtc *crtc,
			     uint32_t *start_vbl_count);
void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
 
/* intel_tv.c */
void intel_tv_init(struct drm_device *dev);
 
#endif /* __INTEL_DRV_H__ */

Rev 5060	Rev 5354
1	/*	1	/*
2	* Copyright (c) 2006 Dave Airlie	2	* Copyright (c) 2006 Dave Airlie
3	* Copyright (c) 2007-2008 Intel Corporation	3	* Copyright (c) 2007-2008 Intel Corporation
4	* Jesse Barnes	4	* Jesse Barnes
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice (including the next	13	* The above copyright notice and this permission notice (including the next
14	* paragraph) shall be included in all copies or substantial portions of the	14	* paragraph) shall be included in all copies or substantial portions of the
15	* Software.	15	* Software.
16	*	16	*
17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23	* IN THE SOFTWARE.	23	* IN THE SOFTWARE.
24	*/	24	*/
25	#ifndef __INTEL_DRV_H__	25	#ifndef __INTEL_DRV_H__
26	#define __INTEL_DRV_H__	26	#define __INTEL_DRV_H__
-		27
27		28	#include
28	#include	29	#include
29	#include	30	#include
30	#include	31	#include
31	#include "i915_drv.h"	32	#include "i915_drv.h"
32	#include	33	#include
33	#include	34	#include
34	#include	35	#include
35	#include	36	#include
-		37	#include
36		38
37	#define KBUILD_MODNAME "i915.dll"	-
38		-
39		39	#define DIV_ROUND_CLOSEST_ULL(ll, d) \
40	#define cpu_relax() asm volatile("rep; nop")	40	({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
41		41
42	/**	42	/**
43	* _wait_for - magic (register) wait macro	43	* _wait_for - magic (register) wait macro
44	*	44	*
45	* Does the right thing for modeset paths when run under kdgb or similar atomic	45	* Does the right thing for modeset paths when run under kdgb or similar atomic
46	* contexts. Note that it's important that we check the condition again after	46	* contexts. Note that it's important that we check the condition again after
47	* having timed out, since the timeout could be due to preemption or similar and	47	* having timed out, since the timeout could be due to preemption or similar and
48	* we've never had a chance to check the condition before the timeout.	48	* we've never had a chance to check the condition before the timeout.
49	*/	49	*/
50	#define _wait_for(COND, MS, W) ({ \	50	#define _wait_for(COND, MS, W) ({ \
51	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \	51	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52	int ret__ = 0; \	52	int ret__ = 0; \
53	while (!(COND)) { \	53	while (!(COND)) { \
54	if (time_after(jiffies, timeout__)) { \	54	if (time_after(jiffies, timeout__)) { \
55	if (!(COND)) \	55	if (!(COND)) \
56	ret__ = -ETIMEDOUT; \	56	ret__ = -ETIMEDOUT; \
57	break; \	57	break; \
58	} \	58	} \
59	if (W ) { \	59	if (W ) { \
60	msleep(W); \	60	msleep(W); \
61	} else { \	61	} else { \
62	cpu_relax(); \	62	cpu_relax(); \
63	} \	63	} \
64	} \	64	} \
65	ret__; \	65	ret__; \
66	})	66	})
67		67
68	#define wait_for(COND, MS) _wait_for(COND, MS, 1)	68	#define wait_for(COND, MS) _wait_for(COND, MS, 1)
69	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)	69	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
70	#define wait_for_atomic_us(COND, US) _wait_for((COND), \	70	#define wait_for_atomic_us(COND, US) _wait_for((COND), \
71	DIV_ROUND_UP((US), 1000), 0)	71	DIV_ROUND_UP((US), 1000), 0)
72		72
73	#define KHz(x) (1000 * (x))	73	#define KHz(x) (1000 * (x))
74	#define MHz(x) KHz(1000 * (x))	74	#define MHz(x) KHz(1000 * (x))
75		75
76	/*	76	/*
77	* Display related stuff	77	* Display related stuff
78	*/	78	*/
79		79
80	/* store information about an Ixxx DVO */	80	/* store information about an Ixxx DVO */
81	/* The i830->i865 use multiple DVOs with multiple i2cs */	81	/* The i830->i865 use multiple DVOs with multiple i2cs */
82	/* the i915, i945 have a single sDVO i2c bus - which is different */	82	/* the i915, i945 have a single sDVO i2c bus - which is different */
83	#define MAX_OUTPUTS 6	83	#define MAX_OUTPUTS 6
84	/* maximum connectors per crtcs in the mode set */	84	/* maximum connectors per crtcs in the mode set */
85		85
86	/* Maximum cursor sizes */	86	/* Maximum cursor sizes */
87	#define GEN2_CURSOR_WIDTH 64	87	#define GEN2_CURSOR_WIDTH 64
88	#define GEN2_CURSOR_HEIGHT 64	88	#define GEN2_CURSOR_HEIGHT 64
89	#define MAX_CURSOR_WIDTH 256	89	#define MAX_CURSOR_WIDTH 256
90	#define MAX_CURSOR_HEIGHT 256	90	#define MAX_CURSOR_HEIGHT 256
91		91
92	#define INTEL_I2C_BUS_DVO 1	92	#define INTEL_I2C_BUS_DVO 1
93	#define INTEL_I2C_BUS_SDVO 2	93	#define INTEL_I2C_BUS_SDVO 2
94		94
95	/* these are outputs from the chip - integrated only	95	/* these are outputs from the chip - integrated only
96	external chips are via DVO or SDVO output */	96	external chips are via DVO or SDVO output */
-		97	enum intel_output_type {
97	#define INTEL_OUTPUT_UNUSED 0	98	INTEL_OUTPUT_UNUSED = 0,
98	#define INTEL_OUTPUT_ANALOG 1	99	INTEL_OUTPUT_ANALOG = 1,
99	#define INTEL_OUTPUT_DVO 2	100	INTEL_OUTPUT_DVO = 2,
100	#define INTEL_OUTPUT_SDVO 3	101	INTEL_OUTPUT_SDVO = 3,
101	#define INTEL_OUTPUT_LVDS 4	102	INTEL_OUTPUT_LVDS = 4,
102	#define INTEL_OUTPUT_TVOUT 5	103	INTEL_OUTPUT_TVOUT = 5,
103	#define INTEL_OUTPUT_HDMI 6	104	INTEL_OUTPUT_HDMI = 6,
104	#define INTEL_OUTPUT_DISPLAYPORT 7	105	INTEL_OUTPUT_DISPLAYPORT = 7,
105	#define INTEL_OUTPUT_EDP 8	106	INTEL_OUTPUT_EDP = 8,
106	#define INTEL_OUTPUT_DSI 9	107	INTEL_OUTPUT_DSI = 9,
107	#define INTEL_OUTPUT_UNKNOWN 10	108	INTEL_OUTPUT_UNKNOWN = 10,
108	#define INTEL_OUTPUT_DP_MST 11	109	INTEL_OUTPUT_DP_MST = 11,
-		110	};
109		111
110	#define INTEL_DVO_CHIP_NONE 0	112	#define INTEL_DVO_CHIP_NONE 0
111	#define INTEL_DVO_CHIP_LVDS 1	113	#define INTEL_DVO_CHIP_LVDS 1
112	#define INTEL_DVO_CHIP_TMDS 2	114	#define INTEL_DVO_CHIP_TMDS 2
113	#define INTEL_DVO_CHIP_TVOUT 4	115	#define INTEL_DVO_CHIP_TVOUT 4
114		116
115	#define INTEL_DSI_VIDEO_MODE 0	117	#define INTEL_DSI_VIDEO_MODE 0
116	#define INTEL_DSI_COMMAND_MODE 1	118	#define INTEL_DSI_COMMAND_MODE 1
117		119
118	struct intel_framebuffer {	120	struct intel_framebuffer {
119	struct drm_framebuffer base;	121	struct drm_framebuffer base;
120	struct drm_i915_gem_object *obj;	122	struct drm_i915_gem_object *obj;
121	};	123	};
122		124
123	struct intel_fbdev {	125	struct intel_fbdev {
124	struct drm_fb_helper helper;	126	struct drm_fb_helper helper;
125	struct intel_framebuffer *fb;	127	struct intel_framebuffer *fb;
126	struct list_head fbdev_list;	128	struct list_head fbdev_list;
127	struct drm_display_mode *our_mode;	129	struct drm_display_mode *our_mode;
128	int preferred_bpp;	130	int preferred_bpp;
129	};	131	};
130		132
131	struct intel_encoder {	133	struct intel_encoder {
132	struct drm_encoder base;	134	struct drm_encoder base;
133	/*	135	/*
134	* The new crtc this encoder will be driven from. Only differs from	136	* The new crtc this encoder will be driven from. Only differs from
135	* base->crtc while a modeset is in progress.	137	* base->crtc while a modeset is in progress.
136	*/	138	*/
137	struct intel_crtc *new_crtc;	139	struct intel_crtc *new_crtc;
138		140
139	int type;	141	enum intel_output_type type;
140	unsigned int cloneable;	142	unsigned int cloneable;
141	bool connectors_active;	143	bool connectors_active;
142	void (hot_plug)(struct intel_encoder );	144	void (hot_plug)(struct intel_encoder );
143	bool (compute_config)(struct intel_encoder ,	145	bool (compute_config)(struct intel_encoder ,
144	struct intel_crtc_config *);	146	struct intel_crtc_config *);
145	void (pre_pll_enable)(struct intel_encoder );	147	void (pre_pll_enable)(struct intel_encoder );
146	void (pre_enable)(struct intel_encoder );	148	void (pre_enable)(struct intel_encoder );
147	void (enable)(struct intel_encoder );	149	void (enable)(struct intel_encoder );
148	void (mode_set)(struct intel_encoder intel_encoder);	150	void (mode_set)(struct intel_encoder intel_encoder);
149	void (disable)(struct intel_encoder );	151	void (disable)(struct intel_encoder );
150	void (post_disable)(struct intel_encoder );	152	void (post_disable)(struct intel_encoder );
151	/* Read out the current hw state of this connector, returning true if	153	/* Read out the current hw state of this connector, returning true if
152	* the encoder is active. If the encoder is enabled it also set the pipe	154	* the encoder is active. If the encoder is enabled it also set the pipe
153	* it is connected to in the pipe parameter. */	155	* it is connected to in the pipe parameter. */
154	bool (get_hw_state)(struct intel_encoder , enum pipe *pipe);	156	bool (get_hw_state)(struct intel_encoder , enum pipe *pipe);
155	/* Reconstructs the equivalent mode flags for the current hardware	157	/* Reconstructs the equivalent mode flags for the current hardware
156	* state. This must be called _after_ display->get_pipe_config has	158	* state. This must be called _after_ display->get_pipe_config has
157	* pre-filled the pipe config. Note that intel_encoder->base.crtc must	159	* pre-filled the pipe config. Note that intel_encoder->base.crtc must
158	* be set correctly before calling this function. */	160	* be set correctly before calling this function. */
159	void (get_config)(struct intel_encoder ,	161	void (get_config)(struct intel_encoder ,
160	struct intel_crtc_config *pipe_config);	162	struct intel_crtc_config *pipe_config);
161	/*	163	/*
162	* Called during system suspend after all pending requests for the	164	* Called during system suspend after all pending requests for the
163	* encoder are flushed (for example for DP AUX transactions) and	165	* encoder are flushed (for example for DP AUX transactions) and
164	* device interrupts are disabled.	166	* device interrupts are disabled.
165	*/	167	*/
166	void (suspend)(struct intel_encoder );	168	void (suspend)(struct intel_encoder );
167	int crtc_mask;	169	int crtc_mask;
168	enum hpd_pin hpd_pin;	170	enum hpd_pin hpd_pin;
169	};	171	};
170		172
171	struct intel_panel {	173	struct intel_panel {
172	struct drm_display_mode *fixed_mode;	174	struct drm_display_mode *fixed_mode;
173	struct drm_display_mode *downclock_mode;	175	struct drm_display_mode *downclock_mode;
174	int fitting_mode;	176	int fitting_mode;
175		177
176	/* backlight */	178	/* backlight */
177	struct {	179	struct {
178	bool present;	180	bool present;
179	u32 level;	181	u32 level;
180	u32 min;	182	u32 min;
181	u32 max;	183	u32 max;
182	bool enabled;	184	bool enabled;
183	bool combination_mode; /* gen 2/4 only */	185	bool combination_mode; /* gen 2/4 only */
184	bool active_low_pwm;	186	bool active_low_pwm;
185	struct backlight_device *device;	187	struct backlight_device *device;
186	} backlight;	188	} backlight;
-		189
-		190	void (backlight_power)(struct intel_connector , bool enable);
187	};	191	};
188		192
189	struct intel_connector {	193	struct intel_connector {
190	struct drm_connector base;	194	struct drm_connector base;
191	/*	195	/*
192	* The fixed encoder this connector is connected to.	196	* The fixed encoder this connector is connected to.
193	*/	197	*/
194	struct intel_encoder *encoder;	198	struct intel_encoder *encoder;
195		199
196	/*	200	/*
197	* The new encoder this connector will be driven. Only differs from	201	* The new encoder this connector will be driven. Only differs from
198	* encoder while a modeset is in progress.	202	* encoder while a modeset is in progress.
199	*/	203	*/
200	struct intel_encoder *new_encoder;	204	struct intel_encoder *new_encoder;
201		205
202	/* Reads out the current hw, returning true if the connector is enabled	206	/* Reads out the current hw, returning true if the connector is enabled
203	* and active (i.e. dpms ON state). */	207	* and active (i.e. dpms ON state). */
204	bool (get_hw_state)(struct intel_connector );	208	bool (get_hw_state)(struct intel_connector );
205		209
206	/*	210	/*
207	* Removes all interfaces through which the connector is accessible	211	* Removes all interfaces through which the connector is accessible
208	* - like sysfs, debugfs entries -, so that no new operations can be	212	* - like sysfs, debugfs entries -, so that no new operations can be
209	* started on the connector. Also makes sure all currently pending	213	* started on the connector. Also makes sure all currently pending
210	* operations finish before returing.	214	* operations finish before returing.
211	*/	215	*/
212	void (unregister)(struct intel_connector );	216	void (unregister)(struct intel_connector );
213		217
214	/* Panel info for eDP and LVDS */	218	/* Panel info for eDP and LVDS */
215	struct intel_panel panel;	219	struct intel_panel panel;
216		220
217	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */	221	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
218	struct edid *edid;	222	struct edid *edid;
-		223	struct edid *detect_edid;
219		224
220	/* since POLL and HPD connectors may use the same HPD line keep the native	225	/* since POLL and HPD connectors may use the same HPD line keep the native
221	state of connector->polled in case hotplug storm detection changes it */	226	state of connector->polled in case hotplug storm detection changes it */
222	u8 polled;	227	u8 polled;
223		228
224	void port; / store this opaque as its illegal to dereference it */	229	void port; / store this opaque as its illegal to dereference it */
225		230
226	struct intel_dp *mst_port;	231	struct intel_dp *mst_port;
227	};	232	};
228		233
229	typedef struct dpll {	234	typedef struct dpll {
230	/* given values */	235	/* given values */
231	int n;	236	int n;
232	int m1, m2;	237	int m1, m2;
233	int p1, p2;	238	int p1, p2;
234	/* derived values */	239	/* derived values */
235	int dot;	240	int dot;
236	int vco;	241	int vco;
237	int m;	242	int m;
238	int p;	243	int p;
239	} intel_clock_t;	244	} intel_clock_t;
-		245
-		246	struct intel_plane_state {
-		247	struct drm_crtc *crtc;
-		248	struct drm_framebuffer *fb;
-		249	struct drm_rect src;
-		250	struct drm_rect dst;
-		251	struct drm_rect clip;
-		252	struct drm_rect orig_src;
-		253	struct drm_rect orig_dst;
-		254	bool visible;
-		255	};
240		256
241	struct intel_plane_config {	257	struct intel_plane_config {
242	bool tiled;	258	bool tiled;
243	int size;	259	int size;
244	u32 base;	260	u32 base;
245	};	261	};
246		262
247	struct intel_crtc_config {	263	struct intel_crtc_config {
248	/**	264	/**
249	* quirks - bitfield with hw state readout quirks	265	* quirks - bitfield with hw state readout quirks
250	*	266	*
251	* For various reasons the hw state readout code might not be able to	267	* For various reasons the hw state readout code might not be able to
252	* completely faithfully read out the current state. These cases are	268	* completely faithfully read out the current state. These cases are
253	* tracked with quirk flags so that fastboot and state checker can act	269	* tracked with quirk flags so that fastboot and state checker can act
254	* accordingly.	270	* accordingly.
255	*/	271	*/
256	#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */	272	#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
257	#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */	273	#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
258	unsigned long quirks;	274	unsigned long quirks;
259		275
260	/* User requested mode, only valid as a starting point to	276	/* User requested mode, only valid as a starting point to
261	* compute adjusted_mode, except in the case of (S)DVO where	277	* compute adjusted_mode, except in the case of (S)DVO where
262	* it's also for the output timings of the (S)DVO chip.	278	* it's also for the output timings of the (S)DVO chip.
263	* adjusted_mode will then correspond to the S(DVO) chip's	279	* adjusted_mode will then correspond to the S(DVO) chip's
264	* preferred input timings. */	280	* preferred input timings. */
265	struct drm_display_mode requested_mode;	281	struct drm_display_mode requested_mode;
266	/* Actual pipe timings ie. what we program into the pipe timing	282	/* Actual pipe timings ie. what we program into the pipe timing
267	* registers. adjusted_mode.crtc_clock is the pipe pixel clock. */	283	* registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
268	struct drm_display_mode adjusted_mode;	284	struct drm_display_mode adjusted_mode;
269		285
270	/* Pipe source size (ie. panel fitter input size)	286	/* Pipe source size (ie. panel fitter input size)
271	* All planes will be positioned inside this space,	287	* All planes will be positioned inside this space,
272	* and get clipped at the edges. */	288	* and get clipped at the edges. */
273	int pipe_src_w, pipe_src_h;	289	int pipe_src_w, pipe_src_h;
274		290
275	/* Whether to set up the PCH/FDI. Note that we never allow sharing	291	/* Whether to set up the PCH/FDI. Note that we never allow sharing
276	* between pch encoders and cpu encoders. */	292	* between pch encoders and cpu encoders. */
277	bool has_pch_encoder;	293	bool has_pch_encoder;
-		294
-		295	/* Are we sending infoframes on the attached port */
-		296	bool has_infoframe;
278		297
279	/* CPU Transcoder for the pipe. Currently this can only differ from the	298	/* CPU Transcoder for the pipe. Currently this can only differ from the
280	* pipe on Haswell (where we have a special eDP transcoder). */	299	* pipe on Haswell (where we have a special eDP transcoder). */
281	enum transcoder cpu_transcoder;	300	enum transcoder cpu_transcoder;
282		301
283	/*	302	/*
284	* Use reduced/limited/broadcast rbg range, compressing from the full	303	* Use reduced/limited/broadcast rbg range, compressing from the full
285	* range fed into the crtcs.	304	* range fed into the crtcs.
286	*/	305	*/
287	bool limited_color_range;	306	bool limited_color_range;
288		307
289	/* DP has a bunch of special case unfortunately, so mark the pipe	308	/* DP has a bunch of special case unfortunately, so mark the pipe
290	* accordingly. */	309	* accordingly. */
291	bool has_dp_encoder;	310	bool has_dp_encoder;
292		311
293	/* Whether we should send NULL infoframes. Required for audio. */	312	/* Whether we should send NULL infoframes. Required for audio. */
294	bool has_hdmi_sink;	313	bool has_hdmi_sink;
295		314
296	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or	315	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
297	* has_dp_encoder is set. */	316	* has_dp_encoder is set. */
298	bool has_audio;	317	bool has_audio;
299		318
300	/*	319	/*
301	* Enable dithering, used when the selected pipe bpp doesn't match the	320	* Enable dithering, used when the selected pipe bpp doesn't match the
302	* plane bpp.	321	* plane bpp.
303	*/	322	*/
304	bool dither;	323	bool dither;
305		324
306	/* Controls for the clock computation, to override various stages. */	325	/* Controls for the clock computation, to override various stages. */
307	bool clock_set;	326	bool clock_set;
308		327
309	/* SDVO TV has a bunch of special case. To make multifunction encoders	328	/* SDVO TV has a bunch of special case. To make multifunction encoders
310	* work correctly, we need to track this at runtime.*/	329	* work correctly, we need to track this at runtime.*/
311	bool sdvo_tv_clock;	330	bool sdvo_tv_clock;
312		331
313	/*	332	/*
314	* crtc bandwidth limit, don't increase pipe bpp or clock if not really	333	* crtc bandwidth limit, don't increase pipe bpp or clock if not really
315	* required. This is set in the 2nd loop of calling encoder's	334	* required. This is set in the 2nd loop of calling encoder's
316	* ->compute_config if the first pick doesn't work out.	335	* ->compute_config if the first pick doesn't work out.
317	*/	336	*/
318	bool bw_constrained;	337	bool bw_constrained;
319		338
320	/* Settings for the intel dpll used on pretty much everything but	339	/* Settings for the intel dpll used on pretty much everything but
321	* haswell. */	340	* haswell. */
322	struct dpll dpll;	341	struct dpll dpll;
323		342
324	/* Selected dpll when shared or DPLL_ID_PRIVATE. */	343	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
325	enum intel_dpll_id shared_dpll;	344	enum intel_dpll_id shared_dpll;
-		345
326		346	/*
-		347	* - PORT_CLK_SEL for DDI ports on HSW/BDW.
-		348	* - enum skl_dpll on SKL
327	/* PORT_CLK_SEL for DDI ports. */	349	*/
328	uint32_t ddi_pll_sel;	350	uint32_t ddi_pll_sel;
329		351
330	/* Actual register state of the dpll, for shared dpll cross-checking. */	352	/* Actual register state of the dpll, for shared dpll cross-checking. */
331	struct intel_dpll_hw_state dpll_hw_state;	353	struct intel_dpll_hw_state dpll_hw_state;
332		354
333	int pipe_bpp;	355	int pipe_bpp;
334	struct intel_link_m_n dp_m_n;	356	struct intel_link_m_n dp_m_n;
335		357
336	/* m2_n2 for eDP downclock */	358	/* m2_n2 for eDP downclock */
337	struct intel_link_m_n dp_m2_n2;	359	struct intel_link_m_n dp_m2_n2;
-		360	bool has_drrs;
338		361
339	/*	362	/*
340	* Frequence the dpll for the port should run at. Differs from the	363	* Frequence the dpll for the port should run at. Differs from the
341	* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also	364	* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
342	* already multiplied by pixel_multiplier.	365	* already multiplied by pixel_multiplier.
343	*/	366	*/
344	int port_clock;	367	int port_clock;
345		368
346	/* Used by SDVO (and if we ever fix it, HDMI). */	369	/* Used by SDVO (and if we ever fix it, HDMI). */
347	unsigned pixel_multiplier;	370	unsigned pixel_multiplier;
348		371
349	/* Panel fitter controls for gen2-gen4 + VLV */	372	/* Panel fitter controls for gen2-gen4 + VLV */
350	struct {	373	struct {
351	u32 control;	374	u32 control;
352	u32 pgm_ratios;	375	u32 pgm_ratios;
353	u32 lvds_border_bits;	376	u32 lvds_border_bits;
354	} gmch_pfit;	377	} gmch_pfit;
355		378
356	/* Panel fitter placement and size for Ironlake+ */	379	/* Panel fitter placement and size for Ironlake+ */
357	struct {	380	struct {
358	u32 pos;	381	u32 pos;
359	u32 size;	382	u32 size;
360	bool enabled;	383	bool enabled;
361	bool force_thru;	384	bool force_thru;
362	} pch_pfit;	385	} pch_pfit;
363		386
364	/* FDI configuration, only valid if has_pch_encoder is set. */	387	/* FDI configuration, only valid if has_pch_encoder is set. */
365	int fdi_lanes;	388	int fdi_lanes;
366	struct intel_link_m_n fdi_m_n;	389	struct intel_link_m_n fdi_m_n;
367		390
368	bool ips_enabled;	391	bool ips_enabled;
369		392
370	bool double_wide;	393	bool double_wide;
371		394
372	bool dp_encoder_is_mst;	395	bool dp_encoder_is_mst;
373	int pbn;	396	int pbn;
374	};	397	};
375		398
376	struct intel_pipe_wm {	399	struct intel_pipe_wm {
377	struct intel_wm_level wm[5];	400	struct intel_wm_level wm[5];
378	uint32_t linetime;	401	uint32_t linetime;
379	bool fbc_wm_enabled;	402	bool fbc_wm_enabled;
380	bool pipe_enabled;	403	bool pipe_enabled;
381	bool sprites_enabled;	404	bool sprites_enabled;
382	bool sprites_scaled;	405	bool sprites_scaled;
383	};	406	};
384		407
385	struct intel_mmio_flip {	408	struct intel_mmio_flip {
386	u32 seqno;	409	u32 seqno;
-		410	struct intel_engine_cs *ring;
-		411	struct work_struct work;
-		412	};
-		413
-		414	struct skl_pipe_wm {
-		415	struct skl_wm_level wm[8];
-		416	struct skl_wm_level trans_wm;
387	u32 ring_id;	417	uint32_t linetime;
388	};	418	};
389		419
390	struct intel_crtc {	420	struct intel_crtc {
391	struct drm_crtc base;	421	struct drm_crtc base;
392	enum pipe pipe;	422	enum pipe pipe;
393	enum plane plane;	423	enum plane plane;
394	u8 lut_r[256], lut_g[256], lut_b[256];	424	u8 lut_r[256], lut_g[256], lut_b[256];
395	/*	425	/*
396	* Whether the crtc and the connected output pipeline is active. Implies	426	* Whether the crtc and the connected output pipeline is active. Implies
397	* that crtc->enabled is set, i.e. the current mode configuration has	427	* that crtc->enabled is set, i.e. the current mode configuration has
398	* some outputs connected to this crtc.	428	* some outputs connected to this crtc.
399	*/	429	*/
400	bool active;	430	bool active;
401	unsigned long enabled_power_domains;	431	unsigned long enabled_power_domains;
402	bool primary_enabled; /* is the primary plane (partially) visible? */	432	bool primary_enabled; /* is the primary plane (partially) visible? */
403	bool lowfreq_avail;	433	bool lowfreq_avail;
404	struct intel_overlay *overlay;	434	struct intel_overlay *overlay;
405	struct intel_unpin_work *unpin_work;	435	struct intel_unpin_work *unpin_work;
406		436
407	atomic_t unpin_work_count;	437	atomic_t unpin_work_count;
408		438
409	/* Display surface base address adjustement for pageflips. Note that on	439	/* Display surface base address adjustement for pageflips. Note that on
410	* gen4+ this only adjusts up to a tile, offsets within a tile are	440	* gen4+ this only adjusts up to a tile, offsets within a tile are
411	* handled in the hw itself (with the TILEOFF register). */	441	* handled in the hw itself (with the TILEOFF register). */
412	unsigned long dspaddr_offset;	442	unsigned long dspaddr_offset;
413		443
414	struct drm_i915_gem_object *cursor_bo;	444	struct drm_i915_gem_object *cursor_bo;
415	uint32_t cursor_addr;	445	uint32_t cursor_addr;
416	int16_t cursor_width, cursor_height;	446	int16_t cursor_width, cursor_height;
417	uint32_t cursor_cntl;	447	uint32_t cursor_cntl;
-		448	uint32_t cursor_size;
418	uint32_t cursor_base;	449	uint32_t cursor_base;
419		450
420	struct intel_plane_config plane_config;	451	struct intel_plane_config plane_config;
421	struct intel_crtc_config config;	452	struct intel_crtc_config config;
422	struct intel_crtc_config *new_config;	453	struct intel_crtc_config *new_config;
423	bool new_enabled;	454	bool new_enabled;
424		455
425	/* reset counter value when the last flip was submitted */	456	/* reset counter value when the last flip was submitted */
426	unsigned int reset_counter;	457	unsigned int reset_counter;
427		458
428	/* Access to these should be protected by dev_priv->irq_lock. */	459	/* Access to these should be protected by dev_priv->irq_lock. */
429	bool cpu_fifo_underrun_disabled;	460	bool cpu_fifo_underrun_disabled;
430	bool pch_fifo_underrun_disabled;	461	bool pch_fifo_underrun_disabled;
431		462
432	/* per-pipe watermark state */	463	/* per-pipe watermark state */
433	struct {	464	struct {
434	/* watermarks currently being used */	465	/* watermarks currently being used */
435	struct intel_pipe_wm active;	466	struct intel_pipe_wm active;
-		467	/* SKL wm values currently in use */
-		468	struct skl_pipe_wm skl_active;
436	} wm;	469	} wm;
437		-
438	wait_queue_head_t vbl_wait;	-
439		470
-		471	int scanline_offset;
440	int scanline_offset;	472	struct intel_mmio_flip mmio_flip;
441	};	473	};
442		474
443	struct intel_plane_wm_parameters {	475	struct intel_plane_wm_parameters {
444	uint32_t horiz_pixels;	476	uint32_t horiz_pixels;
445	uint32_t vert_pixels;	477	uint32_t vert_pixels;
446	uint8_t bytes_per_pixel;	478	uint8_t bytes_per_pixel;
447	bool enabled;	479	bool enabled;
448	bool scaled;	480	bool scaled;
449	};	481	};
450		482
451	struct intel_plane {	483	struct intel_plane {
452	struct drm_plane base;	484	struct drm_plane base;
453	int plane;	485	int plane;
454	enum pipe pipe;	486	enum pipe pipe;
455	struct drm_i915_gem_object *obj;	487	struct drm_i915_gem_object *obj;
456	bool can_scale;	488	bool can_scale;
457	int max_downscale;	489	int max_downscale;
458	int crtc_x, crtc_y;	490	int crtc_x, crtc_y;
459	unsigned int crtc_w, crtc_h;	491	unsigned int crtc_w, crtc_h;
460	uint32_t src_x, src_y;	492	uint32_t src_x, src_y;
461	uint32_t src_w, src_h;	493	uint32_t src_w, src_h;
-		494	unsigned int rotation;
462		495
463	/* Since we need to change the watermarks before/after	496	/* Since we need to change the watermarks before/after

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/i915/intel_drv.h @ 6937 – Rev 5060 → 5354