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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Keith Packard |
24 | * Keith Packard |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include |
31 | #include |
32 | #include |
32 | #include |
33 | #include |
33 | #include |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | #include "intel_drv.h" |
36 | #include "intel_drv.h" |
37 | #include |
37 | #include |
38 | #include "i915_drv.h" |
38 | #include "i915_drv.h" |
39 | 39 | ||
40 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
41 | 41 | ||
42 | /* Compliance test status bits */ |
42 | /* Compliance test status bits */ |
43 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
43 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
44 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
44 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
45 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
45 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
46 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
47 | 47 | ||
48 | struct dp_link_dpll { |
48 | struct dp_link_dpll { |
49 | int clock; |
49 | int clock; |
50 | struct dpll dpll; |
50 | struct dpll dpll; |
51 | }; |
51 | }; |
52 | 52 | ||
53 | static const struct dp_link_dpll gen4_dpll[] = { |
53 | static const struct dp_link_dpll gen4_dpll[] = { |
54 | { 162000, |
54 | { 162000, |
55 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
55 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
56 | { 270000, |
56 | { 270000, |
57 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
57 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
58 | }; |
58 | }; |
59 | 59 | ||
60 | static const struct dp_link_dpll pch_dpll[] = { |
60 | static const struct dp_link_dpll pch_dpll[] = { |
61 | { 162000, |
61 | { 162000, |
62 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
62 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
63 | { 270000, |
63 | { 270000, |
64 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
64 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
65 | }; |
65 | }; |
66 | 66 | ||
67 | static const struct dp_link_dpll vlv_dpll[] = { |
67 | static const struct dp_link_dpll vlv_dpll[] = { |
68 | { 162000, |
68 | { 162000, |
69 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
69 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
70 | { 270000, |
70 | { 270000, |
71 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
71 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
72 | }; |
72 | }; |
73 | 73 | ||
74 | /* |
74 | /* |
75 | * CHV supports eDP 1.4 that have more link rates. |
75 | * CHV supports eDP 1.4 that have more link rates. |
76 | * Below only provides the fixed rate but exclude variable rate. |
76 | * Below only provides the fixed rate but exclude variable rate. |
77 | */ |
77 | */ |
78 | static const struct dp_link_dpll chv_dpll[] = { |
78 | static const struct dp_link_dpll chv_dpll[] = { |
79 | /* |
79 | /* |
80 | * CHV requires to program fractional division for m2. |
80 | * CHV requires to program fractional division for m2. |
81 | * m2 is stored in fixed point format using formula below |
81 | * m2 is stored in fixed point format using formula below |
82 | * (m2_int << 22) | m2_fraction |
82 | * (m2_int << 22) | m2_fraction |
83 | */ |
83 | */ |
84 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
84 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
85 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
85 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
86 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
86 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
87 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
87 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
88 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
88 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
89 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
89 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
90 | }; |
90 | }; |
91 | 91 | ||
92 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
92 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
93 | 324000, 432000, 540000 }; |
93 | 324000, 432000, 540000 }; |
94 | static const int skl_rates[] = { 162000, 216000, 270000, |
94 | static const int skl_rates[] = { 162000, 216000, 270000, |
95 | 324000, 432000, 540000 }; |
95 | 324000, 432000, 540000 }; |
96 | static const int default_rates[] = { 162000, 270000, 540000 }; |
96 | static const int default_rates[] = { 162000, 270000, 540000 }; |
97 | 97 | ||
98 | /** |
98 | /** |
99 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
99 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
100 | * @intel_dp: DP struct |
100 | * @intel_dp: DP struct |
101 | * |
101 | * |
102 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
102 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
103 | * will return true, and false otherwise. |
103 | * will return true, and false otherwise. |
104 | */ |
104 | */ |
105 | static bool is_edp(struct intel_dp *intel_dp) |
105 | static bool is_edp(struct intel_dp *intel_dp) |
106 | { |
106 | { |
107 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
107 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
108 | 108 | ||
109 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
109 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
110 | } |
110 | } |
111 | 111 | ||
112 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
112 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
113 | { |
113 | { |
114 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
114 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
115 | 115 | ||
116 | return intel_dig_port->base.base.dev; |
116 | return intel_dig_port->base.base.dev; |
117 | } |
117 | } |
118 | 118 | ||
119 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
119 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
120 | { |
120 | { |
121 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
121 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
122 | } |
122 | } |
123 | 123 | ||
124 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
124 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
125 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
125 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
126 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
126 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
127 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
127 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
128 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
128 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
129 | enum pipe pipe); |
129 | enum pipe pipe); |
130 | 130 | ||
131 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
131 | static unsigned int intel_dp_unused_lane_mask(int lane_count) |
132 | { |
132 | { |
133 | return ~((1 << lane_count) - 1) & 0xf; |
133 | return ~((1 << lane_count) - 1) & 0xf; |
134 | } |
134 | } |
135 | 135 | ||
136 | static int |
136 | static int |
137 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
137 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
138 | { |
138 | { |
139 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
139 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
140 | 140 | ||
141 | switch (max_link_bw) { |
141 | switch (max_link_bw) { |
142 | case DP_LINK_BW_1_62: |
142 | case DP_LINK_BW_1_62: |
143 | case DP_LINK_BW_2_7: |
143 | case DP_LINK_BW_2_7: |
144 | case DP_LINK_BW_5_4: |
144 | case DP_LINK_BW_5_4: |
145 | break; |
145 | break; |
146 | default: |
146 | default: |
147 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
147 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | max_link_bw); |
148 | max_link_bw); |
149 | max_link_bw = DP_LINK_BW_1_62; |
149 | max_link_bw = DP_LINK_BW_1_62; |
150 | break; |
150 | break; |
151 | } |
151 | } |
152 | return max_link_bw; |
152 | return max_link_bw; |
153 | } |
153 | } |
154 | 154 | ||
155 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
155 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | { |
156 | { |
157 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
157 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
158 | struct drm_device *dev = intel_dig_port->base.base.dev; |
158 | struct drm_device *dev = intel_dig_port->base.base.dev; |
159 | u8 source_max, sink_max; |
159 | u8 source_max, sink_max; |
160 | 160 | ||
161 | source_max = 4; |
161 | source_max = 4; |
162 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
162 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
163 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
163 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
164 | source_max = 2; |
164 | source_max = 2; |
165 | 165 | ||
166 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
166 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
167 | 167 | ||
168 | return min(source_max, sink_max); |
168 | return min(source_max, sink_max); |
169 | } |
169 | } |
170 | 170 | ||
171 | /* |
171 | /* |
172 | * The units on the numbers in the next two are... bizarre. Examples will |
172 | * The units on the numbers in the next two are... bizarre. Examples will |
173 | * make it clearer; this one parallels an example in the eDP spec. |
173 | * make it clearer; this one parallels an example in the eDP spec. |
174 | * |
174 | * |
175 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
175 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
176 | * |
176 | * |
177 | * 270000 * 1 * 8 / 10 == 216000 |
177 | * 270000 * 1 * 8 / 10 == 216000 |
178 | * |
178 | * |
179 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
179 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
180 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
180 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
181 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
181 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
182 | * 119000. At 18bpp that's 2142000 kilobits per second. |
182 | * 119000. At 18bpp that's 2142000 kilobits per second. |
183 | * |
183 | * |
184 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
184 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
185 | * get the result in decakilobits instead of kilobits. |
185 | * get the result in decakilobits instead of kilobits. |
186 | */ |
186 | */ |
187 | 187 | ||
188 | static int |
188 | static int |
189 | intel_dp_link_required(int pixel_clock, int bpp) |
189 | intel_dp_link_required(int pixel_clock, int bpp) |
190 | { |
190 | { |
191 | return (pixel_clock * bpp + 9) / 10; |
191 | return (pixel_clock * bpp + 9) / 10; |
192 | } |
192 | } |
193 | 193 | ||
194 | static int |
194 | static int |
195 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
195 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
196 | { |
196 | { |
197 | return (max_link_clock * max_lanes * 8) / 10; |
197 | return (max_link_clock * max_lanes * 8) / 10; |
198 | } |
198 | } |
199 | 199 | ||
200 | static enum drm_mode_status |
200 | static enum drm_mode_status |
201 | intel_dp_mode_valid(struct drm_connector *connector, |
201 | intel_dp_mode_valid(struct drm_connector *connector, |
202 | struct drm_display_mode *mode) |
202 | struct drm_display_mode *mode) |
203 | { |
203 | { |
204 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
204 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
205 | struct intel_connector *intel_connector = to_intel_connector(connector); |
205 | struct intel_connector *intel_connector = to_intel_connector(connector); |
206 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
206 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
207 | int target_clock = mode->clock; |
207 | int target_clock = mode->clock; |
208 | int max_rate, mode_rate, max_lanes, max_link_clock; |
208 | int max_rate, mode_rate, max_lanes, max_link_clock; |
209 | 209 | ||
210 | if (is_edp(intel_dp) && fixed_mode) { |
210 | if (is_edp(intel_dp) && fixed_mode) { |
211 | if (mode->hdisplay > fixed_mode->hdisplay) |
211 | if (mode->hdisplay > fixed_mode->hdisplay) |
212 | return MODE_PANEL; |
212 | return MODE_PANEL; |
213 | 213 | ||
214 | if (mode->vdisplay > fixed_mode->vdisplay) |
214 | if (mode->vdisplay > fixed_mode->vdisplay) |
215 | return MODE_PANEL; |
215 | return MODE_PANEL; |
216 | 216 | ||
217 | target_clock = fixed_mode->clock; |
217 | target_clock = fixed_mode->clock; |
218 | } |
218 | } |
219 | 219 | ||
220 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
220 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
221 | max_lanes = intel_dp_max_lane_count(intel_dp); |
221 | max_lanes = intel_dp_max_lane_count(intel_dp); |
222 | 222 | ||
223 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
223 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
224 | mode_rate = intel_dp_link_required(target_clock, 18); |
224 | mode_rate = intel_dp_link_required(target_clock, 18); |
225 | 225 | ||
226 | if (mode_rate > max_rate) |
226 | if (mode_rate > max_rate) |
227 | return MODE_CLOCK_HIGH; |
227 | return MODE_CLOCK_HIGH; |
228 | 228 | ||
229 | if (mode->clock < 10000) |
229 | if (mode->clock < 10000) |
230 | return MODE_CLOCK_LOW; |
230 | return MODE_CLOCK_LOW; |
231 | 231 | ||
232 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
232 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
233 | return MODE_H_ILLEGAL; |
233 | return MODE_H_ILLEGAL; |
234 | 234 | ||
235 | return MODE_OK; |
235 | return MODE_OK; |
236 | } |
236 | } |
237 | 237 | ||
238 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
238 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
239 | { |
239 | { |
240 | int i; |
240 | int i; |
241 | uint32_t v = 0; |
241 | uint32_t v = 0; |
242 | 242 | ||
243 | if (src_bytes > 4) |
243 | if (src_bytes > 4) |
244 | src_bytes = 4; |
244 | src_bytes = 4; |
245 | for (i = 0; i < src_bytes; i++) |
245 | for (i = 0; i < src_bytes; i++) |
246 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
246 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
247 | return v; |
247 | return v; |
248 | } |
248 | } |
249 | 249 | ||
250 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
250 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
251 | { |
251 | { |
252 | int i; |
252 | int i; |
253 | if (dst_bytes > 4) |
253 | if (dst_bytes > 4) |
254 | dst_bytes = 4; |
254 | dst_bytes = 4; |
255 | for (i = 0; i < dst_bytes; i++) |
255 | for (i = 0; i < dst_bytes; i++) |
256 | dst[i] = src >> ((3-i) * 8); |
256 | dst[i] = src >> ((3-i) * 8); |
257 | } |
257 | } |
258 | 258 | ||
259 | static void |
259 | static void |
260 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
260 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
261 | struct intel_dp *intel_dp); |
261 | struct intel_dp *intel_dp); |
262 | static void |
262 | static void |
263 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
263 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
264 | struct intel_dp *intel_dp); |
264 | struct intel_dp *intel_dp); |
265 | 265 | ||
266 | static void pps_lock(struct intel_dp *intel_dp) |
266 | static void pps_lock(struct intel_dp *intel_dp) |
267 | { |
267 | { |
268 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
268 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
269 | struct intel_encoder *encoder = &intel_dig_port->base; |
269 | struct intel_encoder *encoder = &intel_dig_port->base; |
270 | struct drm_device *dev = encoder->base.dev; |
270 | struct drm_device *dev = encoder->base.dev; |
271 | struct drm_i915_private *dev_priv = dev->dev_private; |
271 | struct drm_i915_private *dev_priv = dev->dev_private; |
272 | enum intel_display_power_domain power_domain; |
272 | enum intel_display_power_domain power_domain; |
273 | 273 | ||
274 | /* |
274 | /* |
275 | * See vlv_power_sequencer_reset() why we need |
275 | * See vlv_power_sequencer_reset() why we need |
276 | * a power domain reference here. |
276 | * a power domain reference here. |
277 | */ |
277 | */ |
278 | power_domain = intel_display_port_aux_power_domain(encoder); |
278 | power_domain = intel_display_port_aux_power_domain(encoder); |
279 | intel_display_power_get(dev_priv, power_domain); |
279 | intel_display_power_get(dev_priv, power_domain); |
280 | 280 | ||
281 | mutex_lock(&dev_priv->pps_mutex); |
281 | mutex_lock(&dev_priv->pps_mutex); |
282 | } |
282 | } |
283 | 283 | ||
284 | static void pps_unlock(struct intel_dp *intel_dp) |
284 | static void pps_unlock(struct intel_dp *intel_dp) |
285 | { |
285 | { |
286 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
286 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
287 | struct intel_encoder *encoder = &intel_dig_port->base; |
287 | struct intel_encoder *encoder = &intel_dig_port->base; |
288 | struct drm_device *dev = encoder->base.dev; |
288 | struct drm_device *dev = encoder->base.dev; |
289 | struct drm_i915_private *dev_priv = dev->dev_private; |
289 | struct drm_i915_private *dev_priv = dev->dev_private; |
290 | enum intel_display_power_domain power_domain; |
290 | enum intel_display_power_domain power_domain; |
291 | 291 | ||
292 | mutex_unlock(&dev_priv->pps_mutex); |
292 | mutex_unlock(&dev_priv->pps_mutex); |
293 | 293 | ||
294 | power_domain = intel_display_port_aux_power_domain(encoder); |
294 | power_domain = intel_display_port_aux_power_domain(encoder); |
295 | intel_display_power_put(dev_priv, power_domain); |
295 | intel_display_power_put(dev_priv, power_domain); |
296 | } |
296 | } |
297 | 297 | ||
298 | static void |
298 | static void |
299 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
299 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
300 | { |
300 | { |
301 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
301 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
302 | struct drm_device *dev = intel_dig_port->base.base.dev; |
302 | struct drm_device *dev = intel_dig_port->base.base.dev; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; |
304 | enum pipe pipe = intel_dp->pps_pipe; |
304 | enum pipe pipe = intel_dp->pps_pipe; |
305 | bool pll_enabled, release_cl_override = false; |
305 | bool pll_enabled, release_cl_override = false; |
306 | enum dpio_phy phy = DPIO_PHY(pipe); |
306 | enum dpio_phy phy = DPIO_PHY(pipe); |
307 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
307 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
308 | uint32_t DP; |
308 | uint32_t DP; |
309 | 309 | ||
310 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
310 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
311 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
311 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
312 | pipe_name(pipe), port_name(intel_dig_port->port))) |
312 | pipe_name(pipe), port_name(intel_dig_port->port))) |
313 | return; |
313 | return; |
314 | 314 | ||
315 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
315 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
316 | pipe_name(pipe), port_name(intel_dig_port->port)); |
316 | pipe_name(pipe), port_name(intel_dig_port->port)); |
317 | 317 | ||
318 | /* Preserve the BIOS-computed detected bit. This is |
318 | /* Preserve the BIOS-computed detected bit. This is |
319 | * supposed to be read-only. |
319 | * supposed to be read-only. |
320 | */ |
320 | */ |
321 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
321 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
322 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
322 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
323 | DP |= DP_PORT_WIDTH(1); |
323 | DP |= DP_PORT_WIDTH(1); |
324 | DP |= DP_LINK_TRAIN_PAT_1; |
324 | DP |= DP_LINK_TRAIN_PAT_1; |
325 | 325 | ||
326 | if (IS_CHERRYVIEW(dev)) |
326 | if (IS_CHERRYVIEW(dev)) |
327 | DP |= DP_PIPE_SELECT_CHV(pipe); |
327 | DP |= DP_PIPE_SELECT_CHV(pipe); |
328 | else if (pipe == PIPE_B) |
328 | else if (pipe == PIPE_B) |
329 | DP |= DP_PIPEB_SELECT; |
329 | DP |= DP_PIPEB_SELECT; |
330 | 330 | ||
331 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
331 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
332 | 332 | ||
333 | /* |
333 | /* |
334 | * The DPLL for the pipe must be enabled for this to work. |
334 | * The DPLL for the pipe must be enabled for this to work. |
335 | * So enable temporarily it if it's not already enabled. |
335 | * So enable temporarily it if it's not already enabled. |
336 | */ |
336 | */ |
337 | if (!pll_enabled) { |
337 | if (!pll_enabled) { |
338 | release_cl_override = IS_CHERRYVIEW(dev) && |
338 | release_cl_override = IS_CHERRYVIEW(dev) && |
339 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
339 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
340 | 340 | ||
341 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
341 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
342 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
342 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); |
343 | } |
343 | } |
344 | 344 | ||
345 | /* |
345 | /* |
346 | * Similar magic as in intel_dp_enable_port(). |
346 | * Similar magic as in intel_dp_enable_port(). |
347 | * We _must_ do this port enable + disable trick |
347 | * We _must_ do this port enable + disable trick |
348 | * to make this power seqeuencer lock onto the port. |
348 | * to make this power seqeuencer lock onto the port. |
349 | * Otherwise even VDD force bit won't work. |
349 | * Otherwise even VDD force bit won't work. |
350 | */ |
350 | */ |
351 | I915_WRITE(intel_dp->output_reg, DP); |
351 | I915_WRITE(intel_dp->output_reg, DP); |
352 | POSTING_READ(intel_dp->output_reg); |
352 | POSTING_READ(intel_dp->output_reg); |
353 | 353 | ||
354 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
354 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
355 | POSTING_READ(intel_dp->output_reg); |
355 | POSTING_READ(intel_dp->output_reg); |
356 | 356 | ||
357 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
357 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
358 | POSTING_READ(intel_dp->output_reg); |
358 | POSTING_READ(intel_dp->output_reg); |
359 | 359 | ||
360 | if (!pll_enabled) { |
360 | if (!pll_enabled) { |
361 | vlv_force_pll_off(dev, pipe); |
361 | vlv_force_pll_off(dev, pipe); |
362 | 362 | ||
363 | if (release_cl_override) |
363 | if (release_cl_override) |
364 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
364 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
365 | } |
365 | } |
366 | } |
366 | } |
367 | 367 | ||
368 | static enum pipe |
368 | static enum pipe |
369 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
369 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
370 | { |
370 | { |
371 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
371 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
372 | struct drm_device *dev = intel_dig_port->base.base.dev; |
372 | struct drm_device *dev = intel_dig_port->base.base.dev; |
373 | struct drm_i915_private *dev_priv = dev->dev_private; |
373 | struct drm_i915_private *dev_priv = dev->dev_private; |
374 | struct intel_encoder *encoder; |
374 | struct intel_encoder *encoder; |
375 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
375 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
376 | enum pipe pipe; |
376 | enum pipe pipe; |
377 | 377 | ||
378 | lockdep_assert_held(&dev_priv->pps_mutex); |
378 | lockdep_assert_held(&dev_priv->pps_mutex); |
379 | 379 | ||
380 | /* We should never land here with regular DP ports */ |
380 | /* We should never land here with regular DP ports */ |
381 | WARN_ON(!is_edp(intel_dp)); |
381 | WARN_ON(!is_edp(intel_dp)); |
382 | 382 | ||
383 | if (intel_dp->pps_pipe != INVALID_PIPE) |
383 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | return intel_dp->pps_pipe; |
384 | return intel_dp->pps_pipe; |
385 | 385 | ||
386 | /* |
386 | /* |
387 | * We don't have power sequencer currently. |
387 | * We don't have power sequencer currently. |
388 | * Pick one that's not used by other ports. |
388 | * Pick one that's not used by other ports. |
389 | */ |
389 | */ |
390 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
390 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
391 | base.head) { |
391 | base.head) { |
392 | struct intel_dp *tmp; |
392 | struct intel_dp *tmp; |
393 | 393 | ||
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
394 | if (encoder->type != INTEL_OUTPUT_EDP) |
395 | continue; |
395 | continue; |
396 | 396 | ||
397 | tmp = enc_to_intel_dp(&encoder->base); |
397 | tmp = enc_to_intel_dp(&encoder->base); |
398 | 398 | ||
399 | if (tmp->pps_pipe != INVALID_PIPE) |
399 | if (tmp->pps_pipe != INVALID_PIPE) |
400 | pipes &= ~(1 << tmp->pps_pipe); |
400 | pipes &= ~(1 << tmp->pps_pipe); |
401 | } |
401 | } |
402 | 402 | ||
403 | /* |
403 | /* |
404 | * Didn't find one. This should not happen since there |
404 | * Didn't find one. This should not happen since there |
405 | * are two power sequencers and up to two eDP ports. |
405 | * are two power sequencers and up to two eDP ports. |
406 | */ |
406 | */ |
407 | if (WARN_ON(pipes == 0)) |
407 | if (WARN_ON(pipes == 0)) |
408 | pipe = PIPE_A; |
408 | pipe = PIPE_A; |
409 | else |
409 | else |
410 | pipe = ffs(pipes) - 1; |
410 | pipe = ffs(pipes) - 1; |
411 | 411 | ||
412 | vlv_steal_power_sequencer(dev, pipe); |
412 | vlv_steal_power_sequencer(dev, pipe); |
413 | intel_dp->pps_pipe = pipe; |
413 | intel_dp->pps_pipe = pipe; |
414 | 414 | ||
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
415 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
416 | pipe_name(intel_dp->pps_pipe), |
416 | pipe_name(intel_dp->pps_pipe), |
417 | port_name(intel_dig_port->port)); |
417 | port_name(intel_dig_port->port)); |
418 | 418 | ||
419 | /* init power sequencer on this pipe and port */ |
419 | /* init power sequencer on this pipe and port */ |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
420 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
421 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
422 | 422 | ||
423 | /* |
423 | /* |
424 | * Even vdd force doesn't work until we've made |
424 | * Even vdd force doesn't work until we've made |
425 | * the power sequencer lock in on the port. |
425 | * the power sequencer lock in on the port. |
426 | */ |
426 | */ |
427 | vlv_power_sequencer_kick(intel_dp); |
427 | vlv_power_sequencer_kick(intel_dp); |
428 | 428 | ||
429 | return intel_dp->pps_pipe; |
429 | return intel_dp->pps_pipe; |
430 | } |
430 | } |
431 | 431 | ||
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
432 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
433 | enum pipe pipe); |
433 | enum pipe pipe); |
434 | 434 | ||
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
435 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
436 | enum pipe pipe) |
436 | enum pipe pipe) |
437 | { |
437 | { |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
438 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
439 | } |
439 | } |
440 | 440 | ||
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
441 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
442 | enum pipe pipe) |
442 | enum pipe pipe) |
443 | { |
443 | { |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
444 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
445 | } |
445 | } |
446 | 446 | ||
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
447 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
448 | enum pipe pipe) |
448 | enum pipe pipe) |
449 | { |
449 | { |
450 | return true; |
450 | return true; |
451 | } |
451 | } |
452 | 452 | ||
453 | static enum pipe |
453 | static enum pipe |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
454 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
455 | enum port port, |
455 | enum port port, |
456 | vlv_pipe_check pipe_check) |
456 | vlv_pipe_check pipe_check) |
457 | { |
457 | { |
458 | enum pipe pipe; |
458 | enum pipe pipe; |
459 | 459 | ||
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
460 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
461 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
462 | PANEL_PORT_SELECT_MASK; |
462 | PANEL_PORT_SELECT_MASK; |
463 | 463 | ||
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
464 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
465 | continue; |
465 | continue; |
466 | 466 | ||
467 | if (!pipe_check(dev_priv, pipe)) |
467 | if (!pipe_check(dev_priv, pipe)) |
468 | continue; |
468 | continue; |
469 | 469 | ||
470 | return pipe; |
470 | return pipe; |
471 | } |
471 | } |
472 | 472 | ||
473 | return INVALID_PIPE; |
473 | return INVALID_PIPE; |
474 | } |
474 | } |
475 | 475 | ||
476 | static void |
476 | static void |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
477 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
478 | { |
478 | { |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
480 | struct drm_device *dev = intel_dig_port->base.base.dev; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_private *dev_priv = dev->dev_private; |
482 | enum port port = intel_dig_port->port; |
482 | enum port port = intel_dig_port->port; |
483 | 483 | ||
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
484 | lockdep_assert_held(&dev_priv->pps_mutex); |
485 | 485 | ||
486 | /* try to find a pipe with this port selected */ |
486 | /* try to find a pipe with this port selected */ |
487 | /* first pick one where the panel is on */ |
487 | /* first pick one where the panel is on */ |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
488 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
489 | vlv_pipe_has_pp_on); |
489 | vlv_pipe_has_pp_on); |
490 | /* didn't find one? pick one where vdd is on */ |
490 | /* didn't find one? pick one where vdd is on */ |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
491 | if (intel_dp->pps_pipe == INVALID_PIPE) |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
492 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
493 | vlv_pipe_has_vdd_on); |
493 | vlv_pipe_has_vdd_on); |
494 | /* didn't find one? pick one with just the correct port */ |
494 | /* didn't find one? pick one with just the correct port */ |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
495 | if (intel_dp->pps_pipe == INVALID_PIPE) |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
496 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
497 | vlv_pipe_any); |
497 | vlv_pipe_any); |
498 | 498 | ||
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
499 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
500 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
501 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
502 | port_name(port)); |
502 | port_name(port)); |
503 | return; |
503 | return; |
504 | } |
504 | } |
505 | 505 | ||
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
506 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
507 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
508 | 508 | ||
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
509 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
510 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
511 | } |
511 | } |
512 | 512 | ||
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
513 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
514 | { |
514 | { |
515 | struct drm_device *dev = dev_priv->dev; |
515 | struct drm_device *dev = dev_priv->dev; |
516 | struct intel_encoder *encoder; |
516 | struct intel_encoder *encoder; |
517 | 517 | ||
518 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
518 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
519 | return; |
519 | return; |
520 | 520 | ||
521 | /* |
521 | /* |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
522 | * We can't grab pps_mutex here due to deadlock with power_domain |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
523 | * mutex when power_domain functions are called while holding pps_mutex. |
524 | * That also means that in order to use pps_pipe the code needs to |
524 | * That also means that in order to use pps_pipe the code needs to |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
525 | * hold both a power domain reference and pps_mutex, and the power domain |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
526 | * reference get/put must be done while _not_ holding pps_mutex. |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
527 | * pps_{lock,unlock}() do these steps in the correct order, so one |
528 | * should use them always. |
528 | * should use them always. |
529 | */ |
529 | */ |
530 | 530 | ||
531 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
531 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
532 | struct intel_dp *intel_dp; |
532 | struct intel_dp *intel_dp; |
533 | 533 | ||
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
534 | if (encoder->type != INTEL_OUTPUT_EDP) |
535 | continue; |
535 | continue; |
536 | 536 | ||
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
537 | intel_dp = enc_to_intel_dp(&encoder->base); |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
538 | intel_dp->pps_pipe = INVALID_PIPE; |
539 | } |
539 | } |
540 | } |
540 | } |
541 | 541 | ||
542 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
542 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
543 | { |
543 | { |
544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
545 | 545 | ||
546 | if (IS_BROXTON(dev)) |
546 | if (IS_BROXTON(dev)) |
547 | return BXT_PP_CONTROL(0); |
547 | return BXT_PP_CONTROL(0); |
548 | else if (HAS_PCH_SPLIT(dev)) |
548 | else if (HAS_PCH_SPLIT(dev)) |
549 | return PCH_PP_CONTROL; |
549 | return PCH_PP_CONTROL; |
550 | else |
550 | else |
551 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
551 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
552 | } |
552 | } |
553 | 553 | ||
554 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
554 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
555 | { |
555 | { |
556 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
556 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
557 | 557 | ||
558 | if (IS_BROXTON(dev)) |
558 | if (IS_BROXTON(dev)) |
559 | return BXT_PP_STATUS(0); |
559 | return BXT_PP_STATUS(0); |
560 | else if (HAS_PCH_SPLIT(dev)) |
560 | else if (HAS_PCH_SPLIT(dev)) |
561 | return PCH_PP_STATUS; |
561 | return PCH_PP_STATUS; |
562 | else |
562 | else |
563 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
563 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
564 | } |
564 | } |
565 | 565 | ||
566 | #if 0 |
566 | #if 0 |
567 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
567 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
568 | This function only applicable when panel PM state is not to be tracked */ |
568 | This function only applicable when panel PM state is not to be tracked */ |
569 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
569 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
570 | void *unused) |
570 | void *unused) |
571 | { |
571 | { |
572 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
572 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
573 | edp_notifier); |
573 | edp_notifier); |
574 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
574 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
575 | struct drm_i915_private *dev_priv = dev->dev_private; |
575 | struct drm_i915_private *dev_priv = dev->dev_private; |
576 | 576 | ||
577 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
577 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
578 | return 0; |
578 | return 0; |
579 | 579 | ||
580 | pps_lock(intel_dp); |
580 | pps_lock(intel_dp); |
581 | 581 | ||
582 | if (IS_VALLEYVIEW(dev)) { |
582 | if (IS_VALLEYVIEW(dev)) { |
583 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
583 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
584 | u32 pp_ctrl_reg, pp_div_reg; |
584 | u32 pp_ctrl_reg, pp_div_reg; |
585 | u32 pp_div; |
585 | u32 pp_div; |
586 | 586 | ||
587 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
587 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
588 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
588 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
589 | pp_div = I915_READ(pp_div_reg); |
589 | pp_div = I915_READ(pp_div_reg); |
590 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
590 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
591 | 591 | ||
592 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
592 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
593 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
593 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
594 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
594 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
595 | msleep(intel_dp->panel_power_cycle_delay); |
595 | msleep(intel_dp->panel_power_cycle_delay); |
596 | } |
596 | } |
597 | 597 | ||
598 | pps_unlock(intel_dp); |
598 | pps_unlock(intel_dp); |
599 | 599 | ||
600 | return 0; |
600 | return 0; |
601 | } |
601 | } |
602 | #endif |
602 | #endif |
603 | 603 | ||
604 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
604 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
605 | { |
605 | { |
606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
607 | struct drm_i915_private *dev_priv = dev->dev_private; |
607 | struct drm_i915_private *dev_priv = dev->dev_private; |
608 | 608 | ||
609 | lockdep_assert_held(&dev_priv->pps_mutex); |
609 | lockdep_assert_held(&dev_priv->pps_mutex); |
610 | 610 | ||
611 | if (IS_VALLEYVIEW(dev) && |
611 | if (IS_VALLEYVIEW(dev) && |
612 | intel_dp->pps_pipe == INVALID_PIPE) |
612 | intel_dp->pps_pipe == INVALID_PIPE) |
613 | return false; |
613 | return false; |
614 | 614 | ||
615 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
615 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
616 | } |
616 | } |
617 | 617 | ||
618 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
618 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
619 | { |
619 | { |
620 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
620 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
621 | struct drm_i915_private *dev_priv = dev->dev_private; |
621 | struct drm_i915_private *dev_priv = dev->dev_private; |
622 | 622 | ||
623 | lockdep_assert_held(&dev_priv->pps_mutex); |
623 | lockdep_assert_held(&dev_priv->pps_mutex); |
624 | 624 | ||
625 | if (IS_VALLEYVIEW(dev) && |
625 | if (IS_VALLEYVIEW(dev) && |
626 | intel_dp->pps_pipe == INVALID_PIPE) |
626 | intel_dp->pps_pipe == INVALID_PIPE) |
627 | return false; |
627 | return false; |
628 | 628 | ||
629 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
629 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
630 | } |
630 | } |
631 | 631 | ||
632 | static void |
632 | static void |
633 | intel_dp_check_edp(struct intel_dp *intel_dp) |
633 | intel_dp_check_edp(struct intel_dp *intel_dp) |
634 | { |
634 | { |
635 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
635 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
636 | struct drm_i915_private *dev_priv = dev->dev_private; |
636 | struct drm_i915_private *dev_priv = dev->dev_private; |
637 | 637 | ||
638 | if (!is_edp(intel_dp)) |
638 | if (!is_edp(intel_dp)) |
639 | return; |
639 | return; |
640 | 640 | ||
641 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
641 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
642 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
642 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
643 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
643 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
644 | I915_READ(_pp_stat_reg(intel_dp)), |
644 | I915_READ(_pp_stat_reg(intel_dp)), |
645 | I915_READ(_pp_ctrl_reg(intel_dp))); |
645 | I915_READ(_pp_ctrl_reg(intel_dp))); |
646 | } |
646 | } |
647 | } |
647 | } |
648 | 648 | ||
649 | static uint32_t |
649 | static uint32_t |
650 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
650 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
651 | { |
651 | { |
652 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
652 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
653 | struct drm_device *dev = intel_dig_port->base.base.dev; |
653 | struct drm_device *dev = intel_dig_port->base.base.dev; |
654 | struct drm_i915_private *dev_priv = dev->dev_private; |
654 | struct drm_i915_private *dev_priv = dev->dev_private; |
655 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
655 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
656 | uint32_t status; |
656 | uint32_t status; |
657 | bool done; |
657 | bool done; |
658 | 658 | ||
659 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
659 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
660 | if (has_aux_irq) |
660 | if (has_aux_irq) |
661 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
661 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
662 | msecs_to_jiffies_timeout(10)); |
662 | msecs_to_jiffies_timeout(10)); |
663 | else |
663 | else |
664 | done = wait_for_atomic(C, 10) == 0; |
664 | done = wait_for_atomic(C, 10) == 0; |
665 | if (!done) |
665 | if (!done) |
666 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
666 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
667 | has_aux_irq); |
667 | has_aux_irq); |
668 | #undef C |
668 | #undef C |
669 | 669 | ||
670 | return status; |
670 | return status; |
671 | } |
671 | } |
672 | 672 | ||
673 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
673 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
674 | { |
674 | { |
675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
675 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
676 | struct drm_device *dev = intel_dig_port->base.base.dev; |
676 | struct drm_device *dev = intel_dig_port->base.base.dev; |
677 | 677 | ||
678 | /* |
678 | /* |
679 | * The clock divider is based off the hrawclk, and would like to run at |
679 | * The clock divider is based off the hrawclk, and would like to run at |
680 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
680 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
681 | */ |
681 | */ |
682 | return index ? 0 : intel_hrawclk(dev) / 2; |
682 | return index ? 0 : intel_hrawclk(dev) / 2; |
683 | } |
683 | } |
684 | 684 | ||
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
686 | { |
686 | { |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
688 | struct drm_device *dev = intel_dig_port->base.base.dev; |
688 | struct drm_device *dev = intel_dig_port->base.base.dev; |
689 | struct drm_i915_private *dev_priv = dev->dev_private; |
689 | struct drm_i915_private *dev_priv = dev->dev_private; |
690 | 690 | ||
691 | if (index) |
691 | if (index) |
692 | return 0; |
692 | return 0; |
693 | 693 | ||
694 | if (intel_dig_port->port == PORT_A) { |
694 | if (intel_dig_port->port == PORT_A) { |
695 | return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); |
695 | return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); |
696 | 696 | ||
697 | } else { |
697 | } else { |
698 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
698 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
699 | } |
699 | } |
700 | } |
700 | } |
701 | 701 | ||
702 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
702 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
703 | { |
703 | { |
704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
705 | struct drm_device *dev = intel_dig_port->base.base.dev; |
705 | struct drm_device *dev = intel_dig_port->base.base.dev; |
706 | struct drm_i915_private *dev_priv = dev->dev_private; |
706 | struct drm_i915_private *dev_priv = dev->dev_private; |
707 | 707 | ||
708 | if (intel_dig_port->port == PORT_A) { |
708 | if (intel_dig_port->port == PORT_A) { |
709 | if (index) |
709 | if (index) |
710 | return 0; |
710 | return 0; |
711 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
711 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
712 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
712 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
713 | /* Workaround for non-ULT HSW */ |
713 | /* Workaround for non-ULT HSW */ |
714 | switch (index) { |
714 | switch (index) { |
715 | case 0: return 63; |
715 | case 0: return 63; |
716 | case 1: return 72; |
716 | case 1: return 72; |
717 | default: return 0; |
717 | default: return 0; |
718 | } |
718 | } |
719 | } else { |
719 | } else { |
720 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
720 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
721 | } |
721 | } |
722 | } |
722 | } |
723 | 723 | ||
724 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
724 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
725 | { |
725 | { |
726 | return index ? 0 : 100; |
726 | return index ? 0 : 100; |
727 | } |
727 | } |
728 | 728 | ||
729 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
729 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
730 | { |
730 | { |
731 | /* |
731 | /* |
732 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
732 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
733 | * derive the clock from CDCLK automatically). We still implement the |
733 | * derive the clock from CDCLK automatically). We still implement the |
734 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
734 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
735 | */ |
735 | */ |
736 | return index ? 0 : 1; |
736 | return index ? 0 : 1; |
737 | } |
737 | } |
738 | 738 | ||
739 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
739 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
740 | bool has_aux_irq, |
740 | bool has_aux_irq, |
741 | int send_bytes, |
741 | int send_bytes, |
742 | uint32_t aux_clock_divider) |
742 | uint32_t aux_clock_divider) |
743 | { |
743 | { |
744 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
744 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
745 | struct drm_device *dev = intel_dig_port->base.base.dev; |
745 | struct drm_device *dev = intel_dig_port->base.base.dev; |
746 | uint32_t precharge, timeout; |
746 | uint32_t precharge, timeout; |
747 | 747 | ||
748 | if (IS_GEN6(dev)) |
748 | if (IS_GEN6(dev)) |
749 | precharge = 3; |
749 | precharge = 3; |
750 | else |
750 | else |
751 | precharge = 5; |
751 | precharge = 5; |
752 | 752 | ||
753 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
753 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
754 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
754 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
755 | else |
755 | else |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
756 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
757 | 757 | ||
758 | return DP_AUX_CH_CTL_SEND_BUSY | |
758 | return DP_AUX_CH_CTL_SEND_BUSY | |
759 | DP_AUX_CH_CTL_DONE | |
759 | DP_AUX_CH_CTL_DONE | |
760 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
760 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
761 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
761 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
762 | timeout | |
762 | timeout | |
763 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
763 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
764 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
764 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
765 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
765 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
766 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
766 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
767 | } |
767 | } |
768 | 768 | ||
769 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
769 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
770 | bool has_aux_irq, |
770 | bool has_aux_irq, |
771 | int send_bytes, |
771 | int send_bytes, |
772 | uint32_t unused) |
772 | uint32_t unused) |
773 | { |
773 | { |
774 | return DP_AUX_CH_CTL_SEND_BUSY | |
774 | return DP_AUX_CH_CTL_SEND_BUSY | |
775 | DP_AUX_CH_CTL_DONE | |
775 | DP_AUX_CH_CTL_DONE | |
776 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
776 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
777 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
777 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
778 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
778 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
779 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
779 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
780 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
780 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
781 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
781 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
782 | } |
782 | } |
783 | 783 | ||
784 | static int |
784 | static int |
785 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
785 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
786 | const uint8_t *send, int send_bytes, |
786 | const uint8_t *send, int send_bytes, |
787 | uint8_t *recv, int recv_size) |
787 | uint8_t *recv, int recv_size) |
788 | { |
788 | { |
789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
789 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
790 | struct drm_device *dev = intel_dig_port->base.base.dev; |
790 | struct drm_device *dev = intel_dig_port->base.base.dev; |
791 | struct drm_i915_private *dev_priv = dev->dev_private; |
791 | struct drm_i915_private *dev_priv = dev->dev_private; |
792 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
792 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
793 | uint32_t ch_data = ch_ctl + 4; |
793 | uint32_t ch_data = ch_ctl + 4; |
794 | uint32_t aux_clock_divider; |
794 | uint32_t aux_clock_divider; |
795 | int i, ret, recv_bytes; |
795 | int i, ret, recv_bytes; |
796 | uint32_t status; |
796 | uint32_t status; |
797 | int try, clock = 0; |
797 | int try, clock = 0; |
798 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
798 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
799 | bool vdd; |
799 | bool vdd; |
800 | 800 | ||
801 | pps_lock(intel_dp); |
801 | pps_lock(intel_dp); |
802 | 802 | ||
803 | /* |
803 | /* |
804 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
804 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
805 | * In such cases we want to leave VDD enabled and it's up to upper layers |
805 | * In such cases we want to leave VDD enabled and it's up to upper layers |
806 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
806 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
807 | * ourselves. |
807 | * ourselves. |
808 | */ |
808 | */ |
809 | vdd = edp_panel_vdd_on(intel_dp); |
809 | vdd = edp_panel_vdd_on(intel_dp); |
810 | 810 | ||
811 | /* dp aux is extremely sensitive to irq latency, hence request the |
811 | /* dp aux is extremely sensitive to irq latency, hence request the |
812 | * lowest possible wakeup latency and so prevent the cpu from going into |
812 | * lowest possible wakeup latency and so prevent the cpu from going into |
813 | * deep sleep states. |
813 | * deep sleep states. |
814 | */ |
814 | */ |
815 | 815 | ||
816 | intel_dp_check_edp(intel_dp); |
816 | intel_dp_check_edp(intel_dp); |
817 | 817 | ||
818 | /* Try to wait for any previous AUX channel activity */ |
818 | /* Try to wait for any previous AUX channel activity */ |
819 | for (try = 0; try < 3; try++) { |
819 | for (try = 0; try < 3; try++) { |
820 | status = I915_READ_NOTRACE(ch_ctl); |
820 | status = I915_READ_NOTRACE(ch_ctl); |
821 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
821 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
822 | break; |
822 | break; |
823 | msleep(1); |
823 | msleep(1); |
824 | } |
824 | } |
825 | 825 | ||
826 | if (try == 3) { |
826 | if (try == 3) { |
827 | static u32 last_status = -1; |
827 | static u32 last_status = -1; |
828 | const u32 status = I915_READ(ch_ctl); |
828 | const u32 status = I915_READ(ch_ctl); |
829 | 829 | ||
830 | if (status != last_status) { |
830 | if (status != last_status) { |
831 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
831 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
832 | status); |
832 | status); |
833 | last_status = status; |
833 | last_status = status; |
834 | } |
834 | } |
835 | 835 | ||
836 | ret = -EBUSY; |
836 | ret = -EBUSY; |
837 | goto out; |
837 | goto out; |
838 | } |
838 | } |
839 | 839 | ||
840 | /* Only 5 data registers! */ |
840 | /* Only 5 data registers! */ |
841 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
841 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
842 | ret = -E2BIG; |
842 | ret = -E2BIG; |
843 | goto out; |
843 | goto out; |
844 | } |
844 | } |
845 | 845 | ||
846 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
846 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
847 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
847 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
848 | has_aux_irq, |
848 | has_aux_irq, |
849 | send_bytes, |
849 | send_bytes, |
850 | aux_clock_divider); |
850 | aux_clock_divider); |
851 | 851 | ||
852 | /* Must try at least 3 times according to DP spec */ |
852 | /* Must try at least 3 times according to DP spec */ |
853 | for (try = 0; try < 5; try++) { |
853 | for (try = 0; try < 5; try++) { |
854 | /* Load the send data into the aux channel data registers */ |
854 | /* Load the send data into the aux channel data registers */ |
855 | for (i = 0; i < send_bytes; i += 4) |
855 | for (i = 0; i < send_bytes; i += 4) |
856 | I915_WRITE(ch_data + i, |
856 | I915_WRITE(ch_data + i, |
857 | intel_dp_pack_aux(send + i, |
857 | intel_dp_pack_aux(send + i, |
858 | send_bytes - i)); |
858 | send_bytes - i)); |
859 | 859 | ||
860 | /* Send the command and wait for it to complete */ |
860 | /* Send the command and wait for it to complete */ |
861 | I915_WRITE(ch_ctl, send_ctl); |
861 | I915_WRITE(ch_ctl, send_ctl); |
862 | 862 | ||
863 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
863 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
864 | 864 | ||
865 | /* Clear done status and any errors */ |
865 | /* Clear done status and any errors */ |
866 | I915_WRITE(ch_ctl, |
866 | I915_WRITE(ch_ctl, |
867 | status | |
867 | status | |
868 | DP_AUX_CH_CTL_DONE | |
868 | DP_AUX_CH_CTL_DONE | |
869 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
869 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
870 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
870 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
871 | 871 | ||
872 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
872 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
873 | continue; |
873 | continue; |
874 | 874 | ||
875 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
875 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
876 | * 400us delay required for errors and timeouts |
876 | * 400us delay required for errors and timeouts |
877 | * Timeout errors from the HW already meet this |
877 | * Timeout errors from the HW already meet this |
878 | * requirement so skip to next iteration |
878 | * requirement so skip to next iteration |
879 | */ |
879 | */ |
880 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
880 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
881 | usleep_range(400, 500); |
881 | usleep_range(400, 500); |
882 | continue; |
882 | continue; |
883 | } |
883 | } |
884 | if (status & DP_AUX_CH_CTL_DONE) |
884 | if (status & DP_AUX_CH_CTL_DONE) |
885 | goto done; |
885 | goto done; |
886 | } |
886 | } |
887 | } |
887 | } |
888 | 888 | ||
889 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
889 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
890 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
890 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
891 | ret = -EBUSY; |
891 | ret = -EBUSY; |
892 | goto out; |
892 | goto out; |
893 | } |
893 | } |
894 | 894 | ||
895 | done: |
895 | done: |
896 | /* Check for timeout or receive error. |
896 | /* Check for timeout or receive error. |
897 | * Timeouts occur when the sink is not connected |
897 | * Timeouts occur when the sink is not connected |
898 | */ |
898 | */ |
899 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
899 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
900 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
900 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
901 | ret = -EIO; |
901 | ret = -EIO; |
902 | goto out; |
902 | goto out; |
903 | } |
903 | } |
904 | 904 | ||
905 | /* Timeouts occur when the device isn't connected, so they're |
905 | /* Timeouts occur when the device isn't connected, so they're |
906 | * "normal" -- don't fill the kernel log with these */ |
906 | * "normal" -- don't fill the kernel log with these */ |
907 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
907 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
908 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
908 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
909 | ret = -ETIMEDOUT; |
909 | ret = -ETIMEDOUT; |
910 | goto out; |
910 | goto out; |
911 | } |
911 | } |
912 | 912 | ||
913 | /* Unload any bytes sent back from the other side */ |
913 | /* Unload any bytes sent back from the other side */ |
914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
916 | if (recv_bytes > recv_size) |
916 | if (recv_bytes > recv_size) |
917 | recv_bytes = recv_size; |
917 | recv_bytes = recv_size; |
918 | 918 | ||
919 | for (i = 0; i < recv_bytes; i += 4) |
919 | for (i = 0; i < recv_bytes; i += 4) |
920 | intel_dp_unpack_aux(I915_READ(ch_data + i), |
920 | intel_dp_unpack_aux(I915_READ(ch_data + i), |
921 | recv + i, recv_bytes - i); |
921 | recv + i, recv_bytes - i); |
922 | 922 | ||
923 | ret = recv_bytes; |
923 | ret = recv_bytes; |
924 | out: |
924 | out: |
925 | 925 | ||
926 | if (vdd) |
926 | if (vdd) |
927 | edp_panel_vdd_off(intel_dp, false); |
927 | edp_panel_vdd_off(intel_dp, false); |
928 | 928 | ||
929 | pps_unlock(intel_dp); |
929 | pps_unlock(intel_dp); |
930 | 930 | ||
931 | return ret; |
931 | return ret; |
932 | } |
932 | } |
933 | 933 | ||
934 | #define BARE_ADDRESS_SIZE 3 |
934 | #define BARE_ADDRESS_SIZE 3 |
935 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
935 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
936 | static ssize_t |
936 | static ssize_t |
937 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
937 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
938 | { |
938 | { |
939 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
939 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
940 | uint8_t txbuf[20], rxbuf[20]; |
940 | uint8_t txbuf[20], rxbuf[20]; |
941 | size_t txsize, rxsize; |
941 | size_t txsize, rxsize; |
942 | int ret; |
942 | int ret; |
943 | 943 | ||
944 | txbuf[0] = (msg->request << 4) | |
944 | txbuf[0] = (msg->request << 4) | |
945 | ((msg->address >> 16) & 0xf); |
945 | ((msg->address >> 16) & 0xf); |
946 | txbuf[1] = (msg->address >> 8) & 0xff; |
946 | txbuf[1] = (msg->address >> 8) & 0xff; |
947 | txbuf[2] = msg->address & 0xff; |
947 | txbuf[2] = msg->address & 0xff; |
948 | txbuf[3] = msg->size - 1; |
948 | txbuf[3] = msg->size - 1; |
949 | 949 | ||
950 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
950 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
951 | case DP_AUX_NATIVE_WRITE: |
951 | case DP_AUX_NATIVE_WRITE: |
952 | case DP_AUX_I2C_WRITE: |
952 | case DP_AUX_I2C_WRITE: |
953 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
953 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
954 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
954 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
955 | rxsize = 2; /* 0 or 1 data bytes */ |
955 | rxsize = 2; /* 0 or 1 data bytes */ |
956 | 956 | ||
957 | if (WARN_ON(txsize > 20)) |
957 | if (WARN_ON(txsize > 20)) |
958 | return -E2BIG; |
958 | return -E2BIG; |
959 | 959 | ||
960 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
960 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
961 | 961 | ||
962 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
962 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
963 | if (ret > 0) { |
963 | if (ret > 0) { |
964 | msg->reply = rxbuf[0] >> 4; |
964 | msg->reply = rxbuf[0] >> 4; |
965 | 965 | ||
966 | if (ret > 1) { |
966 | if (ret > 1) { |
967 | /* Number of bytes written in a short write. */ |
967 | /* Number of bytes written in a short write. */ |
968 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
968 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
969 | } else { |
969 | } else { |
970 | /* Return payload size. */ |
970 | /* Return payload size. */ |
971 | ret = msg->size; |
971 | ret = msg->size; |
972 | } |
972 | } |
973 | } |
973 | } |
974 | break; |
974 | break; |
975 | 975 | ||
976 | case DP_AUX_NATIVE_READ: |
976 | case DP_AUX_NATIVE_READ: |
977 | case DP_AUX_I2C_READ: |
977 | case DP_AUX_I2C_READ: |
978 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
978 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
979 | rxsize = msg->size + 1; |
979 | rxsize = msg->size + 1; |
980 | 980 | ||
981 | if (WARN_ON(rxsize > 20)) |
981 | if (WARN_ON(rxsize > 20)) |
982 | return -E2BIG; |
982 | return -E2BIG; |
983 | 983 | ||
984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
984 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
985 | if (ret > 0) { |
985 | if (ret > 0) { |
986 | msg->reply = rxbuf[0] >> 4; |
986 | msg->reply = rxbuf[0] >> 4; |
987 | /* |
987 | /* |
988 | * Assume happy day, and copy the data. The caller is |
988 | * Assume happy day, and copy the data. The caller is |
989 | * expected to check msg->reply before touching it. |
989 | * expected to check msg->reply before touching it. |
990 | * |
990 | * |
991 | * Return payload size. |
991 | * Return payload size. |
992 | */ |
992 | */ |
993 | ret--; |
993 | ret--; |
994 | memcpy(msg->buffer, rxbuf + 1, ret); |
994 | memcpy(msg->buffer, rxbuf + 1, ret); |
995 | } |
995 | } |
996 | break; |
996 | break; |
997 | 997 | ||
998 | default: |
998 | default: |
999 | ret = -EINVAL; |
999 | ret = -EINVAL; |
1000 | break; |
1000 | break; |
1001 | } |
1001 | } |
1002 | 1002 | ||
1003 | return ret; |
1003 | return ret; |
1004 | } |
1004 | } |
1005 | 1005 | ||
1006 | static void |
1006 | static void |
1007 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1007 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1008 | { |
1008 | { |
1009 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1009 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; |
1011 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1011 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1012 | enum port port = intel_dig_port->port; |
1012 | enum port port = intel_dig_port->port; |
1013 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
1013 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
1014 | const char *name = NULL; |
1014 | const char *name = NULL; |
1015 | uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1015 | uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1016 | int ret; |
1016 | int ret; |
1017 | 1017 | ||
1018 | /* On SKL we don't have Aux for port E so we rely on VBT to set |
1018 | /* On SKL we don't have Aux for port E so we rely on VBT to set |
1019 | * a proper alternate aux channel. |
1019 | * a proper alternate aux channel. |
1020 | */ |
1020 | */ |
1021 | if (IS_SKYLAKE(dev) && port == PORT_E) { |
1021 | if (IS_SKYLAKE(dev) && port == PORT_E) { |
1022 | switch (info->alternate_aux_channel) { |
1022 | switch (info->alternate_aux_channel) { |
1023 | case DP_AUX_B: |
1023 | case DP_AUX_B: |
1024 | porte_aux_ctl_reg = DPB_AUX_CH_CTL; |
1024 | porte_aux_ctl_reg = DPB_AUX_CH_CTL; |
1025 | break; |
1025 | break; |
1026 | case DP_AUX_C: |
1026 | case DP_AUX_C: |
1027 | porte_aux_ctl_reg = DPC_AUX_CH_CTL; |
1027 | porte_aux_ctl_reg = DPC_AUX_CH_CTL; |
1028 | break; |
1028 | break; |
1029 | case DP_AUX_D: |
1029 | case DP_AUX_D: |
1030 | porte_aux_ctl_reg = DPD_AUX_CH_CTL; |
1030 | porte_aux_ctl_reg = DPD_AUX_CH_CTL; |
1031 | break; |
1031 | break; |
1032 | case DP_AUX_A: |
1032 | case DP_AUX_A: |
1033 | default: |
1033 | default: |
1034 | porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1034 | porte_aux_ctl_reg = DPA_AUX_CH_CTL; |
1035 | } |
1035 | } |
1036 | } |
1036 | } |
1037 | 1037 | ||
1038 | switch (port) { |
1038 | switch (port) { |
1039 | case PORT_A: |
1039 | case PORT_A: |
1040 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
1040 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
1041 | name = "DPDDC-A"; |
1041 | name = "DPDDC-A"; |
1042 | break; |
1042 | break; |
1043 | case PORT_B: |
1043 | case PORT_B: |
1044 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
1044 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
1045 | name = "DPDDC-B"; |
1045 | name = "DPDDC-B"; |
1046 | break; |
1046 | break; |
1047 | case PORT_C: |
1047 | case PORT_C: |
1048 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
1048 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
1049 | name = "DPDDC-C"; |
1049 | name = "DPDDC-C"; |
1050 | break; |
1050 | break; |
1051 | case PORT_D: |
1051 | case PORT_D: |
1052 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
1052 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
1053 | name = "DPDDC-D"; |
1053 | name = "DPDDC-D"; |
1054 | break; |
1054 | break; |
1055 | case PORT_E: |
1055 | case PORT_E: |
1056 | intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg; |
1056 | intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg; |
1057 | name = "DPDDC-E"; |
1057 | name = "DPDDC-E"; |
1058 | break; |
1058 | break; |
1059 | default: |
1059 | default: |
1060 | BUG(); |
1060 | BUG(); |
1061 | } |
1061 | } |
1062 | 1062 | ||
1063 | /* |
1063 | /* |
1064 | * The AUX_CTL register is usually DP_CTL + 0x10. |
1064 | * The AUX_CTL register is usually DP_CTL + 0x10. |
1065 | * |
1065 | * |
1066 | * On Haswell and Broadwell though: |
1066 | * On Haswell and Broadwell though: |
1067 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU |
1067 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU |
1068 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU |
1068 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU |
1069 | * |
1069 | * |
1070 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. |
1070 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. |
1071 | */ |
1071 | */ |
1072 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E) |
1072 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E) |
1073 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
1073 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
1074 | 1074 | ||
1075 | intel_dp->aux.name = name; |
1075 | intel_dp->aux.name = name; |
1076 | intel_dp->aux.dev = dev->dev; |
1076 | intel_dp->aux.dev = dev->dev; |
1077 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1077 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
1078 | 1078 | ||
1079 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
1079 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
1080 | ""); |
1080 | ""); |
1081 | 1081 | ||
1082 | ret = drm_dp_aux_register(&intel_dp->aux); |
1082 | ret = drm_dp_aux_register(&intel_dp->aux); |
1083 | if (ret < 0) { |
1083 | if (ret < 0) { |
1084 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1084 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
1085 | name, ret); |
1085 | name, ret); |
1086 | return; |
1086 | return; |
1087 | } |
1087 | } |
1088 | 1088 | ||
1089 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1089 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1090 | &intel_dp->aux.ddc.dev.kobj, |
1090 | &intel_dp->aux.ddc.dev.kobj, |
1091 | intel_dp->aux.ddc.dev.kobj.name); |
1091 | intel_dp->aux.ddc.dev.kobj.name); |
1092 | if (ret < 0) { |
1092 | if (ret < 0) { |
1093 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); |
1093 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); |
1094 | drm_dp_aux_unregister(&intel_dp->aux); |
1094 | drm_dp_aux_unregister(&intel_dp->aux); |
1095 | } |
1095 | } |
1096 | } |
1096 | } |
1097 | 1097 | ||
1098 | static void |
1098 | static void |
1099 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1099 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
1100 | { |
1100 | { |
1101 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1101 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
1102 | 1102 | ||
1103 | if (!intel_connector->mst_port) |
1103 | if (!intel_connector->mst_port) |
1104 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
1104 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
1105 | intel_dp->aux.ddc.dev.kobj.name); |
1105 | intel_dp->aux.ddc.dev.kobj.name); |
1106 | intel_connector_unregister(intel_connector); |
1106 | intel_connector_unregister(intel_connector); |
1107 | } |
1107 | } |
1108 | 1108 | ||
1109 | static void |
1109 | static void |
1110 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1110 | skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) |
1111 | { |
1111 | { |
1112 | u32 ctrl1; |
1112 | u32 ctrl1; |
1113 | 1113 | ||
1114 | memset(&pipe_config->dpll_hw_state, 0, |
1114 | memset(&pipe_config->dpll_hw_state, 0, |
1115 | sizeof(pipe_config->dpll_hw_state)); |
1115 | sizeof(pipe_config->dpll_hw_state)); |
1116 | 1116 | ||
1117 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1117 | pipe_config->ddi_pll_sel = SKL_DPLL0; |
1118 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1118 | pipe_config->dpll_hw_state.cfgcr1 = 0; |
1119 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1119 | pipe_config->dpll_hw_state.cfgcr2 = 0; |
1120 | 1120 | ||
1121 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1121 | ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); |
1122 | switch (pipe_config->port_clock / 2) { |
1122 | switch (pipe_config->port_clock / 2) { |
1123 | case 81000: |
1123 | case 81000: |
1124 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1124 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, |
1125 | SKL_DPLL0); |
1125 | SKL_DPLL0); |
1126 | break; |
1126 | break; |
1127 | case 135000: |
1127 | case 135000: |
1128 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1128 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, |
1129 | SKL_DPLL0); |
1129 | SKL_DPLL0); |
1130 | break; |
1130 | break; |
1131 | case 270000: |
1131 | case 270000: |
1132 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1132 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, |
1133 | SKL_DPLL0); |
1133 | SKL_DPLL0); |
1134 | break; |
1134 | break; |
1135 | case 162000: |
1135 | case 162000: |
1136 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1136 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, |
1137 | SKL_DPLL0); |
1137 | SKL_DPLL0); |
1138 | break; |
1138 | break; |
1139 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1139 | /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which |
1140 | results in CDCLK change. Need to handle the change of CDCLK by |
1140 | results in CDCLK change. Need to handle the change of CDCLK by |
1141 | disabling pipes and re-enabling them */ |
1141 | disabling pipes and re-enabling them */ |
1142 | case 108000: |
1142 | case 108000: |
1143 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1143 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
1144 | SKL_DPLL0); |
1144 | SKL_DPLL0); |
1145 | break; |
1145 | break; |
1146 | case 216000: |
1146 | case 216000: |
1147 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1147 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, |
1148 | SKL_DPLL0); |
1148 | SKL_DPLL0); |
1149 | break; |
1149 | break; |
1150 | 1150 | ||
1151 | } |
1151 | } |
1152 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1152 | pipe_config->dpll_hw_state.ctrl1 = ctrl1; |
1153 | } |
1153 | } |
1154 | 1154 | ||
1155 | void |
1155 | void |
1156 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1156 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) |
1157 | { |
1157 | { |
1158 | memset(&pipe_config->dpll_hw_state, 0, |
1158 | memset(&pipe_config->dpll_hw_state, 0, |
1159 | sizeof(pipe_config->dpll_hw_state)); |
1159 | sizeof(pipe_config->dpll_hw_state)); |
1160 | 1160 | ||
1161 | switch (pipe_config->port_clock / 2) { |
1161 | switch (pipe_config->port_clock / 2) { |
1162 | case 81000: |
1162 | case 81000: |
1163 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1163 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
1164 | break; |
1164 | break; |
1165 | case 135000: |
1165 | case 135000: |
1166 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1166 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
1167 | break; |
1167 | break; |
1168 | case 270000: |
1168 | case 270000: |
1169 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1169 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
1170 | break; |
1170 | break; |
1171 | } |
1171 | } |
1172 | } |
1172 | } |
1173 | 1173 | ||
1174 | static int |
1174 | static int |
1175 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1175 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
1176 | { |
1176 | { |
1177 | if (intel_dp->num_sink_rates) { |
1177 | if (intel_dp->num_sink_rates) { |
1178 | *sink_rates = intel_dp->sink_rates; |
1178 | *sink_rates = intel_dp->sink_rates; |
1179 | return intel_dp->num_sink_rates; |
1179 | return intel_dp->num_sink_rates; |
1180 | } |
1180 | } |
1181 | 1181 | ||
1182 | *sink_rates = default_rates; |
1182 | *sink_rates = default_rates; |
1183 | 1183 | ||
1184 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1184 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
1185 | } |
1185 | } |
1186 | 1186 | ||
1187 | static bool intel_dp_source_supports_hbr2(struct drm_device *dev) |
1187 | static bool intel_dp_source_supports_hbr2(struct drm_device *dev) |
1188 | { |
1188 | { |
1189 | /* WaDisableHBR2:skl */ |
1189 | /* WaDisableHBR2:skl */ |
1190 | if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) |
1190 | if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) |
1191 | return false; |
1191 | return false; |
1192 | 1192 | ||
1193 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1193 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
1194 | (INTEL_INFO(dev)->gen >= 9)) |
1194 | (INTEL_INFO(dev)->gen >= 9)) |
1195 | return true; |
1195 | return true; |
1196 | else |
1196 | else |
1197 | return false; |
1197 | return false; |
1198 | } |
1198 | } |
1199 | 1199 | ||
1200 | static int |
1200 | static int |
1201 | intel_dp_source_rates(struct drm_device *dev, const int **source_rates) |
1201 | intel_dp_source_rates(struct drm_device *dev, const int **source_rates) |
1202 | { |
1202 | { |
1203 | int size; |
1203 | int size; |
1204 | 1204 | ||
1205 | if (IS_BROXTON(dev)) { |
1205 | if (IS_BROXTON(dev)) { |
1206 | *source_rates = bxt_rates; |
1206 | *source_rates = bxt_rates; |
1207 | size = ARRAY_SIZE(bxt_rates); |
1207 | size = ARRAY_SIZE(bxt_rates); |
1208 | } else if (IS_SKYLAKE(dev)) { |
1208 | } else if (IS_SKYLAKE(dev)) { |
1209 | *source_rates = skl_rates; |
1209 | *source_rates = skl_rates; |
1210 | size = ARRAY_SIZE(skl_rates); |
1210 | size = ARRAY_SIZE(skl_rates); |
1211 | } else { |
1211 | } else { |
1212 | *source_rates = default_rates; |
1212 | *source_rates = default_rates; |
1213 | size = ARRAY_SIZE(default_rates); |
1213 | size = ARRAY_SIZE(default_rates); |
1214 | } |
1214 | } |
1215 | 1215 | ||
1216 | /* This depends on the fact that 5.4 is last value in the array */ |
1216 | /* This depends on the fact that 5.4 is last value in the array */ |
1217 | if (!intel_dp_source_supports_hbr2(dev)) |
1217 | if (!intel_dp_source_supports_hbr2(dev)) |
1218 | size--; |
1218 | size--; |
1219 | 1219 | ||
1220 | return size; |
1220 | return size; |
1221 | } |
1221 | } |
1222 | 1222 | ||
1223 | static void |
1223 | static void |
1224 | intel_dp_set_clock(struct intel_encoder *encoder, |
1224 | intel_dp_set_clock(struct intel_encoder *encoder, |
1225 | struct intel_crtc_state *pipe_config) |
1225 | struct intel_crtc_state *pipe_config) |
1226 | { |
1226 | { |
1227 | struct drm_device *dev = encoder->base.dev; |
1227 | struct drm_device *dev = encoder->base.dev; |
1228 | const struct dp_link_dpll *divisor = NULL; |
1228 | const struct dp_link_dpll *divisor = NULL; |
1229 | int i, count = 0; |
1229 | int i, count = 0; |
1230 | 1230 | ||
1231 | if (IS_G4X(dev)) { |
1231 | if (IS_G4X(dev)) { |
1232 | divisor = gen4_dpll; |
1232 | divisor = gen4_dpll; |
1233 | count = ARRAY_SIZE(gen4_dpll); |
1233 | count = ARRAY_SIZE(gen4_dpll); |
1234 | } else if (HAS_PCH_SPLIT(dev)) { |
1234 | } else if (HAS_PCH_SPLIT(dev)) { |
1235 | divisor = pch_dpll; |
1235 | divisor = pch_dpll; |
1236 | count = ARRAY_SIZE(pch_dpll); |
1236 | count = ARRAY_SIZE(pch_dpll); |
1237 | } else if (IS_CHERRYVIEW(dev)) { |
1237 | } else if (IS_CHERRYVIEW(dev)) { |
1238 | divisor = chv_dpll; |
1238 | divisor = chv_dpll; |
1239 | count = ARRAY_SIZE(chv_dpll); |
1239 | count = ARRAY_SIZE(chv_dpll); |
1240 | } else if (IS_VALLEYVIEW(dev)) { |
1240 | } else if (IS_VALLEYVIEW(dev)) { |
1241 | divisor = vlv_dpll; |
1241 | divisor = vlv_dpll; |
1242 | count = ARRAY_SIZE(vlv_dpll); |
1242 | count = ARRAY_SIZE(vlv_dpll); |
1243 | } |
1243 | } |
1244 | 1244 | ||
1245 | if (divisor && count) { |
1245 | if (divisor && count) { |
1246 | for (i = 0; i < count; i++) { |
1246 | for (i = 0; i < count; i++) { |
1247 | if (pipe_config->port_clock == divisor[i].clock) { |
1247 | if (pipe_config->port_clock == divisor[i].clock) { |
1248 | pipe_config->dpll = divisor[i].dpll; |
1248 | pipe_config->dpll = divisor[i].dpll; |
1249 | pipe_config->clock_set = true; |
1249 | pipe_config->clock_set = true; |
1250 | break; |
1250 | break; |
1251 | } |
1251 | } |
1252 | } |
1252 | } |
1253 | } |
1253 | } |
1254 | } |
1254 | } |
1255 | 1255 | ||
1256 | static int intersect_rates(const int *source_rates, int source_len, |
1256 | static int intersect_rates(const int *source_rates, int source_len, |
1257 | const int *sink_rates, int sink_len, |
1257 | const int *sink_rates, int sink_len, |
1258 | int *common_rates) |
1258 | int *common_rates) |
1259 | { |
1259 | { |
1260 | int i = 0, j = 0, k = 0; |
1260 | int i = 0, j = 0, k = 0; |
1261 | 1261 | ||
1262 | while (i < source_len && j < sink_len) { |
1262 | while (i < source_len && j < sink_len) { |
1263 | if (source_rates[i] == sink_rates[j]) { |
1263 | if (source_rates[i] == sink_rates[j]) { |
1264 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1264 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1265 | return k; |
1265 | return k; |
1266 | common_rates[k] = source_rates[i]; |
1266 | common_rates[k] = source_rates[i]; |
1267 | ++k; |
1267 | ++k; |
1268 | ++i; |
1268 | ++i; |
1269 | ++j; |
1269 | ++j; |
1270 | } else if (source_rates[i] < sink_rates[j]) { |
1270 | } else if (source_rates[i] < sink_rates[j]) { |
1271 | ++i; |
1271 | ++i; |
1272 | } else { |
1272 | } else { |
1273 | ++j; |
1273 | ++j; |
1274 | } |
1274 | } |
1275 | } |
1275 | } |
1276 | return k; |
1276 | return k; |
1277 | } |
1277 | } |
1278 | 1278 | ||
1279 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1279 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1280 | int *common_rates) |
1280 | int *common_rates) |
1281 | { |
1281 | { |
1282 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1282 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1283 | const int *source_rates, *sink_rates; |
1283 | const int *source_rates, *sink_rates; |
1284 | int source_len, sink_len; |
1284 | int source_len, sink_len; |
1285 | 1285 | ||
1286 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1286 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1287 | source_len = intel_dp_source_rates(dev, &source_rates); |
1287 | source_len = intel_dp_source_rates(dev, &source_rates); |
1288 | 1288 | ||
1289 | return intersect_rates(source_rates, source_len, |
1289 | return intersect_rates(source_rates, source_len, |
1290 | sink_rates, sink_len, |
1290 | sink_rates, sink_len, |
1291 | common_rates); |
1291 | common_rates); |
1292 | } |
1292 | } |
1293 | 1293 | ||
1294 | static void snprintf_int_array(char *str, size_t len, |
1294 | static void snprintf_int_array(char *str, size_t len, |
1295 | const int *array, int nelem) |
1295 | const int *array, int nelem) |
1296 | { |
1296 | { |
1297 | int i; |
1297 | int i; |
1298 | 1298 | ||
1299 | str[0] = '\0'; |
1299 | str[0] = '\0'; |
1300 | 1300 | ||
1301 | for (i = 0; i < nelem; i++) { |
1301 | for (i = 0; i < nelem; i++) { |
1302 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1302 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
1303 | if (r >= len) |
1303 | if (r >= len) |
1304 | return; |
1304 | return; |
1305 | str += r; |
1305 | str += r; |
1306 | len -= r; |
1306 | len -= r; |
1307 | } |
1307 | } |
1308 | } |
1308 | } |
1309 | 1309 | ||
1310 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1310 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
1311 | { |
1311 | { |
1312 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1312 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1313 | const int *source_rates, *sink_rates; |
1313 | const int *source_rates, *sink_rates; |
1314 | int source_len, sink_len, common_len; |
1314 | int source_len, sink_len, common_len; |
1315 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1315 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
1316 | char str[128]; /* FIXME: too big for stack? */ |
1316 | char str[128]; /* FIXME: too big for stack? */ |
1317 | 1317 | ||
1318 | if ((drm_debug & DRM_UT_KMS) == 0) |
1318 | if ((drm_debug & DRM_UT_KMS) == 0) |
1319 | return; |
1319 | return; |
1320 | 1320 | ||
1321 | source_len = intel_dp_source_rates(dev, &source_rates); |
1321 | source_len = intel_dp_source_rates(dev, &source_rates); |
1322 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1322 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1323 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1323 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1324 | 1324 | ||
1325 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1325 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
1326 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1326 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
1327 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1327 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1328 | 1328 | ||
1329 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1329 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1330 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1330 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
1331 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1331 | DRM_DEBUG_KMS("common rates: %s\n", str); |
1332 | } |
1332 | } |
1333 | 1333 | ||
1334 | static int rate_to_index(int find, const int *rates) |
1334 | static int rate_to_index(int find, const int *rates) |
1335 | { |
1335 | { |
1336 | int i = 0; |
1336 | int i = 0; |
1337 | 1337 | ||
1338 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1338 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
1339 | if (find == rates[i]) |
1339 | if (find == rates[i]) |
1340 | break; |
1340 | break; |
1341 | 1341 | ||
1342 | return i; |
1342 | return i; |
1343 | } |
1343 | } |
1344 | 1344 | ||
1345 | int |
1345 | int |
1346 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1346 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
1347 | { |
1347 | { |
1348 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1348 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
1349 | int len; |
1349 | int len; |
1350 | 1350 | ||
1351 | len = intel_dp_common_rates(intel_dp, rates); |
1351 | len = intel_dp_common_rates(intel_dp, rates); |
1352 | if (WARN_ON(len <= 0)) |
1352 | if (WARN_ON(len <= 0)) |
1353 | return 162000; |
1353 | return 162000; |
1354 | 1354 | ||
1355 | return rates[rate_to_index(0, rates) - 1]; |
1355 | return rates[rate_to_index(0, rates) - 1]; |
1356 | } |
1356 | } |
1357 | 1357 | ||
1358 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1358 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1359 | { |
1359 | { |
1360 | return rate_to_index(rate, intel_dp->sink_rates); |
1360 | return rate_to_index(rate, intel_dp->sink_rates); |
1361 | } |
1361 | } |
1362 | 1362 | ||
1363 | static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1363 | static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1364 | uint8_t *link_bw, uint8_t *rate_select) |
1364 | uint8_t *link_bw, uint8_t *rate_select) |
1365 | { |
1365 | { |
1366 | if (intel_dp->num_sink_rates) { |
1366 | if (intel_dp->num_sink_rates) { |
1367 | *link_bw = 0; |
1367 | *link_bw = 0; |
1368 | *rate_select = |
1368 | *rate_select = |
1369 | intel_dp_rate_select(intel_dp, port_clock); |
1369 | intel_dp_rate_select(intel_dp, port_clock); |
1370 | } else { |
1370 | } else { |
1371 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1371 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
1372 | *rate_select = 0; |
1372 | *rate_select = 0; |
1373 | } |
1373 | } |
1374 | } |
1374 | } |
1375 | 1375 | ||
1376 | bool |
1376 | bool |
1377 | intel_dp_compute_config(struct intel_encoder *encoder, |
1377 | intel_dp_compute_config(struct intel_encoder *encoder, |
1378 | struct intel_crtc_state *pipe_config) |
1378 | struct intel_crtc_state *pipe_config) |
1379 | { |
1379 | { |
1380 | struct drm_device *dev = encoder->base.dev; |
1380 | struct drm_device *dev = encoder->base.dev; |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
1382 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1382 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1384 | enum port port = dp_to_dig_port(intel_dp)->port; |
1384 | enum port port = dp_to_dig_port(intel_dp)->port; |
1385 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1385 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
1386 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1386 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
1387 | int lane_count, clock; |
1387 | int lane_count, clock; |
1388 | int min_lane_count = 1; |
1388 | int min_lane_count = 1; |
1389 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1389 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
1390 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1390 | /* Conveniently, the link BW constants become indices with a shift...*/ |
1391 | int min_clock = 0; |
1391 | int min_clock = 0; |
1392 | int max_clock; |
1392 | int max_clock; |
1393 | int bpp, mode_rate; |
1393 | int bpp, mode_rate; |
1394 | int link_avail, link_clock; |
1394 | int link_avail, link_clock; |
1395 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1395 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1396 | int common_len; |
1396 | int common_len; |
1397 | uint8_t link_bw, rate_select; |
1397 | uint8_t link_bw, rate_select; |
1398 | 1398 | ||
1399 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1399 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1400 | 1400 | ||
1401 | /* No common link rates between source and sink */ |
1401 | /* No common link rates between source and sink */ |
1402 | WARN_ON(common_len <= 0); |
1402 | WARN_ON(common_len <= 0); |
1403 | 1403 | ||
1404 | max_clock = common_len - 1; |
1404 | max_clock = common_len - 1; |
1405 | 1405 | ||
1406 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1406 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
1407 | pipe_config->has_pch_encoder = true; |
1407 | pipe_config->has_pch_encoder = true; |
1408 | 1408 | ||
1409 | pipe_config->has_dp_encoder = true; |
1409 | pipe_config->has_dp_encoder = true; |
1410 | pipe_config->has_drrs = false; |
1410 | pipe_config->has_drrs = false; |
1411 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1411 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
1412 | 1412 | ||
1413 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1413 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1414 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1414 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
1415 | adjusted_mode); |
1415 | adjusted_mode); |
1416 | 1416 | ||
1417 | if (INTEL_INFO(dev)->gen >= 9) { |
1417 | if (INTEL_INFO(dev)->gen >= 9) { |
1418 | int ret; |
1418 | int ret; |
1419 | ret = skl_update_scaler_crtc(pipe_config); |
1419 | ret = skl_update_scaler_crtc(pipe_config); |
1420 | if (ret) |
1420 | if (ret) |
1421 | return ret; |
1421 | return ret; |
1422 | } |
1422 | } |
1423 | 1423 | ||
1424 | if (!HAS_PCH_SPLIT(dev)) |
1424 | if (!HAS_PCH_SPLIT(dev)) |
1425 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1425 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1426 | intel_connector->panel.fitting_mode); |
1426 | intel_connector->panel.fitting_mode); |
1427 | else |
1427 | else |
1428 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1428 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1429 | intel_connector->panel.fitting_mode); |
1429 | intel_connector->panel.fitting_mode); |
1430 | } |
1430 | } |
1431 | 1431 | ||
1432 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1432 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
1433 | return false; |
1433 | return false; |
1434 | 1434 | ||
1435 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1435 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1436 | "max bw %d pixel clock %iKHz\n", |
1436 | "max bw %d pixel clock %iKHz\n", |
1437 | max_lane_count, common_rates[max_clock], |
1437 | max_lane_count, common_rates[max_clock], |
1438 | adjusted_mode->crtc_clock); |
1438 | adjusted_mode->crtc_clock); |
1439 | 1439 | ||
1440 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1440 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1441 | * bpc in between. */ |
1441 | * bpc in between. */ |
1442 | bpp = pipe_config->pipe_bpp; |
1442 | bpp = pipe_config->pipe_bpp; |
1443 | if (is_edp(intel_dp)) { |
1443 | if (is_edp(intel_dp)) { |
1444 | 1444 | ||
1445 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1445 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
1446 | if (intel_connector->base.display_info.bpc == 0 && |
1446 | if (intel_connector->base.display_info.bpc == 0 && |
1447 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1447 | (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) { |
1448 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1448 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
1449 | dev_priv->vbt.edp_bpp); |
1449 | dev_priv->vbt.edp_bpp); |
1450 | bpp = dev_priv->vbt.edp_bpp; |
1450 | bpp = dev_priv->vbt.edp_bpp; |
1451 | } |
1451 | } |
1452 | 1452 | ||
1453 | /* |
1453 | /* |
1454 | * Use the maximum clock and number of lanes the eDP panel |
1454 | * Use the maximum clock and number of lanes the eDP panel |
1455 | * advertizes being capable of. The panels are generally |
1455 | * advertizes being capable of. The panels are generally |
1456 | * designed to support only a single clock and lane |
1456 | * designed to support only a single clock and lane |
1457 | * configuration, and typically these values correspond to the |
1457 | * configuration, and typically these values correspond to the |
1458 | * native resolution of the panel. |
1458 | * native resolution of the panel. |
1459 | */ |
1459 | */ |
1460 | min_lane_count = max_lane_count; |
1460 | min_lane_count = max_lane_count; |
1461 | min_clock = max_clock; |
1461 | min_clock = max_clock; |
1462 | } |
1462 | } |
1463 | 1463 | ||
1464 | for (; bpp >= 6*3; bpp -= 2*3) { |
1464 | for (; bpp >= 6*3; bpp -= 2*3) { |
1465 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1465 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1466 | bpp); |
1466 | bpp); |
1467 | 1467 | ||
1468 | for (clock = min_clock; clock <= max_clock; clock++) { |
1468 | for (clock = min_clock; clock <= max_clock; clock++) { |
1469 | for (lane_count = min_lane_count; |
1469 | for (lane_count = min_lane_count; |
1470 | lane_count <= max_lane_count; |
1470 | lane_count <= max_lane_count; |
1471 | lane_count <<= 1) { |
1471 | lane_count <<= 1) { |
1472 | 1472 | ||
1473 | link_clock = common_rates[clock]; |
1473 | link_clock = common_rates[clock]; |
1474 | link_avail = intel_dp_max_data_rate(link_clock, |
1474 | link_avail = intel_dp_max_data_rate(link_clock, |
1475 | lane_count); |
1475 | lane_count); |
1476 | 1476 | ||
1477 | if (mode_rate <= link_avail) { |
1477 | if (mode_rate <= link_avail) { |
1478 | goto found; |
1478 | goto found; |
1479 | } |
1479 | } |
1480 | } |
1480 | } |
1481 | } |
1481 | } |
1482 | } |
1482 | } |
1483 | 1483 | ||
1484 | return false; |
1484 | return false; |
1485 | 1485 | ||
1486 | found: |
1486 | found: |
1487 | if (intel_dp->color_range_auto) { |
1487 | if (intel_dp->color_range_auto) { |
1488 | /* |
1488 | /* |
1489 | * See: |
1489 | * See: |
1490 | * CEA-861-E - 5.1 Default Encoding Parameters |
1490 | * CEA-861-E - 5.1 Default Encoding Parameters |
1491 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1491 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
1492 | */ |
1492 | */ |
1493 | pipe_config->limited_color_range = |
1493 | pipe_config->limited_color_range = |
1494 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1494 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
1495 | } else { |
1495 | } else { |
1496 | pipe_config->limited_color_range = |
1496 | pipe_config->limited_color_range = |
1497 | intel_dp->limited_color_range; |
1497 | intel_dp->limited_color_range; |
1498 | } |
1498 | } |
1499 | 1499 | ||
1500 | pipe_config->lane_count = lane_count; |
1500 | pipe_config->lane_count = lane_count; |
1501 | 1501 | ||
1502 | pipe_config->pipe_bpp = bpp; |
1502 | pipe_config->pipe_bpp = bpp; |
1503 | pipe_config->port_clock = common_rates[clock]; |
1503 | pipe_config->port_clock = common_rates[clock]; |
1504 | 1504 | ||
1505 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1505 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1506 | &link_bw, &rate_select); |
1506 | &link_bw, &rate_select); |
1507 | 1507 | ||
1508 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1508 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
1509 | link_bw, rate_select, pipe_config->lane_count, |
1509 | link_bw, rate_select, pipe_config->lane_count, |
1510 | pipe_config->port_clock, bpp); |
1510 | pipe_config->port_clock, bpp); |
1511 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1511 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1512 | mode_rate, link_avail); |
1512 | mode_rate, link_avail); |
1513 | 1513 | ||
1514 | intel_link_compute_m_n(bpp, lane_count, |
1514 | intel_link_compute_m_n(bpp, lane_count, |
1515 | adjusted_mode->crtc_clock, |
1515 | adjusted_mode->crtc_clock, |
1516 | pipe_config->port_clock, |
1516 | pipe_config->port_clock, |
1517 | &pipe_config->dp_m_n); |
1517 | &pipe_config->dp_m_n); |
1518 | 1518 | ||
1519 | if (intel_connector->panel.downclock_mode != NULL && |
1519 | if (intel_connector->panel.downclock_mode != NULL && |
1520 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1520 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
1521 | pipe_config->has_drrs = true; |
1521 | pipe_config->has_drrs = true; |
1522 | intel_link_compute_m_n(bpp, lane_count, |
1522 | intel_link_compute_m_n(bpp, lane_count, |
1523 | intel_connector->panel.downclock_mode->clock, |
1523 | intel_connector->panel.downclock_mode->clock, |
1524 | pipe_config->port_clock, |
1524 | pipe_config->port_clock, |
1525 | &pipe_config->dp_m2_n2); |
1525 | &pipe_config->dp_m2_n2); |
1526 | } |
1526 | } |
1527 | 1527 | ||
1528 | if (IS_SKYLAKE(dev) && is_edp(intel_dp)) |
1528 | if (IS_SKYLAKE(dev) && is_edp(intel_dp)) |
1529 | skl_edp_set_pll_config(pipe_config); |
1529 | skl_edp_set_pll_config(pipe_config); |
1530 | else if (IS_BROXTON(dev)) |
1530 | else if (IS_BROXTON(dev)) |
1531 | /* handled in ddi */; |
1531 | /* handled in ddi */; |
1532 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1532 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1533 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1533 | hsw_dp_set_ddi_pll_sel(pipe_config); |
1534 | else |
1534 | else |
1535 | intel_dp_set_clock(encoder, pipe_config); |
1535 | intel_dp_set_clock(encoder, pipe_config); |
1536 | 1536 | ||
1537 | return true; |
1537 | return true; |
1538 | } |
1538 | } |
1539 | 1539 | ||
1540 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
1540 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
1541 | { |
1541 | { |
1542 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1542 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1543 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
1543 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
1544 | struct drm_device *dev = crtc->base.dev; |
1544 | struct drm_device *dev = crtc->base.dev; |
1545 | struct drm_i915_private *dev_priv = dev->dev_private; |
1545 | struct drm_i915_private *dev_priv = dev->dev_private; |
1546 | u32 dpa_ctl; |
1546 | u32 dpa_ctl; |
1547 | 1547 | ||
1548 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", |
1548 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", |
1549 | crtc->config->port_clock); |
1549 | crtc->config->port_clock); |
1550 | dpa_ctl = I915_READ(DP_A); |
1550 | dpa_ctl = I915_READ(DP_A); |
1551 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
1551 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
1552 | 1552 | ||
1553 | if (crtc->config->port_clock == 162000) { |
1553 | if (crtc->config->port_clock == 162000) { |
1554 | /* For a long time we've carried around a ILK-DevA w/a for the |
1554 | /* For a long time we've carried around a ILK-DevA w/a for the |
1555 | * 160MHz clock. If we're really unlucky, it's still required. |
1555 | * 160MHz clock. If we're really unlucky, it's still required. |
1556 | */ |
1556 | */ |
1557 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
1557 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
1558 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
1558 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
1559 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
1559 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
1560 | } else { |
1560 | } else { |
1561 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
1561 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
1562 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
1562 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
1563 | } |
1563 | } |
1564 | 1564 | ||
1565 | I915_WRITE(DP_A, dpa_ctl); |
1565 | I915_WRITE(DP_A, dpa_ctl); |
1566 | 1566 | ||
1567 | POSTING_READ(DP_A); |
1567 | POSTING_READ(DP_A); |
1568 | udelay(500); |
1568 | udelay(500); |
1569 | } |
1569 | } |
1570 | 1570 | ||
1571 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1571 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1572 | const struct intel_crtc_state *pipe_config) |
1572 | const struct intel_crtc_state *pipe_config) |
1573 | { |
1573 | { |
1574 | intel_dp->link_rate = pipe_config->port_clock; |
1574 | intel_dp->link_rate = pipe_config->port_clock; |
1575 | intel_dp->lane_count = pipe_config->lane_count; |
1575 | intel_dp->lane_count = pipe_config->lane_count; |
1576 | } |
1576 | } |
1577 | 1577 | ||
1578 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1578 | static void intel_dp_prepare(struct intel_encoder *encoder) |
1579 | { |
1579 | { |
1580 | struct drm_device *dev = encoder->base.dev; |
1580 | struct drm_device *dev = encoder->base.dev; |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; |
1582 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1582 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1583 | enum port port = dp_to_dig_port(intel_dp)->port; |
1583 | enum port port = dp_to_dig_port(intel_dp)->port; |
1584 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1584 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1585 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1585 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
1586 | 1586 | ||
1587 | intel_dp_set_link_params(intel_dp, crtc->config); |
1587 | intel_dp_set_link_params(intel_dp, crtc->config); |
1588 | 1588 | ||
1589 | /* |
1589 | /* |
1590 | * There are four kinds of DP registers: |
1590 | * There are four kinds of DP registers: |
1591 | * |
1591 | * |
1592 | * IBX PCH |
1592 | * IBX PCH |
1593 | * SNB CPU |
1593 | * SNB CPU |
1594 | * IVB CPU |
1594 | * IVB CPU |
1595 | * CPT PCH |
1595 | * CPT PCH |
1596 | * |
1596 | * |
1597 | * IBX PCH and CPU are the same for almost everything, |
1597 | * IBX PCH and CPU are the same for almost everything, |
1598 | * except that the CPU DP PLL is configured in this |
1598 | * except that the CPU DP PLL is configured in this |
1599 | * register |
1599 | * register |
1600 | * |
1600 | * |
1601 | * CPT PCH is quite different, having many bits moved |
1601 | * CPT PCH is quite different, having many bits moved |
1602 | * to the TRANS_DP_CTL register instead. That |
1602 | * to the TRANS_DP_CTL register instead. That |
1603 | * configuration happens (oddly) in ironlake_pch_enable |
1603 | * configuration happens (oddly) in ironlake_pch_enable |
1604 | */ |
1604 | */ |
1605 | 1605 | ||
1606 | /* Preserve the BIOS-computed detected bit. This is |
1606 | /* Preserve the BIOS-computed detected bit. This is |
1607 | * supposed to be read-only. |
1607 | * supposed to be read-only. |
1608 | */ |
1608 | */ |
1609 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1609 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
1610 | 1610 | ||
1611 | /* Handle DP bits in common between all three register formats */ |
1611 | /* Handle DP bits in common between all three register formats */ |
1612 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1612 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
1613 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1613 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
1614 | 1614 | ||
1615 | if (crtc->config->has_audio) |
1615 | if (crtc->config->has_audio) |
1616 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
1616 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
1617 | 1617 | ||
1618 | /* Split out the IBX/CPU vs CPT settings */ |
1618 | /* Split out the IBX/CPU vs CPT settings */ |
1619 | 1619 | ||
1620 | if (IS_GEN7(dev) && port == PORT_A) { |
1620 | if (IS_GEN7(dev) && port == PORT_A) { |
1621 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1621 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1622 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1622 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1623 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1623 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1624 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1624 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1625 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1625 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1626 | 1626 | ||
1627 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1627 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1628 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1628 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1629 | 1629 | ||
1630 | intel_dp->DP |= crtc->pipe << 29; |
1630 | intel_dp->DP |= crtc->pipe << 29; |
1631 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1631 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
1632 | u32 trans_dp; |
1632 | u32 trans_dp; |
1633 | 1633 | ||
1634 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1634 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
1635 | 1635 | ||
1636 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1636 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
1637 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1637 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1638 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1638 | trans_dp |= TRANS_DP_ENH_FRAMING; |
1639 | else |
1639 | else |
1640 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1640 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
1641 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1641 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
1642 | } else { |
1642 | } else { |
1643 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1643 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
1644 | crtc->config->limited_color_range) |
1644 | crtc->config->limited_color_range) |
1645 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1645 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
1646 | 1646 | ||
1647 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1647 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1648 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1648 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
1649 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1649 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
1650 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1650 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
1651 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1651 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
1652 | 1652 | ||
1653 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1653 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1654 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1654 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1655 | 1655 | ||
1656 | if (IS_CHERRYVIEW(dev)) |
1656 | if (IS_CHERRYVIEW(dev)) |
1657 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1657 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
1658 | else if (crtc->pipe == PIPE_B) |
1658 | else if (crtc->pipe == PIPE_B) |
1659 | intel_dp->DP |= DP_PIPEB_SELECT; |
1659 | intel_dp->DP |= DP_PIPEB_SELECT; |
1660 | } |
1660 | } |
1661 | } |
1661 | } |
1662 | 1662 | ||
1663 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1663 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1664 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1664 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
1665 | 1665 | ||
1666 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1666 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1667 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1667 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
1668 | 1668 | ||
1669 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1669 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1670 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1670 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
1671 | 1671 | ||
1672 | static void wait_panel_status(struct intel_dp *intel_dp, |
1672 | static void wait_panel_status(struct intel_dp *intel_dp, |
1673 | u32 mask, |
1673 | u32 mask, |
1674 | u32 value) |
1674 | u32 value) |
1675 | { |
1675 | { |
1676 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1676 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; |
1678 | u32 pp_stat_reg, pp_ctrl_reg; |
1678 | u32 pp_stat_reg, pp_ctrl_reg; |
1679 | 1679 | ||
1680 | lockdep_assert_held(&dev_priv->pps_mutex); |
1680 | lockdep_assert_held(&dev_priv->pps_mutex); |
1681 | 1681 | ||
1682 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1682 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1683 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1683 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1684 | 1684 | ||
1685 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1685 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
1686 | mask, value, |
1686 | mask, value, |
1687 | I915_READ(pp_stat_reg), |
1687 | I915_READ(pp_stat_reg), |
1688 | I915_READ(pp_ctrl_reg)); |
1688 | I915_READ(pp_ctrl_reg)); |
1689 | 1689 | ||
1690 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1690 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
1691 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1691 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
1692 | I915_READ(pp_stat_reg), |
1692 | I915_READ(pp_stat_reg), |
1693 | I915_READ(pp_ctrl_reg)); |
1693 | I915_READ(pp_ctrl_reg)); |
1694 | } |
1694 | } |
1695 | 1695 | ||
1696 | DRM_DEBUG_KMS("Wait complete\n"); |
1696 | DRM_DEBUG_KMS("Wait complete\n"); |
1697 | } |
1697 | } |
1698 | 1698 | ||
1699 | static void wait_panel_on(struct intel_dp *intel_dp) |
1699 | static void wait_panel_on(struct intel_dp *intel_dp) |
1700 | { |
1700 | { |
1701 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1701 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
1702 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1702 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
1703 | } |
1703 | } |
1704 | 1704 | ||
1705 | static void wait_panel_off(struct intel_dp *intel_dp) |
1705 | static void wait_panel_off(struct intel_dp *intel_dp) |
1706 | { |
1706 | { |
1707 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1707 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
1708 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1708 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
1709 | } |
1709 | } |
1710 | 1710 | ||
1711 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1711 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
1712 | { |
1712 | { |
1713 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1713 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
1714 | 1714 | ||
1715 | /* When we disable the VDD override bit last we have to do the manual |
1715 | /* When we disable the VDD override bit last we have to do the manual |
1716 | * wait. */ |
1716 | * wait. */ |
1717 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1717 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
1718 | intel_dp->panel_power_cycle_delay); |
1718 | intel_dp->panel_power_cycle_delay); |
1719 | 1719 | ||
1720 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1720 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
1721 | } |
1721 | } |
1722 | 1722 | ||
1723 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1723 | static void wait_backlight_on(struct intel_dp *intel_dp) |
1724 | { |
1724 | { |
1725 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1725 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
1726 | intel_dp->backlight_on_delay); |
1726 | intel_dp->backlight_on_delay); |
1727 | } |
1727 | } |
1728 | 1728 | ||
1729 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1729 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
1730 | { |
1730 | { |
1731 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1731 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
1732 | intel_dp->backlight_off_delay); |
1732 | intel_dp->backlight_off_delay); |
1733 | } |
1733 | } |
1734 | 1734 | ||
1735 | /* Read the current pp_control value, unlocking the register if it |
1735 | /* Read the current pp_control value, unlocking the register if it |
1736 | * is locked |
1736 | * is locked |
1737 | */ |
1737 | */ |
1738 | 1738 | ||
1739 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1739 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
1740 | { |
1740 | { |
1741 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1741 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
1743 | u32 control; |
1743 | u32 control; |
1744 | 1744 | ||
1745 | lockdep_assert_held(&dev_priv->pps_mutex); |
1745 | lockdep_assert_held(&dev_priv->pps_mutex); |
1746 | 1746 | ||
1747 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1747 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
1748 | if (!IS_BROXTON(dev)) { |
1748 | if (!IS_BROXTON(dev)) { |
1749 | control &= ~PANEL_UNLOCK_MASK; |
1749 | control &= ~PANEL_UNLOCK_MASK; |
1750 | control |= PANEL_UNLOCK_REGS; |
1750 | control |= PANEL_UNLOCK_REGS; |
1751 | } |
1751 | } |
1752 | return control; |
1752 | return control; |
1753 | } |
1753 | } |
1754 | 1754 | ||
1755 | /* |
1755 | /* |
1756 | * Must be paired with edp_panel_vdd_off(). |
1756 | * Must be paired with edp_panel_vdd_off(). |
1757 | * Must hold pps_mutex around the whole on/off sequence. |
1757 | * Must hold pps_mutex around the whole on/off sequence. |
1758 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1758 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1759 | */ |
1759 | */ |
1760 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1760 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
1761 | { |
1761 | { |
1762 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1762 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1763 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1763 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1764 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1764 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; |
1766 | enum intel_display_power_domain power_domain; |
1766 | enum intel_display_power_domain power_domain; |
1767 | u32 pp; |
1767 | u32 pp; |
1768 | u32 pp_stat_reg, pp_ctrl_reg; |
1768 | u32 pp_stat_reg, pp_ctrl_reg; |
1769 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1769 | bool need_to_disable = !intel_dp->want_panel_vdd; |
1770 | 1770 | ||
1771 | lockdep_assert_held(&dev_priv->pps_mutex); |
1771 | lockdep_assert_held(&dev_priv->pps_mutex); |
1772 | 1772 | ||
1773 | if (!is_edp(intel_dp)) |
1773 | if (!is_edp(intel_dp)) |
1774 | return false; |
1774 | return false; |
1775 | 1775 | ||
1776 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
1776 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
1777 | intel_dp->want_panel_vdd = true; |
1777 | intel_dp->want_panel_vdd = true; |
1778 | 1778 | ||
1779 | if (edp_have_panel_vdd(intel_dp)) |
1779 | if (edp_have_panel_vdd(intel_dp)) |
1780 | return need_to_disable; |
1780 | return need_to_disable; |
1781 | 1781 | ||
1782 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1782 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1783 | intel_display_power_get(dev_priv, power_domain); |
1783 | intel_display_power_get(dev_priv, power_domain); |
1784 | 1784 | ||
1785 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1785 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1786 | port_name(intel_dig_port->port)); |
1786 | port_name(intel_dig_port->port)); |
1787 | 1787 | ||
1788 | if (!edp_have_panel_power(intel_dp)) |
1788 | if (!edp_have_panel_power(intel_dp)) |
1789 | wait_panel_power_cycle(intel_dp); |
1789 | wait_panel_power_cycle(intel_dp); |
1790 | 1790 | ||
1791 | pp = ironlake_get_pp_control(intel_dp); |
1791 | pp = ironlake_get_pp_control(intel_dp); |
1792 | pp |= EDP_FORCE_VDD; |
1792 | pp |= EDP_FORCE_VDD; |
1793 | 1793 | ||
1794 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1794 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1795 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1795 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1796 | 1796 | ||
1797 | I915_WRITE(pp_ctrl_reg, pp); |
1797 | I915_WRITE(pp_ctrl_reg, pp); |
1798 | POSTING_READ(pp_ctrl_reg); |
1798 | POSTING_READ(pp_ctrl_reg); |
1799 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1799 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1800 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1800 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1801 | /* |
1801 | /* |
1802 | * If the panel wasn't on, delay before accessing aux channel |
1802 | * If the panel wasn't on, delay before accessing aux channel |
1803 | */ |
1803 | */ |
1804 | if (!edp_have_panel_power(intel_dp)) { |
1804 | if (!edp_have_panel_power(intel_dp)) { |
1805 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1805 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1806 | port_name(intel_dig_port->port)); |
1806 | port_name(intel_dig_port->port)); |
1807 | msleep(intel_dp->panel_power_up_delay); |
1807 | msleep(intel_dp->panel_power_up_delay); |
1808 | } |
1808 | } |
1809 | 1809 | ||
1810 | return need_to_disable; |
1810 | return need_to_disable; |
1811 | } |
1811 | } |
1812 | 1812 | ||
1813 | /* |
1813 | /* |
1814 | * Must be paired with intel_edp_panel_vdd_off() or |
1814 | * Must be paired with intel_edp_panel_vdd_off() or |
1815 | * intel_edp_panel_off(). |
1815 | * intel_edp_panel_off(). |
1816 | * Nested calls to these functions are not allowed since |
1816 | * Nested calls to these functions are not allowed since |
1817 | * we drop the lock. Caller must use some higher level |
1817 | * we drop the lock. Caller must use some higher level |
1818 | * locking to prevent nested calls from other threads. |
1818 | * locking to prevent nested calls from other threads. |
1819 | */ |
1819 | */ |
1820 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1820 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
1821 | { |
1821 | { |
1822 | bool vdd; |
1822 | bool vdd; |
1823 | 1823 | ||
1824 | if (!is_edp(intel_dp)) |
1824 | if (!is_edp(intel_dp)) |
1825 | return; |
1825 | return; |
1826 | 1826 | ||
1827 | pps_lock(intel_dp); |
1827 | pps_lock(intel_dp); |
1828 | vdd = edp_panel_vdd_on(intel_dp); |
1828 | vdd = edp_panel_vdd_on(intel_dp); |
1829 | pps_unlock(intel_dp); |
1829 | pps_unlock(intel_dp); |
1830 | 1830 | ||
1831 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1831 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
1832 | port_name(dp_to_dig_port(intel_dp)->port)); |
1832 | port_name(dp_to_dig_port(intel_dp)->port)); |
1833 | } |
1833 | } |
1834 | 1834 | ||
1835 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1835 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
1836 | { |
1836 | { |
1837 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1837 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1838 | struct drm_i915_private *dev_priv = dev->dev_private; |
1838 | struct drm_i915_private *dev_priv = dev->dev_private; |
1839 | struct intel_digital_port *intel_dig_port = |
1839 | struct intel_digital_port *intel_dig_port = |
1840 | dp_to_dig_port(intel_dp); |
1840 | dp_to_dig_port(intel_dp); |
1841 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1841 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1842 | enum intel_display_power_domain power_domain; |
1842 | enum intel_display_power_domain power_domain; |
1843 | u32 pp; |
1843 | u32 pp; |
1844 | u32 pp_stat_reg, pp_ctrl_reg; |
1844 | u32 pp_stat_reg, pp_ctrl_reg; |
1845 | 1845 | ||
1846 | lockdep_assert_held(&dev_priv->pps_mutex); |
1846 | lockdep_assert_held(&dev_priv->pps_mutex); |
1847 | 1847 | ||
1848 | WARN_ON(intel_dp->want_panel_vdd); |
1848 | WARN_ON(intel_dp->want_panel_vdd); |
1849 | 1849 | ||
1850 | if (!edp_have_panel_vdd(intel_dp)) |
1850 | if (!edp_have_panel_vdd(intel_dp)) |
1851 | return; |
1851 | return; |
1852 | 1852 | ||
1853 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1853 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1854 | port_name(intel_dig_port->port)); |
1854 | port_name(intel_dig_port->port)); |
1855 | 1855 | ||
1856 | pp = ironlake_get_pp_control(intel_dp); |
1856 | pp = ironlake_get_pp_control(intel_dp); |
1857 | pp &= ~EDP_FORCE_VDD; |
1857 | pp &= ~EDP_FORCE_VDD; |
1858 | 1858 | ||
1859 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1859 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1860 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1860 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1861 | 1861 | ||
1862 | I915_WRITE(pp_ctrl_reg, pp); |
1862 | I915_WRITE(pp_ctrl_reg, pp); |
1863 | POSTING_READ(pp_ctrl_reg); |
1863 | POSTING_READ(pp_ctrl_reg); |
1864 | 1864 | ||
1865 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1865 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1866 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1866 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
1867 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1867 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
1868 | 1868 | ||
1869 | if ((pp & POWER_TARGET_ON) == 0) |
1869 | if ((pp & POWER_TARGET_ON) == 0) |
1870 | intel_dp->last_power_cycle = jiffies; |
1870 | intel_dp->last_power_cycle = jiffies; |
1871 | 1871 | ||
1872 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1872 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1873 | intel_display_power_put(dev_priv, power_domain); |
1873 | intel_display_power_put(dev_priv, power_domain); |
1874 | } |
1874 | } |
1875 | 1875 | ||
1876 | static void edp_panel_vdd_work(struct work_struct *__work) |
1876 | static void edp_panel_vdd_work(struct work_struct *__work) |
1877 | { |
1877 | { |
1878 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1878 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
1879 | struct intel_dp, panel_vdd_work); |
1879 | struct intel_dp, panel_vdd_work); |
1880 | 1880 | ||
1881 | pps_lock(intel_dp); |
1881 | pps_lock(intel_dp); |
1882 | if (!intel_dp->want_panel_vdd) |
1882 | if (!intel_dp->want_panel_vdd) |
1883 | edp_panel_vdd_off_sync(intel_dp); |
1883 | edp_panel_vdd_off_sync(intel_dp); |
1884 | pps_unlock(intel_dp); |
1884 | pps_unlock(intel_dp); |
1885 | } |
1885 | } |
1886 | 1886 | ||
1887 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1887 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1888 | { |
1888 | { |
1889 | unsigned long delay; |
1889 | unsigned long delay; |
1890 | 1890 | ||
1891 | /* |
1891 | /* |
1892 | * Queue the timer to fire a long time from now (relative to the power |
1892 | * Queue the timer to fire a long time from now (relative to the power |
1893 | * down delay) to keep the panel power up across a sequence of |
1893 | * down delay) to keep the panel power up across a sequence of |
1894 | * operations. |
1894 | * operations. |
1895 | */ |
1895 | */ |
1896 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1896 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
1897 | // schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1897 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
1898 | } |
1898 | } |
1899 | 1899 | ||
1900 | /* |
1900 | /* |
1901 | * Must be paired with edp_panel_vdd_on(). |
1901 | * Must be paired with edp_panel_vdd_on(). |
1902 | * Must hold pps_mutex around the whole on/off sequence. |
1902 | * Must hold pps_mutex around the whole on/off sequence. |
1903 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1903 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
1904 | */ |
1904 | */ |
1905 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1905 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
1906 | { |
1906 | { |
1907 | struct drm_i915_private *dev_priv = |
1907 | struct drm_i915_private *dev_priv = |
1908 | intel_dp_to_dev(intel_dp)->dev_private; |
1908 | intel_dp_to_dev(intel_dp)->dev_private; |
1909 | 1909 | ||
1910 | lockdep_assert_held(&dev_priv->pps_mutex); |
1910 | lockdep_assert_held(&dev_priv->pps_mutex); |
1911 | 1911 | ||
1912 | if (!is_edp(intel_dp)) |
1912 | if (!is_edp(intel_dp)) |
1913 | return; |
1913 | return; |
1914 | 1914 | ||
1915 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
1915 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
1916 | port_name(dp_to_dig_port(intel_dp)->port)); |
1916 | port_name(dp_to_dig_port(intel_dp)->port)); |
1917 | 1917 | ||
1918 | intel_dp->want_panel_vdd = false; |
1918 | intel_dp->want_panel_vdd = false; |
1919 | 1919 | ||
1920 | if (sync) |
1920 | if (sync) |
1921 | edp_panel_vdd_off_sync(intel_dp); |
1921 | edp_panel_vdd_off_sync(intel_dp); |
1922 | else |
1922 | else |
1923 | edp_panel_vdd_schedule_off(intel_dp); |
1923 | edp_panel_vdd_schedule_off(intel_dp); |
1924 | } |
1924 | } |
1925 | 1925 | ||
1926 | static void edp_panel_on(struct intel_dp *intel_dp) |
1926 | static void edp_panel_on(struct intel_dp *intel_dp) |
1927 | { |
1927 | { |
1928 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1928 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; |
1930 | u32 pp; |
1930 | u32 pp; |
1931 | u32 pp_ctrl_reg; |
1931 | u32 pp_ctrl_reg; |
1932 | 1932 | ||
1933 | lockdep_assert_held(&dev_priv->pps_mutex); |
1933 | lockdep_assert_held(&dev_priv->pps_mutex); |
1934 | 1934 | ||
1935 | if (!is_edp(intel_dp)) |
1935 | if (!is_edp(intel_dp)) |
1936 | return; |
1936 | return; |
1937 | 1937 | ||
1938 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1938 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1939 | port_name(dp_to_dig_port(intel_dp)->port)); |
1939 | port_name(dp_to_dig_port(intel_dp)->port)); |
1940 | 1940 | ||
1941 | if (WARN(edp_have_panel_power(intel_dp), |
1941 | if (WARN(edp_have_panel_power(intel_dp), |
1942 | "eDP port %c panel power already on\n", |
1942 | "eDP port %c panel power already on\n", |
1943 | port_name(dp_to_dig_port(intel_dp)->port))) |
1943 | port_name(dp_to_dig_port(intel_dp)->port))) |
1944 | return; |
1944 | return; |
1945 | 1945 | ||
1946 | wait_panel_power_cycle(intel_dp); |
1946 | wait_panel_power_cycle(intel_dp); |
1947 | 1947 | ||
1948 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1948 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1949 | pp = ironlake_get_pp_control(intel_dp); |
1949 | pp = ironlake_get_pp_control(intel_dp); |
1950 | if (IS_GEN5(dev)) { |
1950 | if (IS_GEN5(dev)) { |
1951 | /* ILK workaround: disable reset around power sequence */ |
1951 | /* ILK workaround: disable reset around power sequence */ |
1952 | pp &= ~PANEL_POWER_RESET; |
1952 | pp &= ~PANEL_POWER_RESET; |
1953 | I915_WRITE(pp_ctrl_reg, pp); |
1953 | I915_WRITE(pp_ctrl_reg, pp); |
1954 | POSTING_READ(pp_ctrl_reg); |
1954 | POSTING_READ(pp_ctrl_reg); |
1955 | } |
1955 | } |
1956 | 1956 | ||
1957 | pp |= POWER_TARGET_ON; |
1957 | pp |= POWER_TARGET_ON; |
1958 | if (!IS_GEN5(dev)) |
1958 | if (!IS_GEN5(dev)) |
1959 | pp |= PANEL_POWER_RESET; |
1959 | pp |= PANEL_POWER_RESET; |
1960 | 1960 | ||
1961 | I915_WRITE(pp_ctrl_reg, pp); |
1961 | I915_WRITE(pp_ctrl_reg, pp); |
1962 | POSTING_READ(pp_ctrl_reg); |
1962 | POSTING_READ(pp_ctrl_reg); |
1963 | 1963 | ||
1964 | wait_panel_on(intel_dp); |
1964 | wait_panel_on(intel_dp); |
1965 | intel_dp->last_power_on = jiffies; |
1965 | intel_dp->last_power_on = jiffies; |
1966 | 1966 | ||
1967 | if (IS_GEN5(dev)) { |
1967 | if (IS_GEN5(dev)) { |
1968 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1968 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1969 | I915_WRITE(pp_ctrl_reg, pp); |
1969 | I915_WRITE(pp_ctrl_reg, pp); |
1970 | POSTING_READ(pp_ctrl_reg); |
1970 | POSTING_READ(pp_ctrl_reg); |
1971 | } |
1971 | } |
1972 | } |
1972 | } |
1973 | 1973 | ||
1974 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1974 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1975 | { |
1975 | { |
1976 | if (!is_edp(intel_dp)) |
1976 | if (!is_edp(intel_dp)) |
1977 | return; |
1977 | return; |
1978 | 1978 | ||
1979 | pps_lock(intel_dp); |
1979 | pps_lock(intel_dp); |
1980 | edp_panel_on(intel_dp); |
1980 | edp_panel_on(intel_dp); |
1981 | pps_unlock(intel_dp); |
1981 | pps_unlock(intel_dp); |
1982 | } |
1982 | } |
1983 | 1983 | ||
1984 | 1984 | ||
1985 | static void edp_panel_off(struct intel_dp *intel_dp) |
1985 | static void edp_panel_off(struct intel_dp *intel_dp) |
1986 | { |
1986 | { |
1987 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1987 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1988 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1988 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
1989 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1989 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1990 | struct drm_i915_private *dev_priv = dev->dev_private; |
1990 | struct drm_i915_private *dev_priv = dev->dev_private; |
1991 | enum intel_display_power_domain power_domain; |
1991 | enum intel_display_power_domain power_domain; |
1992 | u32 pp; |
1992 | u32 pp; |
1993 | u32 pp_ctrl_reg; |
1993 | u32 pp_ctrl_reg; |
1994 | 1994 | ||
1995 | lockdep_assert_held(&dev_priv->pps_mutex); |
1995 | lockdep_assert_held(&dev_priv->pps_mutex); |
1996 | 1996 | ||
1997 | if (!is_edp(intel_dp)) |
1997 | if (!is_edp(intel_dp)) |
1998 | return; |
1998 | return; |
1999 | 1999 | ||
2000 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2000 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2001 | port_name(dp_to_dig_port(intel_dp)->port)); |
2001 | port_name(dp_to_dig_port(intel_dp)->port)); |
2002 | 2002 | ||
2003 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2003 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2004 | port_name(dp_to_dig_port(intel_dp)->port)); |
2004 | port_name(dp_to_dig_port(intel_dp)->port)); |
2005 | 2005 | ||
2006 | pp = ironlake_get_pp_control(intel_dp); |
2006 | pp = ironlake_get_pp_control(intel_dp); |
2007 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2007 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2008 | * panels get very unhappy and cease to work. */ |
2008 | * panels get very unhappy and cease to work. */ |
2009 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2009 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2010 | EDP_BLC_ENABLE); |
2010 | EDP_BLC_ENABLE); |
2011 | 2011 | ||
2012 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2012 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2013 | 2013 | ||
2014 | intel_dp->want_panel_vdd = false; |
2014 | intel_dp->want_panel_vdd = false; |
2015 | 2015 | ||
2016 | I915_WRITE(pp_ctrl_reg, pp); |
2016 | I915_WRITE(pp_ctrl_reg, pp); |
2017 | POSTING_READ(pp_ctrl_reg); |
2017 | POSTING_READ(pp_ctrl_reg); |
2018 | 2018 | ||
2019 | intel_dp->last_power_cycle = jiffies; |
2019 | intel_dp->last_power_cycle = jiffies; |
2020 | wait_panel_off(intel_dp); |
2020 | wait_panel_off(intel_dp); |
2021 | 2021 | ||
2022 | /* We got a reference when we enabled the VDD. */ |
2022 | /* We got a reference when we enabled the VDD. */ |
2023 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2023 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
2024 | intel_display_power_put(dev_priv, power_domain); |
2024 | intel_display_power_put(dev_priv, power_domain); |
2025 | } |
2025 | } |
2026 | 2026 | ||
2027 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2027 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2028 | { |
2028 | { |
2029 | if (!is_edp(intel_dp)) |
2029 | if (!is_edp(intel_dp)) |
2030 | return; |
2030 | return; |
2031 | 2031 | ||
2032 | pps_lock(intel_dp); |
2032 | pps_lock(intel_dp); |
2033 | edp_panel_off(intel_dp); |
2033 | edp_panel_off(intel_dp); |
2034 | pps_unlock(intel_dp); |
2034 | pps_unlock(intel_dp); |
2035 | } |
2035 | } |
2036 | 2036 | ||
2037 | /* Enable backlight in the panel power control. */ |
2037 | /* Enable backlight in the panel power control. */ |
2038 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2038 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
2039 | { |
2039 | { |
2040 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2040 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2041 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2041 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2042 | struct drm_i915_private *dev_priv = dev->dev_private; |
2042 | struct drm_i915_private *dev_priv = dev->dev_private; |
2043 | u32 pp; |
2043 | u32 pp; |
2044 | u32 pp_ctrl_reg; |
2044 | u32 pp_ctrl_reg; |
2045 | 2045 | ||
2046 | /* |
2046 | /* |
2047 | * If we enable the backlight right away following a panel power |
2047 | * If we enable the backlight right away following a panel power |
2048 | * on, we may see slight flicker as the panel syncs with the eDP |
2048 | * on, we may see slight flicker as the panel syncs with the eDP |
2049 | * link. So delay a bit to make sure the image is solid before |
2049 | * link. So delay a bit to make sure the image is solid before |
2050 | * allowing it to appear. |
2050 | * allowing it to appear. |
2051 | */ |
2051 | */ |
2052 | wait_backlight_on(intel_dp); |
2052 | wait_backlight_on(intel_dp); |
2053 | 2053 | ||
2054 | pps_lock(intel_dp); |
2054 | pps_lock(intel_dp); |
2055 | 2055 | ||
2056 | pp = ironlake_get_pp_control(intel_dp); |
2056 | pp = ironlake_get_pp_control(intel_dp); |
2057 | pp |= EDP_BLC_ENABLE; |
2057 | pp |= EDP_BLC_ENABLE; |
2058 | 2058 | ||
2059 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2059 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2060 | 2060 | ||
2061 | I915_WRITE(pp_ctrl_reg, pp); |
2061 | I915_WRITE(pp_ctrl_reg, pp); |
2062 | POSTING_READ(pp_ctrl_reg); |
2062 | POSTING_READ(pp_ctrl_reg); |
2063 | 2063 | ||
2064 | pps_unlock(intel_dp); |
2064 | pps_unlock(intel_dp); |
2065 | } |
2065 | } |
2066 | 2066 | ||
2067 | /* Enable backlight PWM and backlight PP control. */ |
2067 | /* Enable backlight PWM and backlight PP control. */ |
2068 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2068 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
2069 | { |
2069 | { |
2070 | if (!is_edp(intel_dp)) |
2070 | if (!is_edp(intel_dp)) |
2071 | return; |
2071 | return; |
2072 | 2072 | ||
2073 | DRM_DEBUG_KMS("\n"); |
2073 | DRM_DEBUG_KMS("\n"); |
2074 | 2074 | ||
2075 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2075 | intel_panel_enable_backlight(intel_dp->attached_connector); |
2076 | _intel_edp_backlight_on(intel_dp); |
2076 | _intel_edp_backlight_on(intel_dp); |
2077 | } |
2077 | } |
2078 | 2078 | ||
2079 | /* Disable backlight in the panel power control. */ |
2079 | /* Disable backlight in the panel power control. */ |
2080 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2080 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
2081 | { |
2081 | { |
2082 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2082 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; |
2084 | u32 pp; |
2084 | u32 pp; |
2085 | u32 pp_ctrl_reg; |
2085 | u32 pp_ctrl_reg; |
2086 | 2086 | ||
2087 | if (!is_edp(intel_dp)) |
2087 | if (!is_edp(intel_dp)) |
2088 | return; |
2088 | return; |
2089 | 2089 | ||
2090 | pps_lock(intel_dp); |
2090 | pps_lock(intel_dp); |
2091 | 2091 | ||
2092 | pp = ironlake_get_pp_control(intel_dp); |
2092 | pp = ironlake_get_pp_control(intel_dp); |
2093 | pp &= ~EDP_BLC_ENABLE; |
2093 | pp &= ~EDP_BLC_ENABLE; |
2094 | 2094 | ||
2095 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2095 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2096 | 2096 | ||
2097 | I915_WRITE(pp_ctrl_reg, pp); |
2097 | I915_WRITE(pp_ctrl_reg, pp); |
2098 | POSTING_READ(pp_ctrl_reg); |
2098 | POSTING_READ(pp_ctrl_reg); |
2099 | 2099 | ||
2100 | pps_unlock(intel_dp); |
2100 | pps_unlock(intel_dp); |
2101 | 2101 | ||
2102 | intel_dp->last_backlight_off = jiffies; |
2102 | intel_dp->last_backlight_off = jiffies; |
2103 | edp_wait_backlight_off(intel_dp); |
2103 | edp_wait_backlight_off(intel_dp); |
2104 | } |
2104 | } |
2105 | 2105 | ||
2106 | /* Disable backlight PP control and backlight PWM. */ |
2106 | /* Disable backlight PP control and backlight PWM. */ |
2107 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2107 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
2108 | { |
2108 | { |
2109 | if (!is_edp(intel_dp)) |
2109 | if (!is_edp(intel_dp)) |
2110 | return; |
2110 | return; |
2111 | 2111 | ||
2112 | DRM_DEBUG_KMS("\n"); |
2112 | DRM_DEBUG_KMS("\n"); |
2113 | 2113 | ||
2114 | _intel_edp_backlight_off(intel_dp); |
2114 | _intel_edp_backlight_off(intel_dp); |
2115 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2115 | intel_panel_disable_backlight(intel_dp->attached_connector); |
2116 | } |
2116 | } |
2117 | 2117 | ||
2118 | /* |
2118 | /* |
2119 | * Hook for controlling the panel power control backlight through the bl_power |
2119 | * Hook for controlling the panel power control backlight through the bl_power |
2120 | * sysfs attribute. Take care to handle multiple calls. |
2120 | * sysfs attribute. Take care to handle multiple calls. |
2121 | */ |
2121 | */ |
2122 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2122 | static void intel_edp_backlight_power(struct intel_connector *connector, |
2123 | bool enable) |
2123 | bool enable) |
2124 | { |
2124 | { |
2125 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2125 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
2126 | bool is_enabled; |
2126 | bool is_enabled; |
2127 | 2127 | ||
2128 | pps_lock(intel_dp); |
2128 | pps_lock(intel_dp); |
2129 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2129 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
2130 | pps_unlock(intel_dp); |
2130 | pps_unlock(intel_dp); |
2131 | 2131 | ||
2132 | if (is_enabled == enable) |
2132 | if (is_enabled == enable) |
2133 | return; |
2133 | return; |
2134 | 2134 | ||
2135 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2135 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2136 | enable ? "enable" : "disable"); |
2136 | enable ? "enable" : "disable"); |
2137 | 2137 | ||
2138 | if (enable) |
2138 | if (enable) |
2139 | _intel_edp_backlight_on(intel_dp); |
2139 | _intel_edp_backlight_on(intel_dp); |
2140 | else |
2140 | else |
2141 | _intel_edp_backlight_off(intel_dp); |
2141 | _intel_edp_backlight_off(intel_dp); |
2142 | } |
2142 | } |
2143 | 2143 | ||
2144 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2144 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2145 | { |
2145 | { |
2146 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2146 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2147 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2147 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2148 | struct drm_device *dev = crtc->dev; |
2148 | struct drm_device *dev = crtc->dev; |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
2150 | u32 dpa_ctl; |
2150 | u32 dpa_ctl; |
2151 | 2151 | ||
2152 | assert_pipe_disabled(dev_priv, |
2152 | assert_pipe_disabled(dev_priv, |
2153 | to_intel_crtc(crtc)->pipe); |
2153 | to_intel_crtc(crtc)->pipe); |
2154 | 2154 | ||
2155 | DRM_DEBUG_KMS("\n"); |
2155 | DRM_DEBUG_KMS("\n"); |
2156 | dpa_ctl = I915_READ(DP_A); |
2156 | dpa_ctl = I915_READ(DP_A); |
2157 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
2157 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
2158 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
2158 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
2159 | 2159 | ||
2160 | /* We don't adjust intel_dp->DP while tearing down the link, to |
2160 | /* We don't adjust intel_dp->DP while tearing down the link, to |
2161 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
2161 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
2162 | * enable bits here to ensure that we don't enable too much. */ |
2162 | * enable bits here to ensure that we don't enable too much. */ |
2163 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
2163 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
2164 | intel_dp->DP |= DP_PLL_ENABLE; |
2164 | intel_dp->DP |= DP_PLL_ENABLE; |
2165 | I915_WRITE(DP_A, intel_dp->DP); |
2165 | I915_WRITE(DP_A, intel_dp->DP); |
2166 | POSTING_READ(DP_A); |
2166 | POSTING_READ(DP_A); |
2167 | udelay(200); |
2167 | udelay(200); |
2168 | } |
2168 | } |
2169 | 2169 | ||
2170 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2170 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2171 | { |
2171 | { |
2172 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2172 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2173 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2173 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2174 | struct drm_device *dev = crtc->dev; |
2174 | struct drm_device *dev = crtc->dev; |
2175 | struct drm_i915_private *dev_priv = dev->dev_private; |
2175 | struct drm_i915_private *dev_priv = dev->dev_private; |
2176 | u32 dpa_ctl; |
2176 | u32 dpa_ctl; |
2177 | 2177 | ||
2178 | assert_pipe_disabled(dev_priv, |
2178 | assert_pipe_disabled(dev_priv, |
2179 | to_intel_crtc(crtc)->pipe); |
2179 | to_intel_crtc(crtc)->pipe); |
2180 | 2180 | ||
2181 | dpa_ctl = I915_READ(DP_A); |
2181 | dpa_ctl = I915_READ(DP_A); |
2182 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
2182 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
2183 | "dp pll off, should be on\n"); |
2183 | "dp pll off, should be on\n"); |
2184 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
2184 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
2185 | 2185 | ||
2186 | /* We can't rely on the value tracked for the DP register in |
2186 | /* We can't rely on the value tracked for the DP register in |
2187 | * intel_dp->DP because link_down must not change that (otherwise link |
2187 | * intel_dp->DP because link_down must not change that (otherwise link |
2188 | * re-training will fail. */ |
2188 | * re-training will fail. */ |
2189 | dpa_ctl &= ~DP_PLL_ENABLE; |
2189 | dpa_ctl &= ~DP_PLL_ENABLE; |
2190 | I915_WRITE(DP_A, dpa_ctl); |
2190 | I915_WRITE(DP_A, dpa_ctl); |
2191 | POSTING_READ(DP_A); |
2191 | POSTING_READ(DP_A); |
2192 | udelay(200); |
2192 | udelay(200); |
2193 | } |
2193 | } |
2194 | 2194 | ||
2195 | /* If the sink supports it, try to set the power state appropriately */ |
2195 | /* If the sink supports it, try to set the power state appropriately */ |
2196 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2196 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2197 | { |
2197 | { |
2198 | int ret, i; |
2198 | int ret, i; |
2199 | 2199 | ||
2200 | /* Should have a valid DPCD by this point */ |
2200 | /* Should have a valid DPCD by this point */ |
2201 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2201 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
2202 | return; |
2202 | return; |
2203 | 2203 | ||
2204 | if (mode != DRM_MODE_DPMS_ON) { |
2204 | if (mode != DRM_MODE_DPMS_ON) { |
2205 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2205 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2206 | DP_SET_POWER_D3); |
2206 | DP_SET_POWER_D3); |
2207 | } else { |
2207 | } else { |
2208 | /* |
2208 | /* |
2209 | * When turning on, we need to retry for 1ms to give the sink |
2209 | * When turning on, we need to retry for 1ms to give the sink |
2210 | * time to wake up. |
2210 | * time to wake up. |
2211 | */ |
2211 | */ |
2212 | for (i = 0; i < 3; i++) { |
2212 | for (i = 0; i < 3; i++) { |
2213 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2213 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2214 | DP_SET_POWER_D0); |
2214 | DP_SET_POWER_D0); |
2215 | if (ret == 1) |
2215 | if (ret == 1) |
2216 | break; |
2216 | break; |
2217 | msleep(1); |
2217 | msleep(1); |
2218 | } |
2218 | } |
2219 | } |
2219 | } |
2220 | 2220 | ||
2221 | if (ret != 1) |
2221 | if (ret != 1) |
2222 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2222 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
2223 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2223 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
2224 | } |
2224 | } |
2225 | 2225 | ||
2226 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2226 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2227 | enum pipe *pipe) |
2227 | enum pipe *pipe) |
2228 | { |
2228 | { |
2229 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2229 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2230 | enum port port = dp_to_dig_port(intel_dp)->port; |
2230 | enum port port = dp_to_dig_port(intel_dp)->port; |
2231 | struct drm_device *dev = encoder->base.dev; |
2231 | struct drm_device *dev = encoder->base.dev; |
2232 | struct drm_i915_private *dev_priv = dev->dev_private; |
2232 | struct drm_i915_private *dev_priv = dev->dev_private; |
2233 | enum intel_display_power_domain power_domain; |
2233 | enum intel_display_power_domain power_domain; |
2234 | u32 tmp; |
2234 | u32 tmp; |
2235 | 2235 | ||
2236 | power_domain = intel_display_port_power_domain(encoder); |
2236 | power_domain = intel_display_port_power_domain(encoder); |
2237 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
2237 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
2238 | return false; |
2238 | return false; |
2239 | 2239 | ||
2240 | tmp = I915_READ(intel_dp->output_reg); |
2240 | tmp = I915_READ(intel_dp->output_reg); |
2241 | 2241 | ||
2242 | if (!(tmp & DP_PORT_EN)) |
2242 | if (!(tmp & DP_PORT_EN)) |
2243 | return false; |
2243 | return false; |
2244 | 2244 | ||
2245 | if (IS_GEN7(dev) && port == PORT_A) { |
2245 | if (IS_GEN7(dev) && port == PORT_A) { |
2246 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2246 | *pipe = PORT_TO_PIPE_CPT(tmp); |
2247 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2247 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2248 | enum pipe p; |
2248 | enum pipe p; |
2249 | 2249 | ||
2250 | for_each_pipe(dev_priv, p) { |
2250 | for_each_pipe(dev_priv, p) { |
2251 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2251 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
2252 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2252 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
2253 | *pipe = p; |
2253 | *pipe = p; |
2254 | return true; |
2254 | return true; |
2255 | } |
2255 | } |
2256 | } |
2256 | } |
2257 | 2257 | ||
2258 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2258 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
2259 | intel_dp->output_reg); |
2259 | intel_dp->output_reg); |
2260 | } else if (IS_CHERRYVIEW(dev)) { |
2260 | } else if (IS_CHERRYVIEW(dev)) { |
2261 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2261 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2262 | } else { |
2262 | } else { |
2263 | *pipe = PORT_TO_PIPE(tmp); |
2263 | *pipe = PORT_TO_PIPE(tmp); |
2264 | } |
2264 | } |
2265 | 2265 | ||
2266 | return true; |
2266 | return true; |
2267 | } |
2267 | } |
2268 | 2268 | ||
2269 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2269 | static void intel_dp_get_config(struct intel_encoder *encoder, |
2270 | struct intel_crtc_state *pipe_config) |
2270 | struct intel_crtc_state *pipe_config) |
2271 | { |
2271 | { |
2272 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2272 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2273 | u32 tmp, flags = 0; |
2273 | u32 tmp, flags = 0; |
2274 | struct drm_device *dev = encoder->base.dev; |
2274 | struct drm_device *dev = encoder->base.dev; |
2275 | struct drm_i915_private *dev_priv = dev->dev_private; |
2275 | struct drm_i915_private *dev_priv = dev->dev_private; |
2276 | enum port port = dp_to_dig_port(intel_dp)->port; |
2276 | enum port port = dp_to_dig_port(intel_dp)->port; |
2277 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2277 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2278 | int dotclock; |
2278 | int dotclock; |
2279 | 2279 | ||
2280 | tmp = I915_READ(intel_dp->output_reg); |
2280 | tmp = I915_READ(intel_dp->output_reg); |
2281 | 2281 | ||
2282 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2282 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
2283 | 2283 | ||
2284 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2284 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
2285 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2285 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2286 | 2286 | ||
2287 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2287 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
2288 | flags |= DRM_MODE_FLAG_PHSYNC; |
2288 | flags |= DRM_MODE_FLAG_PHSYNC; |
2289 | else |
2289 | else |
2290 | flags |= DRM_MODE_FLAG_NHSYNC; |
2290 | flags |= DRM_MODE_FLAG_NHSYNC; |
2291 | 2291 | ||
2292 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2292 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2293 | flags |= DRM_MODE_FLAG_PVSYNC; |
2293 | flags |= DRM_MODE_FLAG_PVSYNC; |
2294 | else |
2294 | else |
2295 | flags |= DRM_MODE_FLAG_NVSYNC; |
2295 | flags |= DRM_MODE_FLAG_NVSYNC; |
2296 | } else { |
2296 | } else { |
2297 | if (tmp & DP_SYNC_HS_HIGH) |
2297 | if (tmp & DP_SYNC_HS_HIGH) |
2298 | flags |= DRM_MODE_FLAG_PHSYNC; |
2298 | flags |= DRM_MODE_FLAG_PHSYNC; |
2299 | else |
2299 | else |
2300 | flags |= DRM_MODE_FLAG_NHSYNC; |
2300 | flags |= DRM_MODE_FLAG_NHSYNC; |
2301 | 2301 | ||
2302 | if (tmp & DP_SYNC_VS_HIGH) |
2302 | if (tmp & DP_SYNC_VS_HIGH) |
2303 | flags |= DRM_MODE_FLAG_PVSYNC; |
2303 | flags |= DRM_MODE_FLAG_PVSYNC; |
2304 | else |
2304 | else |
2305 | flags |= DRM_MODE_FLAG_NVSYNC; |
2305 | flags |= DRM_MODE_FLAG_NVSYNC; |
2306 | } |
2306 | } |
2307 | 2307 | ||
2308 | pipe_config->base.adjusted_mode.flags |= flags; |
2308 | pipe_config->base.adjusted_mode.flags |= flags; |
2309 | 2309 | ||
2310 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2310 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2311 | tmp & DP_COLOR_RANGE_16_235) |
2311 | tmp & DP_COLOR_RANGE_16_235) |
2312 | pipe_config->limited_color_range = true; |
2312 | pipe_config->limited_color_range = true; |
2313 | 2313 | ||
2314 | pipe_config->has_dp_encoder = true; |
2314 | pipe_config->has_dp_encoder = true; |
2315 | 2315 | ||
2316 | pipe_config->lane_count = |
2316 | pipe_config->lane_count = |
2317 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2317 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
2318 | 2318 | ||
2319 | intel_dp_get_m_n(crtc, pipe_config); |
2319 | intel_dp_get_m_n(crtc, pipe_config); |
2320 | 2320 | ||
2321 | if (port == PORT_A) { |
2321 | if (port == PORT_A) { |
2322 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
2322 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
2323 | pipe_config->port_clock = 162000; |
2323 | pipe_config->port_clock = 162000; |
2324 | else |
2324 | else |
2325 | pipe_config->port_clock = 270000; |
2325 | pipe_config->port_clock = 270000; |
2326 | } |
2326 | } |
2327 | 2327 | ||
2328 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2328 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
2329 | &pipe_config->dp_m_n); |
2329 | &pipe_config->dp_m_n); |
2330 | 2330 | ||
2331 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2331 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
2332 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2332 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
2333 | 2333 | ||
2334 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2334 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
2335 | 2335 | ||
2336 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2336 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2337 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2337 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
2338 | /* |
2338 | /* |
2339 | * This is a big fat ugly hack. |
2339 | * This is a big fat ugly hack. |
2340 | * |
2340 | * |
2341 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2341 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
2342 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2342 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
2343 | * unknown we fail to light up. Yet the same BIOS boots up with |
2343 | * unknown we fail to light up. Yet the same BIOS boots up with |
2344 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2344 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
2345 | * max, not what it tells us to use. |
2345 | * max, not what it tells us to use. |
2346 | * |
2346 | * |
2347 | * Note: This will still be broken if the eDP panel is not lit |
2347 | * Note: This will still be broken if the eDP panel is not lit |
2348 | * up by the BIOS, and thus we can't get the mode at module |
2348 | * up by the BIOS, and thus we can't get the mode at module |
2349 | * load. |
2349 | * load. |
2350 | */ |
2350 | */ |
2351 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2351 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
2352 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2352 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
2353 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2353 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
2354 | } |
2354 | } |
2355 | } |
2355 | } |
2356 | 2356 | ||
2357 | static void intel_disable_dp(struct intel_encoder *encoder) |
2357 | static void intel_disable_dp(struct intel_encoder *encoder) |
2358 | { |
2358 | { |
2359 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2359 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2360 | struct drm_device *dev = encoder->base.dev; |
2360 | struct drm_device *dev = encoder->base.dev; |
2361 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2361 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2362 | 2362 | ||
2363 | if (crtc->config->has_audio) |
2363 | if (crtc->config->has_audio) |
2364 | intel_audio_codec_disable(encoder); |
2364 | intel_audio_codec_disable(encoder); |
2365 | 2365 | ||
2366 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2366 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2367 | intel_psr_disable(intel_dp); |
2367 | intel_psr_disable(intel_dp); |
2368 | 2368 | ||
2369 | /* Make sure the panel is off before trying to change the mode. But also |
2369 | /* Make sure the panel is off before trying to change the mode. But also |
2370 | * ensure that we have vdd while we switch off the panel. */ |
2370 | * ensure that we have vdd while we switch off the panel. */ |
2371 | intel_edp_panel_vdd_on(intel_dp); |
2371 | intel_edp_panel_vdd_on(intel_dp); |
2372 | intel_edp_backlight_off(intel_dp); |
2372 | intel_edp_backlight_off(intel_dp); |
2373 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2373 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
2374 | intel_edp_panel_off(intel_dp); |
2374 | intel_edp_panel_off(intel_dp); |
2375 | 2375 | ||
2376 | /* disable the port before the pipe on g4x */ |
2376 | /* disable the port before the pipe on g4x */ |
2377 | if (INTEL_INFO(dev)->gen < 5) |
2377 | if (INTEL_INFO(dev)->gen < 5) |
2378 | intel_dp_link_down(intel_dp); |
2378 | intel_dp_link_down(intel_dp); |
2379 | } |
2379 | } |
2380 | 2380 | ||
2381 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2381 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
2382 | { |
2382 | { |
2383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2383 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2384 | enum port port = dp_to_dig_port(intel_dp)->port; |
2384 | enum port port = dp_to_dig_port(intel_dp)->port; |
2385 | 2385 | ||
2386 | intel_dp_link_down(intel_dp); |
2386 | intel_dp_link_down(intel_dp); |
2387 | if (port == PORT_A) |
2387 | if (port == PORT_A) |
2388 | ironlake_edp_pll_off(intel_dp); |
2388 | ironlake_edp_pll_off(intel_dp); |
2389 | } |
2389 | } |
2390 | 2390 | ||
2391 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2391 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
2392 | { |
2392 | { |
2393 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2393 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2394 | 2394 | ||
2395 | intel_dp_link_down(intel_dp); |
2395 | intel_dp_link_down(intel_dp); |
2396 | } |
2396 | } |
2397 | 2397 | ||
2398 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2398 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2399 | bool reset) |
2399 | bool reset) |
2400 | { |
2400 | { |
2401 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2401 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2402 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2402 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); |
2403 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2403 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2404 | enum pipe pipe = crtc->pipe; |
2404 | enum pipe pipe = crtc->pipe; |
2405 | uint32_t val; |
2405 | uint32_t val; |
2406 | 2406 | ||
2407 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2407 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
2408 | if (reset) |
2408 | if (reset) |
2409 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2409 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2410 | else |
2410 | else |
2411 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2411 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2412 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2412 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
2413 | 2413 | ||
2414 | if (crtc->config->lane_count > 2) { |
2414 | if (crtc->config->lane_count > 2) { |
2415 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2415 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
2416 | if (reset) |
2416 | if (reset) |
2417 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2417 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
2418 | else |
2418 | else |
2419 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2419 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; |
2420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
2421 | } |
2421 | } |
2422 | 2422 | ||
2423 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2423 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
2424 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2424 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2425 | if (reset) |
2425 | if (reset) |
2426 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2426 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2427 | else |
2427 | else |
2428 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2428 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2429 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2429 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2430 | 2430 | ||
2431 | if (crtc->config->lane_count > 2) { |
2431 | if (crtc->config->lane_count > 2) { |
2432 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2432 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2433 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2433 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
2434 | if (reset) |
2434 | if (reset) |
2435 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2435 | val &= ~DPIO_PCS_CLK_SOFT_RESET; |
2436 | else |
2436 | else |
2437 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2437 | val |= DPIO_PCS_CLK_SOFT_RESET; |
2438 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2438 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
2439 | } |
2439 | } |
2440 | } |
2440 | } |
2441 | 2441 | ||
2442 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2442 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2443 | { |
2443 | { |
2444 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2444 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2445 | struct drm_device *dev = encoder->base.dev; |
2445 | struct drm_device *dev = encoder->base.dev; |
2446 | struct drm_i915_private *dev_priv = dev->dev_private; |
2446 | struct drm_i915_private *dev_priv = dev->dev_private; |
2447 | 2447 | ||
2448 | intel_dp_link_down(intel_dp); |
2448 | intel_dp_link_down(intel_dp); |
2449 | 2449 | ||
2450 | mutex_lock(&dev_priv->sb_lock); |
2450 | mutex_lock(&dev_priv->sb_lock); |
2451 | 2451 | ||
2452 | /* Assert data lane reset */ |
2452 | /* Assert data lane reset */ |
2453 | chv_data_lane_soft_reset(encoder, true); |
2453 | chv_data_lane_soft_reset(encoder, true); |
2454 | 2454 | ||
2455 | mutex_unlock(&dev_priv->sb_lock); |
2455 | mutex_unlock(&dev_priv->sb_lock); |
2456 | } |
2456 | } |
2457 | 2457 | ||
2458 | static void |
2458 | static void |
2459 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2459 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
2460 | uint32_t *DP, |
2460 | uint32_t *DP, |
2461 | uint8_t dp_train_pat) |
2461 | uint8_t dp_train_pat) |
2462 | { |
2462 | { |
2463 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2463 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2464 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2464 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2465 | struct drm_i915_private *dev_priv = dev->dev_private; |
2465 | struct drm_i915_private *dev_priv = dev->dev_private; |
2466 | enum port port = intel_dig_port->port; |
2466 | enum port port = intel_dig_port->port; |
2467 | 2467 | ||
2468 | if (HAS_DDI(dev)) { |
2468 | if (HAS_DDI(dev)) { |
2469 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2469 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2470 | 2470 | ||
2471 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2471 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
2472 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2472 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
2473 | else |
2473 | else |
2474 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2474 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
2475 | 2475 | ||
2476 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2476 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
2477 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2477 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2478 | case DP_TRAINING_PATTERN_DISABLE: |
2478 | case DP_TRAINING_PATTERN_DISABLE: |
2479 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2479 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2480 | 2480 | ||
2481 | break; |
2481 | break; |
2482 | case DP_TRAINING_PATTERN_1: |
2482 | case DP_TRAINING_PATTERN_1: |
2483 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2483 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
2484 | break; |
2484 | break; |
2485 | case DP_TRAINING_PATTERN_2: |
2485 | case DP_TRAINING_PATTERN_2: |
2486 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2486 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
2487 | break; |
2487 | break; |
2488 | case DP_TRAINING_PATTERN_3: |
2488 | case DP_TRAINING_PATTERN_3: |
2489 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2489 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
2490 | break; |
2490 | break; |
2491 | } |
2491 | } |
2492 | I915_WRITE(DP_TP_CTL(port), temp); |
2492 | I915_WRITE(DP_TP_CTL(port), temp); |
2493 | 2493 | ||
2494 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2494 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2495 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2495 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
2496 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2496 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2497 | 2497 | ||
2498 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2498 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2499 | case DP_TRAINING_PATTERN_DISABLE: |
2499 | case DP_TRAINING_PATTERN_DISABLE: |
2500 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2500 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
2501 | break; |
2501 | break; |
2502 | case DP_TRAINING_PATTERN_1: |
2502 | case DP_TRAINING_PATTERN_1: |
2503 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2503 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
2504 | break; |
2504 | break; |
2505 | case DP_TRAINING_PATTERN_2: |
2505 | case DP_TRAINING_PATTERN_2: |
2506 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2506 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2507 | break; |
2507 | break; |
2508 | case DP_TRAINING_PATTERN_3: |
2508 | case DP_TRAINING_PATTERN_3: |
2509 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2509 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2510 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2510 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2511 | break; |
2511 | break; |
2512 | } |
2512 | } |
2513 | 2513 | ||
2514 | } else { |
2514 | } else { |
2515 | if (IS_CHERRYVIEW(dev)) |
2515 | if (IS_CHERRYVIEW(dev)) |
2516 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2516 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2517 | else |
2517 | else |
2518 | *DP &= ~DP_LINK_TRAIN_MASK; |
2518 | *DP &= ~DP_LINK_TRAIN_MASK; |
2519 | 2519 | ||
2520 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2520 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
2521 | case DP_TRAINING_PATTERN_DISABLE: |
2521 | case DP_TRAINING_PATTERN_DISABLE: |
2522 | *DP |= DP_LINK_TRAIN_OFF; |
2522 | *DP |= DP_LINK_TRAIN_OFF; |
2523 | break; |
2523 | break; |
2524 | case DP_TRAINING_PATTERN_1: |
2524 | case DP_TRAINING_PATTERN_1: |
2525 | *DP |= DP_LINK_TRAIN_PAT_1; |
2525 | *DP |= DP_LINK_TRAIN_PAT_1; |
2526 | break; |
2526 | break; |
2527 | case DP_TRAINING_PATTERN_2: |
2527 | case DP_TRAINING_PATTERN_2: |
2528 | *DP |= DP_LINK_TRAIN_PAT_2; |
2528 | *DP |= DP_LINK_TRAIN_PAT_2; |
2529 | break; |
2529 | break; |
2530 | case DP_TRAINING_PATTERN_3: |
2530 | case DP_TRAINING_PATTERN_3: |
2531 | if (IS_CHERRYVIEW(dev)) { |
2531 | if (IS_CHERRYVIEW(dev)) { |
2532 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2532 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2533 | } else { |
2533 | } else { |
2534 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2534 | DRM_ERROR("DP training pattern 3 not supported\n"); |
2535 | *DP |= DP_LINK_TRAIN_PAT_2; |
2535 | *DP |= DP_LINK_TRAIN_PAT_2; |
2536 | } |
2536 | } |
2537 | break; |
2537 | break; |
2538 | } |
2538 | } |
2539 | } |
2539 | } |
2540 | } |
2540 | } |
2541 | 2541 | ||
2542 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2542 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
2543 | { |
2543 | { |
2544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2544 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
2546 | 2546 | ||
2547 | /* enable with pattern 1 (as per spec) */ |
2547 | /* enable with pattern 1 (as per spec) */ |
2548 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2548 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
2549 | DP_TRAINING_PATTERN_1); |
2549 | DP_TRAINING_PATTERN_1); |
2550 | 2550 | ||
2551 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2551 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2552 | POSTING_READ(intel_dp->output_reg); |
2552 | POSTING_READ(intel_dp->output_reg); |
2553 | 2553 | ||
2554 | /* |
2554 | /* |
2555 | * Magic for VLV/CHV. We _must_ first set up the register |
2555 | * Magic for VLV/CHV. We _must_ first set up the register |
2556 | * without actually enabling the port, and then do another |
2556 | * without actually enabling the port, and then do another |
2557 | * write to enable the port. Otherwise link training will |
2557 | * write to enable the port. Otherwise link training will |
2558 | * fail when the power sequencer is freshly used for this port. |
2558 | * fail when the power sequencer is freshly used for this port. |
2559 | */ |
2559 | */ |
2560 | intel_dp->DP |= DP_PORT_EN; |
2560 | intel_dp->DP |= DP_PORT_EN; |
2561 | 2561 | ||
2562 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2562 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
2563 | POSTING_READ(intel_dp->output_reg); |
2563 | POSTING_READ(intel_dp->output_reg); |
2564 | } |
2564 | } |
2565 | 2565 | ||
2566 | static void intel_enable_dp(struct intel_encoder *encoder) |
2566 | static void intel_enable_dp(struct intel_encoder *encoder) |
2567 | { |
2567 | { |
2568 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2568 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2569 | struct drm_device *dev = encoder->base.dev; |
2569 | struct drm_device *dev = encoder->base.dev; |
2570 | struct drm_i915_private *dev_priv = dev->dev_private; |
2570 | struct drm_i915_private *dev_priv = dev->dev_private; |
2571 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2571 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2572 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2572 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
2573 | 2573 | ||
2574 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2574 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2575 | return; |
2575 | return; |
2576 | 2576 | ||
2577 | pps_lock(intel_dp); |
2577 | pps_lock(intel_dp); |
2578 | 2578 | ||
2579 | if (IS_VALLEYVIEW(dev)) |
2579 | if (IS_VALLEYVIEW(dev)) |
2580 | vlv_init_panel_power_sequencer(intel_dp); |
2580 | vlv_init_panel_power_sequencer(intel_dp); |
2581 | 2581 | ||
2582 | intel_dp_enable_port(intel_dp); |
2582 | intel_dp_enable_port(intel_dp); |
2583 | 2583 | ||
2584 | edp_panel_vdd_on(intel_dp); |
2584 | edp_panel_vdd_on(intel_dp); |
2585 | edp_panel_on(intel_dp); |
2585 | edp_panel_on(intel_dp); |
2586 | edp_panel_vdd_off(intel_dp, true); |
2586 | edp_panel_vdd_off(intel_dp, true); |
2587 | 2587 | ||
2588 | pps_unlock(intel_dp); |
2588 | pps_unlock(intel_dp); |
2589 | 2589 | ||
2590 | if (IS_VALLEYVIEW(dev)) { |
2590 | if (IS_VALLEYVIEW(dev)) { |
2591 | unsigned int lane_mask = 0x0; |
2591 | unsigned int lane_mask = 0x0; |
2592 | 2592 | ||
2593 | if (IS_CHERRYVIEW(dev)) |
2593 | if (IS_CHERRYVIEW(dev)) |
2594 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2594 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
2595 | 2595 | ||
2596 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2596 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2597 | lane_mask); |
2597 | lane_mask); |
2598 | } |
2598 | } |
2599 | 2599 | ||
2600 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2600 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2601 | intel_dp_start_link_train(intel_dp); |
2601 | intel_dp_start_link_train(intel_dp); |
2602 | intel_dp_stop_link_train(intel_dp); |
2602 | intel_dp_stop_link_train(intel_dp); |
2603 | 2603 | ||
2604 | if (crtc->config->has_audio) { |
2604 | if (crtc->config->has_audio) { |
2605 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2605 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
2606 | pipe_name(crtc->pipe)); |
2606 | pipe_name(crtc->pipe)); |
2607 | intel_audio_codec_enable(encoder); |
2607 | intel_audio_codec_enable(encoder); |
2608 | } |
2608 | } |
2609 | } |
2609 | } |
2610 | 2610 | ||
2611 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2611 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2612 | { |
2612 | { |
2613 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2613 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2614 | 2614 | ||
2615 | intel_enable_dp(encoder); |
2615 | intel_enable_dp(encoder); |
2616 | intel_edp_backlight_on(intel_dp); |
2616 | intel_edp_backlight_on(intel_dp); |
2617 | } |
2617 | } |
2618 | 2618 | ||
2619 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2619 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2620 | { |
2620 | { |
2621 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2621 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2622 | 2622 | ||
2623 | intel_edp_backlight_on(intel_dp); |
2623 | intel_edp_backlight_on(intel_dp); |
2624 | intel_psr_enable(intel_dp); |
2624 | intel_psr_enable(intel_dp); |
2625 | } |
2625 | } |
2626 | 2626 | ||
2627 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2627 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
2628 | { |
2628 | { |
2629 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2629 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2630 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2630 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2631 | 2631 | ||
2632 | intel_dp_prepare(encoder); |
2632 | intel_dp_prepare(encoder); |
2633 | 2633 | ||
2634 | /* Only ilk+ has port A */ |
2634 | /* Only ilk+ has port A */ |
2635 | if (dport->port == PORT_A) { |
2635 | if (dport->port == PORT_A) { |
2636 | ironlake_set_pll_cpu_edp(intel_dp); |
2636 | ironlake_set_pll_cpu_edp(intel_dp); |
2637 | ironlake_edp_pll_on(intel_dp); |
2637 | ironlake_edp_pll_on(intel_dp); |
2638 | } |
2638 | } |
2639 | } |
2639 | } |
2640 | 2640 | ||
2641 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2641 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2642 | { |
2642 | { |
2643 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2643 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2644 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2644 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; |
2645 | enum pipe pipe = intel_dp->pps_pipe; |
2645 | enum pipe pipe = intel_dp->pps_pipe; |
2646 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2646 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
2647 | 2647 | ||
2648 | edp_panel_vdd_off_sync(intel_dp); |
2648 | edp_panel_vdd_off_sync(intel_dp); |
2649 | 2649 | ||
2650 | /* |
2650 | /* |
2651 | * VLV seems to get confused when multiple power seqeuencers |
2651 | * VLV seems to get confused when multiple power seqeuencers |
2652 | * have the same port selected (even if only one has power/vdd |
2652 | * have the same port selected (even if only one has power/vdd |
2653 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2653 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
2654 | * CHV on the other hand doesn't seem to mind having the same port |
2654 | * CHV on the other hand doesn't seem to mind having the same port |
2655 | * selected in multiple power seqeuencers, but let's clear the |
2655 | * selected in multiple power seqeuencers, but let's clear the |
2656 | * port select always when logically disconnecting a power sequencer |
2656 | * port select always when logically disconnecting a power sequencer |
2657 | * from a port. |
2657 | * from a port. |
2658 | */ |
2658 | */ |
2659 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2659 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
2660 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2660 | pipe_name(pipe), port_name(intel_dig_port->port)); |
2661 | I915_WRITE(pp_on_reg, 0); |
2661 | I915_WRITE(pp_on_reg, 0); |
2662 | POSTING_READ(pp_on_reg); |
2662 | POSTING_READ(pp_on_reg); |
2663 | 2663 | ||
2664 | intel_dp->pps_pipe = INVALID_PIPE; |
2664 | intel_dp->pps_pipe = INVALID_PIPE; |
2665 | } |
2665 | } |
2666 | 2666 | ||
2667 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2667 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2668 | enum pipe pipe) |
2668 | enum pipe pipe) |
2669 | { |
2669 | { |
2670 | struct drm_i915_private *dev_priv = dev->dev_private; |
2670 | struct drm_i915_private *dev_priv = dev->dev_private; |
2671 | struct intel_encoder *encoder; |
2671 | struct intel_encoder *encoder; |
2672 | 2672 | ||
2673 | lockdep_assert_held(&dev_priv->pps_mutex); |
2673 | lockdep_assert_held(&dev_priv->pps_mutex); |
2674 | 2674 | ||
2675 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2675 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2676 | return; |
2676 | return; |
2677 | 2677 | ||
2678 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2678 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2679 | base.head) { |
2679 | base.head) { |
2680 | struct intel_dp *intel_dp; |
2680 | struct intel_dp *intel_dp; |
2681 | enum port port; |
2681 | enum port port; |
2682 | 2682 | ||
2683 | if (encoder->type != INTEL_OUTPUT_EDP) |
2683 | if (encoder->type != INTEL_OUTPUT_EDP) |
2684 | continue; |
2684 | continue; |
2685 | 2685 | ||
2686 | intel_dp = enc_to_intel_dp(&encoder->base); |
2686 | intel_dp = enc_to_intel_dp(&encoder->base); |
2687 | port = dp_to_dig_port(intel_dp)->port; |
2687 | port = dp_to_dig_port(intel_dp)->port; |
2688 | 2688 | ||
2689 | if (intel_dp->pps_pipe != pipe) |
2689 | if (intel_dp->pps_pipe != pipe) |
2690 | continue; |
2690 | continue; |
2691 | 2691 | ||
2692 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2692 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
2693 | pipe_name(pipe), port_name(port)); |
2693 | pipe_name(pipe), port_name(port)); |
2694 | 2694 | ||
2695 | WARN(encoder->base.crtc, |
2695 | WARN(encoder->base.crtc, |
2696 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2696 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2697 | pipe_name(pipe), port_name(port)); |
2697 | pipe_name(pipe), port_name(port)); |
2698 | 2698 | ||
2699 | /* make sure vdd is off before we steal it */ |
2699 | /* make sure vdd is off before we steal it */ |
2700 | vlv_detach_power_sequencer(intel_dp); |
2700 | vlv_detach_power_sequencer(intel_dp); |
2701 | } |
2701 | } |
2702 | } |
2702 | } |
2703 | 2703 | ||
2704 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2704 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
2705 | { |
2705 | { |
2706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2707 | struct intel_encoder *encoder = &intel_dig_port->base; |
2707 | struct intel_encoder *encoder = &intel_dig_port->base; |
2708 | struct drm_device *dev = encoder->base.dev; |
2708 | struct drm_device *dev = encoder->base.dev; |
2709 | struct drm_i915_private *dev_priv = dev->dev_private; |
2709 | struct drm_i915_private *dev_priv = dev->dev_private; |
2710 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2710 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2711 | 2711 | ||
2712 | lockdep_assert_held(&dev_priv->pps_mutex); |
2712 | lockdep_assert_held(&dev_priv->pps_mutex); |
2713 | 2713 | ||
2714 | if (!is_edp(intel_dp)) |
2714 | if (!is_edp(intel_dp)) |
2715 | return; |
2715 | return; |
2716 | 2716 | ||
2717 | if (intel_dp->pps_pipe == crtc->pipe) |
2717 | if (intel_dp->pps_pipe == crtc->pipe) |
2718 | return; |
2718 | return; |
2719 | 2719 | ||
2720 | /* |
2720 | /* |
2721 | * If another power sequencer was being used on this |
2721 | * If another power sequencer was being used on this |
2722 | * port previously make sure to turn off vdd there while |
2722 | * port previously make sure to turn off vdd there while |
2723 | * we still have control of it. |
2723 | * we still have control of it. |
2724 | */ |
2724 | */ |
2725 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2725 | if (intel_dp->pps_pipe != INVALID_PIPE) |
2726 | vlv_detach_power_sequencer(intel_dp); |
2726 | vlv_detach_power_sequencer(intel_dp); |
2727 | 2727 | ||
2728 | /* |
2728 | /* |
2729 | * We may be stealing the power |
2729 | * We may be stealing the power |
2730 | * sequencer from another port. |
2730 | * sequencer from another port. |
2731 | */ |
2731 | */ |
2732 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2732 | vlv_steal_power_sequencer(dev, crtc->pipe); |
2733 | 2733 | ||
2734 | /* now it's all ours */ |
2734 | /* now it's all ours */ |
2735 | intel_dp->pps_pipe = crtc->pipe; |
2735 | intel_dp->pps_pipe = crtc->pipe; |
2736 | 2736 | ||
2737 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2737 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
2738 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2738 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
2739 | 2739 | ||
2740 | /* init power sequencer on this pipe and port */ |
2740 | /* init power sequencer on this pipe and port */ |
2741 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2741 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2742 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2742 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
2743 | } |
2743 | } |
2744 | 2744 | ||
2745 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2745 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
2746 | { |
2746 | { |
2747 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2747 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2748 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2748 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2749 | struct drm_device *dev = encoder->base.dev; |
2749 | struct drm_device *dev = encoder->base.dev; |
2750 | struct drm_i915_private *dev_priv = dev->dev_private; |
2750 | struct drm_i915_private *dev_priv = dev->dev_private; |
2751 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2751 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
2752 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2752 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2753 | int pipe = intel_crtc->pipe; |
2753 | int pipe = intel_crtc->pipe; |
2754 | u32 val; |
2754 | u32 val; |
2755 | 2755 | ||
2756 | mutex_lock(&dev_priv->sb_lock); |
2756 | mutex_lock(&dev_priv->sb_lock); |
2757 | 2757 | ||
2758 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2758 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
2759 | val = 0; |
2759 | val = 0; |
2760 | if (pipe) |
2760 | if (pipe) |
2761 | val |= (1<<21); |
2761 | val |= (1<<21); |
2762 | else |
2762 | else |
2763 | val &= ~(1<<21); |
2763 | val &= ~(1<<21); |
2764 | val |= 0x001000c4; |
2764 | val |= 0x001000c4; |
2765 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2765 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2766 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2766 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
2767 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2767 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
2768 | 2768 | ||
2769 | mutex_unlock(&dev_priv->sb_lock); |
2769 | mutex_unlock(&dev_priv->sb_lock); |
2770 | 2770 | ||
2771 | intel_enable_dp(encoder); |
2771 | intel_enable_dp(encoder); |
2772 | } |
2772 | } |
2773 | 2773 | ||
2774 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2774 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2775 | { |
2775 | { |
2776 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2776 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2777 | struct drm_device *dev = encoder->base.dev; |
2777 | struct drm_device *dev = encoder->base.dev; |
2778 | struct drm_i915_private *dev_priv = dev->dev_private; |
2778 | struct drm_i915_private *dev_priv = dev->dev_private; |
2779 | struct intel_crtc *intel_crtc = |
2779 | struct intel_crtc *intel_crtc = |
2780 | to_intel_crtc(encoder->base.crtc); |
2780 | to_intel_crtc(encoder->base.crtc); |
2781 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2781 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2782 | int pipe = intel_crtc->pipe; |
2782 | int pipe = intel_crtc->pipe; |
2783 | 2783 | ||
2784 | intel_dp_prepare(encoder); |
2784 | intel_dp_prepare(encoder); |
2785 | 2785 | ||
2786 | /* Program Tx lane resets to default */ |
2786 | /* Program Tx lane resets to default */ |
2787 | mutex_lock(&dev_priv->sb_lock); |
2787 | mutex_lock(&dev_priv->sb_lock); |
2788 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2788 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
2789 | DPIO_PCS_TX_LANE2_RESET | |
2789 | DPIO_PCS_TX_LANE2_RESET | |
2790 | DPIO_PCS_TX_LANE1_RESET); |
2790 | DPIO_PCS_TX_LANE1_RESET); |
2791 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2791 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
2792 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2792 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2793 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2793 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
2794 | (1< |
2794 | (1< |
2795 | DPIO_PCS_CLK_SOFT_RESET); |
2795 | DPIO_PCS_CLK_SOFT_RESET); |
2796 | 2796 | ||
2797 | /* Fix up inter-pair skew failure */ |
2797 | /* Fix up inter-pair skew failure */ |
2798 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2798 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2799 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2799 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
2800 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2800 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
2801 | mutex_unlock(&dev_priv->sb_lock); |
2801 | mutex_unlock(&dev_priv->sb_lock); |
2802 | } |
2802 | } |
2803 | 2803 | ||
2804 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2804 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2805 | { |
2805 | { |
2806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2807 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2807 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
2808 | struct drm_device *dev = encoder->base.dev; |
2808 | struct drm_device *dev = encoder->base.dev; |
2809 | struct drm_i915_private *dev_priv = dev->dev_private; |
2809 | struct drm_i915_private *dev_priv = dev->dev_private; |
2810 | struct intel_crtc *intel_crtc = |
2810 | struct intel_crtc *intel_crtc = |
2811 | to_intel_crtc(encoder->base.crtc); |
2811 | to_intel_crtc(encoder->base.crtc); |
2812 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2812 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2813 | int pipe = intel_crtc->pipe; |
2813 | int pipe = intel_crtc->pipe; |
2814 | int data, i, stagger; |
2814 | int data, i, stagger; |
2815 | u32 val; |
2815 | u32 val; |
2816 | 2816 | ||
2817 | mutex_lock(&dev_priv->sb_lock); |
2817 | mutex_lock(&dev_priv->sb_lock); |
2818 | 2818 | ||
2819 | /* allow hardware to manage TX FIFO reset source */ |
2819 | /* allow hardware to manage TX FIFO reset source */ |
2820 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2820 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2821 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2821 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2822 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2822 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2823 | 2823 | ||
2824 | if (intel_crtc->config->lane_count > 2) { |
2824 | if (intel_crtc->config->lane_count > 2) { |
2825 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2825 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2826 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2826 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
2827 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2827 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2828 | } |
2828 | } |
2829 | 2829 | ||
2830 | /* Program Tx lane latency optimal setting*/ |
2830 | /* Program Tx lane latency optimal setting*/ |
2831 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
2831 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
2832 | /* Set the upar bit */ |
2832 | /* Set the upar bit */ |
2833 | if (intel_crtc->config->lane_count == 1) |
2833 | if (intel_crtc->config->lane_count == 1) |
2834 | data = 0x0; |
2834 | data = 0x0; |
2835 | else |
2835 | else |
2836 | data = (i == 1) ? 0x0 : 0x1; |
2836 | data = (i == 1) ? 0x0 : 0x1; |
2837 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
2837 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
2838 | data << DPIO_UPAR_SHIFT); |
2838 | data << DPIO_UPAR_SHIFT); |
2839 | } |
2839 | } |
2840 | 2840 | ||
2841 | /* Data lane stagger programming */ |
2841 | /* Data lane stagger programming */ |
2842 | if (intel_crtc->config->port_clock > 270000) |
2842 | if (intel_crtc->config->port_clock > 270000) |
2843 | stagger = 0x18; |
2843 | stagger = 0x18; |
2844 | else if (intel_crtc->config->port_clock > 135000) |
2844 | else if (intel_crtc->config->port_clock > 135000) |
2845 | stagger = 0xd; |
2845 | stagger = 0xd; |
2846 | else if (intel_crtc->config->port_clock > 67500) |
2846 | else if (intel_crtc->config->port_clock > 67500) |
2847 | stagger = 0x7; |
2847 | stagger = 0x7; |
2848 | else if (intel_crtc->config->port_clock > 33750) |
2848 | else if (intel_crtc->config->port_clock > 33750) |
2849 | stagger = 0x4; |
2849 | stagger = 0x4; |
2850 | else |
2850 | else |
2851 | stagger = 0x2; |
2851 | stagger = 0x2; |
2852 | 2852 | ||
2853 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2853 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
2854 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2854 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2855 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2855 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
2856 | 2856 | ||
2857 | if (intel_crtc->config->lane_count > 2) { |
2857 | if (intel_crtc->config->lane_count > 2) { |
2858 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2858 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
2859 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2859 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
2860 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2860 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
2861 | } |
2861 | } |
2862 | 2862 | ||
2863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
2863 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), |
2864 | DPIO_LANESTAGGER_STRAP(stagger) | |
2864 | DPIO_LANESTAGGER_STRAP(stagger) | |
2865 | DPIO_LANESTAGGER_STRAP_OVRD | |
2865 | DPIO_LANESTAGGER_STRAP_OVRD | |
2866 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2866 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2867 | DPIO_TX1_STAGGER_MULT(6) | |
2867 | DPIO_TX1_STAGGER_MULT(6) | |
2868 | DPIO_TX2_STAGGER_MULT(0)); |
2868 | DPIO_TX2_STAGGER_MULT(0)); |
2869 | 2869 | ||
2870 | if (intel_crtc->config->lane_count > 2) { |
2870 | if (intel_crtc->config->lane_count > 2) { |
2871 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
2871 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
2872 | DPIO_LANESTAGGER_STRAP(stagger) | |
2872 | DPIO_LANESTAGGER_STRAP(stagger) | |
2873 | DPIO_LANESTAGGER_STRAP_OVRD | |
2873 | DPIO_LANESTAGGER_STRAP_OVRD | |
2874 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2874 | DPIO_TX1_STAGGER_MASK(0x1f) | |
2875 | DPIO_TX1_STAGGER_MULT(7) | |
2875 | DPIO_TX1_STAGGER_MULT(7) | |
2876 | DPIO_TX2_STAGGER_MULT(5)); |
2876 | DPIO_TX2_STAGGER_MULT(5)); |
2877 | } |
2877 | } |
2878 | 2878 | ||
2879 | /* Deassert data lane reset */ |
2879 | /* Deassert data lane reset */ |
2880 | chv_data_lane_soft_reset(encoder, false); |
2880 | chv_data_lane_soft_reset(encoder, false); |
2881 | 2881 | ||
2882 | mutex_unlock(&dev_priv->sb_lock); |
2882 | mutex_unlock(&dev_priv->sb_lock); |
2883 | 2883 | ||
2884 | intel_enable_dp(encoder); |
2884 | intel_enable_dp(encoder); |
2885 | 2885 | ||
2886 | /* Second common lane will stay alive on its own now */ |
2886 | /* Second common lane will stay alive on its own now */ |
2887 | if (dport->release_cl2_override) { |
2887 | if (dport->release_cl2_override) { |
2888 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
2888 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
2889 | dport->release_cl2_override = false; |
2889 | dport->release_cl2_override = false; |
2890 | } |
2890 | } |
2891 | } |
2891 | } |
2892 | 2892 | ||
2893 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2893 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2894 | { |
2894 | { |
2895 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2895 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
2896 | struct drm_device *dev = encoder->base.dev; |
2896 | struct drm_device *dev = encoder->base.dev; |
2897 | struct drm_i915_private *dev_priv = dev->dev_private; |
2897 | struct drm_i915_private *dev_priv = dev->dev_private; |
2898 | struct intel_crtc *intel_crtc = |
2898 | struct intel_crtc *intel_crtc = |
2899 | to_intel_crtc(encoder->base.crtc); |
2899 | to_intel_crtc(encoder->base.crtc); |
2900 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2900 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2901 | enum pipe pipe = intel_crtc->pipe; |
2901 | enum pipe pipe = intel_crtc->pipe; |
2902 | unsigned int lane_mask = |
2902 | unsigned int lane_mask = |
2903 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
2903 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); |
2904 | u32 val; |
2904 | u32 val; |
2905 | 2905 | ||
2906 | intel_dp_prepare(encoder); |
2906 | intel_dp_prepare(encoder); |
2907 | 2907 | ||
2908 | /* |
2908 | /* |
2909 | * Must trick the second common lane into life. |
2909 | * Must trick the second common lane into life. |
2910 | * Otherwise we can't even access the PLL. |
2910 | * Otherwise we can't even access the PLL. |
2911 | */ |
2911 | */ |
2912 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
2912 | if (ch == DPIO_CH0 && pipe == PIPE_B) |
2913 | dport->release_cl2_override = |
2913 | dport->release_cl2_override = |
2914 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
2914 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
2915 | 2915 | ||
2916 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
2916 | chv_phy_powergate_lanes(encoder, true, lane_mask); |
2917 | 2917 | ||
2918 | mutex_lock(&dev_priv->sb_lock); |
2918 | mutex_lock(&dev_priv->sb_lock); |
2919 | 2919 | ||
2920 | /* Assert data lane reset */ |
2920 | /* Assert data lane reset */ |
2921 | chv_data_lane_soft_reset(encoder, true); |
2921 | chv_data_lane_soft_reset(encoder, true); |
2922 | 2922 | ||
2923 | /* program left/right clock distribution */ |
2923 | /* program left/right clock distribution */ |
2924 | if (pipe != PIPE_B) { |
2924 | if (pipe != PIPE_B) { |
2925 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2925 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2926 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2926 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2927 | if (ch == DPIO_CH0) |
2927 | if (ch == DPIO_CH0) |
2928 | val |= CHV_BUFLEFTENA1_FORCE; |
2928 | val |= CHV_BUFLEFTENA1_FORCE; |
2929 | if (ch == DPIO_CH1) |
2929 | if (ch == DPIO_CH1) |
2930 | val |= CHV_BUFRIGHTENA1_FORCE; |
2930 | val |= CHV_BUFRIGHTENA1_FORCE; |
2931 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2931 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2932 | } else { |
2932 | } else { |
2933 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2933 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2934 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2934 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2935 | if (ch == DPIO_CH0) |
2935 | if (ch == DPIO_CH0) |
2936 | val |= CHV_BUFLEFTENA2_FORCE; |
2936 | val |= CHV_BUFLEFTENA2_FORCE; |
2937 | if (ch == DPIO_CH1) |
2937 | if (ch == DPIO_CH1) |
2938 | val |= CHV_BUFRIGHTENA2_FORCE; |
2938 | val |= CHV_BUFRIGHTENA2_FORCE; |
2939 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2939 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2940 | } |
2940 | } |
2941 | 2941 | ||
2942 | /* program clock channel usage */ |
2942 | /* program clock channel usage */ |
2943 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
2943 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
2944 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2944 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2945 | if (pipe != PIPE_B) |
2945 | if (pipe != PIPE_B) |
2946 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2946 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2947 | else |
2947 | else |
2948 | val |= CHV_PCS_USEDCLKCHANNEL; |
2948 | val |= CHV_PCS_USEDCLKCHANNEL; |
2949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
2949 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
2950 | 2950 | ||
2951 | if (intel_crtc->config->lane_count > 2) { |
2951 | if (intel_crtc->config->lane_count > 2) { |
2952 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
2952 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
2953 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2953 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
2954 | if (pipe != PIPE_B) |
2954 | if (pipe != PIPE_B) |
2955 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2955 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
2956 | else |
2956 | else |
2957 | val |= CHV_PCS_USEDCLKCHANNEL; |
2957 | val |= CHV_PCS_USEDCLKCHANNEL; |
2958 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
2958 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
2959 | } |
2959 | } |
2960 | 2960 | ||
2961 | /* |
2961 | /* |
2962 | * This a a bit weird since generally CL |
2962 | * This a a bit weird since generally CL |
2963 | * matches the pipe, but here we need to |
2963 | * matches the pipe, but here we need to |
2964 | * pick the CL based on the port. |
2964 | * pick the CL based on the port. |
2965 | */ |
2965 | */ |
2966 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
2966 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
2967 | if (pipe != PIPE_B) |
2967 | if (pipe != PIPE_B) |
2968 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
2968 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
2969 | else |
2969 | else |
2970 | val |= CHV_CMN_USEDCLKCHANNEL; |
2970 | val |= CHV_CMN_USEDCLKCHANNEL; |
2971 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
2971 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
2972 | 2972 | ||
2973 | mutex_unlock(&dev_priv->sb_lock); |
2973 | mutex_unlock(&dev_priv->sb_lock); |
2974 | } |
2974 | } |
2975 | 2975 | ||
2976 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2976 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2977 | { |
2977 | { |
2978 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2978 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2979 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
2979 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
2980 | u32 val; |
2980 | u32 val; |
2981 | 2981 | ||
2982 | mutex_lock(&dev_priv->sb_lock); |
2982 | mutex_lock(&dev_priv->sb_lock); |
2983 | 2983 | ||
2984 | /* disable left/right clock distribution */ |
2984 | /* disable left/right clock distribution */ |
2985 | if (pipe != PIPE_B) { |
2985 | if (pipe != PIPE_B) { |
2986 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2986 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
2987 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2987 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
2988 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2988 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
2989 | } else { |
2989 | } else { |
2990 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2990 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
2991 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2991 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
2992 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2992 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
2993 | } |
2993 | } |
2994 | 2994 | ||
2995 | mutex_unlock(&dev_priv->sb_lock); |
2995 | mutex_unlock(&dev_priv->sb_lock); |
2996 | 2996 | ||
2997 | /* |
2997 | /* |
2998 | * Leave the power down bit cleared for at least one |
2998 | * Leave the power down bit cleared for at least one |
2999 | * lane so that chv_powergate_phy_ch() will power |
2999 | * lane so that chv_powergate_phy_ch() will power |
3000 | * on something when the channel is otherwise unused. |
3000 | * on something when the channel is otherwise unused. |
3001 | * When the port is off and the override is removed |
3001 | * When the port is off and the override is removed |
3002 | * the lanes power down anyway, so otherwise it doesn't |
3002 | * the lanes power down anyway, so otherwise it doesn't |
3003 | * really matter what the state of power down bits is |
3003 | * really matter what the state of power down bits is |
3004 | * after this. |
3004 | * after this. |
3005 | */ |
3005 | */ |
3006 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3006 | chv_phy_powergate_lanes(encoder, false, 0x0); |
3007 | } |
3007 | } |
3008 | 3008 | ||
3009 | /* |
3009 | /* |
3010 | * Native read with retry for link status and receiver capability reads for |
3010 | * Native read with retry for link status and receiver capability reads for |
3011 | * cases where the sink may still be asleep. |
3011 | * cases where the sink may still be asleep. |
3012 | * |
3012 | * |
3013 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3013 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
3014 | * supposed to retry 3 times per the spec. |
3014 | * supposed to retry 3 times per the spec. |
3015 | */ |
3015 | */ |
3016 | static ssize_t |
3016 | static ssize_t |
3017 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3017 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
3018 | void *buffer, size_t size) |
3018 | void *buffer, size_t size) |
3019 | { |
3019 | { |
3020 | ssize_t ret; |
3020 | ssize_t ret; |
3021 | int i; |
3021 | int i; |
3022 | 3022 | ||
3023 | /* |
3023 | /* |
3024 | * Sometime we just get the same incorrect byte repeated |
3024 | * Sometime we just get the same incorrect byte repeated |
3025 | * over the entire buffer. Doing just one throw away read |
3025 | * over the entire buffer. Doing just one throw away read |
3026 | * initially seems to "solve" it. |
3026 | * initially seems to "solve" it. |
3027 | */ |
3027 | */ |
3028 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3028 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); |
3029 | 3029 | ||
3030 | for (i = 0; i < 3; i++) { |
3030 | for (i = 0; i < 3; i++) { |
3031 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3031 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3032 | if (ret == size) |
3032 | if (ret == size) |
3033 | return ret; |
3033 | return ret; |
3034 | msleep(1); |
3034 | msleep(1); |
3035 | } |
3035 | } |
3036 | 3036 | ||
3037 | return ret; |
3037 | return ret; |
3038 | } |
3038 | } |
3039 | 3039 | ||
3040 | /* |
3040 | /* |
3041 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3041 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
3042 | * link status information |
3042 | * link status information |
3043 | */ |
3043 | */ |
3044 | static bool |
3044 | static bool |
3045 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3045 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3046 | { |
3046 | { |
3047 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3047 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3048 | DP_LANE0_1_STATUS, |
3048 | DP_LANE0_1_STATUS, |
3049 | link_status, |
3049 | link_status, |
3050 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3050 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
3051 | } |
3051 | } |
3052 | 3052 | ||
3053 | /* These are source-specific values. */ |
3053 | /* These are source-specific values. */ |
3054 | static uint8_t |
3054 | static uint8_t |
3055 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3055 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
3056 | { |
3056 | { |
3057 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3057 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3058 | struct drm_i915_private *dev_priv = dev->dev_private; |
3058 | struct drm_i915_private *dev_priv = dev->dev_private; |
3059 | enum port port = dp_to_dig_port(intel_dp)->port; |
3059 | enum port port = dp_to_dig_port(intel_dp)->port; |
3060 | 3060 | ||
3061 | if (IS_BROXTON(dev)) |
3061 | if (IS_BROXTON(dev)) |
3062 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3062 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3063 | else if (INTEL_INFO(dev)->gen >= 9) { |
3063 | else if (INTEL_INFO(dev)->gen >= 9) { |
3064 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3064 | if (dev_priv->edp_low_vswing && port == PORT_A) |
3065 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3065 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3066 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3066 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3067 | } else if (IS_VALLEYVIEW(dev)) |
3067 | } else if (IS_VALLEYVIEW(dev)) |
3068 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3068 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3069 | else if (IS_GEN7(dev) && port == PORT_A) |
3069 | else if (IS_GEN7(dev) && port == PORT_A) |
3070 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3070 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3071 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3071 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
3072 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3072 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3073 | else |
3073 | else |
3074 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3074 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
3075 | } |
3075 | } |
3076 | 3076 | ||
3077 | static uint8_t |
3077 | static uint8_t |
3078 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3078 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3079 | { |
3079 | { |
3080 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3080 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3081 | enum port port = dp_to_dig_port(intel_dp)->port; |
3081 | enum port port = dp_to_dig_port(intel_dp)->port; |
3082 | 3082 | ||
3083 | if (INTEL_INFO(dev)->gen >= 9) { |
3083 | if (INTEL_INFO(dev)->gen >= 9) { |
3084 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3084 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3085 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3085 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3086 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3086 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3087 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3087 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3088 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3088 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3090 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3090 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3091 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3091 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3092 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3092 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3093 | default: |
3093 | default: |
3094 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3094 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3095 | } |
3095 | } |
3096 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3096 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3097 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3097 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3099 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3099 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3101 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3101 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3102 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3102 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3103 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3103 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3105 | default: |
3105 | default: |
3106 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3106 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3107 | } |
3107 | } |
3108 | } else if (IS_VALLEYVIEW(dev)) { |
3108 | } else if (IS_VALLEYVIEW(dev)) { |
3109 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3109 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3110 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3110 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3111 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3111 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3113 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3113 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3115 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3115 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3116 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3116 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3117 | default: |
3117 | default: |
3118 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3118 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3119 | } |
3119 | } |
3120 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3120 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3121 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3121 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3123 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3123 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3125 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3125 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3126 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3126 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3127 | default: |
3127 | default: |
3128 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3128 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3129 | } |
3129 | } |
3130 | } else { |
3130 | } else { |
3131 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3131 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3132 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3132 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3133 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3133 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3134 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3134 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3135 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3135 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3137 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3137 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
3138 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3138 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3139 | default: |
3139 | default: |
3140 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3140 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
3141 | } |
3141 | } |
3142 | } |
3142 | } |
3143 | } |
3143 | } |
3144 | 3144 | ||
3145 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3145 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
3146 | { |
3146 | { |
3147 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3147 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3148 | struct drm_i915_private *dev_priv = dev->dev_private; |
3148 | struct drm_i915_private *dev_priv = dev->dev_private; |
3149 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3149 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3150 | struct intel_crtc *intel_crtc = |
3150 | struct intel_crtc *intel_crtc = |
3151 | to_intel_crtc(dport->base.base.crtc); |
3151 | to_intel_crtc(dport->base.base.crtc); |
3152 | unsigned long demph_reg_value, preemph_reg_value, |
3152 | unsigned long demph_reg_value, preemph_reg_value, |
3153 | uniqtranscale_reg_value; |
3153 | uniqtranscale_reg_value; |
3154 | uint8_t train_set = intel_dp->train_set[0]; |
3154 | uint8_t train_set = intel_dp->train_set[0]; |
3155 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3155 | enum dpio_channel port = vlv_dport_to_channel(dport); |
3156 | int pipe = intel_crtc->pipe; |
3156 | int pipe = intel_crtc->pipe; |
3157 | 3157 | ||
3158 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3158 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3159 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3159 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3160 | preemph_reg_value = 0x0004000; |
3160 | preemph_reg_value = 0x0004000; |
3161 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3161 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3162 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3162 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3163 | demph_reg_value = 0x2B405555; |
3163 | demph_reg_value = 0x2B405555; |
3164 | uniqtranscale_reg_value = 0x552AB83A; |
3164 | uniqtranscale_reg_value = 0x552AB83A; |
3165 | break; |
3165 | break; |
3166 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3166 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3167 | demph_reg_value = 0x2B404040; |
3167 | demph_reg_value = 0x2B404040; |
3168 | uniqtranscale_reg_value = 0x5548B83A; |
3168 | uniqtranscale_reg_value = 0x5548B83A; |
3169 | break; |
3169 | break; |
3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3171 | demph_reg_value = 0x2B245555; |
3171 | demph_reg_value = 0x2B245555; |
3172 | uniqtranscale_reg_value = 0x5560B83A; |
3172 | uniqtranscale_reg_value = 0x5560B83A; |
3173 | break; |
3173 | break; |
3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3175 | demph_reg_value = 0x2B405555; |
3175 | demph_reg_value = 0x2B405555; |
3176 | uniqtranscale_reg_value = 0x5598DA3A; |
3176 | uniqtranscale_reg_value = 0x5598DA3A; |
3177 | break; |
3177 | break; |
3178 | default: |
3178 | default: |
3179 | return 0; |
3179 | return 0; |
3180 | } |
3180 | } |
3181 | break; |
3181 | break; |
3182 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3182 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3183 | preemph_reg_value = 0x0002000; |
3183 | preemph_reg_value = 0x0002000; |
3184 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3184 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3186 | demph_reg_value = 0x2B404040; |
3186 | demph_reg_value = 0x2B404040; |
3187 | uniqtranscale_reg_value = 0x5552B83A; |
3187 | uniqtranscale_reg_value = 0x5552B83A; |
3188 | break; |
3188 | break; |
3189 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3189 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3190 | demph_reg_value = 0x2B404848; |
3190 | demph_reg_value = 0x2B404848; |
3191 | uniqtranscale_reg_value = 0x5580B83A; |
3191 | uniqtranscale_reg_value = 0x5580B83A; |
3192 | break; |
3192 | break; |
3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3194 | demph_reg_value = 0x2B404040; |
3194 | demph_reg_value = 0x2B404040; |
3195 | uniqtranscale_reg_value = 0x55ADDA3A; |
3195 | uniqtranscale_reg_value = 0x55ADDA3A; |
3196 | break; |
3196 | break; |
3197 | default: |
3197 | default: |
3198 | return 0; |
3198 | return 0; |
3199 | } |
3199 | } |
3200 | break; |
3200 | break; |
3201 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3201 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3202 | preemph_reg_value = 0x0000000; |
3202 | preemph_reg_value = 0x0000000; |
3203 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3203 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3205 | demph_reg_value = 0x2B305555; |
3205 | demph_reg_value = 0x2B305555; |
3206 | uniqtranscale_reg_value = 0x5570B83A; |
3206 | uniqtranscale_reg_value = 0x5570B83A; |
3207 | break; |
3207 | break; |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3209 | demph_reg_value = 0x2B2B4040; |
3209 | demph_reg_value = 0x2B2B4040; |
3210 | uniqtranscale_reg_value = 0x55ADDA3A; |
3210 | uniqtranscale_reg_value = 0x55ADDA3A; |
3211 | break; |
3211 | break; |
3212 | default: |
3212 | default: |
3213 | return 0; |
3213 | return 0; |
3214 | } |
3214 | } |
3215 | break; |
3215 | break; |
3216 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3216 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3217 | preemph_reg_value = 0x0006000; |
3217 | preemph_reg_value = 0x0006000; |
3218 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3218 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3220 | demph_reg_value = 0x1B405555; |
3220 | demph_reg_value = 0x1B405555; |
3221 | uniqtranscale_reg_value = 0x55ADDA3A; |
3221 | uniqtranscale_reg_value = 0x55ADDA3A; |
3222 | break; |
3222 | break; |
3223 | default: |
3223 | default: |
3224 | return 0; |
3224 | return 0; |
3225 | } |
3225 | } |
3226 | break; |
3226 | break; |
3227 | default: |
3227 | default: |
3228 | return 0; |
3228 | return 0; |
3229 | } |
3229 | } |
3230 | 3230 | ||
3231 | mutex_lock(&dev_priv->sb_lock); |
3231 | mutex_lock(&dev_priv->sb_lock); |
3232 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3232 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3233 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3233 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
3234 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3234 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
3235 | uniqtranscale_reg_value); |
3235 | uniqtranscale_reg_value); |
3236 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3236 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3237 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3237 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
3238 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3238 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
3239 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3239 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
3240 | mutex_unlock(&dev_priv->sb_lock); |
3240 | mutex_unlock(&dev_priv->sb_lock); |
3241 | 3241 | ||
3242 | return 0; |
3242 | return 0; |
3243 | } |
3243 | } |
3244 | 3244 | ||
3245 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3245 | static bool chv_need_uniq_trans_scale(uint8_t train_set) |
3246 | { |
3246 | { |
3247 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3247 | return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && |
3248 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3248 | (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
3249 | } |
3249 | } |
3250 | 3250 | ||
3251 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3251 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
3252 | { |
3252 | { |
3253 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3253 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
3255 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3255 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
3256 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3256 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
3257 | u32 deemph_reg_value, margin_reg_value, val; |
3257 | u32 deemph_reg_value, margin_reg_value, val; |
3258 | uint8_t train_set = intel_dp->train_set[0]; |
3258 | uint8_t train_set = intel_dp->train_set[0]; |
3259 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3259 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
3260 | enum pipe pipe = intel_crtc->pipe; |
3260 | enum pipe pipe = intel_crtc->pipe; |
3261 | int i; |
3261 | int i; |
3262 | 3262 | ||
3263 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3263 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3264 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3264 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3265 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3265 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3266 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3266 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3267 | deemph_reg_value = 128; |
3267 | deemph_reg_value = 128; |
3268 | margin_reg_value = 52; |
3268 | margin_reg_value = 52; |
3269 | break; |
3269 | break; |
3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3270 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3271 | deemph_reg_value = 128; |
3271 | deemph_reg_value = 128; |
3272 | margin_reg_value = 77; |
3272 | margin_reg_value = 77; |
3273 | break; |
3273 | break; |
3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3275 | deemph_reg_value = 128; |
3275 | deemph_reg_value = 128; |
3276 | margin_reg_value = 102; |
3276 | margin_reg_value = 102; |
3277 | break; |
3277 | break; |
3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3279 | deemph_reg_value = 128; |
3279 | deemph_reg_value = 128; |
3280 | margin_reg_value = 154; |
3280 | margin_reg_value = 154; |
3281 | /* FIXME extra to set for 1200 */ |
3281 | /* FIXME extra to set for 1200 */ |
3282 | break; |
3282 | break; |
3283 | default: |
3283 | default: |
3284 | return 0; |
3284 | return 0; |
3285 | } |
3285 | } |
3286 | break; |
3286 | break; |
3287 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3287 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3288 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3288 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3290 | deemph_reg_value = 85; |
3290 | deemph_reg_value = 85; |
3291 | margin_reg_value = 78; |
3291 | margin_reg_value = 78; |
3292 | break; |
3292 | break; |
3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3294 | deemph_reg_value = 85; |
3294 | deemph_reg_value = 85; |
3295 | margin_reg_value = 116; |
3295 | margin_reg_value = 116; |
3296 | break; |
3296 | break; |
3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3298 | deemph_reg_value = 85; |
3298 | deemph_reg_value = 85; |
3299 | margin_reg_value = 154; |
3299 | margin_reg_value = 154; |
3300 | break; |
3300 | break; |
3301 | default: |
3301 | default: |
3302 | return 0; |
3302 | return 0; |
3303 | } |
3303 | } |
3304 | break; |
3304 | break; |
3305 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3305 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3306 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3306 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3308 | deemph_reg_value = 64; |
3308 | deemph_reg_value = 64; |
3309 | margin_reg_value = 104; |
3309 | margin_reg_value = 104; |
3310 | break; |
3310 | break; |
3311 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3311 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3312 | deemph_reg_value = 64; |
3312 | deemph_reg_value = 64; |
3313 | margin_reg_value = 154; |
3313 | margin_reg_value = 154; |
3314 | break; |
3314 | break; |
3315 | default: |
3315 | default: |
3316 | return 0; |
3316 | return 0; |
3317 | } |
3317 | } |
3318 | break; |
3318 | break; |
3319 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3319 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3320 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3320 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3322 | deemph_reg_value = 43; |
3322 | deemph_reg_value = 43; |
3323 | margin_reg_value = 154; |
3323 | margin_reg_value = 154; |
3324 | break; |
3324 | break; |
3325 | default: |
3325 | default: |
3326 | return 0; |
3326 | return 0; |
3327 | } |
3327 | } |
3328 | break; |
3328 | break; |
3329 | default: |
3329 | default: |
3330 | return 0; |
3330 | return 0; |
3331 | } |
3331 | } |
3332 | 3332 | ||
3333 | mutex_lock(&dev_priv->sb_lock); |
3333 | mutex_lock(&dev_priv->sb_lock); |
3334 | 3334 | ||
3335 | /* Clear calc init */ |
3335 | /* Clear calc init */ |
3336 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3336 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3337 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3337 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3338 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3338 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3339 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3339 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3340 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3340 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3341 | 3341 | ||
3342 | if (intel_crtc->config->lane_count > 2) { |
3342 | if (intel_crtc->config->lane_count > 2) { |
3343 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3343 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3344 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3344 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
3345 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3345 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3346 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3346 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
3347 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3347 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3348 | } |
3348 | } |
3349 | 3349 | ||
3350 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3350 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3351 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3351 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3352 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3352 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3353 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3353 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
3354 | 3354 | ||
3355 | if (intel_crtc->config->lane_count > 2) { |
3355 | if (intel_crtc->config->lane_count > 2) { |
3356 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3356 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
3357 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3357 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
3358 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3358 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
3359 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3359 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
3360 | } |
3360 | } |
3361 | 3361 | ||
3362 | /* Program swing deemph */ |
3362 | /* Program swing deemph */ |
3363 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3363 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3364 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3364 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
3365 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3365 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
3366 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3366 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
3367 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3367 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
3368 | } |
3368 | } |
3369 | 3369 | ||
3370 | /* Program swing margin */ |
3370 | /* Program swing margin */ |
3371 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3371 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3372 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3372 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
3373 | 3373 | ||
3374 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3374 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3375 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3375 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
3376 | 3376 | ||
3377 | /* |
3377 | /* |
3378 | * Supposedly this value shouldn't matter when unique transition |
3378 | * Supposedly this value shouldn't matter when unique transition |
3379 | * scale is disabled, but in fact it does matter. Let's just |
3379 | * scale is disabled, but in fact it does matter. Let's just |
3380 | * always program the same value and hope it's OK. |
3380 | * always program the same value and hope it's OK. |
3381 | */ |
3381 | */ |
3382 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3382 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
3383 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3383 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; |
3384 | 3384 | ||
3385 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3385 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3386 | } |
3386 | } |
3387 | 3387 | ||
3388 | /* |
3388 | /* |
3389 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3389 | * The document said it needs to set bit 27 for ch0 and bit 26 |
3390 | * for ch1. Might be a typo in the doc. |
3390 | * for ch1. Might be a typo in the doc. |
3391 | * For now, for this unique transition scale selection, set bit |
3391 | * For now, for this unique transition scale selection, set bit |
3392 | * 27 for ch0 and ch1. |
3392 | * 27 for ch0 and ch1. |
3393 | */ |
3393 | */ |
3394 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3394 | for (i = 0; i < intel_crtc->config->lane_count; i++) { |
3395 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3395 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
3396 | if (chv_need_uniq_trans_scale(train_set)) |
3396 | if (chv_need_uniq_trans_scale(train_set)) |
3397 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3397 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3398 | else |
3398 | else |
3399 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3399 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
3400 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3400 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
3401 | } |
3401 | } |
3402 | 3402 | ||
3403 | /* Start swing calculation */ |
3403 | /* Start swing calculation */ |
3404 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3404 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3405 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3405 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3406 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3406 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3407 | 3407 | ||
3408 | if (intel_crtc->config->lane_count > 2) { |
3408 | if (intel_crtc->config->lane_count > 2) { |
3409 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3409 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
3410 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3410 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
3411 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3411 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
3412 | } |
3412 | } |
3413 | 3413 | ||
3414 | mutex_unlock(&dev_priv->sb_lock); |
3414 | mutex_unlock(&dev_priv->sb_lock); |
3415 | 3415 | ||
3416 | return 0; |
3416 | return 0; |
3417 | } |
3417 | } |
3418 | 3418 | ||
3419 | static void |
3419 | static void |
3420 | intel_get_adjust_train(struct intel_dp *intel_dp, |
3420 | intel_get_adjust_train(struct intel_dp *intel_dp, |
3421 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3421 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3422 | { |
3422 | { |
3423 | uint8_t v = 0; |
3423 | uint8_t v = 0; |
3424 | uint8_t p = 0; |
3424 | uint8_t p = 0; |
3425 | int lane; |
3425 | int lane; |
3426 | uint8_t voltage_max; |
3426 | uint8_t voltage_max; |
3427 | uint8_t preemph_max; |
3427 | uint8_t preemph_max; |
3428 | 3428 | ||
3429 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
3429 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
3430 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
3430 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
3431 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
3431 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
3432 | 3432 | ||
3433 | if (this_v > v) |
3433 | if (this_v > v) |
3434 | v = this_v; |
3434 | v = this_v; |
3435 | if (this_p > p) |
3435 | if (this_p > p) |
3436 | p = this_p; |
3436 | p = this_p; |
3437 | } |
3437 | } |
3438 | 3438 | ||
3439 | voltage_max = intel_dp_voltage_max(intel_dp); |
3439 | voltage_max = intel_dp_voltage_max(intel_dp); |
3440 | if (v >= voltage_max) |
3440 | if (v >= voltage_max) |
3441 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
3441 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
3442 | 3442 | ||
3443 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
3443 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
3444 | if (p >= preemph_max) |
3444 | if (p >= preemph_max) |
3445 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
3445 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
3446 | 3446 | ||
3447 | for (lane = 0; lane < 4; lane++) |
3447 | for (lane = 0; lane < 4; lane++) |
3448 | intel_dp->train_set[lane] = v | p; |
3448 | intel_dp->train_set[lane] = v | p; |
3449 | } |
3449 | } |
3450 | 3450 | ||
3451 | static uint32_t |
3451 | static uint32_t |
3452 | gen4_signal_levels(uint8_t train_set) |
3452 | gen4_signal_levels(uint8_t train_set) |
3453 | { |
3453 | { |
3454 | uint32_t signal_levels = 0; |
3454 | uint32_t signal_levels = 0; |
3455 | 3455 | ||
3456 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3456 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3458 | default: |
3458 | default: |
3459 | signal_levels |= DP_VOLTAGE_0_4; |
3459 | signal_levels |= DP_VOLTAGE_0_4; |
3460 | break; |
3460 | break; |
3461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
3462 | signal_levels |= DP_VOLTAGE_0_6; |
3462 | signal_levels |= DP_VOLTAGE_0_6; |
3463 | break; |
3463 | break; |
3464 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3464 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
3465 | signal_levels |= DP_VOLTAGE_0_8; |
3465 | signal_levels |= DP_VOLTAGE_0_8; |
3466 | break; |
3466 | break; |
3467 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3467 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3468 | signal_levels |= DP_VOLTAGE_1_2; |
3468 | signal_levels |= DP_VOLTAGE_1_2; |
3469 | break; |
3469 | break; |
3470 | } |
3470 | } |
3471 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3471 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
3472 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3472 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
3473 | default: |
3473 | default: |
3474 | signal_levels |= DP_PRE_EMPHASIS_0; |
3474 | signal_levels |= DP_PRE_EMPHASIS_0; |
3475 | break; |
3475 | break; |
3476 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3476 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
3477 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3477 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3478 | break; |
3478 | break; |
3479 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3479 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
3480 | signal_levels |= DP_PRE_EMPHASIS_6; |
3480 | signal_levels |= DP_PRE_EMPHASIS_6; |
3481 | break; |
3481 | break; |
3482 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3482 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
3483 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3483 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3484 | break; |
3484 | break; |
3485 | } |
3485 | } |
3486 | return signal_levels; |
3486 | return signal_levels; |
3487 | } |
3487 | } |
3488 | 3488 | ||
3489 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3489 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3490 | static uint32_t |
3490 | static uint32_t |
3491 | gen6_edp_signal_levels(uint8_t train_set) |
3491 | gen6_edp_signal_levels(uint8_t train_set) |
3492 | { |
3492 | { |
3493 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3493 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3494 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3494 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3495 | switch (signal_levels) { |
3495 | switch (signal_levels) { |
3496 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3496 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3497 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3497 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3498 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3498 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3499 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3499 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3500 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3500 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
3501 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3501 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3502 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3502 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3503 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3503 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
3504 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3504 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3505 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3505 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3506 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3506 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
3507 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3507 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3508 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3508 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3509 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3509 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
3510 | default: |
3510 | default: |
3511 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3511 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3512 | "0x%x\n", signal_levels); |
3512 | "0x%x\n", signal_levels); |
3513 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3513 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
3514 | } |
3514 | } |
3515 | } |
3515 | } |
3516 | 3516 | ||
3517 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3517 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3518 | static uint32_t |
3518 | static uint32_t |
3519 | gen7_edp_signal_levels(uint8_t train_set) |
3519 | gen7_edp_signal_levels(uint8_t train_set) |
3520 | { |
3520 | { |
3521 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3521 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3522 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3522 | DP_TRAIN_PRE_EMPHASIS_MASK); |
3523 | switch (signal_levels) { |
3523 | switch (signal_levels) { |
3524 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3524 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3525 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3525 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
3526 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3526 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3527 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3527 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
3528 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3528 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3529 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3529 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3530 | 3530 | ||
3531 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3531 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3532 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3532 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
3533 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3533 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3534 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3534 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3535 | 3535 | ||
3536 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3536 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3537 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3537 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
3538 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3538 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3539 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3539 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3540 | 3540 | ||
3541 | default: |
3541 | default: |
3542 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3542 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3543 | "0x%x\n", signal_levels); |
3543 | "0x%x\n", signal_levels); |
3544 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3544 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
3545 | } |
3545 | } |
3546 | } |
3546 | } |
3547 | 3547 | ||
3548 | /* Properly updates "DP" with the correct signal levels. */ |
3548 | /* Properly updates "DP" with the correct signal levels. */ |
3549 | static void |
3549 | static void |
3550 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
3550 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
3551 | { |
3551 | { |
3552 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3552 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3553 | enum port port = intel_dig_port->port; |
3553 | enum port port = intel_dig_port->port; |
3554 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3554 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3555 | uint32_t signal_levels, mask = 0; |
3555 | uint32_t signal_levels, mask = 0; |
3556 | uint8_t train_set = intel_dp->train_set[0]; |
3556 | uint8_t train_set = intel_dp->train_set[0]; |
3557 | 3557 | ||
3558 | if (HAS_DDI(dev)) { |
3558 | if (HAS_DDI(dev)) { |
3559 | signal_levels = ddi_signal_levels(intel_dp); |
3559 | signal_levels = ddi_signal_levels(intel_dp); |
3560 | 3560 | ||
3561 | if (IS_BROXTON(dev)) |
3561 | if (IS_BROXTON(dev)) |
3562 | signal_levels = 0; |
3562 | signal_levels = 0; |
3563 | else |
3563 | else |
3564 | mask = DDI_BUF_EMP_MASK; |
3564 | mask = DDI_BUF_EMP_MASK; |
3565 | } else if (IS_CHERRYVIEW(dev)) { |
3565 | } else if (IS_CHERRYVIEW(dev)) { |
3566 | signal_levels = chv_signal_levels(intel_dp); |
3566 | signal_levels = chv_signal_levels(intel_dp); |
3567 | } else if (IS_VALLEYVIEW(dev)) { |
3567 | } else if (IS_VALLEYVIEW(dev)) { |
3568 | signal_levels = vlv_signal_levels(intel_dp); |
3568 | signal_levels = vlv_signal_levels(intel_dp); |
3569 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3569 | } else if (IS_GEN7(dev) && port == PORT_A) { |
3570 | signal_levels = gen7_edp_signal_levels(train_set); |
3570 | signal_levels = gen7_edp_signal_levels(train_set); |
3571 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3571 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
3572 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3572 | } else if (IS_GEN6(dev) && port == PORT_A) { |
3573 | signal_levels = gen6_edp_signal_levels(train_set); |
3573 | signal_levels = gen6_edp_signal_levels(train_set); |
3574 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3574 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3575 | } else { |
3575 | } else { |
3576 | signal_levels = gen4_signal_levels(train_set); |
3576 | signal_levels = gen4_signal_levels(train_set); |
3577 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3577 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3578 | } |
3578 | } |
3579 | 3579 | ||
3580 | if (mask) |
3580 | if (mask) |
3581 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3581 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
3582 | 3582 | ||
3583 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3583 | DRM_DEBUG_KMS("Using vswing level %d\n", |
3584 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3584 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
3585 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3585 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
3586 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3586 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
3587 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3587 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
3588 | 3588 | ||
3589 | *DP = (*DP & ~mask) | signal_levels; |
3589 | *DP = (*DP & ~mask) | signal_levels; |
3590 | } |
3590 | } |
3591 | 3591 | ||
3592 | static bool |
3592 | static bool |
3593 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
3593 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
3594 | uint32_t *DP, |
3594 | uint32_t *DP, |
3595 | uint8_t dp_train_pat) |
3595 | uint8_t dp_train_pat) |
3596 | { |
3596 | { |
3597 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3597 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3598 | struct drm_i915_private *dev_priv = |
3598 | struct drm_i915_private *dev_priv = |
3599 | to_i915(intel_dig_port->base.base.dev); |
3599 | to_i915(intel_dig_port->base.base.dev); |
3600 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
3600 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
3601 | int ret, len; |
3601 | int ret, len; |
3602 | 3602 | ||
3603 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
3603 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
3604 | 3604 | ||
3605 | I915_WRITE(intel_dp->output_reg, *DP); |
3605 | I915_WRITE(intel_dp->output_reg, *DP); |
3606 | POSTING_READ(intel_dp->output_reg); |
3606 | POSTING_READ(intel_dp->output_reg); |
3607 | 3607 | ||
3608 | buf[0] = dp_train_pat; |
3608 | buf[0] = dp_train_pat; |
3609 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
3609 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
3610 | DP_TRAINING_PATTERN_DISABLE) { |
3610 | DP_TRAINING_PATTERN_DISABLE) { |
3611 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
3611 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
3612 | len = 1; |
3612 | len = 1; |
3613 | } else { |
3613 | } else { |
3614 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
3614 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
3615 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
3615 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
3616 | len = intel_dp->lane_count + 1; |
3616 | len = intel_dp->lane_count + 1; |
3617 | } |
3617 | } |
3618 | 3618 | ||
3619 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
3619 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
3620 | buf, len); |
3620 | buf, len); |
3621 | 3621 | ||
3622 | return ret == len; |
3622 | return ret == len; |
3623 | } |
3623 | } |
3624 | 3624 | ||
3625 | static bool |
3625 | static bool |
3626 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
3626 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
3627 | uint8_t dp_train_pat) |
3627 | uint8_t dp_train_pat) |
3628 | { |
3628 | { |
3629 | if (!intel_dp->train_set_valid) |
3629 | if (!intel_dp->train_set_valid) |
3630 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
3630 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
3631 | intel_dp_set_signal_levels(intel_dp, DP); |
3631 | intel_dp_set_signal_levels(intel_dp, DP); |
3632 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
3632 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
3633 | } |
3633 | } |
3634 | 3634 | ||
3635 | static bool |
3635 | static bool |
3636 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
3636 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
3637 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3637 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
3638 | { |
3638 | { |
3639 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3639 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3640 | struct drm_i915_private *dev_priv = |
3640 | struct drm_i915_private *dev_priv = |
3641 | to_i915(intel_dig_port->base.base.dev); |
3641 | to_i915(intel_dig_port->base.base.dev); |
3642 | int ret; |
3642 | int ret; |
3643 | 3643 | ||
3644 | intel_get_adjust_train(intel_dp, link_status); |
3644 | intel_get_adjust_train(intel_dp, link_status); |
3645 | intel_dp_set_signal_levels(intel_dp, DP); |
3645 | intel_dp_set_signal_levels(intel_dp, DP); |
3646 | 3646 | ||
3647 | I915_WRITE(intel_dp->output_reg, *DP); |
3647 | I915_WRITE(intel_dp->output_reg, *DP); |
3648 | POSTING_READ(intel_dp->output_reg); |
3648 | POSTING_READ(intel_dp->output_reg); |
3649 | 3649 | ||
3650 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
3650 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
3651 | intel_dp->train_set, intel_dp->lane_count); |
3651 | intel_dp->train_set, intel_dp->lane_count); |
3652 | 3652 | ||
3653 | return ret == intel_dp->lane_count; |
3653 | return ret == intel_dp->lane_count; |
3654 | } |
3654 | } |
3655 | 3655 | ||
3656 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3656 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3657 | { |
3657 | { |
3658 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3658 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3659 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3659 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3660 | struct drm_i915_private *dev_priv = dev->dev_private; |
3660 | struct drm_i915_private *dev_priv = dev->dev_private; |
3661 | enum port port = intel_dig_port->port; |
3661 | enum port port = intel_dig_port->port; |
3662 | uint32_t val; |
3662 | uint32_t val; |
3663 | 3663 | ||
3664 | if (!HAS_DDI(dev)) |
3664 | if (!HAS_DDI(dev)) |
3665 | return; |
3665 | return; |
3666 | 3666 | ||
3667 | val = I915_READ(DP_TP_CTL(port)); |
3667 | val = I915_READ(DP_TP_CTL(port)); |
3668 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3668 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
3669 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3669 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
3670 | I915_WRITE(DP_TP_CTL(port), val); |
3670 | I915_WRITE(DP_TP_CTL(port), val); |
3671 | 3671 | ||
3672 | /* |
3672 | /* |
3673 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3673 | * On PORT_A we can have only eDP in SST mode. There the only reason |
3674 | * we need to set idle transmission mode is to work around a HW issue |
3674 | * we need to set idle transmission mode is to work around a HW issue |
3675 | * where we enable the pipe while not in idle link-training mode. |
3675 | * where we enable the pipe while not in idle link-training mode. |
3676 | * In this case there is requirement to wait for a minimum number of |
3676 | * In this case there is requirement to wait for a minimum number of |
3677 | * idle patterns to be sent. |
3677 | * idle patterns to be sent. |
3678 | */ |
3678 | */ |
3679 | if (port == PORT_A) |
3679 | if (port == PORT_A) |
3680 | return; |
3680 | return; |
3681 | 3681 | ||
3682 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3682 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
3683 | 1)) |
3683 | 1)) |
3684 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3684 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3685 | } |
3685 | } |
3686 | 3686 | ||
3687 | /* Enable corresponding port and start training pattern 1 */ |
3687 | /* Enable corresponding port and start training pattern 1 */ |
3688 | static void |
3688 | static void |
3689 | intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) |
3689 | intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) |
3690 | { |
3690 | { |
3691 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
3691 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
3692 | struct drm_device *dev = encoder->dev; |
3692 | struct drm_device *dev = encoder->dev; |
3693 | int i; |
3693 | int i; |
3694 | uint8_t voltage; |
3694 | uint8_t voltage; |
3695 | int voltage_tries, loop_tries; |
3695 | int voltage_tries, loop_tries; |
3696 | uint32_t DP = intel_dp->DP; |
3696 | uint32_t DP = intel_dp->DP; |
3697 | uint8_t link_config[2]; |
3697 | uint8_t link_config[2]; |
3698 | uint8_t link_bw, rate_select; |
3698 | uint8_t link_bw, rate_select; |
3699 | 3699 | ||
3700 | if (HAS_DDI(dev)) |
3700 | if (HAS_DDI(dev)) |
3701 | intel_ddi_prepare_link_retrain(encoder); |
3701 | intel_ddi_prepare_link_retrain(encoder); |
3702 | 3702 | ||
3703 | intel_dp_compute_rate(intel_dp, intel_dp->link_rate, |
3703 | intel_dp_compute_rate(intel_dp, intel_dp->link_rate, |
3704 | &link_bw, &rate_select); |
3704 | &link_bw, &rate_select); |
3705 | 3705 | ||
3706 | /* Write the link configuration data */ |
3706 | /* Write the link configuration data */ |
3707 | link_config[0] = link_bw; |
3707 | link_config[0] = link_bw; |
3708 | link_config[1] = intel_dp->lane_count; |
3708 | link_config[1] = intel_dp->lane_count; |
3709 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3709 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3710 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
3710 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
3711 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
3711 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
3712 | if (intel_dp->num_sink_rates) |
3712 | if (intel_dp->num_sink_rates) |
3713 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, |
3713 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, |
3714 | &rate_select, 1); |
3714 | &rate_select, 1); |
3715 | 3715 | ||
3716 | link_config[0] = 0; |
3716 | link_config[0] = 0; |
3717 | link_config[1] = DP_SET_ANSI_8B10B; |
3717 | link_config[1] = DP_SET_ANSI_8B10B; |
3718 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
3718 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
3719 | 3719 | ||
3720 | DP |= DP_PORT_EN; |
3720 | DP |= DP_PORT_EN; |
3721 | 3721 | ||
3722 | /* clock recovery */ |
3722 | /* clock recovery */ |
3723 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
3723 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
3724 | DP_TRAINING_PATTERN_1 | |
3724 | DP_TRAINING_PATTERN_1 | |
3725 | DP_LINK_SCRAMBLING_DISABLE)) { |
3725 | DP_LINK_SCRAMBLING_DISABLE)) { |
3726 | DRM_ERROR("failed to enable link training\n"); |
3726 | DRM_ERROR("failed to enable link training\n"); |
3727 | return; |
3727 | return; |
3728 | } |
3728 | } |
3729 | 3729 | ||
3730 | voltage = 0xff; |
3730 | voltage = 0xff; |
3731 | voltage_tries = 0; |
3731 | voltage_tries = 0; |
3732 | loop_tries = 0; |
3732 | loop_tries = 0; |
3733 | for (;;) { |
3733 | for (;;) { |
3734 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3734 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3735 | 3735 | ||
3736 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
3736 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
3737 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3737 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3738 | DRM_ERROR("failed to get link status\n"); |
3738 | DRM_ERROR("failed to get link status\n"); |
3739 | break; |
3739 | break; |
3740 | } |
3740 | } |
3741 | 3741 | ||
3742 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
3742 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
3743 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3743 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3744 | break; |
3744 | break; |
3745 | } |
3745 | } |
3746 | 3746 | ||
3747 | /* |
3747 | /* |
3748 | * if we used previously trained voltage and pre-emphasis values |
3748 | * if we used previously trained voltage and pre-emphasis values |
3749 | * and we don't get clock recovery, reset link training values |
3749 | * and we don't get clock recovery, reset link training values |
3750 | */ |
3750 | */ |
3751 | if (intel_dp->train_set_valid) { |
3751 | if (intel_dp->train_set_valid) { |
3752 | DRM_DEBUG_KMS("clock recovery not ok, reset"); |
3752 | DRM_DEBUG_KMS("clock recovery not ok, reset"); |
3753 | /* clear the flag as we are not reusing train set */ |
3753 | /* clear the flag as we are not reusing train set */ |
3754 | intel_dp->train_set_valid = false; |
3754 | intel_dp->train_set_valid = false; |
3755 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
3755 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
3756 | DP_TRAINING_PATTERN_1 | |
3756 | DP_TRAINING_PATTERN_1 | |
3757 | DP_LINK_SCRAMBLING_DISABLE)) { |
3757 | DP_LINK_SCRAMBLING_DISABLE)) { |
3758 | DRM_ERROR("failed to enable link training\n"); |
3758 | DRM_ERROR("failed to enable link training\n"); |
3759 | return; |
3759 | return; |
3760 | } |
3760 | } |
3761 | continue; |
3761 | continue; |
3762 | } |
3762 | } |
3763 | 3763 | ||
3764 | /* Check to see if we've tried the max voltage */ |
3764 | /* Check to see if we've tried the max voltage */ |
3765 | for (i = 0; i < intel_dp->lane_count; i++) |
3765 | for (i = 0; i < intel_dp->lane_count; i++) |
3766 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
3766 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
3767 | break; |
3767 | break; |
3768 | if (i == intel_dp->lane_count) { |
3768 | if (i == intel_dp->lane_count) { |
3769 | ++loop_tries; |
3769 | ++loop_tries; |
3770 | if (loop_tries == 5) { |
3770 | if (loop_tries == 5) { |
3771 | DRM_ERROR("too many full retries, give up\n"); |
3771 | DRM_ERROR("too many full retries, give up\n"); |
3772 | break; |
3772 | break; |
3773 | } |
3773 | } |
3774 | intel_dp_reset_link_train(intel_dp, &DP, |
3774 | intel_dp_reset_link_train(intel_dp, &DP, |
3775 | DP_TRAINING_PATTERN_1 | |
3775 | DP_TRAINING_PATTERN_1 | |
3776 | DP_LINK_SCRAMBLING_DISABLE); |
3776 | DP_LINK_SCRAMBLING_DISABLE); |
3777 | voltage_tries = 0; |
3777 | voltage_tries = 0; |
3778 | continue; |
3778 | continue; |
3779 | } |
3779 | } |
3780 | 3780 | ||
3781 | /* Check to see if we've tried the same voltage 5 times */ |
3781 | /* Check to see if we've tried the same voltage 5 times */ |
3782 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
3782 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
3783 | ++voltage_tries; |
3783 | ++voltage_tries; |
3784 | if (voltage_tries == 5) { |
3784 | if (voltage_tries == 5) { |
3785 | DRM_ERROR("too many voltage retries, give up\n"); |
3785 | DRM_ERROR("too many voltage retries, give up\n"); |
3786 | break; |
3786 | break; |
3787 | } |
3787 | } |
3788 | } else |
3788 | } else |
3789 | voltage_tries = 0; |
3789 | voltage_tries = 0; |
3790 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
3790 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
3791 | 3791 | ||
3792 | /* Update training set as requested by target */ |
3792 | /* Update training set as requested by target */ |
3793 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3793 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3794 | DRM_ERROR("failed to update link training\n"); |
3794 | DRM_ERROR("failed to update link training\n"); |
3795 | break; |
3795 | break; |
3796 | } |
3796 | } |
3797 | } |
3797 | } |
3798 | 3798 | ||
3799 | intel_dp->DP = DP; |
3799 | intel_dp->DP = DP; |
3800 | } |
3800 | } |
3801 | 3801 | ||
3802 | static void |
3802 | static void |
3803 | intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) |
3803 | intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) |
3804 | { |
3804 | { |
3805 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3805 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3806 | struct drm_device *dev = dig_port->base.base.dev; |
3806 | struct drm_device *dev = dig_port->base.base.dev; |
3807 | bool channel_eq = false; |
3807 | bool channel_eq = false; |
3808 | int tries, cr_tries; |
3808 | int tries, cr_tries; |
3809 | uint32_t DP = intel_dp->DP; |
3809 | uint32_t DP = intel_dp->DP; |
3810 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
3810 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
3811 | 3811 | ||
3812 | /* |
3812 | /* |
3813 | * Training Pattern 3 for HBR2 or 1.2 devices that support it. |
3813 | * Training Pattern 3 for HBR2 or 1.2 devices that support it. |
3814 | * |
3814 | * |
3815 | * Intel platforms that support HBR2 also support TPS3. TPS3 support is |
3815 | * Intel platforms that support HBR2 also support TPS3. TPS3 support is |
3816 | * also mandatory for downstream devices that support HBR2. |
3816 | * also mandatory for downstream devices that support HBR2. |
3817 | * |
3817 | * |
3818 | * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is |
3818 | * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is |
3819 | * supported but still not enabled. |
3819 | * supported but still not enabled. |
3820 | */ |
3820 | */ |
3821 | if (intel_dp_source_supports_hbr2(dev) && |
3821 | if (intel_dp_source_supports_hbr2(dev) && |
3822 | drm_dp_tps3_supported(intel_dp->dpcd)) |
3822 | drm_dp_tps3_supported(intel_dp->dpcd)) |
3823 | training_pattern = DP_TRAINING_PATTERN_3; |
3823 | training_pattern = DP_TRAINING_PATTERN_3; |
3824 | else if (intel_dp->link_rate == 540000) |
3824 | else if (intel_dp->link_rate == 540000) |
3825 | DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n"); |
3825 | DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n"); |
3826 | 3826 | ||
3827 | /* channel equalization */ |
3827 | /* channel equalization */ |
3828 | if (!intel_dp_set_link_train(intel_dp, &DP, |
3828 | if (!intel_dp_set_link_train(intel_dp, &DP, |
3829 | training_pattern | |
3829 | training_pattern | |
3830 | DP_LINK_SCRAMBLING_DISABLE)) { |
3830 | DP_LINK_SCRAMBLING_DISABLE)) { |
3831 | DRM_ERROR("failed to start channel equalization\n"); |
3831 | DRM_ERROR("failed to start channel equalization\n"); |
3832 | return; |
3832 | return; |
3833 | } |
3833 | } |
3834 | 3834 | ||
3835 | tries = 0; |
3835 | tries = 0; |
3836 | cr_tries = 0; |
3836 | cr_tries = 0; |
3837 | channel_eq = false; |
3837 | channel_eq = false; |
3838 | for (;;) { |
3838 | for (;;) { |
3839 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3839 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
3840 | 3840 | ||
3841 | if (cr_tries > 5) { |
3841 | if (cr_tries > 5) { |
3842 | DRM_ERROR("failed to train DP, aborting\n"); |
3842 | DRM_ERROR("failed to train DP, aborting\n"); |
3843 | break; |
3843 | break; |
3844 | } |
3844 | } |
3845 | 3845 | ||
3846 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
3846 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
3847 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3847 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3848 | DRM_ERROR("failed to get link status\n"); |
3848 | DRM_ERROR("failed to get link status\n"); |
3849 | break; |
3849 | break; |
3850 | } |
3850 | } |
3851 | 3851 | ||
3852 | /* Make sure clock is still ok */ |
3852 | /* Make sure clock is still ok */ |
3853 | if (!drm_dp_clock_recovery_ok(link_status, |
3853 | if (!drm_dp_clock_recovery_ok(link_status, |
3854 | intel_dp->lane_count)) { |
3854 | intel_dp->lane_count)) { |
3855 | intel_dp->train_set_valid = false; |
3855 | intel_dp->train_set_valid = false; |
3856 | intel_dp_link_training_clock_recovery(intel_dp); |
3856 | intel_dp_link_training_clock_recovery(intel_dp); |
3857 | intel_dp_set_link_train(intel_dp, &DP, |
3857 | intel_dp_set_link_train(intel_dp, &DP, |
3858 | training_pattern | |
3858 | training_pattern | |
3859 | DP_LINK_SCRAMBLING_DISABLE); |
3859 | DP_LINK_SCRAMBLING_DISABLE); |
3860 | cr_tries++; |
3860 | cr_tries++; |
3861 | continue; |
3861 | continue; |
3862 | } |
3862 | } |
3863 | 3863 | ||
3864 | if (drm_dp_channel_eq_ok(link_status, |
3864 | if (drm_dp_channel_eq_ok(link_status, |
3865 | intel_dp->lane_count)) { |
3865 | intel_dp->lane_count)) { |
3866 | channel_eq = true; |
3866 | channel_eq = true; |
3867 | break; |
3867 | break; |
3868 | } |
3868 | } |
3869 | 3869 | ||
3870 | /* Try 5 times, then try clock recovery if that fails */ |
3870 | /* Try 5 times, then try clock recovery if that fails */ |
3871 | if (tries > 5) { |
3871 | if (tries > 5) { |
3872 | intel_dp->train_set_valid = false; |
3872 | intel_dp->train_set_valid = false; |
3873 | intel_dp_link_training_clock_recovery(intel_dp); |
3873 | intel_dp_link_training_clock_recovery(intel_dp); |
3874 | intel_dp_set_link_train(intel_dp, &DP, |
3874 | intel_dp_set_link_train(intel_dp, &DP, |
3875 | training_pattern | |
3875 | training_pattern | |
3876 | DP_LINK_SCRAMBLING_DISABLE); |
3876 | DP_LINK_SCRAMBLING_DISABLE); |
3877 | tries = 0; |
3877 | tries = 0; |
3878 | cr_tries++; |
3878 | cr_tries++; |
3879 | continue; |
3879 | continue; |
3880 | } |
3880 | } |
3881 | 3881 | ||
3882 | /* Update training set as requested by target */ |
3882 | /* Update training set as requested by target */ |
3883 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3883 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
3884 | DRM_ERROR("failed to update link training\n"); |
3884 | DRM_ERROR("failed to update link training\n"); |
3885 | break; |
3885 | break; |
3886 | } |
3886 | } |
3887 | ++tries; |
3887 | ++tries; |
3888 | } |
3888 | } |
3889 | 3889 | ||
3890 | intel_dp_set_idle_link_train(intel_dp); |
3890 | intel_dp_set_idle_link_train(intel_dp); |
3891 | 3891 | ||
3892 | intel_dp->DP = DP; |
3892 | intel_dp->DP = DP; |
3893 | 3893 | ||
3894 | if (channel_eq) { |
3894 | if (channel_eq) { |
3895 | intel_dp->train_set_valid = true; |
3895 | intel_dp->train_set_valid = true; |
3896 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
3896 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
3897 | } |
3897 | } |
3898 | } |
3898 | } |
3899 | 3899 | ||
3900 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
3900 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
3901 | { |
3901 | { |
3902 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3902 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3903 | DP_TRAINING_PATTERN_DISABLE); |
3903 | DP_TRAINING_PATTERN_DISABLE); |
3904 | } |
3904 | } |
3905 | 3905 | ||
3906 | void |
3906 | void |
3907 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
3907 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
3908 | { |
3908 | { |
3909 | intel_dp_link_training_clock_recovery(intel_dp); |
3909 | intel_dp_link_training_clock_recovery(intel_dp); |
3910 | intel_dp_link_training_channel_equalization(intel_dp); |
3910 | intel_dp_link_training_channel_equalization(intel_dp); |
3911 | } |
3911 | } |
3912 | 3912 | ||
3913 | static void |
3913 | static void |
3914 | intel_dp_link_down(struct intel_dp *intel_dp) |
3914 | intel_dp_link_down(struct intel_dp *intel_dp) |
3915 | { |
3915 | { |
3916 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3916 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3917 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3917 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
3918 | enum port port = intel_dig_port->port; |
3918 | enum port port = intel_dig_port->port; |
3919 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3919 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3920 | struct drm_i915_private *dev_priv = dev->dev_private; |
3920 | struct drm_i915_private *dev_priv = dev->dev_private; |
3921 | uint32_t DP = intel_dp->DP; |
3921 | uint32_t DP = intel_dp->DP; |
3922 | 3922 | ||
3923 | if (WARN_ON(HAS_DDI(dev))) |
3923 | if (WARN_ON(HAS_DDI(dev))) |
3924 | return; |
3924 | return; |
3925 | 3925 | ||
3926 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3926 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
3927 | return; |
3927 | return; |
3928 | 3928 | ||
3929 | DRM_DEBUG_KMS("\n"); |
3929 | DRM_DEBUG_KMS("\n"); |
3930 | 3930 | ||
3931 | if ((IS_GEN7(dev) && port == PORT_A) || |
3931 | if ((IS_GEN7(dev) && port == PORT_A) || |
3932 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3932 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
3933 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3933 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3934 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3934 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
3935 | } else { |
3935 | } else { |
3936 | if (IS_CHERRYVIEW(dev)) |
3936 | if (IS_CHERRYVIEW(dev)) |
3937 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3937 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3938 | else |
3938 | else |
3939 | DP &= ~DP_LINK_TRAIN_MASK; |
3939 | DP &= ~DP_LINK_TRAIN_MASK; |
3940 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3940 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
3941 | } |
3941 | } |
3942 | I915_WRITE(intel_dp->output_reg, DP); |
3942 | I915_WRITE(intel_dp->output_reg, DP); |
3943 | POSTING_READ(intel_dp->output_reg); |
3943 | POSTING_READ(intel_dp->output_reg); |
3944 | 3944 | ||
3945 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3945 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3946 | I915_WRITE(intel_dp->output_reg, DP); |
3946 | I915_WRITE(intel_dp->output_reg, DP); |
3947 | POSTING_READ(intel_dp->output_reg); |
3947 | POSTING_READ(intel_dp->output_reg); |
3948 | 3948 | ||
3949 | /* |
3949 | /* |
3950 | * HW workaround for IBX, we need to move the port |
3950 | * HW workaround for IBX, we need to move the port |
3951 | * to transcoder A after disabling it to allow the |
3951 | * to transcoder A after disabling it to allow the |
3952 | * matching HDMI port to be enabled on transcoder A. |
3952 | * matching HDMI port to be enabled on transcoder A. |
3953 | */ |
3953 | */ |
3954 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
3954 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
3955 | /* always enable with pattern 1 (as per spec) */ |
3955 | /* always enable with pattern 1 (as per spec) */ |
3956 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3956 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
3957 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3957 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
3958 | I915_WRITE(intel_dp->output_reg, DP); |
3958 | I915_WRITE(intel_dp->output_reg, DP); |
3959 | POSTING_READ(intel_dp->output_reg); |
3959 | POSTING_READ(intel_dp->output_reg); |
3960 | 3960 | ||
3961 | DP &= ~DP_PORT_EN; |
3961 | DP &= ~DP_PORT_EN; |
3962 | I915_WRITE(intel_dp->output_reg, DP); |
3962 | I915_WRITE(intel_dp->output_reg, DP); |
3963 | POSTING_READ(intel_dp->output_reg); |
3963 | POSTING_READ(intel_dp->output_reg); |
3964 | } |
3964 | } |
3965 | 3965 | ||
3966 | msleep(intel_dp->panel_power_down_delay); |
3966 | msleep(intel_dp->panel_power_down_delay); |
3967 | } |
3967 | } |
3968 | 3968 | ||
3969 | static bool |
3969 | static bool |
3970 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3970 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
3971 | { |
3971 | { |
3972 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3972 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3973 | struct drm_device *dev = dig_port->base.base.dev; |
3973 | struct drm_device *dev = dig_port->base.base.dev; |
3974 | struct drm_i915_private *dev_priv = dev->dev_private; |
3974 | struct drm_i915_private *dev_priv = dev->dev_private; |
3975 | uint8_t rev; |
3975 | uint8_t rev; |
3976 | 3976 | ||
3977 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3977 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3978 | sizeof(intel_dp->dpcd)) < 0) |
3978 | sizeof(intel_dp->dpcd)) < 0) |
3979 | return false; /* aux transfer failed */ |
3979 | return false; /* aux transfer failed */ |
3980 | 3980 | ||
3981 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3981 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
3982 | 3982 | ||
3983 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3983 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3984 | return false; /* DPCD not present */ |
3984 | return false; /* DPCD not present */ |
3985 | 3985 | ||
3986 | /* Check if the panel supports PSR */ |
3986 | /* Check if the panel supports PSR */ |
3987 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3987 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
3988 | if (is_edp(intel_dp)) { |
3988 | if (is_edp(intel_dp)) { |
3989 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3989 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3990 | intel_dp->psr_dpcd, |
3990 | intel_dp->psr_dpcd, |
3991 | sizeof(intel_dp->psr_dpcd)); |
3991 | sizeof(intel_dp->psr_dpcd)); |
3992 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3992 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3993 | dev_priv->psr.sink_support = true; |
3993 | dev_priv->psr.sink_support = true; |
3994 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3994 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
3995 | } |
3995 | } |
3996 | 3996 | ||
3997 | if (INTEL_INFO(dev)->gen >= 9 && |
3997 | if (INTEL_INFO(dev)->gen >= 9 && |
3998 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3998 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
3999 | uint8_t frame_sync_cap; |
3999 | uint8_t frame_sync_cap; |
4000 | 4000 | ||
4001 | dev_priv->psr.sink_support = true; |
4001 | dev_priv->psr.sink_support = true; |
4002 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
4002 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
4003 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
4003 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
4004 | &frame_sync_cap, 1); |
4004 | &frame_sync_cap, 1); |
4005 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
4005 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
4006 | /* PSR2 needs frame sync as well */ |
4006 | /* PSR2 needs frame sync as well */ |
4007 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
4007 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
4008 | DRM_DEBUG_KMS("PSR2 %s on sink", |
4008 | DRM_DEBUG_KMS("PSR2 %s on sink", |
4009 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
4009 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
4010 | } |
4010 | } |
4011 | } |
4011 | } |
4012 | 4012 | ||
4013 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4013 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4014 | yesno(intel_dp_source_supports_hbr2(dev)), |
4014 | yesno(intel_dp_source_supports_hbr2(dev)), |
4015 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
4015 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
4016 | 4016 | ||
4017 | /* Intermediate frequency support */ |
4017 | /* Intermediate frequency support */ |
4018 | if (is_edp(intel_dp) && |
4018 | if (is_edp(intel_dp) && |
4019 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
4019 | (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
4020 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
4020 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && |
4021 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
4021 | (rev >= 0x03)) { /* eDp v1.4 or higher */ |
4022 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
4022 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
4023 | int i; |
4023 | int i; |
4024 | 4024 | ||
4025 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
4025 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
4026 | DP_SUPPORTED_LINK_RATES, |
4026 | DP_SUPPORTED_LINK_RATES, |
4027 | sink_rates, |
4027 | sink_rates, |
4028 | sizeof(sink_rates)); |
4028 | sizeof(sink_rates)); |
4029 | 4029 | ||
4030 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4030 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4031 | int val = le16_to_cpu(sink_rates[i]); |
4031 | int val = le16_to_cpu(sink_rates[i]); |
4032 | 4032 | ||
4033 | if (val == 0) |
4033 | if (val == 0) |
4034 | break; |
4034 | break; |
4035 | 4035 | ||
4036 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
4036 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
4037 | intel_dp->sink_rates[i] = (val * 200) / 10; |
4037 | intel_dp->sink_rates[i] = (val * 200) / 10; |
4038 | } |
4038 | } |
4039 | intel_dp->num_sink_rates = i; |
4039 | intel_dp->num_sink_rates = i; |
4040 | } |
4040 | } |
4041 | 4041 | ||
4042 | intel_dp_print_rates(intel_dp); |
4042 | intel_dp_print_rates(intel_dp); |
4043 | 4043 | ||
4044 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4044 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4045 | DP_DWN_STRM_PORT_PRESENT)) |
4045 | DP_DWN_STRM_PORT_PRESENT)) |
4046 | return true; /* native DP sink */ |
4046 | return true; /* native DP sink */ |
4047 | 4047 | ||
4048 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
4048 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
4049 | return true; /* no per-port downstream info */ |
4049 | return true; /* no per-port downstream info */ |
4050 | 4050 | ||
4051 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
4051 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
4052 | intel_dp->downstream_ports, |
4052 | intel_dp->downstream_ports, |
4053 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
4053 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
4054 | return false; /* downstream port status fetch failed */ |
4054 | return false; /* downstream port status fetch failed */ |
4055 | 4055 | ||
4056 | return true; |
4056 | return true; |
4057 | } |
4057 | } |
4058 | 4058 | ||
4059 | static void |
4059 | static void |
4060 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
4060 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
4061 | { |
4061 | { |
4062 | u8 buf[3]; |
4062 | u8 buf[3]; |
4063 | 4063 | ||
4064 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
4064 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
4065 | return; |
4065 | return; |
4066 | 4066 | ||
4067 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
4067 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
4068 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
4068 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
4069 | buf[0], buf[1], buf[2]); |
4069 | buf[0], buf[1], buf[2]); |
4070 | 4070 | ||
4071 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
4071 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
4072 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
4072 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
4073 | buf[0], buf[1], buf[2]); |
4073 | buf[0], buf[1], buf[2]); |
4074 | } |
4074 | } |
4075 | 4075 | ||
4076 | static bool |
4076 | static bool |
4077 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
4077 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
4078 | { |
4078 | { |
4079 | u8 buf[1]; |
4079 | u8 buf[1]; |
4080 | 4080 | ||
4081 | if (!intel_dp->can_mst) |
4081 | if (!intel_dp->can_mst) |
4082 | return false; |
4082 | return false; |
4083 | 4083 | ||
4084 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
4084 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
4085 | return false; |
4085 | return false; |
4086 | 4086 | ||
4087 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
4087 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
4088 | if (buf[0] & DP_MST_CAP) { |
4088 | if (buf[0] & DP_MST_CAP) { |
4089 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
4089 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
4090 | intel_dp->is_mst = true; |
4090 | intel_dp->is_mst = true; |
4091 | } else { |
4091 | } else { |
4092 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
4092 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
4093 | intel_dp->is_mst = false; |
4093 | intel_dp->is_mst = false; |
4094 | } |
4094 | } |
4095 | } |
4095 | } |
4096 | 4096 | ||
4097 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4097 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4098 | return intel_dp->is_mst; |
4098 | return intel_dp->is_mst; |
4099 | } |
4099 | } |
4100 | 4100 | ||
4101 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
4101 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
4102 | { |
4102 | { |
4103 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4103 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4104 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4104 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4105 | u8 buf; |
4105 | u8 buf; |
4106 | int ret = 0; |
4106 | int ret = 0; |
4107 | 4107 | ||
4108 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4108 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
4109 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4109 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4110 | ret = -EIO; |
4110 | ret = -EIO; |
4111 | goto out; |
4111 | goto out; |
4112 | } |
4112 | } |
4113 | 4113 | ||
4114 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4114 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4115 | buf & ~DP_TEST_SINK_START) < 0) { |
4115 | buf & ~DP_TEST_SINK_START) < 0) { |
4116 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4116 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
4117 | ret = -EIO; |
4117 | ret = -EIO; |
4118 | goto out; |
4118 | goto out; |
4119 | } |
4119 | } |
4120 | 4120 | ||
4121 | intel_dp->sink_crc.started = false; |
4121 | intel_dp->sink_crc.started = false; |
4122 | out: |
4122 | out: |
4123 | hsw_enable_ips(intel_crtc); |
4123 | hsw_enable_ips(intel_crtc); |
4124 | return ret; |
4124 | return ret; |
4125 | } |
4125 | } |
4126 | 4126 | ||
4127 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4127 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
4128 | { |
4128 | { |
4129 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4129 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4130 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4130 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4131 | u8 buf; |
4131 | u8 buf; |
4132 | int ret; |
4132 | int ret; |
4133 | 4133 | ||
4134 | if (intel_dp->sink_crc.started) { |
4134 | if (intel_dp->sink_crc.started) { |
4135 | ret = intel_dp_sink_crc_stop(intel_dp); |
4135 | ret = intel_dp_sink_crc_stop(intel_dp); |
4136 | if (ret) |
4136 | if (ret) |
4137 | return ret; |
4137 | return ret; |
4138 | } |
4138 | } |
4139 | 4139 | ||
4140 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4140 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
4141 | return -EIO; |
4141 | return -EIO; |
4142 | 4142 | ||
4143 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4143 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
4144 | return -ENOTTY; |
4144 | return -ENOTTY; |
4145 | 4145 | ||
4146 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
4146 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
4147 | 4147 | ||
4148 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4148 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4149 | return -EIO; |
4149 | return -EIO; |
4150 | 4150 | ||
4151 | hsw_disable_ips(intel_crtc); |
4151 | hsw_disable_ips(intel_crtc); |
4152 | 4152 | ||
4153 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4153 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
4154 | buf | DP_TEST_SINK_START) < 0) { |
4154 | buf | DP_TEST_SINK_START) < 0) { |
4155 | hsw_enable_ips(intel_crtc); |
4155 | hsw_enable_ips(intel_crtc); |
4156 | return -EIO; |
4156 | return -EIO; |
4157 | } |
4157 | } |
4158 | 4158 | ||
4159 | intel_dp->sink_crc.started = true; |
4159 | intel_dp->sink_crc.started = true; |
4160 | return 0; |
4160 | return 0; |
4161 | } |
4161 | } |
4162 | 4162 | ||
4163 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4163 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4164 | { |
4164 | { |
4165 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4165 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4166 | struct drm_device *dev = dig_port->base.base.dev; |
4166 | struct drm_device *dev = dig_port->base.base.dev; |
4167 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4167 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
4168 | u8 buf; |
4168 | u8 buf; |
4169 | int count, ret; |
4169 | int count, ret; |
4170 | int attempts = 6; |
4170 | int attempts = 6; |
4171 | bool old_equal_new; |
4171 | bool old_equal_new; |
4172 | 4172 | ||
4173 | ret = intel_dp_sink_crc_start(intel_dp); |
4173 | ret = intel_dp_sink_crc_start(intel_dp); |
4174 | if (ret) |
4174 | if (ret) |
4175 | return ret; |
4175 | return ret; |
4176 | 4176 | ||
4177 | do { |
4177 | do { |
4178 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4178 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4179 | 4179 | ||
4180 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4180 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4181 | DP_TEST_SINK_MISC, &buf) < 0) { |
4181 | DP_TEST_SINK_MISC, &buf) < 0) { |
4182 | ret = -EIO; |
4182 | ret = -EIO; |
4183 | goto stop; |
4183 | goto stop; |
4184 | } |
4184 | } |
4185 | count = buf & DP_TEST_COUNT_MASK; |
4185 | count = buf & DP_TEST_COUNT_MASK; |
4186 | 4186 | ||
4187 | /* |
4187 | /* |
4188 | * Count might be reset during the loop. In this case |
4188 | * Count might be reset during the loop. In this case |
4189 | * last known count needs to be reset as well. |
4189 | * last known count needs to be reset as well. |
4190 | */ |
4190 | */ |
4191 | if (count == 0) |
4191 | if (count == 0) |
4192 | intel_dp->sink_crc.last_count = 0; |
4192 | intel_dp->sink_crc.last_count = 0; |
4193 | 4193 | ||
4194 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
4194 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
4195 | ret = -EIO; |
4195 | ret = -EIO; |
4196 | goto stop; |
4196 | goto stop; |
4197 | } |
4197 | } |
4198 | 4198 | ||
4199 | old_equal_new = (count == intel_dp->sink_crc.last_count && |
4199 | old_equal_new = (count == intel_dp->sink_crc.last_count && |
4200 | !memcmp(intel_dp->sink_crc.last_crc, crc, |
4200 | !memcmp(intel_dp->sink_crc.last_crc, crc, |
4201 | 6 * sizeof(u8))); |
4201 | 6 * sizeof(u8))); |
4202 | 4202 | ||
4203 | } while (--attempts && (count == 0 || old_equal_new)); |
4203 | } while (--attempts && (count == 0 || old_equal_new)); |
4204 | 4204 | ||
4205 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
4205 | intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK; |
4206 | memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8)); |
4206 | memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8)); |
4207 | 4207 | ||
4208 | if (attempts == 0) { |
4208 | if (attempts == 0) { |
4209 | if (old_equal_new) { |
4209 | if (old_equal_new) { |
4210 | DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n"); |
4210 | DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n"); |
4211 | } else { |
4211 | } else { |
4212 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4212 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4213 | ret = -ETIMEDOUT; |
4213 | ret = -ETIMEDOUT; |
4214 | goto stop; |
4214 | goto stop; |
4215 | } |
4215 | } |
4216 | } |
4216 | } |
4217 | 4217 | ||
4218 | stop: |
4218 | stop: |
4219 | intel_dp_sink_crc_stop(intel_dp); |
4219 | intel_dp_sink_crc_stop(intel_dp); |
4220 | return ret; |
4220 | return ret; |
4221 | } |
4221 | } |
4222 | 4222 | ||
4223 | static bool |
4223 | static bool |
4224 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4224 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4225 | { |
4225 | { |
4226 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4226 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4227 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4227 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4228 | sink_irq_vector, 1) == 1; |
4228 | sink_irq_vector, 1) == 1; |
4229 | } |
4229 | } |
4230 | 4230 | ||
4231 | static bool |
4231 | static bool |
4232 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4232 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
4233 | { |
4233 | { |
4234 | int ret; |
4234 | int ret; |
4235 | 4235 | ||
4236 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4236 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
4237 | DP_SINK_COUNT_ESI, |
4237 | DP_SINK_COUNT_ESI, |
4238 | sink_irq_vector, 14); |
4238 | sink_irq_vector, 14); |
4239 | if (ret != 14) |
4239 | if (ret != 14) |
4240 | return false; |
4240 | return false; |
4241 | 4241 | ||
4242 | return true; |
4242 | return true; |
4243 | } |
4243 | } |
4244 | 4244 | ||
4245 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4245 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4246 | { |
4246 | { |
4247 | uint8_t test_result = DP_TEST_ACK; |
4247 | uint8_t test_result = DP_TEST_ACK; |
4248 | return test_result; |
4248 | return test_result; |
4249 | } |
4249 | } |
4250 | 4250 | ||
4251 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4251 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
4252 | { |
4252 | { |
4253 | uint8_t test_result = DP_TEST_NAK; |
4253 | uint8_t test_result = DP_TEST_NAK; |
4254 | return test_result; |
4254 | return test_result; |
4255 | } |
4255 | } |
4256 | 4256 | ||
4257 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4257 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
4258 | { |
4258 | { |
4259 | uint8_t test_result = DP_TEST_NAK; |
4259 | uint8_t test_result = DP_TEST_NAK; |
4260 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4260 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4261 | struct drm_connector *connector = &intel_connector->base; |
4261 | struct drm_connector *connector = &intel_connector->base; |
4262 | 4262 | ||
4263 | if (intel_connector->detect_edid == NULL || |
4263 | if (intel_connector->detect_edid == NULL || |
4264 | connector->edid_corrupt || |
4264 | connector->edid_corrupt || |
4265 | intel_dp->aux.i2c_defer_count > 6) { |
4265 | intel_dp->aux.i2c_defer_count > 6) { |
4266 | /* Check EDID read for NACKs, DEFERs and corruption |
4266 | /* Check EDID read for NACKs, DEFERs and corruption |
4267 | * (DP CTS 1.2 Core r1.1) |
4267 | * (DP CTS 1.2 Core r1.1) |
4268 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4268 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
4269 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4269 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
4270 | * 4.2.2.6 : EDID corruption detected |
4270 | * 4.2.2.6 : EDID corruption detected |
4271 | * Use failsafe mode for all cases |
4271 | * Use failsafe mode for all cases |
4272 | */ |
4272 | */ |
4273 | if (intel_dp->aux.i2c_nack_count > 0 || |
4273 | if (intel_dp->aux.i2c_nack_count > 0 || |
4274 | intel_dp->aux.i2c_defer_count > 0) |
4274 | intel_dp->aux.i2c_defer_count > 0) |
4275 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4275 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
4276 | intel_dp->aux.i2c_nack_count, |
4276 | intel_dp->aux.i2c_nack_count, |
4277 | intel_dp->aux.i2c_defer_count); |
4277 | intel_dp->aux.i2c_defer_count); |
4278 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4278 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
4279 | } else { |
4279 | } else { |
4280 | struct edid *block = intel_connector->detect_edid; |
4280 | struct edid *block = intel_connector->detect_edid; |
4281 | 4281 | ||
4282 | /* We have to write the checksum |
4282 | /* We have to write the checksum |
4283 | * of the last block read |
4283 | * of the last block read |
4284 | */ |
4284 | */ |
4285 | block += intel_connector->detect_edid->extensions; |
4285 | block += intel_connector->detect_edid->extensions; |
4286 | 4286 | ||
4287 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4287 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4288 | DP_TEST_EDID_CHECKSUM, |
4288 | DP_TEST_EDID_CHECKSUM, |
4289 | &block->checksum, |
4289 | &block->checksum, |
4290 | 1)) |
4290 | 1)) |
4291 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4291 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4292 | 4292 | ||
4293 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4293 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
4294 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4294 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
4295 | } |
4295 | } |
4296 | 4296 | ||
4297 | /* Set test active flag here so userspace doesn't interrupt things */ |
4297 | /* Set test active flag here so userspace doesn't interrupt things */ |
4298 | intel_dp->compliance_test_active = 1; |
4298 | intel_dp->compliance_test_active = 1; |
4299 | 4299 | ||
4300 | return test_result; |
4300 | return test_result; |
4301 | } |
4301 | } |
4302 | 4302 | ||
4303 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4303 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
4304 | { |
4304 | { |
4305 | uint8_t test_result = DP_TEST_NAK; |
4305 | uint8_t test_result = DP_TEST_NAK; |
4306 | return test_result; |
4306 | return test_result; |
4307 | } |
4307 | } |
4308 | 4308 | ||
4309 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4309 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
4310 | { |
4310 | { |
4311 | uint8_t response = DP_TEST_NAK; |
4311 | uint8_t response = DP_TEST_NAK; |
4312 | uint8_t rxdata = 0; |
4312 | uint8_t rxdata = 0; |
4313 | int status = 0; |
4313 | int status = 0; |
4314 | 4314 | ||
4315 | intel_dp->compliance_test_active = 0; |
4315 | intel_dp->compliance_test_active = 0; |
4316 | intel_dp->compliance_test_type = 0; |
4316 | intel_dp->compliance_test_type = 0; |
4317 | intel_dp->compliance_test_data = 0; |
4317 | intel_dp->compliance_test_data = 0; |
4318 | 4318 | ||
4319 | intel_dp->aux.i2c_nack_count = 0; |
4319 | intel_dp->aux.i2c_nack_count = 0; |
4320 | intel_dp->aux.i2c_defer_count = 0; |
4320 | intel_dp->aux.i2c_defer_count = 0; |
4321 | 4321 | ||
4322 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4322 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
4323 | if (status <= 0) { |
4323 | if (status <= 0) { |
4324 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4324 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
4325 | goto update_status; |
4325 | goto update_status; |
4326 | } |
4326 | } |
4327 | 4327 | ||
4328 | switch (rxdata) { |
4328 | switch (rxdata) { |
4329 | case DP_TEST_LINK_TRAINING: |
4329 | case DP_TEST_LINK_TRAINING: |
4330 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4330 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
4331 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4331 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
4332 | response = intel_dp_autotest_link_training(intel_dp); |
4332 | response = intel_dp_autotest_link_training(intel_dp); |
4333 | break; |
4333 | break; |
4334 | case DP_TEST_LINK_VIDEO_PATTERN: |
4334 | case DP_TEST_LINK_VIDEO_PATTERN: |
4335 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4335 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
4336 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4336 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
4337 | response = intel_dp_autotest_video_pattern(intel_dp); |
4337 | response = intel_dp_autotest_video_pattern(intel_dp); |
4338 | break; |
4338 | break; |
4339 | case DP_TEST_LINK_EDID_READ: |
4339 | case DP_TEST_LINK_EDID_READ: |
4340 | DRM_DEBUG_KMS("EDID test requested\n"); |
4340 | DRM_DEBUG_KMS("EDID test requested\n"); |
4341 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4341 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
4342 | response = intel_dp_autotest_edid(intel_dp); |
4342 | response = intel_dp_autotest_edid(intel_dp); |
4343 | break; |
4343 | break; |
4344 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4344 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
4345 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4345 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
4346 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4346 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
4347 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4347 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4348 | break; |
4348 | break; |
4349 | default: |
4349 | default: |
4350 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4350 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
4351 | break; |
4351 | break; |
4352 | } |
4352 | } |
4353 | 4353 | ||
4354 | update_status: |
4354 | update_status: |
4355 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4355 | status = drm_dp_dpcd_write(&intel_dp->aux, |
4356 | DP_TEST_RESPONSE, |
4356 | DP_TEST_RESPONSE, |
4357 | &response, 1); |
4357 | &response, 1); |
4358 | if (status <= 0) |
4358 | if (status <= 0) |
4359 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4359 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
4360 | } |
4360 | } |
4361 | 4361 | ||
4362 | static int |
4362 | static int |
4363 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4363 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4364 | { |
4364 | { |
4365 | bool bret; |
4365 | bool bret; |
4366 | 4366 | ||
4367 | if (intel_dp->is_mst) { |
4367 | if (intel_dp->is_mst) { |
4368 | u8 esi[16] = { 0 }; |
4368 | u8 esi[16] = { 0 }; |
4369 | int ret = 0; |
4369 | int ret = 0; |
4370 | int retry; |
4370 | int retry; |
4371 | bool handled; |
4371 | bool handled; |
4372 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4372 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4373 | go_again: |
4373 | go_again: |
4374 | if (bret == true) { |
4374 | if (bret == true) { |
4375 | 4375 | ||
4376 | /* check link status - esi[10] = 0x200c */ |
4376 | /* check link status - esi[10] = 0x200c */ |
4377 | if (intel_dp->active_mst_links && |
4377 | if (intel_dp->active_mst_links && |
4378 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4378 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
4379 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4379 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4380 | intel_dp_start_link_train(intel_dp); |
4380 | intel_dp_start_link_train(intel_dp); |
4381 | intel_dp_stop_link_train(intel_dp); |
4381 | intel_dp_stop_link_train(intel_dp); |
4382 | } |
4382 | } |
4383 | 4383 | ||
4384 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4384 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
4385 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4385 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4386 | 4386 | ||
4387 | if (handled) { |
4387 | if (handled) { |
4388 | for (retry = 0; retry < 3; retry++) { |
4388 | for (retry = 0; retry < 3; retry++) { |
4389 | int wret; |
4389 | int wret; |
4390 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4390 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
4391 | DP_SINK_COUNT_ESI+1, |
4391 | DP_SINK_COUNT_ESI+1, |
4392 | &esi[1], 3); |
4392 | &esi[1], 3); |
4393 | if (wret == 3) { |
4393 | if (wret == 3) { |
4394 | break; |
4394 | break; |
4395 | } |
4395 | } |
4396 | } |
4396 | } |
4397 | 4397 | ||
4398 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4398 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
4399 | if (bret == true) { |
4399 | if (bret == true) { |
4400 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4400 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
4401 | goto go_again; |
4401 | goto go_again; |
4402 | } |
4402 | } |
4403 | } else |
4403 | } else |
4404 | ret = 0; |
4404 | ret = 0; |
4405 | 4405 | ||
4406 | return ret; |
4406 | return ret; |
4407 | } else { |
4407 | } else { |
4408 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4408 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4409 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4409 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
4410 | intel_dp->is_mst = false; |
4410 | intel_dp->is_mst = false; |
4411 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4411 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4412 | /* send a hotplug event */ |
4412 | /* send a hotplug event */ |
4413 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4413 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
4414 | } |
4414 | } |
4415 | } |
4415 | } |
4416 | return -EINVAL; |
4416 | return -EINVAL; |
4417 | } |
4417 | } |
4418 | 4418 | ||
4419 | /* |
4419 | /* |
4420 | * According to DP spec |
4420 | * According to DP spec |
4421 | * 5.1.2: |
4421 | * 5.1.2: |
4422 | * 1. Read DPCD |
4422 | * 1. Read DPCD |
4423 | * 2. Configure link according to Receiver Capabilities |
4423 | * 2. Configure link according to Receiver Capabilities |
4424 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4424 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
4425 | * 4. Check link status on receipt of hot-plug interrupt |
4425 | * 4. Check link status on receipt of hot-plug interrupt |
4426 | */ |
4426 | */ |
4427 | static void |
4427 | static void |
4428 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4428 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
4429 | { |
4429 | { |
4430 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4430 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4431 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4431 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4432 | u8 sink_irq_vector; |
4432 | u8 sink_irq_vector; |
4433 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4433 | u8 link_status[DP_LINK_STATUS_SIZE]; |
4434 | 4434 | ||
4435 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4435 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4436 | 4436 | ||
4437 | if (!intel_encoder->base.crtc) |
4437 | if (!intel_encoder->base.crtc) |
4438 | return; |
4438 | return; |
4439 | 4439 | ||
4440 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4440 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4441 | return; |
4441 | return; |
4442 | 4442 | ||
4443 | /* Try to read receiver status if the link appears to be up */ |
4443 | /* Try to read receiver status if the link appears to be up */ |
4444 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4444 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
4445 | return; |
4445 | return; |
4446 | } |
4446 | } |
4447 | 4447 | ||
4448 | /* Now read the DPCD to see if it's actually running */ |
4448 | /* Now read the DPCD to see if it's actually running */ |
4449 | if (!intel_dp_get_dpcd(intel_dp)) { |
4449 | if (!intel_dp_get_dpcd(intel_dp)) { |
4450 | return; |
4450 | return; |
4451 | } |
4451 | } |
4452 | 4452 | ||
4453 | /* Try to read the source of the interrupt */ |
4453 | /* Try to read the source of the interrupt */ |
4454 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4454 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4455 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4455 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4456 | /* Clear interrupt source */ |
4456 | /* Clear interrupt source */ |
4457 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4457 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4458 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4458 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4459 | sink_irq_vector); |
4459 | sink_irq_vector); |
4460 | 4460 | ||
4461 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4461 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4462 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4462 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
4463 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4463 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4464 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4464 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4465 | } |
4465 | } |
4466 | 4466 | ||
4467 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
4467 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
4468 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4468 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4469 | intel_encoder->base.name); |
4469 | intel_encoder->base.name); |
4470 | intel_dp_start_link_train(intel_dp); |
4470 | intel_dp_start_link_train(intel_dp); |
4471 | intel_dp_stop_link_train(intel_dp); |
4471 | intel_dp_stop_link_train(intel_dp); |
4472 | } |
4472 | } |
4473 | } |
4473 | } |
4474 | 4474 | ||
4475 | /* XXX this is probably wrong for multiple downstream ports */ |
4475 | /* XXX this is probably wrong for multiple downstream ports */ |
4476 | static enum drm_connector_status |
4476 | static enum drm_connector_status |
4477 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4477 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
4478 | { |
4478 | { |
4479 | uint8_t *dpcd = intel_dp->dpcd; |
4479 | uint8_t *dpcd = intel_dp->dpcd; |
4480 | uint8_t type; |
4480 | uint8_t type; |
4481 | 4481 | ||
4482 | if (!intel_dp_get_dpcd(intel_dp)) |
4482 | if (!intel_dp_get_dpcd(intel_dp)) |
4483 | return connector_status_disconnected; |
4483 | return connector_status_disconnected; |
4484 | 4484 | ||
4485 | /* if there's no downstream port, we're done */ |
4485 | /* if there's no downstream port, we're done */ |
4486 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4486 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
4487 | return connector_status_connected; |
4487 | return connector_status_connected; |
4488 | 4488 | ||
4489 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4489 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
4490 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4490 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4491 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4491 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
4492 | uint8_t reg; |
4492 | uint8_t reg; |
4493 | 4493 | ||
4494 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4494 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
4495 | ®, 1) < 0) |
4495 | ®, 1) < 0) |
4496 | return connector_status_unknown; |
4496 | return connector_status_unknown; |
4497 | 4497 | ||
4498 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4498 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4499 | : connector_status_disconnected; |
4499 | : connector_status_disconnected; |
4500 | } |
4500 | } |
4501 | 4501 | ||
4502 | /* If no HPD, poke DDC gently */ |
4502 | /* If no HPD, poke DDC gently */ |
4503 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4503 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
4504 | return connector_status_connected; |
4504 | return connector_status_connected; |
4505 | 4505 | ||
4506 | /* Well we tried, say unknown for unreliable port types */ |
4506 | /* Well we tried, say unknown for unreliable port types */ |
4507 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4507 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4508 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4508 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
4509 | if (type == DP_DS_PORT_TYPE_VGA || |
4509 | if (type == DP_DS_PORT_TYPE_VGA || |
4510 | type == DP_DS_PORT_TYPE_NON_EDID) |
4510 | type == DP_DS_PORT_TYPE_NON_EDID) |
4511 | return connector_status_unknown; |
4511 | return connector_status_unknown; |
4512 | } else { |
4512 | } else { |
4513 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4513 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
4514 | DP_DWN_STRM_PORT_TYPE_MASK; |
4514 | DP_DWN_STRM_PORT_TYPE_MASK; |
4515 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4515 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
4516 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4516 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
4517 | return connector_status_unknown; |
4517 | return connector_status_unknown; |
4518 | } |
4518 | } |
4519 | 4519 | ||
4520 | /* Anything else is out of spec, warn and ignore */ |
4520 | /* Anything else is out of spec, warn and ignore */ |
4521 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4521 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
4522 | return connector_status_disconnected; |
4522 | return connector_status_disconnected; |
4523 | } |
4523 | } |
4524 | 4524 | ||
4525 | static enum drm_connector_status |
4525 | static enum drm_connector_status |
4526 | edp_detect(struct intel_dp *intel_dp) |
4526 | edp_detect(struct intel_dp *intel_dp) |
4527 | { |
4527 | { |
4528 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4528 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4529 | enum drm_connector_status status; |
4529 | enum drm_connector_status status; |
4530 | 4530 | ||
4531 | status = intel_panel_detect(dev); |
4531 | status = intel_panel_detect(dev); |
4532 | if (status == connector_status_unknown) |
4532 | if (status == connector_status_unknown) |
4533 | status = connector_status_connected; |
4533 | status = connector_status_connected; |
4534 | 4534 | ||
4535 | return status; |
4535 | return status; |
4536 | } |
4536 | } |
4537 | 4537 | ||
4538 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4538 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4539 | struct intel_digital_port *port) |
4539 | struct intel_digital_port *port) |
4540 | { |
4540 | { |
4541 | u32 bit; |
4541 | u32 bit; |
4542 | 4542 | ||
4543 | switch (port->port) { |
4543 | switch (port->port) { |
4544 | case PORT_A: |
4544 | case PORT_A: |
4545 | return true; |
4545 | return true; |
4546 | case PORT_B: |
4546 | case PORT_B: |
4547 | bit = SDE_PORTB_HOTPLUG; |
4547 | bit = SDE_PORTB_HOTPLUG; |
4548 | break; |
4548 | break; |
4549 | case PORT_C: |
4549 | case PORT_C: |
4550 | bit = SDE_PORTC_HOTPLUG; |
4550 | bit = SDE_PORTC_HOTPLUG; |
4551 | break; |
4551 | break; |
4552 | case PORT_D: |
4552 | case PORT_D: |
4553 | bit = SDE_PORTD_HOTPLUG; |
4553 | bit = SDE_PORTD_HOTPLUG; |
4554 | break; |
4554 | break; |
4555 | default: |
4555 | default: |
4556 | MISSING_CASE(port->port); |
4556 | MISSING_CASE(port->port); |
4557 | return false; |
4557 | return false; |
4558 | } |
4558 | } |
4559 | 4559 | ||
4560 | return I915_READ(SDEISR) & bit; |
4560 | return I915_READ(SDEISR) & bit; |
4561 | } |
4561 | } |
4562 | 4562 | ||
4563 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4563 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
4564 | struct intel_digital_port *port) |
4564 | struct intel_digital_port *port) |
4565 | { |
4565 | { |
4566 | u32 bit; |
4566 | u32 bit; |
4567 | 4567 | ||
4568 | switch (port->port) { |
4568 | switch (port->port) { |
4569 | case PORT_A: |
4569 | case PORT_A: |
4570 | return true; |
4570 | return true; |
4571 | case PORT_B: |
4571 | case PORT_B: |
4572 | bit = SDE_PORTB_HOTPLUG_CPT; |
4572 | bit = SDE_PORTB_HOTPLUG_CPT; |
4573 | break; |
4573 | break; |
4574 | case PORT_C: |
4574 | case PORT_C: |
4575 | bit = SDE_PORTC_HOTPLUG_CPT; |
4575 | bit = SDE_PORTC_HOTPLUG_CPT; |
4576 | break; |
4576 | break; |
4577 | case PORT_D: |
4577 | case PORT_D: |
4578 | bit = SDE_PORTD_HOTPLUG_CPT; |
4578 | bit = SDE_PORTD_HOTPLUG_CPT; |
4579 | break; |
4579 | break; |
4580 | case PORT_E: |
4580 | case PORT_E: |
4581 | bit = SDE_PORTE_HOTPLUG_SPT; |
4581 | bit = SDE_PORTE_HOTPLUG_SPT; |
4582 | break; |
4582 | break; |
4583 | default: |
4583 | default: |
4584 | MISSING_CASE(port->port); |
4584 | MISSING_CASE(port->port); |
4585 | return false; |
4585 | return false; |
4586 | } |
4586 | } |
4587 | 4587 | ||
4588 | return I915_READ(SDEISR) & bit; |
4588 | return I915_READ(SDEISR) & bit; |
4589 | } |
4589 | } |
4590 | 4590 | ||
4591 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4591 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
4592 | struct intel_digital_port *port) |
4592 | struct intel_digital_port *port) |
4593 | { |
4593 | { |
4594 | u32 bit; |
4594 | u32 bit; |
4595 | 4595 | ||
4596 | switch (port->port) { |
4596 | switch (port->port) { |
4597 | case PORT_B: |
4597 | case PORT_B: |
4598 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4598 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4599 | break; |
4599 | break; |
4600 | case PORT_C: |
4600 | case PORT_C: |
4601 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4601 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4602 | break; |
4602 | break; |
4603 | case PORT_D: |
4603 | case PORT_D: |
4604 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4604 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4605 | break; |
4605 | break; |
4606 | default: |
4606 | default: |
4607 | MISSING_CASE(port->port); |
4607 | MISSING_CASE(port->port); |
4608 | return false; |
4608 | return false; |
4609 | } |
4609 | } |
4610 | 4610 | ||
4611 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4611 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4612 | } |
4612 | } |
4613 | 4613 | ||
4614 | static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv, |
4614 | static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv, |
4615 | struct intel_digital_port *port) |
4615 | struct intel_digital_port *port) |
4616 | { |
4616 | { |
4617 | u32 bit; |
4617 | u32 bit; |
4618 | 4618 | ||
4619 | switch (port->port) { |
4619 | switch (port->port) { |
4620 | case PORT_B: |
4620 | case PORT_B: |
4621 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
4621 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
4622 | break; |
4622 | break; |
4623 | case PORT_C: |
4623 | case PORT_C: |
4624 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
4624 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
4625 | break; |
4625 | break; |
4626 | case PORT_D: |
4626 | case PORT_D: |
4627 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
4627 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
4628 | break; |
4628 | break; |
4629 | default: |
4629 | default: |
4630 | MISSING_CASE(port->port); |
4630 | MISSING_CASE(port->port); |
4631 | return false; |
4631 | return false; |
4632 | } |
4632 | } |
4633 | 4633 | ||
4634 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4634 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
4635 | } |
4635 | } |
4636 | 4636 | ||
4637 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4637 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
4638 | struct intel_digital_port *intel_dig_port) |
4638 | struct intel_digital_port *intel_dig_port) |
4639 | { |
4639 | { |
4640 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4640 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4641 | enum port port; |
4641 | enum port port; |
4642 | u32 bit; |
4642 | u32 bit; |
4643 | 4643 | ||
4644 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4644 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4645 | switch (port) { |
4645 | switch (port) { |
4646 | case PORT_A: |
4646 | case PORT_A: |
4647 | bit = BXT_DE_PORT_HP_DDIA; |
4647 | bit = BXT_DE_PORT_HP_DDIA; |
4648 | break; |
4648 | break; |
4649 | case PORT_B: |
4649 | case PORT_B: |
4650 | bit = BXT_DE_PORT_HP_DDIB; |
4650 | bit = BXT_DE_PORT_HP_DDIB; |
4651 | break; |
4651 | break; |
4652 | case PORT_C: |
4652 | case PORT_C: |
4653 | bit = BXT_DE_PORT_HP_DDIC; |
4653 | bit = BXT_DE_PORT_HP_DDIC; |
4654 | break; |
4654 | break; |
4655 | default: |
4655 | default: |
4656 | MISSING_CASE(port); |
4656 | MISSING_CASE(port); |
4657 | return false; |
4657 | return false; |
4658 | } |
4658 | } |
4659 | 4659 | ||
4660 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4660 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
4661 | } |
4661 | } |
4662 | 4662 | ||
4663 | /* |
4663 | /* |
4664 | * intel_digital_port_connected - is the specified port connected? |
4664 | * intel_digital_port_connected - is the specified port connected? |
4665 | * @dev_priv: i915 private structure |
4665 | * @dev_priv: i915 private structure |
4666 | * @port: the port to test |
4666 | * @port: the port to test |
4667 | * |
4667 | * |
4668 | * Return %true if @port is connected, %false otherwise. |
4668 | * Return %true if @port is connected, %false otherwise. |
4669 | */ |
4669 | */ |
4670 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4670 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4671 | struct intel_digital_port *port) |
4671 | struct intel_digital_port *port) |
4672 | { |
4672 | { |
4673 | if (HAS_PCH_IBX(dev_priv)) |
4673 | if (HAS_PCH_IBX(dev_priv)) |
4674 | return ibx_digital_port_connected(dev_priv, port); |
4674 | return ibx_digital_port_connected(dev_priv, port); |
4675 | if (HAS_PCH_SPLIT(dev_priv)) |
4675 | if (HAS_PCH_SPLIT(dev_priv)) |
4676 | return cpt_digital_port_connected(dev_priv, port); |
4676 | return cpt_digital_port_connected(dev_priv, port); |
4677 | else if (IS_BROXTON(dev_priv)) |
4677 | else if (IS_BROXTON(dev_priv)) |
4678 | return bxt_digital_port_connected(dev_priv, port); |
4678 | return bxt_digital_port_connected(dev_priv, port); |
4679 | else if (IS_VALLEYVIEW(dev_priv)) |
4679 | else if (IS_VALLEYVIEW(dev_priv)) |
4680 | return vlv_digital_port_connected(dev_priv, port); |
4680 | return vlv_digital_port_connected(dev_priv, port); |
4681 | else |
4681 | else |
4682 | return g4x_digital_port_connected(dev_priv, port); |
4682 | return g4x_digital_port_connected(dev_priv, port); |
4683 | } |
4683 | } |
4684 | 4684 | ||
4685 | static enum drm_connector_status |
4685 | static enum drm_connector_status |
4686 | ironlake_dp_detect(struct intel_dp *intel_dp) |
4686 | ironlake_dp_detect(struct intel_dp *intel_dp) |
4687 | { |
4687 | { |
4688 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4688 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4689 | struct drm_i915_private *dev_priv = dev->dev_private; |
4689 | struct drm_i915_private *dev_priv = dev->dev_private; |
4690 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4690 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4691 | 4691 | ||
4692 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
4692 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
4693 | return connector_status_disconnected; |
4693 | return connector_status_disconnected; |
4694 | 4694 | ||
4695 | return intel_dp_detect_dpcd(intel_dp); |
4695 | return intel_dp_detect_dpcd(intel_dp); |
4696 | } |
4696 | } |
4697 | 4697 | ||
4698 | static enum drm_connector_status |
4698 | static enum drm_connector_status |
4699 | g4x_dp_detect(struct intel_dp *intel_dp) |
4699 | g4x_dp_detect(struct intel_dp *intel_dp) |
4700 | { |
4700 | { |
4701 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4701 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4702 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4702 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4703 | 4703 | ||
4704 | /* Can't disconnect eDP, but you can close the lid... */ |
4704 | /* Can't disconnect eDP, but you can close the lid... */ |
4705 | if (is_edp(intel_dp)) { |
4705 | if (is_edp(intel_dp)) { |
4706 | enum drm_connector_status status; |
4706 | enum drm_connector_status status; |
4707 | 4707 | ||
4708 | status = intel_panel_detect(dev); |
4708 | status = intel_panel_detect(dev); |
4709 | if (status == connector_status_unknown) |
4709 | if (status == connector_status_unknown) |
4710 | status = connector_status_connected; |
4710 | status = connector_status_connected; |
4711 | return status; |
4711 | return status; |
4712 | } |
4712 | } |
4713 | 4713 | ||
4714 | if (!intel_digital_port_connected(dev->dev_private, intel_dig_port)) |
4714 | if (!intel_digital_port_connected(dev->dev_private, intel_dig_port)) |
4715 | return connector_status_disconnected; |
4715 | return connector_status_disconnected; |
4716 | 4716 | ||
4717 | return intel_dp_detect_dpcd(intel_dp); |
4717 | return intel_dp_detect_dpcd(intel_dp); |
4718 | } |
4718 | } |
4719 | 4719 | ||
4720 | static struct edid * |
4720 | static struct edid * |
4721 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4721 | intel_dp_get_edid(struct intel_dp *intel_dp) |
4722 | { |
4722 | { |
4723 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4723 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4724 | 4724 | ||
4725 | /* use cached edid if we have one */ |
4725 | /* use cached edid if we have one */ |
4726 | if (intel_connector->edid) { |
4726 | if (intel_connector->edid) { |
4727 | /* invalid edid */ |
4727 | /* invalid edid */ |
4728 | if (IS_ERR(intel_connector->edid)) |
4728 | if (IS_ERR(intel_connector->edid)) |
4729 | return NULL; |
4729 | return NULL; |
4730 | 4730 | ||
4731 | return drm_edid_duplicate(intel_connector->edid); |
4731 | return drm_edid_duplicate(intel_connector->edid); |
4732 | } else |
4732 | } else |
4733 | return drm_get_edid(&intel_connector->base, |
4733 | return drm_get_edid(&intel_connector->base, |
4734 | &intel_dp->aux.ddc); |
4734 | &intel_dp->aux.ddc); |
4735 | } |
4735 | } |
4736 | 4736 | ||
4737 | static void |
4737 | static void |
4738 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4738 | intel_dp_set_edid(struct intel_dp *intel_dp) |
4739 | { |
4739 | { |
4740 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4740 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4741 | struct edid *edid; |
4741 | struct edid *edid; |
4742 | 4742 | ||
4743 | edid = intel_dp_get_edid(intel_dp); |
4743 | edid = intel_dp_get_edid(intel_dp); |
4744 | intel_connector->detect_edid = edid; |
4744 | intel_connector->detect_edid = edid; |
4745 | 4745 | ||
4746 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4746 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
4747 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4747 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
4748 | else |
4748 | else |
4749 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4749 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
4750 | } |
4750 | } |
4751 | 4751 | ||
4752 | static void |
4752 | static void |
4753 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4753 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
4754 | { |
4754 | { |
4755 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4755 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4756 | 4756 | ||
4757 | kfree(intel_connector->detect_edid); |
4757 | kfree(intel_connector->detect_edid); |
4758 | intel_connector->detect_edid = NULL; |
4758 | intel_connector->detect_edid = NULL; |
4759 | 4759 | ||
4760 | intel_dp->has_audio = false; |
4760 | intel_dp->has_audio = false; |
4761 | } |
4761 | } |
4762 | 4762 | ||
4763 | static enum drm_connector_status |
4763 | static enum drm_connector_status |
4764 | intel_dp_detect(struct drm_connector *connector, bool force) |
4764 | intel_dp_detect(struct drm_connector *connector, bool force) |
4765 | { |
4765 | { |
4766 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4766 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4767 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4767 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4768 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4768 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4769 | struct drm_device *dev = connector->dev; |
4769 | struct drm_device *dev = connector->dev; |
4770 | enum drm_connector_status status; |
4770 | enum drm_connector_status status; |
4771 | enum intel_display_power_domain power_domain; |
4771 | enum intel_display_power_domain power_domain; |
4772 | bool ret; |
4772 | bool ret; |
4773 | u8 sink_irq_vector; |
4773 | u8 sink_irq_vector; |
4774 | 4774 | ||
4775 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4775 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4776 | connector->base.id, connector->name); |
4776 | connector->base.id, connector->name); |
4777 | intel_dp_unset_edid(intel_dp); |
4777 | intel_dp_unset_edid(intel_dp); |
4778 | 4778 | ||
4779 | if (intel_dp->is_mst) { |
4779 | if (intel_dp->is_mst) { |
4780 | /* MST devices are disconnected from a monitor POV */ |
4780 | /* MST devices are disconnected from a monitor POV */ |
4781 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4781 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4782 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4782 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4783 | return connector_status_disconnected; |
4783 | return connector_status_disconnected; |
4784 | } |
4784 | } |
4785 | 4785 | ||
4786 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4786 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4787 | intel_display_power_get(to_i915(dev), power_domain); |
4787 | intel_display_power_get(to_i915(dev), power_domain); |
4788 | 4788 | ||
4789 | /* Can't disconnect eDP, but you can close the lid... */ |
4789 | /* Can't disconnect eDP, but you can close the lid... */ |
4790 | if (is_edp(intel_dp)) |
4790 | if (is_edp(intel_dp)) |
4791 | status = edp_detect(intel_dp); |
4791 | status = edp_detect(intel_dp); |
4792 | else if (HAS_PCH_SPLIT(dev)) |
4792 | else if (HAS_PCH_SPLIT(dev)) |
4793 | status = ironlake_dp_detect(intel_dp); |
4793 | status = ironlake_dp_detect(intel_dp); |
4794 | else |
4794 | else |
4795 | status = g4x_dp_detect(intel_dp); |
4795 | status = g4x_dp_detect(intel_dp); |
4796 | if (status != connector_status_connected) |
4796 | if (status != connector_status_connected) |
4797 | goto out; |
4797 | goto out; |
4798 | 4798 | ||
4799 | intel_dp_probe_oui(intel_dp); |
4799 | intel_dp_probe_oui(intel_dp); |
4800 | 4800 | ||
4801 | ret = intel_dp_probe_mst(intel_dp); |
4801 | ret = intel_dp_probe_mst(intel_dp); |
4802 | if (ret) { |
4802 | if (ret) { |
4803 | /* if we are in MST mode then this connector |
4803 | /* if we are in MST mode then this connector |
4804 | won't appear connected or have anything with EDID on it */ |
4804 | won't appear connected or have anything with EDID on it */ |
4805 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4805 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4806 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4806 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4807 | status = connector_status_disconnected; |
4807 | status = connector_status_disconnected; |
4808 | goto out; |
4808 | goto out; |
4809 | } |
4809 | } |
4810 | 4810 | ||
4811 | intel_dp_set_edid(intel_dp); |
4811 | intel_dp_set_edid(intel_dp); |
4812 | 4812 | ||
4813 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4813 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4814 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4814 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4815 | status = connector_status_connected; |
4815 | status = connector_status_connected; |
4816 | 4816 | ||
4817 | /* Try to read the source of the interrupt */ |
4817 | /* Try to read the source of the interrupt */ |
4818 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4818 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4819 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4819 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
4820 | /* Clear interrupt source */ |
4820 | /* Clear interrupt source */ |
4821 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4821 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4822 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4822 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
4823 | sink_irq_vector); |
4823 | sink_irq_vector); |
4824 | 4824 | ||
4825 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4825 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
4826 | intel_dp_handle_test_request(intel_dp); |
4826 | intel_dp_handle_test_request(intel_dp); |
4827 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4827 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4828 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4828 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
4829 | } |
4829 | } |
4830 | 4830 | ||
4831 | out: |
4831 | out: |
4832 | intel_display_power_put(to_i915(dev), power_domain); |
4832 | intel_display_power_put(to_i915(dev), power_domain); |
4833 | return status; |
4833 | return status; |
4834 | } |
4834 | } |
4835 | 4835 | ||
4836 | static void |
4836 | static void |
4837 | intel_dp_force(struct drm_connector *connector) |
4837 | intel_dp_force(struct drm_connector *connector) |
4838 | { |
4838 | { |
4839 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4839 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4840 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4840 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
4841 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4841 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
4842 | enum intel_display_power_domain power_domain; |
4842 | enum intel_display_power_domain power_domain; |
4843 | 4843 | ||
4844 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4844 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4845 | connector->base.id, connector->name); |
4845 | connector->base.id, connector->name); |
4846 | intel_dp_unset_edid(intel_dp); |
4846 | intel_dp_unset_edid(intel_dp); |
4847 | 4847 | ||
4848 | if (connector->status != connector_status_connected) |
4848 | if (connector->status != connector_status_connected) |
4849 | return; |
4849 | return; |
4850 | 4850 | ||
4851 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4851 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4852 | intel_display_power_get(dev_priv, power_domain); |
4852 | intel_display_power_get(dev_priv, power_domain); |
4853 | 4853 | ||
4854 | intel_dp_set_edid(intel_dp); |
4854 | intel_dp_set_edid(intel_dp); |
4855 | 4855 | ||
4856 | intel_display_power_put(dev_priv, power_domain); |
4856 | intel_display_power_put(dev_priv, power_domain); |
4857 | 4857 | ||
4858 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4858 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4859 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4859 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
4860 | } |
4860 | } |
4861 | 4861 | ||
4862 | static int intel_dp_get_modes(struct drm_connector *connector) |
4862 | static int intel_dp_get_modes(struct drm_connector *connector) |
4863 | { |
4863 | { |
4864 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4864 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4865 | struct edid *edid; |
4865 | struct edid *edid; |
4866 | 4866 | ||
4867 | edid = intel_connector->detect_edid; |
4867 | edid = intel_connector->detect_edid; |
4868 | if (edid) { |
4868 | if (edid) { |
4869 | int ret = intel_connector_update_modes(connector, edid); |
4869 | int ret = intel_connector_update_modes(connector, edid); |
4870 | if (ret) |
4870 | if (ret) |
4871 | return ret; |
4871 | return ret; |
4872 | } |
4872 | } |
4873 | 4873 | ||
4874 | /* if eDP has no EDID, fall back to fixed mode */ |
4874 | /* if eDP has no EDID, fall back to fixed mode */ |
4875 | if (is_edp(intel_attached_dp(connector)) && |
4875 | if (is_edp(intel_attached_dp(connector)) && |
4876 | intel_connector->panel.fixed_mode) { |
4876 | intel_connector->panel.fixed_mode) { |
4877 | struct drm_display_mode *mode; |
4877 | struct drm_display_mode *mode; |
4878 | 4878 | ||
4879 | mode = drm_mode_duplicate(connector->dev, |
4879 | mode = drm_mode_duplicate(connector->dev, |
4880 | intel_connector->panel.fixed_mode); |
4880 | intel_connector->panel.fixed_mode); |
4881 | if (mode) { |
4881 | if (mode) { |
4882 | drm_mode_probed_add(connector, mode); |
4882 | drm_mode_probed_add(connector, mode); |
4883 | return 1; |
4883 | return 1; |
4884 | } |
4884 | } |
4885 | } |
4885 | } |
4886 | 4886 | ||
4887 | return 0; |
4887 | return 0; |
4888 | } |
4888 | } |
4889 | 4889 | ||
4890 | static bool |
4890 | static bool |
4891 | intel_dp_detect_audio(struct drm_connector *connector) |
4891 | intel_dp_detect_audio(struct drm_connector *connector) |
4892 | { |
4892 | { |
4893 | bool has_audio = false; |
4893 | bool has_audio = false; |
4894 | struct edid *edid; |
4894 | struct edid *edid; |
4895 | 4895 | ||
4896 | edid = to_intel_connector(connector)->detect_edid; |
4896 | edid = to_intel_connector(connector)->detect_edid; |
4897 | if (edid) |
4897 | if (edid) |
4898 | has_audio = drm_detect_monitor_audio(edid); |
4898 | has_audio = drm_detect_monitor_audio(edid); |
4899 | 4899 | ||
4900 | return has_audio; |
4900 | return has_audio; |
4901 | } |
4901 | } |
4902 | 4902 | ||
4903 | static int |
4903 | static int |
4904 | intel_dp_set_property(struct drm_connector *connector, |
4904 | intel_dp_set_property(struct drm_connector *connector, |
4905 | struct drm_property *property, |
4905 | struct drm_property *property, |
4906 | uint64_t val) |
4906 | uint64_t val) |
4907 | { |
4907 | { |
4908 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4908 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
4909 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4909 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4910 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4910 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4911 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4911 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
4912 | int ret; |
4912 | int ret; |
4913 | 4913 | ||
4914 | ret = drm_object_property_set_value(&connector->base, property, val); |
4914 | ret = drm_object_property_set_value(&connector->base, property, val); |
4915 | if (ret) |
4915 | if (ret) |
4916 | return ret; |
4916 | return ret; |
4917 | 4917 | ||
4918 | if (property == dev_priv->force_audio_property) { |
4918 | if (property == dev_priv->force_audio_property) { |
4919 | int i = val; |
4919 | int i = val; |
4920 | bool has_audio; |
4920 | bool has_audio; |
4921 | 4921 | ||
4922 | if (i == intel_dp->force_audio) |
4922 | if (i == intel_dp->force_audio) |
4923 | return 0; |
4923 | return 0; |
4924 | 4924 | ||
4925 | intel_dp->force_audio = i; |
4925 | intel_dp->force_audio = i; |
4926 | 4926 | ||
4927 | if (i == HDMI_AUDIO_AUTO) |
4927 | if (i == HDMI_AUDIO_AUTO) |
4928 | has_audio = intel_dp_detect_audio(connector); |
4928 | has_audio = intel_dp_detect_audio(connector); |
4929 | else |
4929 | else |
4930 | has_audio = (i == HDMI_AUDIO_ON); |
4930 | has_audio = (i == HDMI_AUDIO_ON); |
4931 | 4931 | ||
4932 | if (has_audio == intel_dp->has_audio) |
4932 | if (has_audio == intel_dp->has_audio) |
4933 | return 0; |
4933 | return 0; |
4934 | 4934 | ||
4935 | intel_dp->has_audio = has_audio; |
4935 | intel_dp->has_audio = has_audio; |
4936 | goto done; |
4936 | goto done; |
4937 | } |
4937 | } |
4938 | 4938 | ||
4939 | if (property == dev_priv->broadcast_rgb_property) { |
4939 | if (property == dev_priv->broadcast_rgb_property) { |
4940 | bool old_auto = intel_dp->color_range_auto; |
4940 | bool old_auto = intel_dp->color_range_auto; |
4941 | bool old_range = intel_dp->limited_color_range; |
4941 | bool old_range = intel_dp->limited_color_range; |
4942 | 4942 | ||
4943 | switch (val) { |
4943 | switch (val) { |
4944 | case INTEL_BROADCAST_RGB_AUTO: |
4944 | case INTEL_BROADCAST_RGB_AUTO: |
4945 | intel_dp->color_range_auto = true; |
4945 | intel_dp->color_range_auto = true; |
4946 | break; |
4946 | break; |
4947 | case INTEL_BROADCAST_RGB_FULL: |
4947 | case INTEL_BROADCAST_RGB_FULL: |
4948 | intel_dp->color_range_auto = false; |
4948 | intel_dp->color_range_auto = false; |
4949 | intel_dp->limited_color_range = false; |
4949 | intel_dp->limited_color_range = false; |
4950 | break; |
4950 | break; |
4951 | case INTEL_BROADCAST_RGB_LIMITED: |
4951 | case INTEL_BROADCAST_RGB_LIMITED: |
4952 | intel_dp->color_range_auto = false; |
4952 | intel_dp->color_range_auto = false; |
4953 | intel_dp->limited_color_range = true; |
4953 | intel_dp->limited_color_range = true; |
4954 | break; |
4954 | break; |
4955 | default: |
4955 | default: |
4956 | return -EINVAL; |
4956 | return -EINVAL; |
4957 | } |
4957 | } |
4958 | 4958 | ||
4959 | if (old_auto == intel_dp->color_range_auto && |
4959 | if (old_auto == intel_dp->color_range_auto && |
4960 | old_range == intel_dp->limited_color_range) |
4960 | old_range == intel_dp->limited_color_range) |
4961 | return 0; |
4961 | return 0; |
4962 | 4962 | ||
4963 | goto done; |
4963 | goto done; |
4964 | } |
4964 | } |
4965 | 4965 | ||
4966 | if (is_edp(intel_dp) && |
4966 | if (is_edp(intel_dp) && |
4967 | property == connector->dev->mode_config.scaling_mode_property) { |
4967 | property == connector->dev->mode_config.scaling_mode_property) { |
4968 | if (val == DRM_MODE_SCALE_NONE) { |
4968 | if (val == DRM_MODE_SCALE_NONE) { |
4969 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4969 | DRM_DEBUG_KMS("no scaling not supported\n"); |
4970 | return -EINVAL; |
4970 | return -EINVAL; |
4971 | } |
4971 | } |
4972 | 4972 | ||
4973 | if (intel_connector->panel.fitting_mode == val) { |
4973 | if (intel_connector->panel.fitting_mode == val) { |
4974 | /* the eDP scaling property is not changed */ |
4974 | /* the eDP scaling property is not changed */ |
4975 | return 0; |
4975 | return 0; |
4976 | } |
4976 | } |
4977 | intel_connector->panel.fitting_mode = val; |
4977 | intel_connector->panel.fitting_mode = val; |
4978 | 4978 | ||
4979 | goto done; |
4979 | goto done; |
4980 | } |
4980 | } |
4981 | 4981 | ||
4982 | return -EINVAL; |
4982 | return -EINVAL; |
4983 | 4983 | ||
4984 | done: |
4984 | done: |
4985 | if (intel_encoder->base.crtc) |
4985 | if (intel_encoder->base.crtc) |
4986 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4986 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
4987 | 4987 | ||
4988 | return 0; |
4988 | return 0; |
4989 | } |
4989 | } |
4990 | 4990 | ||
4991 | static void |
4991 | static void |
4992 | intel_dp_connector_destroy(struct drm_connector *connector) |
4992 | intel_dp_connector_destroy(struct drm_connector *connector) |
4993 | { |
4993 | { |
4994 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4994 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4995 | 4995 | ||
4996 | kfree(intel_connector->detect_edid); |
4996 | kfree(intel_connector->detect_edid); |
4997 | 4997 | ||
4998 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4998 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4999 | kfree(intel_connector->edid); |
4999 | kfree(intel_connector->edid); |
5000 | 5000 | ||
5001 | /* Can't call is_edp() since the encoder may have been destroyed |
5001 | /* Can't call is_edp() since the encoder may have been destroyed |
5002 | * already. */ |
5002 | * already. */ |
5003 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
5003 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
5004 | intel_panel_fini(&intel_connector->panel); |
5004 | intel_panel_fini(&intel_connector->panel); |
5005 | 5005 | ||
5006 | drm_connector_cleanup(connector); |
5006 | drm_connector_cleanup(connector); |
5007 | kfree(connector); |
5007 | kfree(connector); |
5008 | } |
5008 | } |
5009 | 5009 | ||
5010 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
5010 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
5011 | { |
5011 | { |
5012 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5012 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5013 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5013 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5014 | 5014 | ||
5015 | drm_dp_aux_unregister(&intel_dp->aux); |
5015 | drm_dp_aux_unregister(&intel_dp->aux); |
5016 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
5016 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
5017 | if (is_edp(intel_dp)) { |
5017 | if (is_edp(intel_dp)) { |
5018 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5018 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5019 | /* |
5019 | /* |
5020 | * vdd might still be enabled do to the delayed vdd off. |
5020 | * vdd might still be enabled do to the delayed vdd off. |
5021 | * Make sure vdd is actually turned off here. |
5021 | * Make sure vdd is actually turned off here. |
5022 | */ |
5022 | */ |
5023 | pps_lock(intel_dp); |
5023 | pps_lock(intel_dp); |
5024 | edp_panel_vdd_off_sync(intel_dp); |
5024 | edp_panel_vdd_off_sync(intel_dp); |
5025 | pps_unlock(intel_dp); |
5025 | pps_unlock(intel_dp); |
5026 | 5026 | ||
5027 | } |
5027 | } |
5028 | drm_encoder_cleanup(encoder); |
5028 | drm_encoder_cleanup(encoder); |
5029 | kfree(intel_dig_port); |
5029 | kfree(intel_dig_port); |
5030 | } |
5030 | } |
5031 | 5031 | ||
5032 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
5032 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
5033 | { |
5033 | { |
5034 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
5034 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
5035 | 5035 | ||
5036 | if (!is_edp(intel_dp)) |
5036 | if (!is_edp(intel_dp)) |
5037 | return; |
5037 | return; |
5038 | 5038 | ||
5039 | /* |
5039 | /* |
5040 | * vdd might still be enabled do to the delayed vdd off. |
5040 | * vdd might still be enabled do to the delayed vdd off. |
5041 | * Make sure vdd is actually turned off here. |
5041 | * Make sure vdd is actually turned off here. |
5042 | */ |
5042 | */ |
5043 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5043 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
5044 | pps_lock(intel_dp); |
5044 | pps_lock(intel_dp); |
5045 | edp_panel_vdd_off_sync(intel_dp); |
5045 | edp_panel_vdd_off_sync(intel_dp); |
5046 | pps_unlock(intel_dp); |
5046 | pps_unlock(intel_dp); |
5047 | } |
5047 | } |
5048 | 5048 | ||
5049 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
5049 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
5050 | { |
5050 | { |
5051 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5051 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5052 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5052 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5053 | struct drm_i915_private *dev_priv = dev->dev_private; |
5053 | struct drm_i915_private *dev_priv = dev->dev_private; |
5054 | enum intel_display_power_domain power_domain; |
5054 | enum intel_display_power_domain power_domain; |
5055 | 5055 | ||
5056 | lockdep_assert_held(&dev_priv->pps_mutex); |
5056 | lockdep_assert_held(&dev_priv->pps_mutex); |
5057 | 5057 | ||
5058 | if (!edp_have_panel_vdd(intel_dp)) |
5058 | if (!edp_have_panel_vdd(intel_dp)) |
5059 | return; |
5059 | return; |
5060 | 5060 | ||
5061 | /* |
5061 | /* |
5062 | * The VDD bit needs a power domain reference, so if the bit is |
5062 | * The VDD bit needs a power domain reference, so if the bit is |
5063 | * already enabled when we boot or resume, grab this reference and |
5063 | * already enabled when we boot or resume, grab this reference and |
5064 | * schedule a vdd off, so we don't hold on to the reference |
5064 | * schedule a vdd off, so we don't hold on to the reference |
5065 | * indefinitely. |
5065 | * indefinitely. |
5066 | */ |
5066 | */ |
5067 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
5067 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
5068 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
5068 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
5069 | intel_display_power_get(dev_priv, power_domain); |
5069 | intel_display_power_get(dev_priv, power_domain); |
5070 | 5070 | ||
5071 | edp_panel_vdd_schedule_off(intel_dp); |
5071 | edp_panel_vdd_schedule_off(intel_dp); |
5072 | } |
5072 | } |
5073 | 5073 | ||
5074 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
5074 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
5075 | { |
5075 | { |
5076 | struct intel_dp *intel_dp; |
5076 | struct intel_dp *intel_dp; |
5077 | 5077 | ||
5078 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
5078 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
5079 | return; |
5079 | return; |
5080 | 5080 | ||
5081 | intel_dp = enc_to_intel_dp(encoder); |
5081 | intel_dp = enc_to_intel_dp(encoder); |
5082 | 5082 | ||
5083 | pps_lock(intel_dp); |
5083 | pps_lock(intel_dp); |
5084 | 5084 | ||
5085 | /* |
5085 | /* |
5086 | * Read out the current power sequencer assignment, |
5086 | * Read out the current power sequencer assignment, |
5087 | * in case the BIOS did something with it. |
5087 | * in case the BIOS did something with it. |
5088 | */ |
5088 | */ |
5089 | if (IS_VALLEYVIEW(encoder->dev)) |
5089 | if (IS_VALLEYVIEW(encoder->dev)) |
5090 | vlv_initial_power_sequencer_setup(intel_dp); |
5090 | vlv_initial_power_sequencer_setup(intel_dp); |
5091 | 5091 | ||
5092 | intel_edp_panel_vdd_sanitize(intel_dp); |
5092 | intel_edp_panel_vdd_sanitize(intel_dp); |
5093 | 5093 | ||
5094 | pps_unlock(intel_dp); |
5094 | pps_unlock(intel_dp); |
5095 | } |
5095 | } |
5096 | 5096 | ||
5097 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
5097 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
5098 | .dpms = drm_atomic_helper_connector_dpms, |
5098 | .dpms = drm_atomic_helper_connector_dpms, |
5099 | .detect = intel_dp_detect, |
5099 | .detect = intel_dp_detect, |
5100 | .force = intel_dp_force, |
5100 | .force = intel_dp_force, |
5101 | .fill_modes = drm_helper_probe_single_connector_modes, |
5101 | .fill_modes = drm_helper_probe_single_connector_modes, |
5102 | .set_property = intel_dp_set_property, |
5102 | .set_property = intel_dp_set_property, |
5103 | .atomic_get_property = intel_connector_atomic_get_property, |
5103 | .atomic_get_property = intel_connector_atomic_get_property, |
5104 | .destroy = intel_dp_connector_destroy, |
5104 | .destroy = intel_dp_connector_destroy, |
5105 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
5105 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
5106 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
5106 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
5107 | }; |
5107 | }; |
5108 | 5108 | ||
5109 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
5109 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
5110 | .get_modes = intel_dp_get_modes, |
5110 | .get_modes = intel_dp_get_modes, |
5111 | .mode_valid = intel_dp_mode_valid, |
5111 | .mode_valid = intel_dp_mode_valid, |
5112 | .best_encoder = intel_best_encoder, |
5112 | .best_encoder = intel_best_encoder, |
5113 | }; |
5113 | }; |
5114 | 5114 | ||
5115 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
5115 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
5116 | .reset = intel_dp_encoder_reset, |
5116 | .reset = intel_dp_encoder_reset, |
5117 | .destroy = intel_dp_encoder_destroy, |
5117 | .destroy = intel_dp_encoder_destroy, |
5118 | }; |
5118 | }; |
5119 | 5119 | ||
5120 | enum irqreturn |
5120 | enum irqreturn |
5121 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5121 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5122 | { |
5122 | { |
5123 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5123 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5124 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5124 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5125 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5125 | struct drm_device *dev = intel_dig_port->base.base.dev; |
5126 | struct drm_i915_private *dev_priv = dev->dev_private; |
5126 | struct drm_i915_private *dev_priv = dev->dev_private; |
5127 | enum intel_display_power_domain power_domain; |
5127 | enum intel_display_power_domain power_domain; |
5128 | enum irqreturn ret = IRQ_NONE; |
5128 | enum irqreturn ret = IRQ_NONE; |
5129 | 5129 | ||
5130 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5130 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5131 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
5131 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
5132 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
5132 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
5133 | 5133 | ||
5134 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5134 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5135 | /* |
5135 | /* |
5136 | * vdd off can generate a long pulse on eDP which |
5136 | * vdd off can generate a long pulse on eDP which |
5137 | * would require vdd on to handle it, and thus we |
5137 | * would require vdd on to handle it, and thus we |
5138 | * would end up in an endless cycle of |
5138 | * would end up in an endless cycle of |
5139 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5139 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
5140 | */ |
5140 | */ |
5141 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5141 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
5142 | port_name(intel_dig_port->port)); |
5142 | port_name(intel_dig_port->port)); |
5143 | return IRQ_HANDLED; |
5143 | return IRQ_HANDLED; |
5144 | } |
5144 | } |
5145 | 5145 | ||
5146 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5146 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5147 | port_name(intel_dig_port->port), |
5147 | port_name(intel_dig_port->port), |
5148 | long_hpd ? "long" : "short"); |
5148 | long_hpd ? "long" : "short"); |
5149 | 5149 | ||
5150 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5150 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
5151 | intel_display_power_get(dev_priv, power_domain); |
5151 | intel_display_power_get(dev_priv, power_domain); |
5152 | 5152 | ||
5153 | if (long_hpd) { |
5153 | if (long_hpd) { |
5154 | /* indicate that we need to restart link training */ |
5154 | /* indicate that we need to restart link training */ |
5155 | intel_dp->train_set_valid = false; |
5155 | intel_dp->train_set_valid = false; |
5156 | 5156 | ||
5157 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5157 | if (!intel_digital_port_connected(dev_priv, intel_dig_port)) |
5158 | goto mst_fail; |
5158 | goto mst_fail; |
5159 | 5159 | ||
5160 | if (!intel_dp_get_dpcd(intel_dp)) { |
5160 | if (!intel_dp_get_dpcd(intel_dp)) { |
5161 | goto mst_fail; |
5161 | goto mst_fail; |
5162 | } |
5162 | } |
5163 | 5163 | ||
5164 | intel_dp_probe_oui(intel_dp); |
5164 | intel_dp_probe_oui(intel_dp); |
5165 | 5165 | ||
5166 | if (!intel_dp_probe_mst(intel_dp)) { |
5166 | if (!intel_dp_probe_mst(intel_dp)) { |
5167 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5167 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5168 | intel_dp_check_link_status(intel_dp); |
5168 | intel_dp_check_link_status(intel_dp); |
5169 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5169 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5170 | goto mst_fail; |
5170 | goto mst_fail; |
5171 | } |
5171 | } |
5172 | } else { |
5172 | } else { |
5173 | if (intel_dp->is_mst) { |
5173 | if (intel_dp->is_mst) { |
5174 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5174 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
5175 | goto mst_fail; |
5175 | goto mst_fail; |
5176 | } |
5176 | } |
5177 | 5177 | ||
5178 | if (!intel_dp->is_mst) { |
5178 | if (!intel_dp->is_mst) { |
5179 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5179 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
5180 | intel_dp_check_link_status(intel_dp); |
5180 | intel_dp_check_link_status(intel_dp); |
5181 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5181 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
5182 | } |
5182 | } |
5183 | } |
5183 | } |
5184 | 5184 | ||
5185 | ret = IRQ_HANDLED; |
5185 | ret = IRQ_HANDLED; |
5186 | 5186 | ||
5187 | goto put_power; |
5187 | goto put_power; |
5188 | mst_fail: |
5188 | mst_fail: |
5189 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5189 | /* if we were in MST mode, and device is not there get out of MST mode */ |
5190 | if (intel_dp->is_mst) { |
5190 | if (intel_dp->is_mst) { |
5191 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5191 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
5192 | intel_dp->is_mst = false; |
5192 | intel_dp->is_mst = false; |
5193 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5193 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
5194 | } |
5194 | } |
5195 | put_power: |
5195 | put_power: |
5196 | intel_display_power_put(dev_priv, power_domain); |
5196 | intel_display_power_put(dev_priv, power_domain); |
5197 | 5197 | ||
5198 | return ret; |
5198 | return ret; |
5199 | } |
5199 | } |
5200 | 5200 | ||
5201 | /* Return which DP Port should be selected for Transcoder DP control */ |
5201 | /* Return which DP Port should be selected for Transcoder DP control */ |
5202 | int |
5202 | int |
5203 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
5203 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
5204 | { |
5204 | { |
5205 | struct drm_device *dev = crtc->dev; |
5205 | struct drm_device *dev = crtc->dev; |
5206 | struct intel_encoder *intel_encoder; |
5206 | struct intel_encoder *intel_encoder; |
5207 | struct intel_dp *intel_dp; |
5207 | struct intel_dp *intel_dp; |
5208 | 5208 | ||
5209 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5209 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5210 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
5210 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
5211 | 5211 | ||
5212 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
5212 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
5213 | intel_encoder->type == INTEL_OUTPUT_EDP) |
5213 | intel_encoder->type == INTEL_OUTPUT_EDP) |
5214 | return intel_dp->output_reg; |
5214 | return intel_dp->output_reg; |
5215 | } |
5215 | } |
5216 | 5216 | ||
5217 | return -1; |
5217 | return -1; |
5218 | } |
5218 | } |
5219 | 5219 | ||
5220 | /* check the VBT to see whether the eDP is on another port */ |
5220 | /* check the VBT to see whether the eDP is on another port */ |
5221 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5221 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
5222 | { |
5222 | { |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; |
5224 | union child_device_config *p_child; |
5224 | union child_device_config *p_child; |
5225 | int i; |
5225 | int i; |
5226 | static const short port_mapping[] = { |
5226 | static const short port_mapping[] = { |
5227 | [PORT_B] = DVO_PORT_DPB, |
5227 | [PORT_B] = DVO_PORT_DPB, |
5228 | [PORT_C] = DVO_PORT_DPC, |
5228 | [PORT_C] = DVO_PORT_DPC, |
5229 | [PORT_D] = DVO_PORT_DPD, |
5229 | [PORT_D] = DVO_PORT_DPD, |
5230 | [PORT_E] = DVO_PORT_DPE, |
5230 | [PORT_E] = DVO_PORT_DPE, |
5231 | }; |
5231 | }; |
5232 | 5232 | ||
5233 | /* |
5233 | /* |
5234 | * eDP not supported on g4x. so bail out early just |
5234 | * eDP not supported on g4x. so bail out early just |
5235 | * for a bit extra safety in case the VBT is bonkers. |
5235 | * for a bit extra safety in case the VBT is bonkers. |
5236 | */ |
5236 | */ |
5237 | if (INTEL_INFO(dev)->gen < 5) |
5237 | if (INTEL_INFO(dev)->gen < 5) |
5238 | return false; |
5238 | return false; |
5239 | 5239 | ||
5240 | if (port == PORT_A) |
5240 | if (port == PORT_A) |
5241 | return true; |
5241 | return true; |
5242 | 5242 | ||
5243 | if (!dev_priv->vbt.child_dev_num) |
5243 | if (!dev_priv->vbt.child_dev_num) |
5244 | return false; |
5244 | return false; |
5245 | 5245 | ||
5246 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5246 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
5247 | p_child = dev_priv->vbt.child_dev + i; |
5247 | p_child = dev_priv->vbt.child_dev + i; |
5248 | 5248 | ||
5249 | if (p_child->common.dvo_port == port_mapping[port] && |
5249 | if (p_child->common.dvo_port == port_mapping[port] && |
5250 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5250 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
5251 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5251 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
5252 | return true; |
5252 | return true; |
5253 | } |
5253 | } |
5254 | return false; |
5254 | return false; |
5255 | } |
5255 | } |
5256 | 5256 | ||
5257 | void |
5257 | void |
5258 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5258 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5259 | { |
5259 | { |
5260 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5260 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5261 | 5261 | ||
5262 | intel_attach_force_audio_property(connector); |
5262 | intel_attach_force_audio_property(connector); |
5263 | intel_attach_broadcast_rgb_property(connector); |
5263 | intel_attach_broadcast_rgb_property(connector); |
5264 | intel_dp->color_range_auto = true; |
5264 | intel_dp->color_range_auto = true; |
5265 | 5265 | ||
5266 | if (is_edp(intel_dp)) { |
5266 | if (is_edp(intel_dp)) { |
5267 | drm_mode_create_scaling_mode_property(connector->dev); |
5267 | drm_mode_create_scaling_mode_property(connector->dev); |
5268 | drm_object_attach_property( |
5268 | drm_object_attach_property( |
5269 | &connector->base, |
5269 | &connector->base, |
5270 | connector->dev->mode_config.scaling_mode_property, |
5270 | connector->dev->mode_config.scaling_mode_property, |
5271 | DRM_MODE_SCALE_ASPECT); |
5271 | DRM_MODE_SCALE_ASPECT); |
5272 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5272 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
5273 | } |
5273 | } |
5274 | } |
5274 | } |
5275 | 5275 | ||
5276 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5276 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5277 | { |
5277 | { |
5278 | intel_dp->last_power_cycle = jiffies; |
5278 | intel_dp->last_power_cycle = jiffies; |
5279 | intel_dp->last_power_on = jiffies; |
5279 | intel_dp->last_power_on = jiffies; |
5280 | intel_dp->last_backlight_off = jiffies; |
5280 | intel_dp->last_backlight_off = jiffies; |
5281 | } |
5281 | } |
5282 | 5282 | ||
5283 | static void |
5283 | static void |
5284 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5284 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
5285 | struct intel_dp *intel_dp) |
5285 | struct intel_dp *intel_dp) |
5286 | { |
5286 | { |
5287 | struct drm_i915_private *dev_priv = dev->dev_private; |
5287 | struct drm_i915_private *dev_priv = dev->dev_private; |
5288 | struct edp_power_seq cur, vbt, spec, |
5288 | struct edp_power_seq cur, vbt, spec, |
5289 | *final = &intel_dp->pps_delays; |
5289 | *final = &intel_dp->pps_delays; |
5290 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5290 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
5291 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0; |
5291 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0; |
5292 | 5292 | ||
5293 | lockdep_assert_held(&dev_priv->pps_mutex); |
5293 | lockdep_assert_held(&dev_priv->pps_mutex); |
5294 | 5294 | ||
5295 | /* already initialized? */ |
5295 | /* already initialized? */ |
5296 | if (final->t11_t12 != 0) |
5296 | if (final->t11_t12 != 0) |
5297 | return; |
5297 | return; |
5298 | 5298 | ||
5299 | if (IS_BROXTON(dev)) { |
5299 | if (IS_BROXTON(dev)) { |
5300 | /* |
5300 | /* |
5301 | * TODO: BXT has 2 sets of PPS registers. |
5301 | * TODO: BXT has 2 sets of PPS registers. |
5302 | * Correct Register for Broxton need to be identified |
5302 | * Correct Register for Broxton need to be identified |
5303 | * using VBT. hardcoding for now |
5303 | * using VBT. hardcoding for now |
5304 | */ |
5304 | */ |
5305 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5305 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5306 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5306 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5307 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5307 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5308 | } else if (HAS_PCH_SPLIT(dev)) { |
5308 | } else if (HAS_PCH_SPLIT(dev)) { |
5309 | pp_ctrl_reg = PCH_PP_CONTROL; |
5309 | pp_ctrl_reg = PCH_PP_CONTROL; |
5310 | pp_on_reg = PCH_PP_ON_DELAYS; |
5310 | pp_on_reg = PCH_PP_ON_DELAYS; |
5311 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5311 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5312 | pp_div_reg = PCH_PP_DIVISOR; |
5312 | pp_div_reg = PCH_PP_DIVISOR; |
5313 | } else { |
5313 | } else { |
5314 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5314 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5315 | 5315 | ||
5316 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5316 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
5317 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5317 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5318 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5318 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5319 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5319 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5320 | } |
5320 | } |
5321 | 5321 | ||
5322 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5322 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
5323 | * the very first thing. */ |
5323 | * the very first thing. */ |
5324 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5324 | pp_ctl = ironlake_get_pp_control(intel_dp); |
5325 | 5325 | ||
5326 | pp_on = I915_READ(pp_on_reg); |
5326 | pp_on = I915_READ(pp_on_reg); |
5327 | pp_off = I915_READ(pp_off_reg); |
5327 | pp_off = I915_READ(pp_off_reg); |
5328 | if (!IS_BROXTON(dev)) { |
5328 | if (!IS_BROXTON(dev)) { |
5329 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5329 | I915_WRITE(pp_ctrl_reg, pp_ctl); |
5330 | pp_div = I915_READ(pp_div_reg); |
5330 | pp_div = I915_READ(pp_div_reg); |
5331 | } |
5331 | } |
5332 | 5332 | ||
5333 | /* Pull timing values out of registers */ |
5333 | /* Pull timing values out of registers */ |
5334 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5334 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5335 | PANEL_POWER_UP_DELAY_SHIFT; |
5335 | PANEL_POWER_UP_DELAY_SHIFT; |
5336 | 5336 | ||
5337 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5337 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5338 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5338 | PANEL_LIGHT_ON_DELAY_SHIFT; |
5339 | 5339 | ||
5340 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5340 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5341 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5341 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
5342 | 5342 | ||
5343 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5343 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5344 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5344 | PANEL_POWER_DOWN_DELAY_SHIFT; |
5345 | 5345 | ||
5346 | if (IS_BROXTON(dev)) { |
5346 | if (IS_BROXTON(dev)) { |
5347 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5347 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5348 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5348 | BXT_POWER_CYCLE_DELAY_SHIFT; |
5349 | if (tmp > 0) |
5349 | if (tmp > 0) |
5350 | cur.t11_t12 = (tmp - 1) * 1000; |
5350 | cur.t11_t12 = (tmp - 1) * 1000; |
5351 | else |
5351 | else |
5352 | cur.t11_t12 = 0; |
5352 | cur.t11_t12 = 0; |
5353 | } else { |
5353 | } else { |
5354 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5354 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
5355 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5355 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
5356 | } |
5356 | } |
5357 | 5357 | ||
5358 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5358 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5359 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5359 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
5360 | 5360 | ||
5361 | vbt = dev_priv->vbt.edp_pps; |
5361 | vbt = dev_priv->vbt.edp_pps; |
5362 | 5362 | ||
5363 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5363 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
5364 | * our hw here, which are all in 100usec. */ |
5364 | * our hw here, which are all in 100usec. */ |
5365 | spec.t1_t3 = 210 * 10; |
5365 | spec.t1_t3 = 210 * 10; |
5366 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5366 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
5367 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5367 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
5368 | spec.t10 = 500 * 10; |
5368 | spec.t10 = 500 * 10; |
5369 | /* This one is special and actually in units of 100ms, but zero |
5369 | /* This one is special and actually in units of 100ms, but zero |
5370 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5370 | * based in the hw (so we need to add 100 ms). But the sw vbt |
5371 | * table multiplies it with 1000 to make it in units of 100usec, |
5371 | * table multiplies it with 1000 to make it in units of 100usec, |
5372 | * too. */ |
5372 | * too. */ |
5373 | spec.t11_t12 = (510 + 100) * 10; |
5373 | spec.t11_t12 = (510 + 100) * 10; |
5374 | 5374 | ||
5375 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5375 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
5376 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5376 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
5377 | 5377 | ||
5378 | /* Use the max of the register settings and vbt. If both are |
5378 | /* Use the max of the register settings and vbt. If both are |
5379 | * unset, fall back to the spec limits. */ |
5379 | * unset, fall back to the spec limits. */ |
5380 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5380 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
5381 | spec.field : \ |
5381 | spec.field : \ |
5382 | max(cur.field, vbt.field)) |
5382 | max(cur.field, vbt.field)) |
5383 | assign_final(t1_t3); |
5383 | assign_final(t1_t3); |
5384 | assign_final(t8); |
5384 | assign_final(t8); |
5385 | assign_final(t9); |
5385 | assign_final(t9); |
5386 | assign_final(t10); |
5386 | assign_final(t10); |
5387 | assign_final(t11_t12); |
5387 | assign_final(t11_t12); |
5388 | #undef assign_final |
5388 | #undef assign_final |
5389 | 5389 | ||
5390 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5390 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
5391 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5391 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5392 | intel_dp->backlight_on_delay = get_delay(t8); |
5392 | intel_dp->backlight_on_delay = get_delay(t8); |
5393 | intel_dp->backlight_off_delay = get_delay(t9); |
5393 | intel_dp->backlight_off_delay = get_delay(t9); |
5394 | intel_dp->panel_power_down_delay = get_delay(t10); |
5394 | intel_dp->panel_power_down_delay = get_delay(t10); |
5395 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5395 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
5396 | #undef get_delay |
5396 | #undef get_delay |
5397 | 5397 | ||
5398 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5398 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5399 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5399 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
5400 | intel_dp->panel_power_cycle_delay); |
5400 | intel_dp->panel_power_cycle_delay); |
5401 | 5401 | ||
5402 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5402 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
5403 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5403 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
5404 | } |
5404 | } |
5405 | 5405 | ||
5406 | static void |
5406 | static void |
5407 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5407 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
5408 | struct intel_dp *intel_dp) |
5408 | struct intel_dp *intel_dp) |
5409 | { |
5409 | { |
5410 | struct drm_i915_private *dev_priv = dev->dev_private; |
5410 | struct drm_i915_private *dev_priv = dev->dev_private; |
5411 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5411 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5412 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5412 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
5413 | int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg; |
5413 | int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg; |
5414 | enum port port = dp_to_dig_port(intel_dp)->port; |
5414 | enum port port = dp_to_dig_port(intel_dp)->port; |
5415 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5415 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
5416 | 5416 | ||
5417 | lockdep_assert_held(&dev_priv->pps_mutex); |
5417 | lockdep_assert_held(&dev_priv->pps_mutex); |
5418 | 5418 | ||
5419 | if (IS_BROXTON(dev)) { |
5419 | if (IS_BROXTON(dev)) { |
5420 | /* |
5420 | /* |
5421 | * TODO: BXT has 2 sets of PPS registers. |
5421 | * TODO: BXT has 2 sets of PPS registers. |
5422 | * Correct Register for Broxton need to be identified |
5422 | * Correct Register for Broxton need to be identified |
5423 | * using VBT. hardcoding for now |
5423 | * using VBT. hardcoding for now |
5424 | */ |
5424 | */ |
5425 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5425 | pp_ctrl_reg = BXT_PP_CONTROL(0); |
5426 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5426 | pp_on_reg = BXT_PP_ON_DELAYS(0); |
5427 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5427 | pp_off_reg = BXT_PP_OFF_DELAYS(0); |
5428 | 5428 | ||
5429 | } else if (HAS_PCH_SPLIT(dev)) { |
5429 | } else if (HAS_PCH_SPLIT(dev)) { |
5430 | pp_on_reg = PCH_PP_ON_DELAYS; |
5430 | pp_on_reg = PCH_PP_ON_DELAYS; |
5431 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5431 | pp_off_reg = PCH_PP_OFF_DELAYS; |
5432 | pp_div_reg = PCH_PP_DIVISOR; |
5432 | pp_div_reg = PCH_PP_DIVISOR; |
5433 | } else { |
5433 | } else { |
5434 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5434 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5435 | 5435 | ||
5436 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5436 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
5437 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5437 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
5438 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5438 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
5439 | } |
5439 | } |
5440 | 5440 | ||
5441 | /* |
5441 | /* |
5442 | * And finally store the new values in the power sequencer. The |
5442 | * And finally store the new values in the power sequencer. The |
5443 | * backlight delays are set to 1 because we do manual waits on them. For |
5443 | * backlight delays are set to 1 because we do manual waits on them. For |
5444 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5444 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
5445 | * we'll end up waiting for the backlight off delay twice: once when we |
5445 | * we'll end up waiting for the backlight off delay twice: once when we |
5446 | * do the manual sleep, and once when we disable the panel and wait for |
5446 | * do the manual sleep, and once when we disable the panel and wait for |
5447 | * the PP_STATUS bit to become zero. |
5447 | * the PP_STATUS bit to become zero. |
5448 | */ |
5448 | */ |
5449 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5449 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
5450 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5450 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5451 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5451 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
5452 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5452 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
5453 | /* Compute the divisor for the pp clock, simply match the Bspec |
5453 | /* Compute the divisor for the pp clock, simply match the Bspec |
5454 | * formula. */ |
5454 | * formula. */ |
5455 | if (IS_BROXTON(dev)) { |
5455 | if (IS_BROXTON(dev)) { |
5456 | pp_div = I915_READ(pp_ctrl_reg); |
5456 | pp_div = I915_READ(pp_ctrl_reg); |
5457 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5457 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5458 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5458 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
5459 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5459 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5460 | } else { |
5460 | } else { |
5461 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5461 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
5462 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5462 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
5463 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5463 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5464 | } |
5464 | } |
5465 | 5465 | ||
5466 | /* Haswell doesn't have any port selection bits for the panel |
5466 | /* Haswell doesn't have any port selection bits for the panel |
5467 | * power sequencer any more. */ |
5467 | * power sequencer any more. */ |
5468 | if (IS_VALLEYVIEW(dev)) { |
5468 | if (IS_VALLEYVIEW(dev)) { |
5469 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5469 | port_sel = PANEL_PORT_SELECT_VLV(port); |
5470 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5470 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
5471 | if (port == PORT_A) |
5471 | if (port == PORT_A) |
5472 | port_sel = PANEL_PORT_SELECT_DPA; |
5472 | port_sel = PANEL_PORT_SELECT_DPA; |
5473 | else |
5473 | else |
5474 | port_sel = PANEL_PORT_SELECT_DPD; |
5474 | port_sel = PANEL_PORT_SELECT_DPD; |
5475 | } |
5475 | } |
5476 | 5476 | ||
5477 | pp_on |= port_sel; |
5477 | pp_on |= port_sel; |
5478 | 5478 | ||
5479 | I915_WRITE(pp_on_reg, pp_on); |
5479 | I915_WRITE(pp_on_reg, pp_on); |
5480 | I915_WRITE(pp_off_reg, pp_off); |
5480 | I915_WRITE(pp_off_reg, pp_off); |
5481 | if (IS_BROXTON(dev)) |
5481 | if (IS_BROXTON(dev)) |
5482 | I915_WRITE(pp_ctrl_reg, pp_div); |
5482 | I915_WRITE(pp_ctrl_reg, pp_div); |
5483 | else |
5483 | else |
5484 | I915_WRITE(pp_div_reg, pp_div); |
5484 | I915_WRITE(pp_div_reg, pp_div); |
5485 | 5485 | ||
5486 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5486 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
5487 | I915_READ(pp_on_reg), |
5487 | I915_READ(pp_on_reg), |
5488 | I915_READ(pp_off_reg), |
5488 | I915_READ(pp_off_reg), |
5489 | IS_BROXTON(dev) ? |
5489 | IS_BROXTON(dev) ? |
5490 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5490 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : |
5491 | I915_READ(pp_div_reg)); |
5491 | I915_READ(pp_div_reg)); |
5492 | } |
5492 | } |
5493 | 5493 | ||
5494 | /** |
5494 | /** |
5495 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5495 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
5496 | * @dev: DRM device |
5496 | * @dev: DRM device |
5497 | * @refresh_rate: RR to be programmed |
5497 | * @refresh_rate: RR to be programmed |
5498 | * |
5498 | * |
5499 | * This function gets called when refresh rate (RR) has to be changed from |
5499 | * This function gets called when refresh rate (RR) has to be changed from |
5500 | * one frequency to another. Switches can be between high and low RR |
5500 | * one frequency to another. Switches can be between high and low RR |
5501 | * supported by the panel or to any other RR based on media playback (in |
5501 | * supported by the panel or to any other RR based on media playback (in |
5502 | * this case, RR value needs to be passed from user space). |
5502 | * this case, RR value needs to be passed from user space). |
5503 | * |
5503 | * |
5504 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5504 | * The caller of this function needs to take a lock on dev_priv->drrs. |
5505 | */ |
5505 | */ |
5506 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5506 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5507 | { |
5507 | { |
5508 | struct drm_i915_private *dev_priv = dev->dev_private; |
5508 | struct drm_i915_private *dev_priv = dev->dev_private; |
5509 | struct intel_encoder *encoder; |
5509 | struct intel_encoder *encoder; |
5510 | struct intel_digital_port *dig_port = NULL; |
5510 | struct intel_digital_port *dig_port = NULL; |
5511 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5511 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
5512 | struct intel_crtc_state *config = NULL; |
5512 | struct intel_crtc_state *config = NULL; |
5513 | struct intel_crtc *intel_crtc = NULL; |
5513 | struct intel_crtc *intel_crtc = NULL; |
5514 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5514 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
5515 | 5515 | ||
5516 | if (refresh_rate <= 0) { |
5516 | if (refresh_rate <= 0) { |
5517 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5517 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
5518 | return; |
5518 | return; |
5519 | } |
5519 | } |
5520 | 5520 | ||
5521 | if (intel_dp == NULL) { |
5521 | if (intel_dp == NULL) { |
5522 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5522 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
5523 | return; |
5523 | return; |
5524 | } |
5524 | } |
5525 | 5525 | ||
5526 | /* |
5526 | /* |
5527 | * FIXME: This needs proper synchronization with psr state for some |
5527 | * FIXME: This needs proper synchronization with psr state for some |
5528 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5528 | * platforms that cannot have PSR and DRRS enabled at the same time. |
5529 | */ |
5529 | */ |
5530 | 5530 | ||
5531 | dig_port = dp_to_dig_port(intel_dp); |
5531 | dig_port = dp_to_dig_port(intel_dp); |
5532 | encoder = &dig_port->base; |
5532 | encoder = &dig_port->base; |
5533 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5533 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
5534 | 5534 | ||
5535 | if (!intel_crtc) { |
5535 | if (!intel_crtc) { |
5536 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5536 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
5537 | return; |
5537 | return; |
5538 | } |
5538 | } |
5539 | 5539 | ||
5540 | config = intel_crtc->config; |
5540 | config = intel_crtc->config; |
5541 | 5541 | ||
5542 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5542 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
5543 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5543 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5544 | return; |
5544 | return; |
5545 | } |
5545 | } |
5546 | 5546 | ||
5547 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5547 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5548 | refresh_rate) |
5548 | refresh_rate) |
5549 | index = DRRS_LOW_RR; |
5549 | index = DRRS_LOW_RR; |
5550 | 5550 | ||
5551 | if (index == dev_priv->drrs.refresh_rate_type) { |
5551 | if (index == dev_priv->drrs.refresh_rate_type) { |
5552 | DRM_DEBUG_KMS( |
5552 | DRM_DEBUG_KMS( |
5553 | "DRRS requested for previously set RR...ignoring\n"); |
5553 | "DRRS requested for previously set RR...ignoring\n"); |
5554 | return; |
5554 | return; |
5555 | } |
5555 | } |
5556 | 5556 | ||
5557 | if (!intel_crtc->active) { |
5557 | if (!intel_crtc->active) { |
5558 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5558 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5559 | return; |
5559 | return; |
5560 | } |
5560 | } |
5561 | 5561 | ||
5562 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5562 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
5563 | switch (index) { |
5563 | switch (index) { |
5564 | case DRRS_HIGH_RR: |
5564 | case DRRS_HIGH_RR: |
5565 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5565 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5566 | break; |
5566 | break; |
5567 | case DRRS_LOW_RR: |
5567 | case DRRS_LOW_RR: |
5568 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5568 | intel_dp_set_m_n(intel_crtc, M2_N2); |
5569 | break; |
5569 | break; |
5570 | case DRRS_MAX_RR: |
5570 | case DRRS_MAX_RR: |
5571 | default: |
5571 | default: |
5572 | DRM_ERROR("Unsupported refreshrate type\n"); |
5572 | DRM_ERROR("Unsupported refreshrate type\n"); |
5573 | } |
5573 | } |
5574 | } else if (INTEL_INFO(dev)->gen > 6) { |
5574 | } else if (INTEL_INFO(dev)->gen > 6) { |
5575 | u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5575 | u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
5576 | u32 val; |
5576 | u32 val; |
5577 | 5577 | ||
5578 | val = I915_READ(reg); |
5578 | val = I915_READ(reg); |
5579 | if (index > DRRS_HIGH_RR) { |
5579 | if (index > DRRS_HIGH_RR) { |
5580 | if (IS_VALLEYVIEW(dev)) |
5580 | if (IS_VALLEYVIEW(dev)) |
5581 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5581 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5582 | else |
5582 | else |
5583 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5583 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
5584 | } else { |
5584 | } else { |
5585 | if (IS_VALLEYVIEW(dev)) |
5585 | if (IS_VALLEYVIEW(dev)) |
5586 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5586 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5587 | else |
5587 | else |
5588 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5588 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
5589 | } |
5589 | } |
5590 | I915_WRITE(reg, val); |
5590 | I915_WRITE(reg, val); |
5591 | } |
5591 | } |
5592 | 5592 | ||
5593 | dev_priv->drrs.refresh_rate_type = index; |
5593 | dev_priv->drrs.refresh_rate_type = index; |
5594 | 5594 | ||
5595 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5595 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
5596 | } |
5596 | } |
5597 | 5597 | ||
5598 | /** |
5598 | /** |
5599 | * intel_edp_drrs_enable - init drrs struct if supported |
5599 | * intel_edp_drrs_enable - init drrs struct if supported |
5600 | * @intel_dp: DP struct |
5600 | * @intel_dp: DP struct |
5601 | * |
5601 | * |
5602 | * Initializes frontbuffer_bits and drrs.dp |
5602 | * Initializes frontbuffer_bits and drrs.dp |
5603 | */ |
5603 | */ |
5604 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5604 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5605 | { |
5605 | { |
5606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5606 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5607 | struct drm_i915_private *dev_priv = dev->dev_private; |
5607 | struct drm_i915_private *dev_priv = dev->dev_private; |
5608 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5608 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5609 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5609 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5611 | 5611 | ||
5612 | if (!intel_crtc->config->has_drrs) { |
5612 | if (!intel_crtc->config->has_drrs) { |
5613 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5613 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5614 | return; |
5614 | return; |
5615 | } |
5615 | } |
5616 | 5616 | ||
5617 | mutex_lock(&dev_priv->drrs.mutex); |
5617 | mutex_lock(&dev_priv->drrs.mutex); |
5618 | if (WARN_ON(dev_priv->drrs.dp)) { |
5618 | if (WARN_ON(dev_priv->drrs.dp)) { |
5619 | DRM_ERROR("DRRS already enabled\n"); |
5619 | DRM_ERROR("DRRS already enabled\n"); |
5620 | goto unlock; |
5620 | goto unlock; |
5621 | } |
5621 | } |
5622 | 5622 | ||
5623 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5623 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
5624 | 5624 | ||
5625 | dev_priv->drrs.dp = intel_dp; |
5625 | dev_priv->drrs.dp = intel_dp; |
5626 | 5626 | ||
5627 | unlock: |
5627 | unlock: |
5628 | mutex_unlock(&dev_priv->drrs.mutex); |
5628 | mutex_unlock(&dev_priv->drrs.mutex); |
5629 | } |
5629 | } |
5630 | 5630 | ||
5631 | /** |
5631 | /** |
5632 | * intel_edp_drrs_disable - Disable DRRS |
5632 | * intel_edp_drrs_disable - Disable DRRS |
5633 | * @intel_dp: DP struct |
5633 | * @intel_dp: DP struct |
5634 | * |
5634 | * |
5635 | */ |
5635 | */ |
5636 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5636 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5637 | { |
5637 | { |
5638 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5638 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5639 | struct drm_i915_private *dev_priv = dev->dev_private; |
5639 | struct drm_i915_private *dev_priv = dev->dev_private; |
5640 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5640 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5641 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5641 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
5642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5643 | 5643 | ||
5644 | if (!intel_crtc->config->has_drrs) |
5644 | if (!intel_crtc->config->has_drrs) |
5645 | return; |
5645 | return; |
5646 | 5646 | ||
5647 | mutex_lock(&dev_priv->drrs.mutex); |
5647 | mutex_lock(&dev_priv->drrs.mutex); |
5648 | if (!dev_priv->drrs.dp) { |
5648 | if (!dev_priv->drrs.dp) { |
5649 | mutex_unlock(&dev_priv->drrs.mutex); |
5649 | mutex_unlock(&dev_priv->drrs.mutex); |
5650 | return; |
5650 | return; |
5651 | } |
5651 | } |
5652 | 5652 | ||
5653 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5653 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5654 | intel_dp_set_drrs_state(dev_priv->dev, |
5654 | intel_dp_set_drrs_state(dev_priv->dev, |
5655 | intel_dp->attached_connector->panel. |
5655 | intel_dp->attached_connector->panel. |
5656 | fixed_mode->vrefresh); |
5656 | fixed_mode->vrefresh); |
5657 | 5657 | ||
5658 | dev_priv->drrs.dp = NULL; |
5658 | dev_priv->drrs.dp = NULL; |
5659 | mutex_unlock(&dev_priv->drrs.mutex); |
5659 | mutex_unlock(&dev_priv->drrs.mutex); |
5660 | 5660 | ||
5661 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
5661 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
5662 | } |
5662 | } |
5663 | 5663 | ||
5664 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5664 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5665 | { |
5665 | { |
5666 | struct drm_i915_private *dev_priv = |
5666 | struct drm_i915_private *dev_priv = |
5667 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5667 | container_of(work, typeof(*dev_priv), drrs.work.work); |
5668 | struct intel_dp *intel_dp; |
5668 | struct intel_dp *intel_dp; |
5669 | 5669 | ||
5670 | mutex_lock(&dev_priv->drrs.mutex); |
5670 | mutex_lock(&dev_priv->drrs.mutex); |
5671 | 5671 | ||
5672 | intel_dp = dev_priv->drrs.dp; |
5672 | intel_dp = dev_priv->drrs.dp; |
5673 | 5673 | ||
5674 | if (!intel_dp) |
5674 | if (!intel_dp) |
5675 | goto unlock; |
5675 | goto unlock; |
5676 | 5676 | ||
5677 | /* |
5677 | /* |
5678 | * The delayed work can race with an invalidate hence we need to |
5678 | * The delayed work can race with an invalidate hence we need to |
5679 | * recheck. |
5679 | * recheck. |
5680 | */ |
5680 | */ |
5681 | 5681 | ||
5682 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5682 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5683 | goto unlock; |
5683 | goto unlock; |
5684 | 5684 | ||
5685 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5685 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5686 | intel_dp_set_drrs_state(dev_priv->dev, |
5686 | intel_dp_set_drrs_state(dev_priv->dev, |
5687 | intel_dp->attached_connector->panel. |
5687 | intel_dp->attached_connector->panel. |
5688 | downclock_mode->vrefresh); |
5688 | downclock_mode->vrefresh); |
5689 | 5689 | ||
5690 | unlock: |
5690 | unlock: |
5691 | mutex_unlock(&dev_priv->drrs.mutex); |
5691 | mutex_unlock(&dev_priv->drrs.mutex); |
5692 | } |
5692 | } |
5693 | 5693 | ||
5694 | /** |
5694 | /** |
5695 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5695 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5696 | * @dev: DRM device |
5696 | * @dev: DRM device |
5697 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5697 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5698 | * |
5698 | * |
5699 | * This function gets called everytime rendering on the given planes start. |
5699 | * This function gets called everytime rendering on the given planes start. |
5700 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5700 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
5701 | * |
5701 | * |
5702 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5702 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5703 | */ |
5703 | */ |
5704 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5704 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5705 | unsigned frontbuffer_bits) |
5705 | unsigned frontbuffer_bits) |
5706 | { |
5706 | { |
5707 | struct drm_i915_private *dev_priv = dev->dev_private; |
5707 | struct drm_i915_private *dev_priv = dev->dev_private; |
5708 | struct drm_crtc *crtc; |
5708 | struct drm_crtc *crtc; |
5709 | enum pipe pipe; |
5709 | enum pipe pipe; |
5710 | 5710 | ||
5711 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5711 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5712 | return; |
5712 | return; |
5713 | 5713 | ||
5714 | cancel_delayed_work(&dev_priv->drrs.work); |
5714 | cancel_delayed_work(&dev_priv->drrs.work); |
5715 | 5715 | ||
5716 | mutex_lock(&dev_priv->drrs.mutex); |
5716 | mutex_lock(&dev_priv->drrs.mutex); |
5717 | if (!dev_priv->drrs.dp) { |
5717 | if (!dev_priv->drrs.dp) { |
5718 | mutex_unlock(&dev_priv->drrs.mutex); |
5718 | mutex_unlock(&dev_priv->drrs.mutex); |
5719 | return; |
5719 | return; |
5720 | } |
5720 | } |
5721 | 5721 | ||
5722 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5722 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5723 | pipe = to_intel_crtc(crtc)->pipe; |
5723 | pipe = to_intel_crtc(crtc)->pipe; |
5724 | 5724 | ||
5725 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5725 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5726 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5726 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
5727 | 5727 | ||
5728 | /* invalidate means busy screen hence upclock */ |
5728 | /* invalidate means busy screen hence upclock */ |
5729 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5729 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5730 | intel_dp_set_drrs_state(dev_priv->dev, |
5730 | intel_dp_set_drrs_state(dev_priv->dev, |
5731 | dev_priv->drrs.dp->attached_connector->panel. |
5731 | dev_priv->drrs.dp->attached_connector->panel. |
5732 | fixed_mode->vrefresh); |
5732 | fixed_mode->vrefresh); |
5733 | 5733 | ||
5734 | mutex_unlock(&dev_priv->drrs.mutex); |
5734 | mutex_unlock(&dev_priv->drrs.mutex); |
5735 | } |
5735 | } |
5736 | 5736 | ||
5737 | /** |
5737 | /** |
5738 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5738 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5739 | * @dev: DRM device |
5739 | * @dev: DRM device |
5740 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5740 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5741 | * |
5741 | * |
5742 | * This function gets called every time rendering on the given planes has |
5742 | * This function gets called every time rendering on the given planes has |
5743 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5743 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
5744 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5744 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
5745 | * if no other planes are dirty. |
5745 | * if no other planes are dirty. |
5746 | * |
5746 | * |
5747 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5747 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
5748 | */ |
5748 | */ |
5749 | void intel_edp_drrs_flush(struct drm_device *dev, |
5749 | void intel_edp_drrs_flush(struct drm_device *dev, |
5750 | unsigned frontbuffer_bits) |
5750 | unsigned frontbuffer_bits) |
5751 | { |
5751 | { |
5752 | struct drm_i915_private *dev_priv = dev->dev_private; |
5752 | struct drm_i915_private *dev_priv = dev->dev_private; |
5753 | struct drm_crtc *crtc; |
5753 | struct drm_crtc *crtc; |
5754 | enum pipe pipe; |
5754 | enum pipe pipe; |
5755 | 5755 | ||
5756 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5756 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
5757 | return; |
5757 | return; |
5758 | 5758 | ||
5759 | // cancel_delayed_work(&dev_priv->drrs.work); |
5759 | cancel_delayed_work(&dev_priv->drrs.work); |
5760 | 5760 | ||
5761 | mutex_lock(&dev_priv->drrs.mutex); |
5761 | mutex_lock(&dev_priv->drrs.mutex); |
5762 | if (!dev_priv->drrs.dp) { |
5762 | if (!dev_priv->drrs.dp) { |
5763 | mutex_unlock(&dev_priv->drrs.mutex); |
5763 | mutex_unlock(&dev_priv->drrs.mutex); |
5764 | return; |
5764 | return; |
5765 | } |
5765 | } |
5766 | 5766 | ||
5767 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5767 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5768 | pipe = to_intel_crtc(crtc)->pipe; |
5768 | pipe = to_intel_crtc(crtc)->pipe; |
5769 | 5769 | ||
5770 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5770 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5771 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5771 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5772 | 5772 | ||
5773 | /* flush means busy screen hence upclock */ |
5773 | /* flush means busy screen hence upclock */ |
5774 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5774 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
5775 | intel_dp_set_drrs_state(dev_priv->dev, |
5775 | intel_dp_set_drrs_state(dev_priv->dev, |
5776 | dev_priv->drrs.dp->attached_connector->panel. |
5776 | dev_priv->drrs.dp->attached_connector->panel. |
5777 | fixed_mode->vrefresh); |
5777 | fixed_mode->vrefresh); |
- | 5778 | ||
- | 5779 | /* |
|
- | 5780 | * flush also means no more activity hence schedule downclock, if all |
|
- | 5781 | * other fbs are quiescent too |
|
- | 5782 | */ |
|
- | 5783 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
|
- | 5784 | schedule_delayed_work(&dev_priv->drrs.work, |
|
5778 | 5785 | msecs_to_jiffies(1000)); |
|
5779 | mutex_unlock(&dev_priv->drrs.mutex); |
5786 | mutex_unlock(&dev_priv->drrs.mutex); |
5780 | } |
5787 | } |
5781 | 5788 | ||
5782 | /** |
5789 | /** |
5783 | * DOC: Display Refresh Rate Switching (DRRS) |
5790 | * DOC: Display Refresh Rate Switching (DRRS) |
5784 | * |
5791 | * |
5785 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5792 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
5786 | * which enables swtching between low and high refresh rates, |
5793 | * which enables swtching between low and high refresh rates, |
5787 | * dynamically, based on the usage scenario. This feature is applicable |
5794 | * dynamically, based on the usage scenario. This feature is applicable |
5788 | * for internal panels. |
5795 | * for internal panels. |
5789 | * |
5796 | * |
5790 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5797 | * Indication that the panel supports DRRS is given by the panel EDID, which |
5791 | * would list multiple refresh rates for one resolution. |
5798 | * would list multiple refresh rates for one resolution. |
5792 | * |
5799 | * |
5793 | * DRRS is of 2 types - static and seamless. |
5800 | * DRRS is of 2 types - static and seamless. |
5794 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5801 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
5795 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5802 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
5796 | * Seamless DRRS involves changing RR without any visual effect to the user |
5803 | * Seamless DRRS involves changing RR without any visual effect to the user |
5797 | * and can be used during normal system usage. This is done by programming |
5804 | * and can be used during normal system usage. This is done by programming |
5798 | * certain registers. |
5805 | * certain registers. |
5799 | * |
5806 | * |
5800 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5807 | * Support for static/seamless DRRS may be indicated in the VBT based on |
5801 | * inputs from the panel spec. |
5808 | * inputs from the panel spec. |
5802 | * |
5809 | * |
5803 | * DRRS saves power by switching to low RR based on usage scenarios. |
5810 | * DRRS saves power by switching to low RR based on usage scenarios. |
5804 | * |
5811 | * |
5805 | * eDP DRRS:- |
5812 | * eDP DRRS:- |
5806 | * The implementation is based on frontbuffer tracking implementation. |
5813 | * The implementation is based on frontbuffer tracking implementation. |
5807 | * When there is a disturbance on the screen triggered by user activity or a |
5814 | * When there is a disturbance on the screen triggered by user activity or a |
5808 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5815 | * periodic system activity, DRRS is disabled (RR is changed to high RR). |
5809 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5816 | * When there is no movement on screen, after a timeout of 1 second, a switch |
5810 | * to low RR is made. |
5817 | * to low RR is made. |
5811 | * For integration with frontbuffer tracking code, |
5818 | * For integration with frontbuffer tracking code, |
5812 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5819 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. |
5813 | * |
5820 | * |
5814 | * DRRS can be further extended to support other internal panels and also |
5821 | * DRRS can be further extended to support other internal panels and also |
5815 | * the scenario of video playback wherein RR is set based on the rate |
5822 | * the scenario of video playback wherein RR is set based on the rate |
5816 | * requested by userspace. |
5823 | * requested by userspace. |
5817 | */ |
5824 | */ |
5818 | 5825 | ||
5819 | /** |
5826 | /** |
5820 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5827 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
5821 | * @intel_connector: eDP connector |
5828 | * @intel_connector: eDP connector |
5822 | * @fixed_mode: preferred mode of panel |
5829 | * @fixed_mode: preferred mode of panel |
5823 | * |
5830 | * |
5824 | * This function is called only once at driver load to initialize basic |
5831 | * This function is called only once at driver load to initialize basic |
5825 | * DRRS stuff. |
5832 | * DRRS stuff. |
5826 | * |
5833 | * |
5827 | * Returns: |
5834 | * Returns: |
5828 | * Downclock mode if panel supports it, else return NULL. |
5835 | * Downclock mode if panel supports it, else return NULL. |
5829 | * DRRS support is determined by the presence of downclock mode (apart |
5836 | * DRRS support is determined by the presence of downclock mode (apart |
5830 | * from VBT setting). |
5837 | * from VBT setting). |
5831 | */ |
5838 | */ |
5832 | static struct drm_display_mode * |
5839 | static struct drm_display_mode * |
5833 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5840 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5834 | struct drm_display_mode *fixed_mode) |
5841 | struct drm_display_mode *fixed_mode) |
5835 | { |
5842 | { |
5836 | struct drm_connector *connector = &intel_connector->base; |
5843 | struct drm_connector *connector = &intel_connector->base; |
5837 | struct drm_device *dev = connector->dev; |
5844 | struct drm_device *dev = connector->dev; |
5838 | struct drm_i915_private *dev_priv = dev->dev_private; |
5845 | struct drm_i915_private *dev_priv = dev->dev_private; |
5839 | struct drm_display_mode *downclock_mode = NULL; |
5846 | struct drm_display_mode *downclock_mode = NULL; |
5840 | 5847 | ||
5841 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5848 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5842 | mutex_init(&dev_priv->drrs.mutex); |
5849 | mutex_init(&dev_priv->drrs.mutex); |
5843 | 5850 | ||
5844 | if (INTEL_INFO(dev)->gen <= 6) { |
5851 | if (INTEL_INFO(dev)->gen <= 6) { |
5845 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5852 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5846 | return NULL; |
5853 | return NULL; |
5847 | } |
5854 | } |
5848 | 5855 | ||
5849 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5856 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
5850 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5857 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
5851 | return NULL; |
5858 | return NULL; |
5852 | } |
5859 | } |
5853 | 5860 | ||
5854 | downclock_mode = intel_find_panel_downclock |
5861 | downclock_mode = intel_find_panel_downclock |
5855 | (dev, fixed_mode, connector); |
5862 | (dev, fixed_mode, connector); |
5856 | 5863 | ||
5857 | if (!downclock_mode) { |
5864 | if (!downclock_mode) { |
5858 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5865 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
5859 | return NULL; |
5866 | return NULL; |
5860 | } |
5867 | } |
5861 | 5868 | ||
5862 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5869 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
5863 | 5870 | ||
5864 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5871 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
5865 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5872 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
5866 | return downclock_mode; |
5873 | return downclock_mode; |
5867 | } |
5874 | } |
5868 | 5875 | ||
5869 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5876 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
5870 | struct intel_connector *intel_connector) |
5877 | struct intel_connector *intel_connector) |
5871 | { |
5878 | { |
5872 | struct drm_connector *connector = &intel_connector->base; |
5879 | struct drm_connector *connector = &intel_connector->base; |
5873 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5880 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5874 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5881 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5875 | struct drm_device *dev = intel_encoder->base.dev; |
5882 | struct drm_device *dev = intel_encoder->base.dev; |
5876 | struct drm_i915_private *dev_priv = dev->dev_private; |
5883 | struct drm_i915_private *dev_priv = dev->dev_private; |
5877 | struct drm_display_mode *fixed_mode = NULL; |
5884 | struct drm_display_mode *fixed_mode = NULL; |
5878 | struct drm_display_mode *downclock_mode = NULL; |
5885 | struct drm_display_mode *downclock_mode = NULL; |
5879 | bool has_dpcd; |
5886 | bool has_dpcd; |
5880 | struct drm_display_mode *scan; |
5887 | struct drm_display_mode *scan; |
5881 | struct edid *edid; |
5888 | struct edid *edid; |
5882 | enum pipe pipe = INVALID_PIPE; |
5889 | enum pipe pipe = INVALID_PIPE; |
5883 | 5890 | ||
5884 | if (!is_edp(intel_dp)) |
5891 | if (!is_edp(intel_dp)) |
5885 | return true; |
5892 | return true; |
5886 | 5893 | ||
5887 | pps_lock(intel_dp); |
5894 | pps_lock(intel_dp); |
5888 | intel_edp_panel_vdd_sanitize(intel_dp); |
5895 | intel_edp_panel_vdd_sanitize(intel_dp); |
5889 | pps_unlock(intel_dp); |
5896 | pps_unlock(intel_dp); |
5890 | 5897 | ||
5891 | /* Cache DPCD and EDID for edp. */ |
5898 | /* Cache DPCD and EDID for edp. */ |
5892 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5899 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
5893 | 5900 | ||
5894 | if (has_dpcd) { |
5901 | if (has_dpcd) { |
5895 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5902 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
5896 | dev_priv->no_aux_handshake = |
5903 | dev_priv->no_aux_handshake = |
5897 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5904 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
5898 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5905 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
5899 | } else { |
5906 | } else { |
5900 | /* if this fails, presume the device is a ghost */ |
5907 | /* if this fails, presume the device is a ghost */ |
5901 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5908 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
5902 | return false; |
5909 | return false; |
5903 | } |
5910 | } |
5904 | 5911 | ||
5905 | /* We now know it's not a ghost, init power sequence regs. */ |
5912 | /* We now know it's not a ghost, init power sequence regs. */ |
5906 | pps_lock(intel_dp); |
5913 | pps_lock(intel_dp); |
5907 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5914 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
5908 | pps_unlock(intel_dp); |
5915 | pps_unlock(intel_dp); |
5909 | 5916 | ||
5910 | mutex_lock(&dev->mode_config.mutex); |
5917 | mutex_lock(&dev->mode_config.mutex); |
5911 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5918 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
5912 | if (edid) { |
5919 | if (edid) { |
5913 | if (drm_add_edid_modes(connector, edid)) { |
5920 | if (drm_add_edid_modes(connector, edid)) { |
5914 | drm_mode_connector_update_edid_property(connector, |
5921 | drm_mode_connector_update_edid_property(connector, |
5915 | edid); |
5922 | edid); |
5916 | drm_edid_to_eld(connector, edid); |
5923 | drm_edid_to_eld(connector, edid); |
5917 | } else { |
5924 | } else { |
5918 | kfree(edid); |
5925 | kfree(edid); |
5919 | edid = ERR_PTR(-EINVAL); |
5926 | edid = ERR_PTR(-EINVAL); |
5920 | } |
5927 | } |
5921 | } else { |
5928 | } else { |
5922 | edid = ERR_PTR(-ENOENT); |
5929 | edid = ERR_PTR(-ENOENT); |
5923 | } |
5930 | } |
5924 | intel_connector->edid = edid; |
5931 | intel_connector->edid = edid; |
5925 | 5932 | ||
5926 | /* prefer fixed mode from EDID if available */ |
5933 | /* prefer fixed mode from EDID if available */ |
5927 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5934 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5928 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5935 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
5929 | fixed_mode = drm_mode_duplicate(dev, scan); |
5936 | fixed_mode = drm_mode_duplicate(dev, scan); |
5930 | downclock_mode = intel_dp_drrs_init( |
5937 | downclock_mode = intel_dp_drrs_init( |
5931 | intel_connector, fixed_mode); |
5938 | intel_connector, fixed_mode); |
5932 | break; |
5939 | break; |
5933 | } |
5940 | } |
5934 | } |
5941 | } |
5935 | 5942 | ||
5936 | /* fallback to VBT if available for eDP */ |
5943 | /* fallback to VBT if available for eDP */ |
5937 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5944 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
5938 | fixed_mode = drm_mode_duplicate(dev, |
5945 | fixed_mode = drm_mode_duplicate(dev, |
5939 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5946 | dev_priv->vbt.lfp_lvds_vbt_mode); |
5940 | if (fixed_mode) |
5947 | if (fixed_mode) |
5941 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5948 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
5942 | } |
5949 | } |
5943 | mutex_unlock(&dev->mode_config.mutex); |
5950 | mutex_unlock(&dev->mode_config.mutex); |
5944 | 5951 | ||
5945 | if (IS_VALLEYVIEW(dev)) { |
5952 | if (IS_VALLEYVIEW(dev)) { |
5946 | 5953 | ||
5947 | /* |
5954 | /* |
5948 | * Figure out the current pipe for the initial backlight setup. |
5955 | * Figure out the current pipe for the initial backlight setup. |
5949 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5956 | * If the current pipe isn't valid, try the PPS pipe, and if that |
5950 | * fails just assume pipe A. |
5957 | * fails just assume pipe A. |
5951 | */ |
5958 | */ |
5952 | if (IS_CHERRYVIEW(dev)) |
5959 | if (IS_CHERRYVIEW(dev)) |
5953 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5960 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5954 | else |
5961 | else |
5955 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5962 | pipe = PORT_TO_PIPE(intel_dp->DP); |
5956 | 5963 | ||
5957 | if (pipe != PIPE_A && pipe != PIPE_B) |
5964 | if (pipe != PIPE_A && pipe != PIPE_B) |
5958 | pipe = intel_dp->pps_pipe; |
5965 | pipe = intel_dp->pps_pipe; |
5959 | 5966 | ||
5960 | if (pipe != PIPE_A && pipe != PIPE_B) |
5967 | if (pipe != PIPE_A && pipe != PIPE_B) |
5961 | pipe = PIPE_A; |
5968 | pipe = PIPE_A; |
5962 | 5969 | ||
5963 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5970 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
5964 | pipe_name(pipe)); |
5971 | pipe_name(pipe)); |
5965 | } |
5972 | } |
5966 | 5973 | ||
5967 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5974 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5968 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5975 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
5969 | intel_panel_setup_backlight(connector, pipe); |
5976 | intel_panel_setup_backlight(connector, pipe); |
5970 | 5977 | ||
5971 | return true; |
5978 | return true; |
5972 | } |
5979 | } |
5973 | 5980 | ||
5974 | bool |
5981 | bool |
5975 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5982 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5976 | struct intel_connector *intel_connector) |
5983 | struct intel_connector *intel_connector) |
5977 | { |
5984 | { |
5978 | struct drm_connector *connector = &intel_connector->base; |
5985 | struct drm_connector *connector = &intel_connector->base; |
5979 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5986 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
5980 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5987 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5981 | struct drm_device *dev = intel_encoder->base.dev; |
5988 | struct drm_device *dev = intel_encoder->base.dev; |
5982 | struct drm_i915_private *dev_priv = dev->dev_private; |
5989 | struct drm_i915_private *dev_priv = dev->dev_private; |
5983 | enum port port = intel_dig_port->port; |
5990 | enum port port = intel_dig_port->port; |
5984 | int type; |
5991 | int type; |
5985 | 5992 | ||
5986 | intel_dp->pps_pipe = INVALID_PIPE; |
5993 | intel_dp->pps_pipe = INVALID_PIPE; |
5987 | 5994 | ||
5988 | /* intel_dp vfuncs */ |
5995 | /* intel_dp vfuncs */ |
5989 | if (INTEL_INFO(dev)->gen >= 9) |
5996 | if (INTEL_INFO(dev)->gen >= 9) |
5990 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5997 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
5991 | else if (IS_VALLEYVIEW(dev)) |
5998 | else if (IS_VALLEYVIEW(dev)) |
5992 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5999 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5993 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
6000 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5994 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6001 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
5995 | else if (HAS_PCH_SPLIT(dev)) |
6002 | else if (HAS_PCH_SPLIT(dev)) |
5996 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
6003 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5997 | else |
6004 | else |
5998 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
6005 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
5999 | 6006 | ||
6000 | if (INTEL_INFO(dev)->gen >= 9) |
6007 | if (INTEL_INFO(dev)->gen >= 9) |
6001 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
6008 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
6002 | else |
6009 | else |
6003 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
6010 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
6004 | 6011 | ||
6005 | /* Preserve the current hw state. */ |
6012 | /* Preserve the current hw state. */ |
6006 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
6013 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
6007 | intel_dp->attached_connector = intel_connector; |
6014 | intel_dp->attached_connector = intel_connector; |
6008 | 6015 | ||
6009 | if (intel_dp_is_edp(dev, port)) |
6016 | if (intel_dp_is_edp(dev, port)) |
6010 | type = DRM_MODE_CONNECTOR_eDP; |
6017 | type = DRM_MODE_CONNECTOR_eDP; |
6011 | else |
6018 | else |
6012 | type = DRM_MODE_CONNECTOR_DisplayPort; |
6019 | type = DRM_MODE_CONNECTOR_DisplayPort; |
6013 | 6020 | ||
6014 | /* |
6021 | /* |
6015 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
6022 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
6016 | * for DP the encoder type can be set by the caller to |
6023 | * for DP the encoder type can be set by the caller to |
6017 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
6024 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
6018 | */ |
6025 | */ |
6019 | if (type == DRM_MODE_CONNECTOR_eDP) |
6026 | if (type == DRM_MODE_CONNECTOR_eDP) |
6020 | intel_encoder->type = INTEL_OUTPUT_EDP; |
6027 | intel_encoder->type = INTEL_OUTPUT_EDP; |
6021 | 6028 | ||
6022 | /* eDP only on port B and/or C on vlv/chv */ |
6029 | /* eDP only on port B and/or C on vlv/chv */ |
6023 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && |
6030 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && |
6024 | port != PORT_B && port != PORT_C)) |
6031 | port != PORT_B && port != PORT_C)) |
6025 | return false; |
6032 | return false; |
6026 | 6033 | ||
6027 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6034 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6028 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
6035 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
6029 | port_name(port)); |
6036 | port_name(port)); |
6030 | 6037 | ||
6031 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
6038 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
6032 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6039 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6033 | 6040 | ||
6034 | connector->interlace_allowed = true; |
6041 | connector->interlace_allowed = true; |
6035 | connector->doublescan_allowed = 0; |
6042 | connector->doublescan_allowed = 0; |
6036 | 6043 | ||
6037 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
6044 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
6038 | edp_panel_vdd_work); |
6045 | edp_panel_vdd_work); |
6039 | 6046 | ||
6040 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
6047 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
6041 | drm_connector_register(connector); |
6048 | drm_connector_register(connector); |
6042 | 6049 | ||
6043 | if (HAS_DDI(dev)) |
6050 | if (HAS_DDI(dev)) |
6044 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6051 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6045 | else |
6052 | else |
6046 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
6053 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
6047 | intel_connector->unregister = intel_dp_connector_unregister; |
6054 | intel_connector->unregister = intel_dp_connector_unregister; |
6048 | 6055 | ||
6049 | /* Set up the hotplug pin. */ |
6056 | /* Set up the hotplug pin. */ |
6050 | switch (port) { |
6057 | switch (port) { |
6051 | case PORT_A: |
6058 | case PORT_A: |
6052 | intel_encoder->hpd_pin = HPD_PORT_A; |
6059 | intel_encoder->hpd_pin = HPD_PORT_A; |
6053 | break; |
6060 | break; |
6054 | case PORT_B: |
6061 | case PORT_B: |
6055 | intel_encoder->hpd_pin = HPD_PORT_B; |
6062 | intel_encoder->hpd_pin = HPD_PORT_B; |
6056 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
6063 | if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) |
6057 | intel_encoder->hpd_pin = HPD_PORT_A; |
6064 | intel_encoder->hpd_pin = HPD_PORT_A; |
6058 | break; |
6065 | break; |
6059 | case PORT_C: |
6066 | case PORT_C: |
6060 | intel_encoder->hpd_pin = HPD_PORT_C; |
6067 | intel_encoder->hpd_pin = HPD_PORT_C; |
6061 | break; |
6068 | break; |
6062 | case PORT_D: |
6069 | case PORT_D: |
6063 | intel_encoder->hpd_pin = HPD_PORT_D; |
6070 | intel_encoder->hpd_pin = HPD_PORT_D; |
6064 | break; |
6071 | break; |
6065 | case PORT_E: |
6072 | case PORT_E: |
6066 | intel_encoder->hpd_pin = HPD_PORT_E; |
6073 | intel_encoder->hpd_pin = HPD_PORT_E; |
6067 | break; |
6074 | break; |
6068 | default: |
6075 | default: |
6069 | BUG(); |
6076 | BUG(); |
6070 | } |
6077 | } |
6071 | 6078 | ||
6072 | if (is_edp(intel_dp)) { |
6079 | if (is_edp(intel_dp)) { |
6073 | pps_lock(intel_dp); |
6080 | pps_lock(intel_dp); |
6074 | intel_dp_init_panel_power_timestamps(intel_dp); |
6081 | intel_dp_init_panel_power_timestamps(intel_dp); |
6075 | if (IS_VALLEYVIEW(dev)) |
6082 | if (IS_VALLEYVIEW(dev)) |
6076 | vlv_initial_power_sequencer_setup(intel_dp); |
6083 | vlv_initial_power_sequencer_setup(intel_dp); |
6077 | else |
6084 | else |
6078 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
6085 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
6079 | pps_unlock(intel_dp); |
6086 | pps_unlock(intel_dp); |
6080 | } |
6087 | } |
6081 | 6088 | ||
6082 | intel_dp_aux_init(intel_dp, intel_connector); |
6089 | intel_dp_aux_init(intel_dp, intel_connector); |
6083 | 6090 | ||
6084 | /* init MST on ports that can support it */ |
6091 | /* init MST on ports that can support it */ |
6085 | if (HAS_DP_MST(dev) && |
6092 | if (HAS_DP_MST(dev) && |
6086 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6093 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6087 | intel_dp_mst_encoder_init(intel_dig_port, |
6094 | intel_dp_mst_encoder_init(intel_dig_port, |
6088 | intel_connector->base.base.id); |
6095 | intel_connector->base.base.id); |
6089 | 6096 | ||
6090 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
6097 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
6091 | drm_dp_aux_unregister(&intel_dp->aux); |
6098 | drm_dp_aux_unregister(&intel_dp->aux); |
6092 | if (is_edp(intel_dp)) { |
6099 | if (is_edp(intel_dp)) { |
6093 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
6100 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
6094 | /* |
6101 | /* |
6095 | * vdd might still be enabled do to the delayed vdd off. |
6102 | * vdd might still be enabled do to the delayed vdd off. |
6096 | * Make sure vdd is actually turned off here. |
6103 | * Make sure vdd is actually turned off here. |
6097 | */ |
6104 | */ |
6098 | pps_lock(intel_dp); |
6105 | pps_lock(intel_dp); |
6099 | edp_panel_vdd_off_sync(intel_dp); |
6106 | edp_panel_vdd_off_sync(intel_dp); |
6100 | pps_unlock(intel_dp); |
6107 | pps_unlock(intel_dp); |
6101 | } |
6108 | } |
6102 | drm_connector_unregister(connector); |
6109 | drm_connector_unregister(connector); |
6103 | drm_connector_cleanup(connector); |
6110 | drm_connector_cleanup(connector); |
6104 | return false; |
6111 | return false; |
6105 | } |
6112 | } |
6106 | 6113 | ||
6107 | intel_dp_add_properties(intel_dp, connector); |
6114 | intel_dp_add_properties(intel_dp, connector); |
6108 | 6115 | ||
6109 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6116 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6110 | * 0xd. Failure to do so will result in spurious interrupts being |
6117 | * 0xd. Failure to do so will result in spurious interrupts being |
6111 | * generated on the port when a cable is not attached. |
6118 | * generated on the port when a cable is not attached. |
6112 | */ |
6119 | */ |
6113 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
6120 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
6114 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6121 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6115 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
6122 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
6116 | } |
6123 | } |
6117 | 6124 | ||
6118 | i915_debugfs_connector_add(connector); |
6125 | i915_debugfs_connector_add(connector); |
6119 | 6126 | ||
6120 | return true; |
6127 | return true; |
6121 | } |
6128 | } |
6122 | 6129 | ||
6123 | void |
6130 | void |
6124 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
6131 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
6125 | { |
6132 | { |
6126 | struct drm_i915_private *dev_priv = dev->dev_private; |
6133 | struct drm_i915_private *dev_priv = dev->dev_private; |
6127 | struct intel_digital_port *intel_dig_port; |
6134 | struct intel_digital_port *intel_dig_port; |
6128 | struct intel_encoder *intel_encoder; |
6135 | struct intel_encoder *intel_encoder; |
6129 | struct drm_encoder *encoder; |
6136 | struct drm_encoder *encoder; |
6130 | struct intel_connector *intel_connector; |
6137 | struct intel_connector *intel_connector; |
6131 | 6138 | ||
6132 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6139 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
6133 | if (!intel_dig_port) |
6140 | if (!intel_dig_port) |
6134 | return; |
6141 | return; |
6135 | 6142 | ||
6136 | intel_connector = intel_connector_alloc(); |
6143 | intel_connector = intel_connector_alloc(); |
6137 | if (!intel_connector) |
6144 | if (!intel_connector) |
6138 | goto err_connector_alloc; |
6145 | goto err_connector_alloc; |
6139 | 6146 | ||
6140 | intel_encoder = &intel_dig_port->base; |
6147 | intel_encoder = &intel_dig_port->base; |
6141 | encoder = &intel_encoder->base; |
6148 | encoder = &intel_encoder->base; |
6142 | 6149 | ||
6143 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
6150 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
6144 | DRM_MODE_ENCODER_TMDS); |
6151 | DRM_MODE_ENCODER_TMDS); |
6145 | 6152 | ||
6146 | intel_encoder->compute_config = intel_dp_compute_config; |
6153 | intel_encoder->compute_config = intel_dp_compute_config; |
6147 | intel_encoder->disable = intel_disable_dp; |
6154 | intel_encoder->disable = intel_disable_dp; |
6148 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6155 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
6149 | intel_encoder->get_config = intel_dp_get_config; |
6156 | intel_encoder->get_config = intel_dp_get_config; |
6150 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6157 | intel_encoder->suspend = intel_dp_encoder_suspend; |
6151 | if (IS_CHERRYVIEW(dev)) { |
6158 | if (IS_CHERRYVIEW(dev)) { |
6152 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6159 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
6153 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6160 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6154 | intel_encoder->enable = vlv_enable_dp; |
6161 | intel_encoder->enable = vlv_enable_dp; |
6155 | intel_encoder->post_disable = chv_post_disable_dp; |
6162 | intel_encoder->post_disable = chv_post_disable_dp; |
6156 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6163 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
6157 | } else if (IS_VALLEYVIEW(dev)) { |
6164 | } else if (IS_VALLEYVIEW(dev)) { |
6158 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6165 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
6159 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6166 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6160 | intel_encoder->enable = vlv_enable_dp; |
6167 | intel_encoder->enable = vlv_enable_dp; |
6161 | intel_encoder->post_disable = vlv_post_disable_dp; |
6168 | intel_encoder->post_disable = vlv_post_disable_dp; |
6162 | } else { |
6169 | } else { |
6163 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6170 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6164 | intel_encoder->enable = g4x_enable_dp; |
6171 | intel_encoder->enable = g4x_enable_dp; |
6165 | if (INTEL_INFO(dev)->gen >= 5) |
6172 | if (INTEL_INFO(dev)->gen >= 5) |
6166 | intel_encoder->post_disable = ilk_post_disable_dp; |
6173 | intel_encoder->post_disable = ilk_post_disable_dp; |
6167 | } |
6174 | } |
6168 | 6175 | ||
6169 | intel_dig_port->port = port; |
6176 | intel_dig_port->port = port; |
6170 | intel_dig_port->dp.output_reg = output_reg; |
6177 | intel_dig_port->dp.output_reg = output_reg; |
6171 | 6178 | ||
6172 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6179 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
6173 | if (IS_CHERRYVIEW(dev)) { |
6180 | if (IS_CHERRYVIEW(dev)) { |
6174 | if (port == PORT_D) |
6181 | if (port == PORT_D) |
6175 | intel_encoder->crtc_mask = 1 << 2; |
6182 | intel_encoder->crtc_mask = 1 << 2; |
6176 | else |
6183 | else |
6177 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6184 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
6178 | } else { |
6185 | } else { |
6179 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6186 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
6180 | } |
6187 | } |
6181 | intel_encoder->cloneable = 0; |
6188 | intel_encoder->cloneable = 0; |
6182 | 6189 | ||
6183 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6190 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
6184 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6191 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
6185 | 6192 | ||
6186 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6193 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6187 | goto err_init_connector; |
6194 | goto err_init_connector; |
6188 | 6195 | ||
6189 | return; |
6196 | return; |
6190 | 6197 | ||
6191 | err_init_connector: |
6198 | err_init_connector: |
6192 | drm_encoder_cleanup(encoder); |
6199 | drm_encoder_cleanup(encoder); |
6193 | kfree(intel_connector); |
6200 | kfree(intel_connector); |
6194 | err_connector_alloc: |
6201 | err_connector_alloc: |
6195 | kfree(intel_dig_port); |
6202 | kfree(intel_dig_port); |
6196 | 6203 | ||
6197 | return; |
6204 | return; |
6198 | } |
6205 | } |
6199 | 6206 | ||
6200 | void intel_dp_mst_suspend(struct drm_device *dev) |
6207 | void intel_dp_mst_suspend(struct drm_device *dev) |
6201 | { |
6208 | { |
6202 | struct drm_i915_private *dev_priv = dev->dev_private; |
6209 | struct drm_i915_private *dev_priv = dev->dev_private; |
6203 | int i; |
6210 | int i; |
6204 | 6211 | ||
6205 | /* disable MST */ |
6212 | /* disable MST */ |
6206 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6213 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6207 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6214 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6208 | if (!intel_dig_port) |
6215 | if (!intel_dig_port) |
6209 | continue; |
6216 | continue; |
6210 | 6217 | ||
6211 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6218 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6212 | if (!intel_dig_port->dp.can_mst) |
6219 | if (!intel_dig_port->dp.can_mst) |
6213 | continue; |
6220 | continue; |
6214 | if (intel_dig_port->dp.is_mst) |
6221 | if (intel_dig_port->dp.is_mst) |
6215 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6222 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
6216 | } |
6223 | } |
6217 | } |
6224 | } |
6218 | } |
6225 | } |
6219 | 6226 | ||
6220 | void intel_dp_mst_resume(struct drm_device *dev) |
6227 | void intel_dp_mst_resume(struct drm_device *dev) |
6221 | { |
6228 | { |
6222 | struct drm_i915_private *dev_priv = dev->dev_private; |
6229 | struct drm_i915_private *dev_priv = dev->dev_private; |
6223 | int i; |
6230 | int i; |
6224 | 6231 | ||
6225 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6232 | for (i = 0; i < I915_MAX_PORTS; i++) { |
6226 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6233 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
6227 | if (!intel_dig_port) |
6234 | if (!intel_dig_port) |
6228 | continue; |
6235 | continue; |
6229 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6236 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
6230 | int ret; |
6237 | int ret; |
6231 | 6238 | ||
6232 | if (!intel_dig_port->dp.can_mst) |
6239 | if (!intel_dig_port->dp.can_mst) |
6233 | continue; |
6240 | continue; |
6234 | 6241 | ||
6235 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6242 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6236 | if (ret != 0) { |
6243 | if (ret != 0) { |
6237 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6244 | intel_dp_check_mst_status(&intel_dig_port->dp); |
6238 | } |
6245 | } |
6239 | } |
6246 | } |
6240 | } |
6247 | } |
6241 | }>>><>><>><>><>><>><>>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6248 | }>>><>><>><>><>><>><>>=>>=>><>><>><>><>><>><>><>>>>>=>=>>>>>>>>>>>>>>>>>><>><>><>>><>>>><>> |
6242 | ><21); |
6249 | ><21); |
6243 | >21); |
6250 | >21); |
6244 | ><21); |
6251 | ><21); |
6245 | >>>>><>=>=><=>=>=>>=>=>>>>>>>=>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |
6252 | >>>>><>=>=><=>=>=>>=>=>>>>>>>=>>>><>>>>>><>><>><>><>=>><>><>><>>><>>>><>><>><>><>><> |