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1 | /* |
1 | /* |
2 | * Copyright © 2008 Intel Corporation |
2 | * Copyright © 2008 Intel Corporation |
3 | * |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
13 | * Software. |
14 | * |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
21 | * IN THE SOFTWARE. |
22 | * |
22 | * |
23 | * Authors: |
23 | * Authors: |
24 | * Eric Anholt |
24 | * Eric Anholt |
25 | * |
25 | * |
26 | */ |
26 | */ |
27 | 27 | ||
28 | #include |
28 | #include |
29 | #include |
29 | #include |
30 | #include |
30 | #include |
31 | #include "i915_drv.h" |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" |
33 | #include "intel_drv.h" |
34 | #include |
34 | #include |
35 | #include |
35 | #include |
36 | //#include |
36 | //#include |
37 | #include |
37 | #include |
38 | #include |
38 | #include |
39 | 39 | ||
40 | extern int x86_clflush_size; |
40 | extern int x86_clflush_size; |
41 | 41 | ||
42 | #define PROT_READ 0x1 /* page can be read */ |
42 | #define PROT_READ 0x1 /* page can be read */ |
43 | #define PROT_WRITE 0x2 /* page can be written */ |
43 | #define PROT_WRITE 0x2 /* page can be written */ |
44 | #define MAP_SHARED 0x01 /* Share changes */ |
44 | #define MAP_SHARED 0x01 /* Share changes */ |
45 | 45 | ||
46 | 46 | ||
47 | u64 nsecs_to_jiffies64(u64 n) |
47 | u64 nsecs_to_jiffies64(u64 n) |
48 | { |
48 | { |
49 | #if (NSEC_PER_SEC % HZ) == 0 |
49 | #if (NSEC_PER_SEC % HZ) == 0 |
50 | /* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */ |
50 | /* Common case, HZ = 100, 128, 200, 250, 256, 500, 512, 1000 etc. */ |
51 | return div_u64(n, NSEC_PER_SEC / HZ); |
51 | return div_u64(n, NSEC_PER_SEC / HZ); |
52 | #elif (HZ % 512) == 0 |
52 | #elif (HZ % 512) == 0 |
53 | /* overflow after 292 years if HZ = 1024 */ |
53 | /* overflow after 292 years if HZ = 1024 */ |
54 | return div_u64(n * HZ / 512, NSEC_PER_SEC / 512); |
54 | return div_u64(n * HZ / 512, NSEC_PER_SEC / 512); |
55 | #else |
55 | #else |
56 | /* |
56 | /* |
57 | * Generic case - optimized for cases where HZ is a multiple of 3. |
57 | * Generic case - optimized for cases where HZ is a multiple of 3. |
58 | * overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc. |
58 | * overflow after 64.99 years, exact for HZ = 60, 72, 90, 120 etc. |
59 | */ |
59 | */ |
60 | return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ); |
60 | return div_u64(n * 9, (9ull * NSEC_PER_SEC + HZ / 2) / HZ); |
61 | #endif |
61 | #endif |
62 | } |
62 | } |
63 | 63 | ||
64 | unsigned long nsecs_to_jiffies(u64 n) |
64 | unsigned long nsecs_to_jiffies(u64 n) |
65 | { |
65 | { |
66 | return (unsigned long)nsecs_to_jiffies64(n); |
66 | return (unsigned long)nsecs_to_jiffies64(n); |
67 | } |
67 | } |
68 | 68 | ||
69 | 69 | ||
70 | struct drm_i915_gem_object *get_fb_obj(); |
70 | struct drm_i915_gem_object *get_fb_obj(); |
71 | 71 | ||
72 | unsigned long vm_mmap(struct file *file, unsigned long addr, |
72 | unsigned long vm_mmap(struct file *file, unsigned long addr, |
73 | unsigned long len, unsigned long prot, |
73 | unsigned long len, unsigned long prot, |
74 | unsigned long flag, unsigned long offset); |
74 | unsigned long flag, unsigned long offset); |
75 | 75 | ||
76 | 76 | ||
77 | #define MAX_ERRNO 4095 |
77 | #define MAX_ERRNO 4095 |
78 | 78 | ||
79 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
79 | #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
80 | 80 | ||
81 | 81 | ||
82 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
82 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
83 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
83 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
84 | bool force); |
84 | bool force); |
85 | static __must_check int |
85 | static __must_check int |
86 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
86 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
87 | bool readonly); |
87 | bool readonly); |
88 | static void |
88 | static void |
89 | i915_gem_object_retire(struct drm_i915_gem_object *obj); |
89 | i915_gem_object_retire(struct drm_i915_gem_object *obj); |
90 | 90 | ||
91 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
91 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
92 | struct drm_i915_gem_object *obj); |
92 | struct drm_i915_gem_object *obj); |
93 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
93 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
94 | struct drm_i915_fence_reg *fence, |
94 | struct drm_i915_fence_reg *fence, |
95 | bool enable); |
95 | bool enable); |
96 | 96 | ||
97 | 97 | ||
98 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
98 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
99 | 99 | ||
100 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
100 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
101 | enum i915_cache_level level) |
101 | enum i915_cache_level level) |
102 | { |
102 | { |
103 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
103 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
104 | } |
104 | } |
105 | 105 | ||
106 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
106 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
107 | { |
107 | { |
108 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
108 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
109 | return true; |
109 | return true; |
110 | 110 | ||
111 | return obj->pin_display; |
111 | return obj->pin_display; |
112 | } |
112 | } |
113 | 113 | ||
114 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
114 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
115 | { |
115 | { |
116 | if (obj->tiling_mode) |
116 | if (obj->tiling_mode) |
117 | i915_gem_release_mmap(obj); |
117 | i915_gem_release_mmap(obj); |
118 | 118 | ||
119 | /* As we do not have an associated fence register, we will force |
119 | /* As we do not have an associated fence register, we will force |
120 | * a tiling change if we ever need to acquire one. |
120 | * a tiling change if we ever need to acquire one. |
121 | */ |
121 | */ |
122 | obj->fence_dirty = false; |
122 | obj->fence_dirty = false; |
123 | obj->fence_reg = I915_FENCE_REG_NONE; |
123 | obj->fence_reg = I915_FENCE_REG_NONE; |
124 | } |
124 | } |
125 | 125 | ||
126 | /* some bookkeeping */ |
126 | /* some bookkeeping */ |
127 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
127 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
128 | size_t size) |
128 | size_t size) |
129 | { |
129 | { |
130 | spin_lock(&dev_priv->mm.object_stat_lock); |
130 | spin_lock(&dev_priv->mm.object_stat_lock); |
131 | dev_priv->mm.object_count++; |
131 | dev_priv->mm.object_count++; |
132 | dev_priv->mm.object_memory += size; |
132 | dev_priv->mm.object_memory += size; |
133 | spin_unlock(&dev_priv->mm.object_stat_lock); |
133 | spin_unlock(&dev_priv->mm.object_stat_lock); |
134 | } |
134 | } |
135 | 135 | ||
136 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
136 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
137 | size_t size) |
137 | size_t size) |
138 | { |
138 | { |
139 | spin_lock(&dev_priv->mm.object_stat_lock); |
139 | spin_lock(&dev_priv->mm.object_stat_lock); |
140 | dev_priv->mm.object_count--; |
140 | dev_priv->mm.object_count--; |
141 | dev_priv->mm.object_memory -= size; |
141 | dev_priv->mm.object_memory -= size; |
142 | spin_unlock(&dev_priv->mm.object_stat_lock); |
142 | spin_unlock(&dev_priv->mm.object_stat_lock); |
143 | } |
143 | } |
144 | 144 | ||
145 | static int |
145 | static int |
146 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
146 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
147 | { |
147 | { |
148 | int ret; |
148 | int ret; |
149 | 149 | ||
150 | #define EXIT_COND (!i915_reset_in_progress(error)) |
150 | #define EXIT_COND (!i915_reset_in_progress(error)) |
151 | if (EXIT_COND) |
151 | if (EXIT_COND) |
152 | return 0; |
152 | return 0; |
153 | #if 0 |
153 | #if 0 |
154 | /* |
154 | /* |
155 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
155 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
156 | * userspace. If it takes that long something really bad is going on and |
156 | * userspace. If it takes that long something really bad is going on and |
157 | * we should simply try to bail out and fail as gracefully as possible. |
157 | * we should simply try to bail out and fail as gracefully as possible. |
158 | */ |
158 | */ |
159 | ret = wait_event_interruptible_timeout(error->reset_queue, |
159 | ret = wait_event_interruptible_timeout(error->reset_queue, |
160 | EXIT_COND, |
160 | EXIT_COND, |
161 | 10*HZ); |
161 | 10*HZ); |
162 | if (ret == 0) { |
162 | if (ret == 0) { |
163 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
163 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
164 | return -EIO; |
164 | return -EIO; |
165 | } else if (ret < 0) { |
165 | } else if (ret < 0) { |
166 | return ret; |
166 | return ret; |
167 | } |
167 | } |
168 | 168 | ||
169 | #endif |
169 | #endif |
170 | #undef EXIT_COND |
170 | #undef EXIT_COND |
171 | 171 | ||
172 | return 0; |
172 | return 0; |
173 | } |
173 | } |
174 | 174 | ||
175 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
175 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
176 | { |
176 | { |
177 | struct drm_i915_private *dev_priv = dev->dev_private; |
177 | struct drm_i915_private *dev_priv = dev->dev_private; |
178 | int ret; |
178 | int ret; |
179 | 179 | ||
180 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
180 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
181 | if (ret) |
181 | if (ret) |
182 | return ret; |
182 | return ret; |
183 | 183 | ||
184 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
184 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
185 | if (ret) |
185 | if (ret) |
186 | return ret; |
186 | return ret; |
187 | 187 | ||
188 | WARN_ON(i915_verify_lists(dev)); |
188 | WARN_ON(i915_verify_lists(dev)); |
189 | return 0; |
189 | return 0; |
190 | } |
190 | } |
191 | 191 | ||
192 | static inline bool |
192 | static inline bool |
193 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
193 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
194 | { |
194 | { |
195 | return i915_gem_obj_bound_any(obj) && !obj->active; |
195 | return i915_gem_obj_bound_any(obj) && !obj->active; |
196 | } |
196 | } |
197 | 197 | ||
198 | int |
198 | int |
199 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
199 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
200 | struct drm_file *file) |
200 | struct drm_file *file) |
201 | { |
201 | { |
202 | struct drm_i915_private *dev_priv = dev->dev_private; |
202 | struct drm_i915_private *dev_priv = dev->dev_private; |
203 | struct drm_i915_gem_get_aperture *args = data; |
203 | struct drm_i915_gem_get_aperture *args = data; |
204 | struct drm_i915_gem_object *obj; |
204 | struct drm_i915_gem_object *obj; |
205 | size_t pinned; |
205 | size_t pinned; |
206 | 206 | ||
207 | pinned = 0; |
207 | pinned = 0; |
208 | mutex_lock(&dev->struct_mutex); |
208 | mutex_lock(&dev->struct_mutex); |
209 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
209 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
210 | if (i915_gem_obj_is_pinned(obj)) |
210 | if (i915_gem_obj_is_pinned(obj)) |
211 | pinned += i915_gem_obj_ggtt_size(obj); |
211 | pinned += i915_gem_obj_ggtt_size(obj); |
212 | mutex_unlock(&dev->struct_mutex); |
212 | mutex_unlock(&dev->struct_mutex); |
213 | 213 | ||
214 | args->aper_size = dev_priv->gtt.base.total; |
214 | args->aper_size = dev_priv->gtt.base.total; |
215 | args->aper_available_size = args->aper_size - pinned; |
215 | args->aper_available_size = args->aper_size - pinned; |
216 | 216 | ||
217 | return 0; |
217 | return 0; |
218 | } |
218 | } |
219 | 219 | ||
220 | void *i915_gem_object_alloc(struct drm_device *dev) |
220 | void *i915_gem_object_alloc(struct drm_device *dev) |
221 | { |
221 | { |
222 | struct drm_i915_private *dev_priv = dev->dev_private; |
222 | struct drm_i915_private *dev_priv = dev->dev_private; |
223 | return kmalloc(sizeof(struct drm_i915_gem_object), 0); |
223 | return kzalloc(sizeof(struct drm_i915_gem_object), 0); |
224 | } |
224 | } |
225 | 225 | ||
226 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
226 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
227 | { |
227 | { |
228 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
228 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
229 | kfree(obj); |
229 | kfree(obj); |
230 | } |
230 | } |
231 | 231 | ||
232 | static int |
232 | static int |
233 | i915_gem_create(struct drm_file *file, |
233 | i915_gem_create(struct drm_file *file, |
234 | struct drm_device *dev, |
234 | struct drm_device *dev, |
235 | uint64_t size, |
235 | uint64_t size, |
236 | uint32_t *handle_p) |
236 | uint32_t *handle_p) |
237 | { |
237 | { |
238 | struct drm_i915_gem_object *obj; |
238 | struct drm_i915_gem_object *obj; |
239 | int ret; |
239 | int ret; |
240 | u32 handle; |
240 | u32 handle; |
241 | 241 | ||
242 | size = roundup(size, PAGE_SIZE); |
242 | size = roundup(size, PAGE_SIZE); |
243 | if (size == 0) |
243 | if (size == 0) |
244 | return -EINVAL; |
244 | return -EINVAL; |
245 | 245 | ||
246 | /* Allocate the new object */ |
246 | /* Allocate the new object */ |
247 | obj = i915_gem_alloc_object(dev, size); |
247 | obj = i915_gem_alloc_object(dev, size); |
248 | if (obj == NULL) |
248 | if (obj == NULL) |
249 | return -ENOMEM; |
249 | return -ENOMEM; |
250 | 250 | ||
251 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
251 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
252 | /* drop reference from allocate - handle holds it now */ |
252 | /* drop reference from allocate - handle holds it now */ |
253 | drm_gem_object_unreference_unlocked(&obj->base); |
253 | drm_gem_object_unreference_unlocked(&obj->base); |
254 | if (ret) |
254 | if (ret) |
255 | return ret; |
255 | return ret; |
256 | 256 | ||
257 | *handle_p = handle; |
257 | *handle_p = handle; |
258 | return 0; |
258 | return 0; |
259 | } |
259 | } |
260 | 260 | ||
261 | int |
261 | int |
262 | i915_gem_dumb_create(struct drm_file *file, |
262 | i915_gem_dumb_create(struct drm_file *file, |
263 | struct drm_device *dev, |
263 | struct drm_device *dev, |
264 | struct drm_mode_create_dumb *args) |
264 | struct drm_mode_create_dumb *args) |
265 | { |
265 | { |
266 | /* have to work out size/pitch and return them */ |
266 | /* have to work out size/pitch and return them */ |
267 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
267 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
268 | args->size = args->pitch * args->height; |
268 | args->size = args->pitch * args->height; |
269 | return i915_gem_create(file, dev, |
269 | return i915_gem_create(file, dev, |
270 | args->size, &args->handle); |
270 | args->size, &args->handle); |
271 | } |
271 | } |
272 | 272 | ||
273 | /** |
273 | /** |
274 | * Creates a new mm object and returns a handle to it. |
274 | * Creates a new mm object and returns a handle to it. |
275 | */ |
275 | */ |
276 | int |
276 | int |
277 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
277 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
278 | struct drm_file *file) |
278 | struct drm_file *file) |
279 | { |
279 | { |
280 | struct drm_i915_gem_create *args = data; |
280 | struct drm_i915_gem_create *args = data; |
281 | 281 | ||
282 | return i915_gem_create(file, dev, |
282 | return i915_gem_create(file, dev, |
283 | args->size, &args->handle); |
283 | args->size, &args->handle); |
284 | } |
284 | } |
285 | 285 | ||
286 | 286 | ||
287 | #if 0 |
287 | #if 0 |
288 | 288 | ||
289 | static inline int |
289 | static inline int |
290 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
290 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
291 | const char *gpu_vaddr, int gpu_offset, |
291 | const char *gpu_vaddr, int gpu_offset, |
292 | int length) |
292 | int length) |
293 | { |
293 | { |
294 | int ret, cpu_offset = 0; |
294 | int ret, cpu_offset = 0; |
295 | 295 | ||
296 | while (length > 0) { |
296 | while (length > 0) { |
297 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
297 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
298 | int this_length = min(cacheline_end - gpu_offset, length); |
298 | int this_length = min(cacheline_end - gpu_offset, length); |
299 | int swizzled_gpu_offset = gpu_offset ^ 64; |
299 | int swizzled_gpu_offset = gpu_offset ^ 64; |
300 | 300 | ||
301 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
301 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
302 | gpu_vaddr + swizzled_gpu_offset, |
302 | gpu_vaddr + swizzled_gpu_offset, |
303 | this_length); |
303 | this_length); |
304 | if (ret) |
304 | if (ret) |
305 | return ret + length; |
305 | return ret + length; |
306 | 306 | ||
307 | cpu_offset += this_length; |
307 | cpu_offset += this_length; |
308 | gpu_offset += this_length; |
308 | gpu_offset += this_length; |
309 | length -= this_length; |
309 | length -= this_length; |
310 | } |
310 | } |
311 | 311 | ||
312 | return 0; |
312 | return 0; |
313 | } |
313 | } |
314 | 314 | ||
315 | static inline int |
315 | static inline int |
316 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
316 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
317 | const char __user *cpu_vaddr, |
317 | const char __user *cpu_vaddr, |
318 | int length) |
318 | int length) |
319 | { |
319 | { |
320 | int ret, cpu_offset = 0; |
320 | int ret, cpu_offset = 0; |
321 | 321 | ||
322 | while (length > 0) { |
322 | while (length > 0) { |
323 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
323 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
324 | int this_length = min(cacheline_end - gpu_offset, length); |
324 | int this_length = min(cacheline_end - gpu_offset, length); |
325 | int swizzled_gpu_offset = gpu_offset ^ 64; |
325 | int swizzled_gpu_offset = gpu_offset ^ 64; |
326 | 326 | ||
327 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
327 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
328 | cpu_vaddr + cpu_offset, |
328 | cpu_vaddr + cpu_offset, |
329 | this_length); |
329 | this_length); |
330 | if (ret) |
330 | if (ret) |
331 | return ret + length; |
331 | return ret + length; |
332 | 332 | ||
333 | cpu_offset += this_length; |
333 | cpu_offset += this_length; |
334 | gpu_offset += this_length; |
334 | gpu_offset += this_length; |
335 | length -= this_length; |
335 | length -= this_length; |
336 | } |
336 | } |
337 | 337 | ||
338 | return 0; |
338 | return 0; |
339 | } |
339 | } |
340 | 340 | ||
341 | /* Per-page copy function for the shmem pread fastpath. |
341 | /* Per-page copy function for the shmem pread fastpath. |
342 | * Flushes invalid cachelines before reading the target if |
342 | * Flushes invalid cachelines before reading the target if |
343 | * needs_clflush is set. */ |
343 | * needs_clflush is set. */ |
344 | static int |
344 | static int |
345 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
345 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
346 | char __user *user_data, |
346 | char __user *user_data, |
347 | bool page_do_bit17_swizzling, bool needs_clflush) |
347 | bool page_do_bit17_swizzling, bool needs_clflush) |
348 | { |
348 | { |
349 | char *vaddr; |
349 | char *vaddr; |
350 | int ret; |
350 | int ret; |
351 | 351 | ||
352 | if (unlikely(page_do_bit17_swizzling)) |
352 | if (unlikely(page_do_bit17_swizzling)) |
353 | return -EINVAL; |
353 | return -EINVAL; |
354 | 354 | ||
355 | vaddr = kmap_atomic(page); |
355 | vaddr = kmap_atomic(page); |
356 | if (needs_clflush) |
356 | if (needs_clflush) |
357 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
357 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
358 | page_length); |
358 | page_length); |
359 | ret = __copy_to_user_inatomic(user_data, |
359 | ret = __copy_to_user_inatomic(user_data, |
360 | vaddr + shmem_page_offset, |
360 | vaddr + shmem_page_offset, |
361 | page_length); |
361 | page_length); |
362 | kunmap_atomic(vaddr); |
362 | kunmap_atomic(vaddr); |
363 | 363 | ||
364 | return ret ? -EFAULT : 0; |
364 | return ret ? -EFAULT : 0; |
365 | } |
365 | } |
366 | 366 | ||
367 | static void |
367 | static void |
368 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
368 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
369 | bool swizzled) |
369 | bool swizzled) |
370 | { |
370 | { |
371 | if (unlikely(swizzled)) { |
371 | if (unlikely(swizzled)) { |
372 | unsigned long start = (unsigned long) addr; |
372 | unsigned long start = (unsigned long) addr; |
373 | unsigned long end = (unsigned long) addr + length; |
373 | unsigned long end = (unsigned long) addr + length; |
374 | 374 | ||
375 | /* For swizzling simply ensure that we always flush both |
375 | /* For swizzling simply ensure that we always flush both |
376 | * channels. Lame, but simple and it works. Swizzled |
376 | * channels. Lame, but simple and it works. Swizzled |
377 | * pwrite/pread is far from a hotpath - current userspace |
377 | * pwrite/pread is far from a hotpath - current userspace |
378 | * doesn't use it at all. */ |
378 | * doesn't use it at all. */ |
379 | start = round_down(start, 128); |
379 | start = round_down(start, 128); |
380 | end = round_up(end, 128); |
380 | end = round_up(end, 128); |
381 | 381 | ||
382 | drm_clflush_virt_range((void *)start, end - start); |
382 | drm_clflush_virt_range((void *)start, end - start); |
383 | } else { |
383 | } else { |
384 | drm_clflush_virt_range(addr, length); |
384 | drm_clflush_virt_range(addr, length); |
385 | } |
385 | } |
386 | 386 | ||
387 | } |
387 | } |
388 | 388 | ||
389 | /* Only difference to the fast-path function is that this can handle bit17 |
389 | /* Only difference to the fast-path function is that this can handle bit17 |
390 | * and uses non-atomic copy and kmap functions. */ |
390 | * and uses non-atomic copy and kmap functions. */ |
391 | static int |
391 | static int |
392 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
392 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
393 | char __user *user_data, |
393 | char __user *user_data, |
394 | bool page_do_bit17_swizzling, bool needs_clflush) |
394 | bool page_do_bit17_swizzling, bool needs_clflush) |
395 | { |
395 | { |
396 | char *vaddr; |
396 | char *vaddr; |
397 | int ret; |
397 | int ret; |
398 | 398 | ||
399 | vaddr = kmap(page); |
399 | vaddr = kmap(page); |
400 | if (needs_clflush) |
400 | if (needs_clflush) |
401 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
401 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
402 | page_length, |
402 | page_length, |
403 | page_do_bit17_swizzling); |
403 | page_do_bit17_swizzling); |
404 | 404 | ||
405 | if (page_do_bit17_swizzling) |
405 | if (page_do_bit17_swizzling) |
406 | ret = __copy_to_user_swizzled(user_data, |
406 | ret = __copy_to_user_swizzled(user_data, |
407 | vaddr, shmem_page_offset, |
407 | vaddr, shmem_page_offset, |
408 | page_length); |
408 | page_length); |
409 | else |
409 | else |
410 | ret = __copy_to_user(user_data, |
410 | ret = __copy_to_user(user_data, |
411 | vaddr + shmem_page_offset, |
411 | vaddr + shmem_page_offset, |
412 | page_length); |
412 | page_length); |
413 | kunmap(page); |
413 | kunmap(page); |
414 | 414 | ||
415 | return ret ? - EFAULT : 0; |
415 | return ret ? - EFAULT : 0; |
416 | } |
416 | } |
417 | 417 | ||
418 | static int |
418 | static int |
419 | i915_gem_shmem_pread(struct drm_device *dev, |
419 | i915_gem_shmem_pread(struct drm_device *dev, |
420 | struct drm_i915_gem_object *obj, |
420 | struct drm_i915_gem_object *obj, |
421 | struct drm_i915_gem_pread *args, |
421 | struct drm_i915_gem_pread *args, |
422 | struct drm_file *file) |
422 | struct drm_file *file) |
423 | { |
423 | { |
424 | char __user *user_data; |
424 | char __user *user_data; |
425 | ssize_t remain; |
425 | ssize_t remain; |
426 | loff_t offset; |
426 | loff_t offset; |
427 | int shmem_page_offset, page_length, ret = 0; |
427 | int shmem_page_offset, page_length, ret = 0; |
428 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
428 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
429 | int prefaulted = 0; |
429 | int prefaulted = 0; |
430 | int needs_clflush = 0; |
430 | int needs_clflush = 0; |
431 | struct sg_page_iter sg_iter; |
431 | struct sg_page_iter sg_iter; |
432 | 432 | ||
433 | user_data = to_user_ptr(args->data_ptr); |
433 | user_data = to_user_ptr(args->data_ptr); |
434 | remain = args->size; |
434 | remain = args->size; |
435 | 435 | ||
436 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
436 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
437 | 437 | ||
438 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
438 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
439 | if (ret) |
439 | if (ret) |
440 | return ret; |
440 | return ret; |
441 | 441 | ||
442 | offset = args->offset; |
442 | offset = args->offset; |
443 | 443 | ||
444 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
444 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
445 | offset >> PAGE_SHIFT) { |
445 | offset >> PAGE_SHIFT) { |
446 | struct page *page = sg_page_iter_page(&sg_iter); |
446 | struct page *page = sg_page_iter_page(&sg_iter); |
447 | 447 | ||
448 | if (remain <= 0) |
448 | if (remain <= 0) |
449 | break; |
449 | break; |
450 | 450 | ||
451 | /* Operation in this page |
451 | /* Operation in this page |
452 | * |
452 | * |
453 | * shmem_page_offset = offset within page in shmem file |
453 | * shmem_page_offset = offset within page in shmem file |
454 | * page_length = bytes to copy for this page |
454 | * page_length = bytes to copy for this page |
455 | */ |
455 | */ |
456 | shmem_page_offset = offset_in_page(offset); |
456 | shmem_page_offset = offset_in_page(offset); |
457 | page_length = remain; |
457 | page_length = remain; |
458 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
458 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
459 | page_length = PAGE_SIZE - shmem_page_offset; |
459 | page_length = PAGE_SIZE - shmem_page_offset; |
460 | 460 | ||
461 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
461 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
462 | (page_to_phys(page) & (1 << 17)) != 0; |
462 | (page_to_phys(page) & (1 << 17)) != 0; |
463 | 463 | ||
464 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
464 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
465 | user_data, page_do_bit17_swizzling, |
465 | user_data, page_do_bit17_swizzling, |
466 | needs_clflush); |
466 | needs_clflush); |
467 | if (ret == 0) |
467 | if (ret == 0) |
468 | goto next_page; |
468 | goto next_page; |
469 | 469 | ||
470 | mutex_unlock(&dev->struct_mutex); |
470 | mutex_unlock(&dev->struct_mutex); |
471 | 471 | ||
472 | if (likely(!i915.prefault_disable) && !prefaulted) { |
472 | if (likely(!i915.prefault_disable) && !prefaulted) { |
473 | ret = fault_in_multipages_writeable(user_data, remain); |
473 | ret = fault_in_multipages_writeable(user_data, remain); |
474 | /* Userspace is tricking us, but we've already clobbered |
474 | /* Userspace is tricking us, but we've already clobbered |
475 | * its pages with the prefault and promised to write the |
475 | * its pages with the prefault and promised to write the |
476 | * data up to the first fault. Hence ignore any errors |
476 | * data up to the first fault. Hence ignore any errors |
477 | * and just continue. */ |
477 | * and just continue. */ |
478 | (void)ret; |
478 | (void)ret; |
479 | prefaulted = 1; |
479 | prefaulted = 1; |
480 | } |
480 | } |
481 | 481 | ||
482 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
482 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
483 | user_data, page_do_bit17_swizzling, |
483 | user_data, page_do_bit17_swizzling, |
484 | needs_clflush); |
484 | needs_clflush); |
485 | 485 | ||
486 | mutex_lock(&dev->struct_mutex); |
486 | mutex_lock(&dev->struct_mutex); |
487 | 487 | ||
488 | if (ret) |
488 | if (ret) |
489 | goto out; |
489 | goto out; |
490 | 490 | ||
491 | next_page: |
491 | next_page: |
492 | remain -= page_length; |
492 | remain -= page_length; |
493 | user_data += page_length; |
493 | user_data += page_length; |
494 | offset += page_length; |
494 | offset += page_length; |
495 | } |
495 | } |
496 | 496 | ||
497 | out: |
497 | out: |
498 | i915_gem_object_unpin_pages(obj); |
498 | i915_gem_object_unpin_pages(obj); |
499 | 499 | ||
500 | return ret; |
500 | return ret; |
501 | } |
501 | } |
502 | 502 | ||
503 | /** |
503 | /** |
504 | * Reads data from the object referenced by handle. |
504 | * Reads data from the object referenced by handle. |
505 | * |
505 | * |
506 | * On error, the contents of *data are undefined. |
506 | * On error, the contents of *data are undefined. |
507 | */ |
507 | */ |
508 | int |
508 | int |
509 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
509 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
510 | struct drm_file *file) |
510 | struct drm_file *file) |
511 | { |
511 | { |
512 | struct drm_i915_gem_pread *args = data; |
512 | struct drm_i915_gem_pread *args = data; |
513 | struct drm_i915_gem_object *obj; |
513 | struct drm_i915_gem_object *obj; |
514 | int ret = 0; |
514 | int ret = 0; |
515 | 515 | ||
516 | if (args->size == 0) |
516 | if (args->size == 0) |
517 | return 0; |
517 | return 0; |
518 | 518 | ||
519 | if (!access_ok(VERIFY_WRITE, |
519 | if (!access_ok(VERIFY_WRITE, |
520 | to_user_ptr(args->data_ptr), |
520 | to_user_ptr(args->data_ptr), |
521 | args->size)) |
521 | args->size)) |
522 | return -EFAULT; |
522 | return -EFAULT; |
523 | 523 | ||
524 | ret = i915_mutex_lock_interruptible(dev); |
524 | ret = i915_mutex_lock_interruptible(dev); |
525 | if (ret) |
525 | if (ret) |
526 | return ret; |
526 | return ret; |
527 | 527 | ||
528 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
528 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
529 | if (&obj->base == NULL) { |
529 | if (&obj->base == NULL) { |
530 | ret = -ENOENT; |
530 | ret = -ENOENT; |
531 | goto unlock; |
531 | goto unlock; |
532 | } |
532 | } |
533 | 533 | ||
534 | /* Bounds check source. */ |
534 | /* Bounds check source. */ |
535 | if (args->offset > obj->base.size || |
535 | if (args->offset > obj->base.size || |
536 | args->size > obj->base.size - args->offset) { |
536 | args->size > obj->base.size - args->offset) { |
537 | ret = -EINVAL; |
537 | ret = -EINVAL; |
538 | goto out; |
538 | goto out; |
539 | } |
539 | } |
540 | 540 | ||
541 | /* prime objects have no backing filp to GEM pread/pwrite |
541 | /* prime objects have no backing filp to GEM pread/pwrite |
542 | * pages from. |
542 | * pages from. |
543 | */ |
543 | */ |
544 | if (!obj->base.filp) { |
544 | if (!obj->base.filp) { |
545 | ret = -EINVAL; |
545 | ret = -EINVAL; |
546 | goto out; |
546 | goto out; |
547 | } |
547 | } |
548 | 548 | ||
549 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
549 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
550 | 550 | ||
551 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
551 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
552 | 552 | ||
553 | out: |
553 | out: |
554 | drm_gem_object_unreference(&obj->base); |
554 | drm_gem_object_unreference(&obj->base); |
555 | unlock: |
555 | unlock: |
556 | mutex_unlock(&dev->struct_mutex); |
556 | mutex_unlock(&dev->struct_mutex); |
557 | return ret; |
557 | return ret; |
558 | } |
558 | } |
559 | 559 | ||
560 | /* This is the fast write path which cannot handle |
560 | /* This is the fast write path which cannot handle |
561 | * page faults in the source data |
561 | * page faults in the source data |
562 | */ |
562 | */ |
563 | 563 | ||
564 | static inline int |
564 | static inline int |
565 | fast_user_write(struct io_mapping *mapping, |
565 | fast_user_write(struct io_mapping *mapping, |
566 | loff_t page_base, int page_offset, |
566 | loff_t page_base, int page_offset, |
567 | char __user *user_data, |
567 | char __user *user_data, |
568 | int length) |
568 | int length) |
569 | { |
569 | { |
570 | void __iomem *vaddr_atomic; |
570 | void __iomem *vaddr_atomic; |
571 | void *vaddr; |
571 | void *vaddr; |
572 | unsigned long unwritten; |
572 | unsigned long unwritten; |
573 | 573 | ||
574 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
574 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
575 | /* We can use the cpu mem copy function because this is X86. */ |
575 | /* We can use the cpu mem copy function because this is X86. */ |
576 | vaddr = (void __force*)vaddr_atomic + page_offset; |
576 | vaddr = (void __force*)vaddr_atomic + page_offset; |
577 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
577 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
578 | user_data, length); |
578 | user_data, length); |
579 | io_mapping_unmap_atomic(vaddr_atomic); |
579 | io_mapping_unmap_atomic(vaddr_atomic); |
580 | return unwritten; |
580 | return unwritten; |
581 | } |
581 | } |
582 | #endif |
582 | #endif |
583 | 583 | ||
584 | #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) |
584 | #define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) |
585 | /** |
585 | /** |
586 | * This is the fast pwrite path, where we copy the data directly from the |
586 | * This is the fast pwrite path, where we copy the data directly from the |
587 | * user into the GTT, uncached. |
587 | * user into the GTT, uncached. |
588 | */ |
588 | */ |
589 | static int |
589 | static int |
590 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
590 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
591 | struct drm_i915_gem_object *obj, |
591 | struct drm_i915_gem_object *obj, |
592 | struct drm_i915_gem_pwrite *args, |
592 | struct drm_i915_gem_pwrite *args, |
593 | struct drm_file *file) |
593 | struct drm_file *file) |
594 | { |
594 | { |
595 | struct drm_i915_private *dev_priv = dev->dev_private; |
595 | struct drm_i915_private *dev_priv = dev->dev_private; |
596 | ssize_t remain; |
596 | ssize_t remain; |
597 | loff_t offset, page_base; |
597 | loff_t offset, page_base; |
598 | char __user *user_data; |
598 | char __user *user_data; |
599 | int page_offset, page_length, ret; |
599 | int page_offset, page_length, ret; |
600 | 600 | ||
601 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
601 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
602 | if (ret) |
602 | if (ret) |
603 | goto out; |
603 | goto out; |
604 | 604 | ||
605 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
605 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
606 | if (ret) |
606 | if (ret) |
607 | goto out_unpin; |
607 | goto out_unpin; |
608 | 608 | ||
609 | ret = i915_gem_object_put_fence(obj); |
609 | ret = i915_gem_object_put_fence(obj); |
610 | if (ret) |
610 | if (ret) |
611 | goto out_unpin; |
611 | goto out_unpin; |
612 | 612 | ||
613 | user_data = to_user_ptr(args->data_ptr); |
613 | user_data = to_user_ptr(args->data_ptr); |
614 | remain = args->size; |
614 | remain = args->size; |
615 | 615 | ||
616 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
616 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
617 | 617 | ||
618 | while (remain > 0) { |
618 | while (remain > 0) { |
619 | /* Operation in this page |
619 | /* Operation in this page |
620 | * |
620 | * |
621 | * page_base = page offset within aperture |
621 | * page_base = page offset within aperture |
622 | * page_offset = offset within page |
622 | * page_offset = offset within page |
623 | * page_length = bytes to copy for this page |
623 | * page_length = bytes to copy for this page |
624 | */ |
624 | */ |
625 | page_base = offset & PAGE_MASK; |
625 | page_base = offset & PAGE_MASK; |
626 | page_offset = offset_in_page(offset); |
626 | page_offset = offset_in_page(offset); |
627 | page_length = remain; |
627 | page_length = remain; |
628 | if ((page_offset + remain) > PAGE_SIZE) |
628 | if ((page_offset + remain) > PAGE_SIZE) |
629 | page_length = PAGE_SIZE - page_offset; |
629 | page_length = PAGE_SIZE - page_offset; |
630 | 630 | ||
631 | MapPage(dev_priv->gtt.mappable, dev_priv->gtt.mappable_base+page_base, PG_SW); |
631 | MapPage(dev_priv->gtt.mappable, dev_priv->gtt.mappable_base+page_base, PG_SW); |
632 | 632 | ||
633 | memcpy((char*)dev_priv->gtt.mappable+page_offset, user_data, page_length); |
633 | memcpy((char*)dev_priv->gtt.mappable+page_offset, user_data, page_length); |
634 | 634 | ||
635 | remain -= page_length; |
635 | remain -= page_length; |
636 | user_data += page_length; |
636 | user_data += page_length; |
637 | offset += page_length; |
637 | offset += page_length; |
638 | } |
638 | } |
639 | 639 | ||
640 | out_unpin: |
640 | out_unpin: |
641 | i915_gem_object_ggtt_unpin(obj); |
641 | i915_gem_object_ggtt_unpin(obj); |
642 | out: |
642 | out: |
643 | return ret; |
643 | return ret; |
644 | } |
644 | } |
645 | 645 | ||
646 | /* Per-page copy function for the shmem pwrite fastpath. |
646 | /* Per-page copy function for the shmem pwrite fastpath. |
647 | * Flushes invalid cachelines before writing to the target if |
647 | * Flushes invalid cachelines before writing to the target if |
648 | * needs_clflush_before is set and flushes out any written cachelines after |
648 | * needs_clflush_before is set and flushes out any written cachelines after |
649 | * writing if needs_clflush is set. */ |
649 | * writing if needs_clflush is set. */ |
650 | static int |
650 | static int |
651 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
651 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
652 | char __user *user_data, |
652 | char __user *user_data, |
653 | bool page_do_bit17_swizzling, |
653 | bool page_do_bit17_swizzling, |
654 | bool needs_clflush_before, |
654 | bool needs_clflush_before, |
655 | bool needs_clflush_after) |
655 | bool needs_clflush_after) |
656 | { |
656 | { |
657 | char *vaddr; |
657 | char *vaddr; |
658 | int ret; |
658 | int ret; |
659 | 659 | ||
660 | if (unlikely(page_do_bit17_swizzling)) |
660 | if (unlikely(page_do_bit17_swizzling)) |
661 | return -EINVAL; |
661 | return -EINVAL; |
662 | 662 | ||
663 | vaddr = kmap_atomic(page); |
663 | vaddr = kmap_atomic(page); |
664 | if (needs_clflush_before) |
664 | if (needs_clflush_before) |
665 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
665 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
666 | page_length); |
666 | page_length); |
667 | memcpy(vaddr + shmem_page_offset, |
667 | memcpy(vaddr + shmem_page_offset, |
668 | user_data, |
668 | user_data, |
669 | page_length); |
669 | page_length); |
670 | if (needs_clflush_after) |
670 | if (needs_clflush_after) |
671 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
671 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
672 | page_length); |
672 | page_length); |
673 | kunmap_atomic(vaddr); |
673 | kunmap_atomic(vaddr); |
674 | 674 | ||
675 | return ret ? -EFAULT : 0; |
675 | return ret ? -EFAULT : 0; |
676 | } |
676 | } |
677 | #if 0 |
677 | #if 0 |
678 | 678 | ||
679 | /* Only difference to the fast-path function is that this can handle bit17 |
679 | /* Only difference to the fast-path function is that this can handle bit17 |
680 | * and uses non-atomic copy and kmap functions. */ |
680 | * and uses non-atomic copy and kmap functions. */ |
681 | static int |
681 | static int |
682 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
682 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
683 | char __user *user_data, |
683 | char __user *user_data, |
684 | bool page_do_bit17_swizzling, |
684 | bool page_do_bit17_swizzling, |
685 | bool needs_clflush_before, |
685 | bool needs_clflush_before, |
686 | bool needs_clflush_after) |
686 | bool needs_clflush_after) |
687 | { |
687 | { |
688 | char *vaddr; |
688 | char *vaddr; |
689 | int ret; |
689 | int ret; |
690 | 690 | ||
691 | vaddr = kmap(page); |
691 | vaddr = kmap(page); |
692 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
692 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
693 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
693 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
694 | page_length, |
694 | page_length, |
695 | page_do_bit17_swizzling); |
695 | page_do_bit17_swizzling); |
696 | if (page_do_bit17_swizzling) |
696 | if (page_do_bit17_swizzling) |
697 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
697 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
698 | user_data, |
698 | user_data, |
699 | page_length); |
699 | page_length); |
700 | else |
700 | else |
701 | ret = __copy_from_user(vaddr + shmem_page_offset, |
701 | ret = __copy_from_user(vaddr + shmem_page_offset, |
702 | user_data, |
702 | user_data, |
703 | page_length); |
703 | page_length); |
704 | if (needs_clflush_after) |
704 | if (needs_clflush_after) |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, |
706 | page_length, |
707 | page_do_bit17_swizzling); |
707 | page_do_bit17_swizzling); |
708 | kunmap(page); |
708 | kunmap(page); |
709 | 709 | ||
710 | return ret ? -EFAULT : 0; |
710 | return ret ? -EFAULT : 0; |
711 | } |
711 | } |
712 | #endif |
712 | #endif |
713 | 713 | ||
714 | 714 | ||
715 | static int |
715 | static int |
716 | i915_gem_shmem_pwrite(struct drm_device *dev, |
716 | i915_gem_shmem_pwrite(struct drm_device *dev, |
717 | struct drm_i915_gem_object *obj, |
717 | struct drm_i915_gem_object *obj, |
718 | struct drm_i915_gem_pwrite *args, |
718 | struct drm_i915_gem_pwrite *args, |
719 | struct drm_file *file) |
719 | struct drm_file *file) |
720 | { |
720 | { |
721 | ssize_t remain; |
721 | ssize_t remain; |
722 | loff_t offset; |
722 | loff_t offset; |
723 | char __user *user_data; |
723 | char __user *user_data; |
724 | int shmem_page_offset, page_length, ret = 0; |
724 | int shmem_page_offset, page_length, ret = 0; |
725 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
725 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
726 | int hit_slowpath = 0; |
726 | int hit_slowpath = 0; |
727 | int needs_clflush_after = 0; |
727 | int needs_clflush_after = 0; |
728 | int needs_clflush_before = 0; |
728 | int needs_clflush_before = 0; |
729 | struct sg_page_iter sg_iter; |
729 | struct sg_page_iter sg_iter; |
730 | 730 | ||
731 | user_data = to_user_ptr(args->data_ptr); |
731 | user_data = to_user_ptr(args->data_ptr); |
732 | remain = args->size; |
732 | remain = args->size; |
733 | 733 | ||
734 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
734 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
735 | 735 | ||
736 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
736 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
737 | /* If we're not in the cpu write domain, set ourself into the gtt |
737 | /* If we're not in the cpu write domain, set ourself into the gtt |
738 | * write domain and manually flush cachelines (if required). This |
738 | * write domain and manually flush cachelines (if required). This |
739 | * optimizes for the case when the gpu will use the data |
739 | * optimizes for the case when the gpu will use the data |
740 | * right away and we therefore have to clflush anyway. */ |
740 | * right away and we therefore have to clflush anyway. */ |
741 | needs_clflush_after = cpu_write_needs_clflush(obj); |
741 | needs_clflush_after = cpu_write_needs_clflush(obj); |
742 | ret = i915_gem_object_wait_rendering(obj, false); |
742 | ret = i915_gem_object_wait_rendering(obj, false); |
743 | if (ret) |
743 | if (ret) |
744 | return ret; |
744 | return ret; |
745 | 745 | ||
746 | i915_gem_object_retire(obj); |
746 | i915_gem_object_retire(obj); |
747 | } |
747 | } |
748 | /* Same trick applies to invalidate partially written cachelines read |
748 | /* Same trick applies to invalidate partially written cachelines read |
749 | * before writing. */ |
749 | * before writing. */ |
750 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
750 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
751 | needs_clflush_before = |
751 | needs_clflush_before = |
752 | !cpu_cache_is_coherent(dev, obj->cache_level); |
752 | !cpu_cache_is_coherent(dev, obj->cache_level); |
753 | 753 | ||
754 | ret = i915_gem_object_get_pages(obj); |
754 | ret = i915_gem_object_get_pages(obj); |
755 | if (ret) |
755 | if (ret) |
756 | return ret; |
756 | return ret; |
757 | 757 | ||
758 | i915_gem_object_pin_pages(obj); |
758 | i915_gem_object_pin_pages(obj); |
759 | 759 | ||
760 | offset = args->offset; |
760 | offset = args->offset; |
761 | obj->dirty = 1; |
761 | obj->dirty = 1; |
762 | 762 | ||
763 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
763 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
764 | offset >> PAGE_SHIFT) { |
764 | offset >> PAGE_SHIFT) { |
765 | struct page *page = sg_page_iter_page(&sg_iter); |
765 | struct page *page = sg_page_iter_page(&sg_iter); |
766 | int partial_cacheline_write; |
766 | int partial_cacheline_write; |
767 | 767 | ||
768 | if (remain <= 0) |
768 | if (remain <= 0) |
769 | break; |
769 | break; |
770 | 770 | ||
771 | /* Operation in this page |
771 | /* Operation in this page |
772 | * |
772 | * |
773 | * shmem_page_offset = offset within page in shmem file |
773 | * shmem_page_offset = offset within page in shmem file |
774 | * page_length = bytes to copy for this page |
774 | * page_length = bytes to copy for this page |
775 | */ |
775 | */ |
776 | shmem_page_offset = offset_in_page(offset); |
776 | shmem_page_offset = offset_in_page(offset); |
777 | 777 | ||
778 | page_length = remain; |
778 | page_length = remain; |
779 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
779 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
780 | page_length = PAGE_SIZE - shmem_page_offset; |
780 | page_length = PAGE_SIZE - shmem_page_offset; |
781 | 781 | ||
782 | /* If we don't overwrite a cacheline completely we need to be |
782 | /* If we don't overwrite a cacheline completely we need to be |
783 | * careful to have up-to-date data by first clflushing. Don't |
783 | * careful to have up-to-date data by first clflushing. Don't |
784 | * overcomplicate things and flush the entire patch. */ |
784 | * overcomplicate things and flush the entire patch. */ |
785 | partial_cacheline_write = needs_clflush_before && |
785 | partial_cacheline_write = needs_clflush_before && |
786 | ((shmem_page_offset | page_length) |
786 | ((shmem_page_offset | page_length) |
787 | & (x86_clflush_size - 1)); |
787 | & (x86_clflush_size - 1)); |
788 | 788 | ||
789 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
789 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
790 | (page_to_phys(page) & (1 << 17)) != 0; |
790 | (page_to_phys(page) & (1 << 17)) != 0; |
791 | 791 | ||
792 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
792 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
793 | user_data, page_do_bit17_swizzling, |
793 | user_data, page_do_bit17_swizzling, |
794 | partial_cacheline_write, |
794 | partial_cacheline_write, |
795 | needs_clflush_after); |
795 | needs_clflush_after); |
796 | if (ret == 0) |
796 | if (ret == 0) |
797 | goto next_page; |
797 | goto next_page; |
798 | 798 | ||
799 | hit_slowpath = 1; |
799 | hit_slowpath = 1; |
800 | mutex_unlock(&dev->struct_mutex); |
800 | mutex_unlock(&dev->struct_mutex); |
801 | dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__); |
801 | dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__); |
802 | 802 | ||
803 | // ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
803 | // ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
804 | // user_data, page_do_bit17_swizzling, |
804 | // user_data, page_do_bit17_swizzling, |
805 | // partial_cacheline_write, |
805 | // partial_cacheline_write, |
806 | // needs_clflush_after); |
806 | // needs_clflush_after); |
807 | 807 | ||
808 | mutex_lock(&dev->struct_mutex); |
808 | mutex_lock(&dev->struct_mutex); |
809 | 809 | ||
810 | if (ret) |
810 | if (ret) |
811 | goto out; |
811 | goto out; |
812 | 812 | ||
813 | next_page: |
813 | next_page: |
814 | remain -= page_length; |
814 | remain -= page_length; |
815 | user_data += page_length; |
815 | user_data += page_length; |
816 | offset += page_length; |
816 | offset += page_length; |
817 | } |
817 | } |
818 | 818 | ||
819 | out: |
819 | out: |
820 | i915_gem_object_unpin_pages(obj); |
820 | i915_gem_object_unpin_pages(obj); |
821 | 821 | ||
822 | if (hit_slowpath) { |
822 | if (hit_slowpath) { |
823 | /* |
823 | /* |
824 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
824 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
825 | * cachelines in-line while writing and the object moved |
825 | * cachelines in-line while writing and the object moved |
826 | * out of the cpu write domain while we've dropped the lock. |
826 | * out of the cpu write domain while we've dropped the lock. |
827 | */ |
827 | */ |
828 | if (!needs_clflush_after && |
828 | if (!needs_clflush_after && |
829 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
829 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
830 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
830 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
831 | i915_gem_chipset_flush(dev); |
831 | i915_gem_chipset_flush(dev); |
832 | } |
832 | } |
833 | } |
833 | } |
834 | 834 | ||
835 | if (needs_clflush_after) |
835 | if (needs_clflush_after) |
836 | i915_gem_chipset_flush(dev); |
836 | i915_gem_chipset_flush(dev); |
837 | 837 | ||
838 | return ret; |
838 | return ret; |
839 | } |
839 | } |
840 | 840 | ||
841 | /** |
841 | /** |
842 | * Writes data to the object referenced by handle. |
842 | * Writes data to the object referenced by handle. |
843 | * |
843 | * |
844 | * On error, the contents of the buffer that were to be modified are undefined. |
844 | * On error, the contents of the buffer that were to be modified are undefined. |
845 | */ |
845 | */ |
846 | int |
846 | int |
847 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
847 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
848 | struct drm_file *file) |
848 | struct drm_file *file) |
849 | { |
849 | { |
850 | struct drm_i915_gem_pwrite *args = data; |
850 | struct drm_i915_gem_pwrite *args = data; |
851 | struct drm_i915_gem_object *obj; |
851 | struct drm_i915_gem_object *obj; |
852 | int ret; |
852 | int ret; |
853 | 853 | ||
854 | if (args->size == 0) |
854 | if (args->size == 0) |
855 | return 0; |
855 | return 0; |
856 | 856 | ||
857 | 857 | ||
858 | ret = i915_mutex_lock_interruptible(dev); |
858 | ret = i915_mutex_lock_interruptible(dev); |
859 | if (ret) |
859 | if (ret) |
860 | return ret; |
860 | return ret; |
861 | 861 | ||
862 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
862 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
863 | if (&obj->base == NULL) { |
863 | if (&obj->base == NULL) { |
864 | ret = -ENOENT; |
864 | ret = -ENOENT; |
865 | goto unlock; |
865 | goto unlock; |
866 | } |
866 | } |
867 | 867 | ||
868 | /* Bounds check destination. */ |
868 | /* Bounds check destination. */ |
869 | if (args->offset > obj->base.size || |
869 | if (args->offset > obj->base.size || |
870 | args->size > obj->base.size - args->offset) { |
870 | args->size > obj->base.size - args->offset) { |
871 | ret = -EINVAL; |
871 | ret = -EINVAL; |
872 | goto out; |
872 | goto out; |
873 | } |
873 | } |
874 | 874 | ||
875 | /* prime objects have no backing filp to GEM pread/pwrite |
875 | /* prime objects have no backing filp to GEM pread/pwrite |
876 | * pages from. |
876 | * pages from. |
877 | */ |
877 | */ |
878 | if (!obj->base.filp) { |
878 | if (!obj->base.filp) { |
879 | ret = -EINVAL; |
879 | ret = -EINVAL; |
880 | goto out; |
880 | goto out; |
881 | } |
881 | } |
882 | 882 | ||
883 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
883 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
884 | 884 | ||
885 | ret = -EFAULT; |
885 | ret = -EFAULT; |
886 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
886 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
887 | * it would end up going through the fenced access, and we'll get |
887 | * it would end up going through the fenced access, and we'll get |
888 | * different detiling behavior between reading and writing. |
888 | * different detiling behavior between reading and writing. |
889 | * pread/pwrite currently are reading and writing from the CPU |
889 | * pread/pwrite currently are reading and writing from the CPU |
890 | * perspective, requiring manual detiling by the client. |
890 | * perspective, requiring manual detiling by the client. |
891 | */ |
891 | */ |
892 | if (obj->tiling_mode == I915_TILING_NONE && |
892 | if (obj->tiling_mode == I915_TILING_NONE && |
893 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
893 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
894 | cpu_write_needs_clflush(obj)) { |
894 | cpu_write_needs_clflush(obj)) { |
895 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
895 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
896 | /* Note that the gtt paths might fail with non-page-backed user |
896 | /* Note that the gtt paths might fail with non-page-backed user |
897 | * pointers (e.g. gtt mappings when moving data between |
897 | * pointers (e.g. gtt mappings when moving data between |
898 | * textures). Fallback to the shmem path in that case. */ |
898 | * textures). Fallback to the shmem path in that case. */ |
899 | } |
899 | } |
900 | 900 | ||
901 | if (ret == -EFAULT || ret == -ENOSPC) |
901 | if (ret == -EFAULT || ret == -ENOSPC) |
902 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
902 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
903 | 903 | ||
904 | out: |
904 | out: |
905 | drm_gem_object_unreference(&obj->base); |
905 | drm_gem_object_unreference(&obj->base); |
906 | unlock: |
906 | unlock: |
907 | mutex_unlock(&dev->struct_mutex); |
907 | mutex_unlock(&dev->struct_mutex); |
908 | return ret; |
908 | return ret; |
909 | } |
909 | } |
910 | 910 | ||
911 | int |
911 | int |
912 | i915_gem_check_wedge(struct i915_gpu_error *error, |
912 | i915_gem_check_wedge(struct i915_gpu_error *error, |
913 | bool interruptible) |
913 | bool interruptible) |
914 | { |
914 | { |
915 | if (i915_reset_in_progress(error)) { |
915 | if (i915_reset_in_progress(error)) { |
916 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
916 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
917 | * -EIO unconditionally for these. */ |
917 | * -EIO unconditionally for these. */ |
918 | if (!interruptible) |
918 | if (!interruptible) |
919 | return -EIO; |
919 | return -EIO; |
920 | 920 | ||
921 | /* Recovery complete, but the reset failed ... */ |
921 | /* Recovery complete, but the reset failed ... */ |
922 | if (i915_terminally_wedged(error)) |
922 | if (i915_terminally_wedged(error)) |
923 | return -EIO; |
923 | return -EIO; |
924 | 924 | ||
925 | return -EAGAIN; |
925 | return -EAGAIN; |
926 | } |
926 | } |
927 | 927 | ||
928 | return 0; |
928 | return 0; |
929 | } |
929 | } |
930 | 930 | ||
931 | /* |
931 | /* |
932 | * Compare seqno against outstanding lazy request. Emit a request if they are |
932 | * Compare seqno against outstanding lazy request. Emit a request if they are |
933 | * equal. |
933 | * equal. |
934 | */ |
934 | */ |
935 | int |
935 | int |
936 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
936 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
937 | { |
937 | { |
938 | int ret; |
938 | int ret; |
939 | 939 | ||
940 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
940 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
941 | 941 | ||
942 | ret = 0; |
942 | ret = 0; |
943 | if (seqno == ring->outstanding_lazy_seqno) |
943 | if (seqno == ring->outstanding_lazy_seqno) |
944 | ret = i915_add_request(ring, NULL); |
944 | ret = i915_add_request(ring, NULL); |
945 | 945 | ||
946 | return ret; |
946 | return ret; |
947 | } |
947 | } |
948 | 948 | ||
949 | static void fake_irq(unsigned long data) |
949 | static void fake_irq(unsigned long data) |
950 | { |
950 | { |
951 | // wake_up_process((struct task_struct *)data); |
951 | // wake_up_process((struct task_struct *)data); |
952 | } |
952 | } |
953 | 953 | ||
954 | static bool missed_irq(struct drm_i915_private *dev_priv, |
954 | static bool missed_irq(struct drm_i915_private *dev_priv, |
955 | struct intel_engine_cs *ring) |
955 | struct intel_engine_cs *ring) |
956 | { |
956 | { |
957 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
957 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
958 | } |
958 | } |
959 | 959 | ||
960 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
960 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
961 | { |
961 | { |
962 | if (file_priv == NULL) |
962 | if (file_priv == NULL) |
963 | return true; |
963 | return true; |
964 | 964 | ||
965 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
965 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
966 | } |
966 | } |
967 | 967 | ||
968 | /** |
968 | /** |
969 | * __i915_wait_seqno - wait until execution of seqno has finished |
969 | * __i915_wait_seqno - wait until execution of seqno has finished |
970 | * @ring: the ring expected to report seqno |
970 | * @ring: the ring expected to report seqno |
971 | * @seqno: duh! |
971 | * @seqno: duh! |
972 | * @reset_counter: reset sequence associated with the given seqno |
972 | * @reset_counter: reset sequence associated with the given seqno |
973 | * @interruptible: do an interruptible wait (normally yes) |
973 | * @interruptible: do an interruptible wait (normally yes) |
974 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
974 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
975 | * |
975 | * |
976 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
976 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
977 | * values have been read by the caller in an smp safe manner. Where read-side |
977 | * values have been read by the caller in an smp safe manner. Where read-side |
978 | * locks are involved, it is sufficient to read the reset_counter before |
978 | * locks are involved, it is sufficient to read the reset_counter before |
979 | * unlocking the lock that protects the seqno. For lockless tricks, the |
979 | * unlocking the lock that protects the seqno. For lockless tricks, the |
980 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
980 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
981 | * inserted. |
981 | * inserted. |
982 | * |
982 | * |
983 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
983 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
984 | * errno with remaining time filled in timeout argument. |
984 | * errno with remaining time filled in timeout argument. |
985 | */ |
985 | */ |
986 | int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
986 | int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
987 | unsigned reset_counter, |
987 | unsigned reset_counter, |
988 | bool interruptible, |
988 | bool interruptible, |
989 | s64 *timeout, |
989 | s64 *timeout, |
990 | struct drm_i915_file_private *file_priv) |
990 | struct drm_i915_file_private *file_priv) |
991 | { |
991 | { |
992 | struct drm_device *dev = ring->dev; |
992 | struct drm_device *dev = ring->dev; |
993 | struct drm_i915_private *dev_priv = dev->dev_private; |
993 | struct drm_i915_private *dev_priv = dev->dev_private; |
994 | const bool irq_test_in_progress = |
994 | const bool irq_test_in_progress = |
995 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
995 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
996 | unsigned long timeout_expire; |
996 | unsigned long timeout_expire; |
997 | s64 before, now; |
997 | s64 before, now; |
998 | 998 | ||
999 | wait_queue_t __wait; |
999 | wait_queue_t __wait; |
1000 | int ret; |
1000 | int ret; |
1001 | 1001 | ||
1002 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
1002 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
1003 | 1003 | ||
1004 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1004 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1005 | return 0; |
1005 | return 0; |
1006 | 1006 | ||
1007 | timeout_expire = timeout ? |
1007 | timeout_expire = timeout ? |
1008 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; |
1008 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; |
1009 | 1009 | ||
1010 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
1010 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
1011 | gen6_rps_boost(dev_priv); |
1011 | gen6_rps_boost(dev_priv); |
1012 | if (file_priv) |
1012 | if (file_priv) |
1013 | mod_delayed_work(dev_priv->wq, |
1013 | mod_delayed_work(dev_priv->wq, |
1014 | &file_priv->mm.idle_work, |
1014 | &file_priv->mm.idle_work, |
1015 | msecs_to_jiffies(100)); |
1015 | msecs_to_jiffies(100)); |
1016 | } |
1016 | } |
1017 | 1017 | ||
1018 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
1018 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
1019 | return -ENODEV; |
1019 | return -ENODEV; |
1020 | 1020 | ||
1021 | INIT_LIST_HEAD(&__wait.task_list); |
1021 | INIT_LIST_HEAD(&__wait.task_list); |
1022 | __wait.evnt = CreateEvent(NULL, MANUAL_DESTROY); |
1022 | __wait.evnt = CreateEvent(NULL, MANUAL_DESTROY); |
1023 | 1023 | ||
1024 | /* Record current time in case interrupted by signal, or wedged */ |
1024 | /* Record current time in case interrupted by signal, or wedged */ |
1025 | trace_i915_gem_request_wait_begin(ring, seqno); |
1025 | trace_i915_gem_request_wait_begin(ring, seqno); |
1026 | 1026 | ||
1027 | for (;;) { |
1027 | for (;;) { |
1028 | unsigned long flags; |
1028 | unsigned long flags; |
1029 | 1029 | ||
1030 | /* We need to check whether any gpu reset happened in between |
1030 | /* We need to check whether any gpu reset happened in between |
1031 | * the caller grabbing the seqno and now ... */ |
1031 | * the caller grabbing the seqno and now ... */ |
1032 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1032 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1033 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
1033 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
1034 | * is truely gone. */ |
1034 | * is truely gone. */ |
1035 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1035 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1036 | if (ret == 0) |
1036 | if (ret == 0) |
1037 | ret = -EAGAIN; |
1037 | ret = -EAGAIN; |
1038 | break; |
1038 | break; |
1039 | } |
1039 | } |
1040 | 1040 | ||
1041 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1041 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1042 | ret = 0; |
1042 | ret = 0; |
1043 | break; |
1043 | break; |
1044 | } |
1044 | } |
1045 | 1045 | ||
1046 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
1046 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
1047 | ret = -ETIME; |
1047 | ret = -ETIME; |
1048 | break; |
1048 | break; |
1049 | } |
1049 | } |
1050 | 1050 | ||
1051 | spin_lock_irqsave(&ring->irq_queue.lock, flags); |
1051 | spin_lock_irqsave(&ring->irq_queue.lock, flags); |
1052 | if (list_empty(&__wait.task_list)) |
1052 | if (list_empty(&__wait.task_list)) |
1053 | __add_wait_queue(&ring->irq_queue, &__wait); |
1053 | __add_wait_queue(&ring->irq_queue, &__wait); |
1054 | spin_unlock_irqrestore(&ring->irq_queue.lock, flags); |
1054 | spin_unlock_irqrestore(&ring->irq_queue.lock, flags); |
1055 | 1055 | ||
1056 | WaitEventTimeout(__wait.evnt, 1); |
1056 | WaitEventTimeout(__wait.evnt, 1); |
1057 | 1057 | ||
1058 | if (!list_empty(&__wait.task_list)) { |
1058 | if (!list_empty(&__wait.task_list)) { |
1059 | spin_lock_irqsave(&ring->irq_queue.lock, flags); |
1059 | spin_lock_irqsave(&ring->irq_queue.lock, flags); |
1060 | list_del_init(&__wait.task_list); |
1060 | list_del_init(&__wait.task_list); |
1061 | spin_unlock_irqrestore(&ring->irq_queue.lock, flags); |
1061 | spin_unlock_irqrestore(&ring->irq_queue.lock, flags); |
1062 | } |
1062 | } |
1063 | }; |
1063 | }; |
1064 | trace_i915_gem_request_wait_end(ring, seqno); |
1064 | trace_i915_gem_request_wait_end(ring, seqno); |
1065 | 1065 | ||
1066 | DestroyEvent(__wait.evnt); |
1066 | DestroyEvent(__wait.evnt); |
1067 | 1067 | ||
1068 | if (!irq_test_in_progress) |
1068 | if (!irq_test_in_progress) |
1069 | ring->irq_put(ring); |
1069 | ring->irq_put(ring); |
1070 | 1070 | ||
1071 | // finish_wait(&ring->irq_queue, &wait); |
1071 | // finish_wait(&ring->irq_queue, &wait); |
1072 | return ret; |
1072 | return ret; |
1073 | } |
1073 | } |
1074 | 1074 | ||
1075 | /** |
1075 | /** |
1076 | * Waits for a sequence number to be signaled, and cleans up the |
1076 | * Waits for a sequence number to be signaled, and cleans up the |
1077 | * request and object lists appropriately for that event. |
1077 | * request and object lists appropriately for that event. |
1078 | */ |
1078 | */ |
1079 | int |
1079 | int |
1080 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
1080 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
1081 | { |
1081 | { |
1082 | struct drm_device *dev = ring->dev; |
1082 | struct drm_device *dev = ring->dev; |
1083 | struct drm_i915_private *dev_priv = dev->dev_private; |
1083 | struct drm_i915_private *dev_priv = dev->dev_private; |
1084 | bool interruptible = dev_priv->mm.interruptible; |
1084 | bool interruptible = dev_priv->mm.interruptible; |
1085 | unsigned reset_counter; |
1085 | unsigned reset_counter; |
1086 | int ret; |
1086 | int ret; |
1087 | 1087 | ||
1088 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1088 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1089 | BUG_ON(seqno == 0); |
1089 | BUG_ON(seqno == 0); |
1090 | 1090 | ||
1091 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1091 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
1092 | if (ret) |
1092 | if (ret) |
1093 | return ret; |
1093 | return ret; |
1094 | 1094 | ||
1095 | ret = i915_gem_check_olr(ring, seqno); |
1095 | ret = i915_gem_check_olr(ring, seqno); |
1096 | if (ret) |
1096 | if (ret) |
1097 | return ret; |
1097 | return ret; |
1098 | 1098 | ||
1099 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1099 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1100 | return __i915_wait_seqno(ring, seqno, reset_counter, interruptible, |
1100 | return __i915_wait_seqno(ring, seqno, reset_counter, interruptible, |
1101 | NULL, NULL); |
1101 | NULL, NULL); |
1102 | } |
1102 | } |
1103 | 1103 | ||
1104 | static int |
1104 | static int |
1105 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
1105 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
1106 | { |
1106 | { |
1107 | if (!obj->active) |
1107 | if (!obj->active) |
1108 | return 0; |
1108 | return 0; |
1109 | 1109 | ||
1110 | /* Manually manage the write flush as we may have not yet |
1110 | /* Manually manage the write flush as we may have not yet |
1111 | * retired the buffer. |
1111 | * retired the buffer. |
1112 | * |
1112 | * |
1113 | * Note that the last_write_seqno is always the earlier of |
1113 | * Note that the last_write_seqno is always the earlier of |
1114 | * the two (read/write) seqno, so if we haved successfully waited, |
1114 | * the two (read/write) seqno, so if we haved successfully waited, |
1115 | * we know we have passed the last write. |
1115 | * we know we have passed the last write. |
1116 | */ |
1116 | */ |
1117 | obj->last_write_seqno = 0; |
1117 | obj->last_write_seqno = 0; |
1118 | 1118 | ||
1119 | return 0; |
1119 | return 0; |
1120 | } |
1120 | } |
1121 | 1121 | ||
1122 | /** |
1122 | /** |
1123 | * Ensures that all rendering to the object has completed and the object is |
1123 | * Ensures that all rendering to the object has completed and the object is |
1124 | * safe to unbind from the GTT or access from the CPU. |
1124 | * safe to unbind from the GTT or access from the CPU. |
1125 | */ |
1125 | */ |
1126 | static __must_check int |
1126 | static __must_check int |
1127 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1127 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1128 | bool readonly) |
1128 | bool readonly) |
1129 | { |
1129 | { |
1130 | struct intel_engine_cs *ring = obj->ring; |
1130 | struct intel_engine_cs *ring = obj->ring; |
1131 | u32 seqno; |
1131 | u32 seqno; |
1132 | int ret; |
1132 | int ret; |
1133 | 1133 | ||
1134 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1134 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1135 | if (seqno == 0) |
1135 | if (seqno == 0) |
1136 | return 0; |
1136 | return 0; |
1137 | 1137 | ||
1138 | ret = i915_wait_seqno(ring, seqno); |
1138 | ret = i915_wait_seqno(ring, seqno); |
1139 | if (ret) |
1139 | if (ret) |
1140 | return ret; |
1140 | return ret; |
1141 | 1141 | ||
1142 | return i915_gem_object_wait_rendering__tail(obj); |
1142 | return i915_gem_object_wait_rendering__tail(obj); |
1143 | } |
1143 | } |
1144 | 1144 | ||
1145 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1145 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1146 | * as the object state may change during this call. |
1146 | * as the object state may change during this call. |
1147 | */ |
1147 | */ |
1148 | static __must_check int |
1148 | static __must_check int |
1149 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
1149 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
1150 | struct drm_i915_file_private *file_priv, |
1150 | struct drm_i915_file_private *file_priv, |
1151 | bool readonly) |
1151 | bool readonly) |
1152 | { |
1152 | { |
1153 | struct drm_device *dev = obj->base.dev; |
1153 | struct drm_device *dev = obj->base.dev; |
1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
1155 | struct intel_engine_cs *ring = obj->ring; |
1155 | struct intel_engine_cs *ring = obj->ring; |
1156 | unsigned reset_counter; |
1156 | unsigned reset_counter; |
1157 | u32 seqno; |
1157 | u32 seqno; |
1158 | int ret; |
1158 | int ret; |
1159 | 1159 | ||
1160 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1160 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1161 | BUG_ON(!dev_priv->mm.interruptible); |
1161 | BUG_ON(!dev_priv->mm.interruptible); |
1162 | 1162 | ||
1163 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1163 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
1164 | if (seqno == 0) |
1164 | if (seqno == 0) |
1165 | return 0; |
1165 | return 0; |
1166 | 1166 | ||
1167 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
1167 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
1168 | if (ret) |
1168 | if (ret) |
1169 | return ret; |
1169 | return ret; |
1170 | 1170 | ||
1171 | ret = i915_gem_check_olr(ring, seqno); |
1171 | ret = i915_gem_check_olr(ring, seqno); |
1172 | if (ret) |
1172 | if (ret) |
1173 | return ret; |
1173 | return ret; |
1174 | 1174 | ||
1175 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1175 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1176 | mutex_unlock(&dev->struct_mutex); |
1176 | mutex_unlock(&dev->struct_mutex); |
1177 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, |
1177 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, |
1178 | file_priv); |
1178 | file_priv); |
1179 | mutex_lock(&dev->struct_mutex); |
1179 | mutex_lock(&dev->struct_mutex); |
1180 | if (ret) |
1180 | if (ret) |
1181 | return ret; |
1181 | return ret; |
1182 | 1182 | ||
1183 | return i915_gem_object_wait_rendering__tail(obj); |
1183 | return i915_gem_object_wait_rendering__tail(obj); |
1184 | } |
1184 | } |
1185 | 1185 | ||
1186 | /** |
1186 | /** |
1187 | * Called when user space prepares to use an object with the CPU, either |
1187 | * Called when user space prepares to use an object with the CPU, either |
1188 | * through the mmap ioctl's mapping or a GTT mapping. |
1188 | * through the mmap ioctl's mapping or a GTT mapping. |
1189 | */ |
1189 | */ |
1190 | int |
1190 | int |
1191 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1191 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1192 | struct drm_file *file) |
1192 | struct drm_file *file) |
1193 | { |
1193 | { |
1194 | struct drm_i915_gem_set_domain *args = data; |
1194 | struct drm_i915_gem_set_domain *args = data; |
1195 | struct drm_i915_gem_object *obj; |
1195 | struct drm_i915_gem_object *obj; |
1196 | uint32_t read_domains = args->read_domains; |
1196 | uint32_t read_domains = args->read_domains; |
1197 | uint32_t write_domain = args->write_domain; |
1197 | uint32_t write_domain = args->write_domain; |
1198 | int ret; |
1198 | int ret; |
1199 | 1199 | ||
1200 | /* Only handle setting domains to types used by the CPU. */ |
1200 | /* Only handle setting domains to types used by the CPU. */ |
1201 | if (write_domain & I915_GEM_GPU_DOMAINS) |
1201 | if (write_domain & I915_GEM_GPU_DOMAINS) |
1202 | return -EINVAL; |
1202 | return -EINVAL; |
1203 | 1203 | ||
1204 | if (read_domains & I915_GEM_GPU_DOMAINS) |
1204 | if (read_domains & I915_GEM_GPU_DOMAINS) |
1205 | return -EINVAL; |
1205 | return -EINVAL; |
1206 | 1206 | ||
1207 | /* Having something in the write domain implies it's in the read |
1207 | /* Having something in the write domain implies it's in the read |
1208 | * domain, and only that read domain. Enforce that in the request. |
1208 | * domain, and only that read domain. Enforce that in the request. |
1209 | */ |
1209 | */ |
1210 | if (write_domain != 0 && read_domains != write_domain) |
1210 | if (write_domain != 0 && read_domains != write_domain) |
1211 | return -EINVAL; |
1211 | return -EINVAL; |
1212 | 1212 | ||
1213 | ret = i915_mutex_lock_interruptible(dev); |
1213 | ret = i915_mutex_lock_interruptible(dev); |
1214 | if (ret) |
1214 | if (ret) |
1215 | return ret; |
1215 | return ret; |
1216 | 1216 | ||
1217 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1217 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1218 | if (&obj->base == NULL) { |
1218 | if (&obj->base == NULL) { |
1219 | ret = -ENOENT; |
1219 | ret = -ENOENT; |
1220 | goto unlock; |
1220 | goto unlock; |
1221 | } |
1221 | } |
1222 | 1222 | ||
1223 | /* Try to flush the object off the GPU without holding the lock. |
1223 | /* Try to flush the object off the GPU without holding the lock. |
1224 | * We will repeat the flush holding the lock in the normal manner |
1224 | * We will repeat the flush holding the lock in the normal manner |
1225 | * to catch cases where we are gazumped. |
1225 | * to catch cases where we are gazumped. |
1226 | */ |
1226 | */ |
1227 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1227 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1228 | file->driver_priv, |
1228 | file->driver_priv, |
1229 | !write_domain); |
1229 | !write_domain); |
1230 | if (ret) |
1230 | if (ret) |
1231 | goto unref; |
1231 | goto unref; |
1232 | 1232 | ||
1233 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1233 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1234 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
1234 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
1235 | 1235 | ||
1236 | /* Silently promote "you're not bound, there was nothing to do" |
1236 | /* Silently promote "you're not bound, there was nothing to do" |
1237 | * to success, since the client was just asking us to |
1237 | * to success, since the client was just asking us to |
1238 | * make sure everything was done. |
1238 | * make sure everything was done. |
1239 | */ |
1239 | */ |
1240 | if (ret == -EINVAL) |
1240 | if (ret == -EINVAL) |
1241 | ret = 0; |
1241 | ret = 0; |
1242 | } else { |
1242 | } else { |
1243 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
1243 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
1244 | } |
1244 | } |
1245 | 1245 | ||
1246 | unref: |
1246 | unref: |
1247 | drm_gem_object_unreference(&obj->base); |
1247 | drm_gem_object_unreference(&obj->base); |
1248 | unlock: |
1248 | unlock: |
1249 | mutex_unlock(&dev->struct_mutex); |
1249 | mutex_unlock(&dev->struct_mutex); |
1250 | return ret; |
1250 | return ret; |
1251 | } |
1251 | } |
1252 | 1252 | ||
1253 | /** |
1253 | /** |
1254 | * Called when user space has done writes to this buffer |
1254 | * Called when user space has done writes to this buffer |
1255 | */ |
1255 | */ |
1256 | int |
1256 | int |
1257 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1257 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
1258 | struct drm_file *file) |
1258 | struct drm_file *file) |
1259 | { |
1259 | { |
1260 | struct drm_i915_gem_sw_finish *args = data; |
1260 | struct drm_i915_gem_sw_finish *args = data; |
1261 | struct drm_i915_gem_object *obj; |
1261 | struct drm_i915_gem_object *obj; |
1262 | int ret = 0; |
1262 | int ret = 0; |
1263 | 1263 | ||
1264 | ret = i915_mutex_lock_interruptible(dev); |
1264 | ret = i915_mutex_lock_interruptible(dev); |
1265 | if (ret) |
1265 | if (ret) |
1266 | return ret; |
1266 | return ret; |
1267 | 1267 | ||
1268 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1268 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1269 | if (&obj->base == NULL) { |
1269 | if (&obj->base == NULL) { |
1270 | ret = -ENOENT; |
1270 | ret = -ENOENT; |
1271 | goto unlock; |
1271 | goto unlock; |
1272 | } |
1272 | } |
1273 | 1273 | ||
1274 | /* Pinned buffers may be scanout, so flush the cache */ |
1274 | /* Pinned buffers may be scanout, so flush the cache */ |
1275 | if (obj->pin_display) |
1275 | if (obj->pin_display) |
1276 | i915_gem_object_flush_cpu_write_domain(obj, true); |
1276 | i915_gem_object_flush_cpu_write_domain(obj, true); |
1277 | 1277 | ||
1278 | drm_gem_object_unreference(&obj->base); |
1278 | drm_gem_object_unreference(&obj->base); |
1279 | unlock: |
1279 | unlock: |
1280 | mutex_unlock(&dev->struct_mutex); |
1280 | mutex_unlock(&dev->struct_mutex); |
1281 | return ret; |
1281 | return ret; |
1282 | } |
1282 | } |
1283 | 1283 | ||
1284 | /** |
1284 | /** |
1285 | * Maps the contents of an object, returning the address it is mapped |
1285 | * Maps the contents of an object, returning the address it is mapped |
1286 | * into. |
1286 | * into. |
1287 | * |
1287 | * |
1288 | * While the mapping holds a reference on the contents of the object, it doesn't |
1288 | * While the mapping holds a reference on the contents of the object, it doesn't |
1289 | * imply a ref on the object itself. |
1289 | * imply a ref on the object itself. |
1290 | * |
1290 | * |
1291 | * IMPORTANT: |
1291 | * IMPORTANT: |
1292 | * |
1292 | * |
1293 | * DRM driver writers who look a this function as an example for how to do GEM |
1293 | * DRM driver writers who look a this function as an example for how to do GEM |
1294 | * mmap support, please don't implement mmap support like here. The modern way |
1294 | * mmap support, please don't implement mmap support like here. The modern way |
1295 | * to implement DRM mmap support is with an mmap offset ioctl (like |
1295 | * to implement DRM mmap support is with an mmap offset ioctl (like |
1296 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
1296 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
1297 | * That way debug tooling like valgrind will understand what's going on, hiding |
1297 | * That way debug tooling like valgrind will understand what's going on, hiding |
1298 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
1298 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
1299 | * does cpu mmaps this way because we didn't know better. |
1299 | * does cpu mmaps this way because we didn't know better. |
1300 | */ |
1300 | */ |
1301 | int |
1301 | int |
1302 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1302 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
1303 | struct drm_file *file) |
1303 | struct drm_file *file) |
1304 | { |
1304 | { |
1305 | struct drm_i915_gem_mmap *args = data; |
1305 | struct drm_i915_gem_mmap *args = data; |
1306 | struct drm_gem_object *obj; |
1306 | struct drm_gem_object *obj; |
1307 | unsigned long addr; |
1307 | unsigned long addr; |
1308 | 1308 | ||
1309 | obj = drm_gem_object_lookup(dev, file, args->handle); |
1309 | obj = drm_gem_object_lookup(dev, file, args->handle); |
1310 | if (obj == NULL) |
1310 | if (obj == NULL) |
1311 | return -ENOENT; |
1311 | return -ENOENT; |
1312 | 1312 | ||
1313 | /* prime objects have no backing filp to GEM mmap |
1313 | /* prime objects have no backing filp to GEM mmap |
1314 | * pages from. |
1314 | * pages from. |
1315 | */ |
1315 | */ |
1316 | if (!obj->filp) { |
1316 | if (!obj->filp) { |
1317 | drm_gem_object_unreference_unlocked(obj); |
1317 | drm_gem_object_unreference_unlocked(obj); |
1318 | return -EINVAL; |
1318 | return -EINVAL; |
1319 | } |
1319 | } |
1320 | 1320 | ||
1321 | addr = vm_mmap(obj->filp, 0, args->size, |
1321 | addr = vm_mmap(obj->filp, 0, args->size, |
1322 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1322 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1323 | args->offset); |
1323 | args->offset); |
1324 | drm_gem_object_unreference_unlocked(obj); |
1324 | drm_gem_object_unreference_unlocked(obj); |
1325 | if (IS_ERR((void *)addr)) |
1325 | if (IS_ERR((void *)addr)) |
1326 | return addr; |
1326 | return addr; |
1327 | 1327 | ||
1328 | args->addr_ptr = (uint64_t) addr; |
1328 | args->addr_ptr = (uint64_t) addr; |
1329 | 1329 | ||
1330 | return 0; |
1330 | return 0; |
1331 | } |
1331 | } |
1332 | 1332 | ||
1333 | 1333 | ||
1334 | 1334 | ||
1335 | 1335 | ||
1336 | 1336 | ||
1337 | 1337 | ||
1338 | 1338 | ||
1339 | 1339 | ||
1340 | 1340 | ||
1341 | 1341 | ||
1342 | 1342 | ||
1343 | 1343 | ||
1344 | 1344 | ||
1345 | /** |
1345 | /** |
1346 | * i915_gem_release_mmap - remove physical page mappings |
1346 | * i915_gem_release_mmap - remove physical page mappings |
1347 | * @obj: obj in question |
1347 | * @obj: obj in question |
1348 | * |
1348 | * |
1349 | * Preserve the reservation of the mmapping with the DRM core code, but |
1349 | * Preserve the reservation of the mmapping with the DRM core code, but |
1350 | * relinquish ownership of the pages back to the system. |
1350 | * relinquish ownership of the pages back to the system. |
1351 | * |
1351 | * |
1352 | * It is vital that we remove the page mapping if we have mapped a tiled |
1352 | * It is vital that we remove the page mapping if we have mapped a tiled |
1353 | * object through the GTT and then lose the fence register due to |
1353 | * object through the GTT and then lose the fence register due to |
1354 | * resource pressure. Similarly if the object has been moved out of the |
1354 | * resource pressure. Similarly if the object has been moved out of the |
1355 | * aperture, than pages mapped into userspace must be revoked. Removing the |
1355 | * aperture, than pages mapped into userspace must be revoked. Removing the |
1356 | * mapping will then trigger a page fault on the next user access, allowing |
1356 | * mapping will then trigger a page fault on the next user access, allowing |
1357 | * fixup by i915_gem_fault(). |
1357 | * fixup by i915_gem_fault(). |
1358 | */ |
1358 | */ |
1359 | void |
1359 | void |
1360 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
1360 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
1361 | { |
1361 | { |
1362 | if (!obj->fault_mappable) |
1362 | if (!obj->fault_mappable) |
1363 | return; |
1363 | return; |
1364 | 1364 | ||
1365 | // drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
1365 | // drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
1366 | obj->fault_mappable = false; |
1366 | obj->fault_mappable = false; |
1367 | } |
1367 | } |
1368 | 1368 | ||
1369 | uint32_t |
1369 | uint32_t |
1370 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
1370 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
1371 | { |
1371 | { |
1372 | uint32_t gtt_size; |
1372 | uint32_t gtt_size; |
1373 | 1373 | ||
1374 | if (INTEL_INFO(dev)->gen >= 4 || |
1374 | if (INTEL_INFO(dev)->gen >= 4 || |
1375 | tiling_mode == I915_TILING_NONE) |
1375 | tiling_mode == I915_TILING_NONE) |
1376 | return size; |
1376 | return size; |
1377 | 1377 | ||
1378 | /* Previous chips need a power-of-two fence region when tiling */ |
1378 | /* Previous chips need a power-of-two fence region when tiling */ |
1379 | if (INTEL_INFO(dev)->gen == 3) |
1379 | if (INTEL_INFO(dev)->gen == 3) |
1380 | gtt_size = 1024*1024; |
1380 | gtt_size = 1024*1024; |
1381 | else |
1381 | else |
1382 | gtt_size = 512*1024; |
1382 | gtt_size = 512*1024; |
1383 | 1383 | ||
1384 | while (gtt_size < size) |
1384 | while (gtt_size < size) |
1385 | gtt_size <<= 1; |
1385 | gtt_size <<= 1; |
1386 | 1386 | ||
1387 | return gtt_size; |
1387 | return gtt_size; |
1388 | } |
1388 | } |
1389 | 1389 | ||
1390 | /** |
1390 | /** |
1391 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
1391 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
1392 | * @obj: object to check |
1392 | * @obj: object to check |
1393 | * |
1393 | * |
1394 | * Return the required GTT alignment for an object, taking into account |
1394 | * Return the required GTT alignment for an object, taking into account |
1395 | * potential fence register mapping. |
1395 | * potential fence register mapping. |
1396 | */ |
1396 | */ |
1397 | uint32_t |
1397 | uint32_t |
1398 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1398 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
1399 | int tiling_mode, bool fenced) |
1399 | int tiling_mode, bool fenced) |
1400 | { |
1400 | { |
1401 | /* |
1401 | /* |
1402 | * Minimum alignment is 4k (GTT page size), but might be greater |
1402 | * Minimum alignment is 4k (GTT page size), but might be greater |
1403 | * if a fence register is needed for the object. |
1403 | * if a fence register is needed for the object. |
1404 | */ |
1404 | */ |
1405 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
1405 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
1406 | tiling_mode == I915_TILING_NONE) |
1406 | tiling_mode == I915_TILING_NONE) |
1407 | return 4096; |
1407 | return 4096; |
1408 | 1408 | ||
1409 | /* |
1409 | /* |
1410 | * Previous chips need to be aligned to the size of the smallest |
1410 | * Previous chips need to be aligned to the size of the smallest |
1411 | * fence register that can contain the object. |
1411 | * fence register that can contain the object. |
1412 | */ |
1412 | */ |
1413 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1413 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
1414 | } |
1414 | } |
1415 | 1415 | ||
1416 | 1416 | ||
1417 | 1417 | ||
1418 | int |
1418 | int |
1419 | i915_gem_mmap_gtt(struct drm_file *file, |
1419 | i915_gem_mmap_gtt(struct drm_file *file, |
1420 | struct drm_device *dev, |
1420 | struct drm_device *dev, |
1421 | uint32_t handle, |
1421 | uint32_t handle, |
1422 | uint64_t *offset) |
1422 | uint64_t *offset) |
1423 | { |
1423 | { |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; |
1424 | struct drm_i915_private *dev_priv = dev->dev_private; |
1425 | struct drm_i915_gem_object *obj; |
1425 | struct drm_i915_gem_object *obj; |
1426 | unsigned long pfn; |
1426 | unsigned long pfn; |
1427 | char *mem, *ptr; |
1427 | char *mem, *ptr; |
1428 | int ret; |
1428 | int ret; |
1429 | 1429 | ||
1430 | ret = i915_mutex_lock_interruptible(dev); |
1430 | ret = i915_mutex_lock_interruptible(dev); |
1431 | if (ret) |
1431 | if (ret) |
1432 | return ret; |
1432 | return ret; |
1433 | 1433 | ||
1434 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
1434 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
1435 | if (&obj->base == NULL) { |
1435 | if (&obj->base == NULL) { |
1436 | ret = -ENOENT; |
1436 | ret = -ENOENT; |
1437 | goto unlock; |
1437 | goto unlock; |
1438 | } |
1438 | } |
1439 | 1439 | ||
1440 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
1440 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
1441 | ret = -E2BIG; |
1441 | ret = -E2BIG; |
1442 | goto out; |
1442 | goto out; |
1443 | } |
1443 | } |
1444 | 1444 | ||
1445 | if (obj->madv != I915_MADV_WILLNEED) { |
1445 | if (obj->madv != I915_MADV_WILLNEED) { |
1446 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
1446 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
1447 | ret = -EFAULT; |
1447 | ret = -EFAULT; |
1448 | goto out; |
1448 | goto out; |
1449 | } |
1449 | } |
1450 | /* Now bind it into the GTT if needed */ |
1450 | /* Now bind it into the GTT if needed */ |
1451 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
1451 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
1452 | if (ret) |
1452 | if (ret) |
1453 | goto out; |
1453 | goto out; |
1454 | 1454 | ||
1455 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
1455 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
1456 | if (ret) |
1456 | if (ret) |
1457 | goto unpin; |
1457 | goto unpin; |
1458 | 1458 | ||
1459 | ret = i915_gem_object_get_fence(obj); |
1459 | ret = i915_gem_object_get_fence(obj); |
1460 | if (ret) |
1460 | if (ret) |
1461 | goto unpin; |
1461 | goto unpin; |
1462 | 1462 | ||
1463 | obj->fault_mappable = true; |
1463 | obj->fault_mappable = true; |
1464 | 1464 | ||
1465 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1465 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1466 | 1466 | ||
1467 | /* Finally, remap it using the new GTT offset */ |
1467 | /* Finally, remap it using the new GTT offset */ |
1468 | 1468 | ||
1469 | mem = UserAlloc(obj->base.size); |
1469 | mem = UserAlloc(obj->base.size); |
1470 | if(unlikely(mem == NULL)) |
1470 | if(unlikely(mem == NULL)) |
1471 | { |
1471 | { |
1472 | ret = -ENOMEM; |
1472 | ret = -ENOMEM; |
1473 | goto unpin; |
1473 | goto unpin; |
1474 | } |
1474 | } |
1475 | 1475 | ||
1476 | for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096) |
1476 | for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096) |
1477 | MapPage(ptr, pfn, PG_SHARED|PG_UW); |
1477 | MapPage(ptr, pfn, PG_SHARED|PG_UW); |
1478 | 1478 | ||
1479 | unpin: |
1479 | unpin: |
1480 | i915_gem_object_unpin_pages(obj); |
1480 | i915_gem_object_unpin_pages(obj); |
1481 | 1481 | ||
1482 | 1482 | ||
1483 | *offset = mem; |
1483 | *offset = (uint32_t)mem; |
1484 | 1484 | ||
1485 | out: |
1485 | out: |
1486 | drm_gem_object_unreference(&obj->base); |
1486 | drm_gem_object_unreference(&obj->base); |
1487 | unlock: |
1487 | unlock: |
1488 | mutex_unlock(&dev->struct_mutex); |
1488 | mutex_unlock(&dev->struct_mutex); |
1489 | return ret; |
1489 | return ret; |
1490 | } |
1490 | } |
1491 | 1491 | ||
1492 | /** |
1492 | /** |
1493 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
1493 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
1494 | * @dev: DRM device |
1494 | * @dev: DRM device |
1495 | * @data: GTT mapping ioctl data |
1495 | * @data: GTT mapping ioctl data |
1496 | * @file: GEM object info |
1496 | * @file: GEM object info |
1497 | * |
1497 | * |
1498 | * Simply returns the fake offset to userspace so it can mmap it. |
1498 | * Simply returns the fake offset to userspace so it can mmap it. |
1499 | * The mmap call will end up in drm_gem_mmap(), which will set things |
1499 | * The mmap call will end up in drm_gem_mmap(), which will set things |
1500 | * up so we can get faults in the handler above. |
1500 | * up so we can get faults in the handler above. |
1501 | * |
1501 | * |
1502 | * The fault handler will take care of binding the object into the GTT |
1502 | * The fault handler will take care of binding the object into the GTT |
1503 | * (since it may have been evicted to make room for something), allocating |
1503 | * (since it may have been evicted to make room for something), allocating |
1504 | * a fence register, and mapping the appropriate aperture address into |
1504 | * a fence register, and mapping the appropriate aperture address into |
1505 | * userspace. |
1505 | * userspace. |
1506 | */ |
1506 | */ |
1507 | int |
1507 | int |
1508 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1508 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1509 | struct drm_file *file) |
1509 | struct drm_file *file) |
1510 | { |
1510 | { |
1511 | struct drm_i915_gem_mmap_gtt *args = data; |
1511 | struct drm_i915_gem_mmap_gtt *args = data; |
1512 | 1512 | ||
1513 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1513 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1514 | } |
1514 | } |
1515 | 1515 | ||
1516 | static inline int |
1516 | static inline int |
1517 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
1517 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
1518 | { |
1518 | { |
1519 | return obj->madv == I915_MADV_DONTNEED; |
1519 | return obj->madv == I915_MADV_DONTNEED; |
1520 | } |
1520 | } |
1521 | 1521 | ||
1522 | /* Immediately discard the backing storage */ |
1522 | /* Immediately discard the backing storage */ |
1523 | static void |
1523 | static void |
1524 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
1524 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
1525 | { |
1525 | { |
1526 | // i915_gem_object_free_mmap_offset(obj); |
1526 | // i915_gem_object_free_mmap_offset(obj); |
1527 | 1527 | ||
1528 | if (obj->base.filp == NULL) |
1528 | if (obj->base.filp == NULL) |
1529 | return; |
1529 | return; |
1530 | 1530 | ||
1531 | /* Our goal here is to return as much of the memory as |
1531 | /* Our goal here is to return as much of the memory as |
1532 | * is possible back to the system as we are called from OOM. |
1532 | * is possible back to the system as we are called from OOM. |
1533 | * To do this we must instruct the shmfs to drop all of its |
1533 | * To do this we must instruct the shmfs to drop all of its |
1534 | * backing pages, *now*. |
1534 | * backing pages, *now*. |
1535 | */ |
1535 | */ |
1536 | // shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
1536 | // shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
1537 | obj->madv = __I915_MADV_PURGED; |
1537 | obj->madv = __I915_MADV_PURGED; |
1538 | } |
1538 | } |
1539 | 1539 | ||
1540 | /* Try to discard unwanted pages */ |
1540 | /* Try to discard unwanted pages */ |
1541 | static void |
1541 | static void |
1542 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
1542 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
1543 | { |
1543 | { |
1544 | struct address_space *mapping; |
1544 | struct address_space *mapping; |
1545 | 1545 | ||
1546 | switch (obj->madv) { |
1546 | switch (obj->madv) { |
1547 | case I915_MADV_DONTNEED: |
1547 | case I915_MADV_DONTNEED: |
1548 | i915_gem_object_truncate(obj); |
1548 | i915_gem_object_truncate(obj); |
1549 | case __I915_MADV_PURGED: |
1549 | case __I915_MADV_PURGED: |
1550 | return; |
1550 | return; |
1551 | } |
1551 | } |
1552 | 1552 | ||
1553 | if (obj->base.filp == NULL) |
1553 | if (obj->base.filp == NULL) |
1554 | return; |
1554 | return; |
1555 | 1555 | ||
1556 | } |
1556 | } |
1557 | 1557 | ||
1558 | static void |
1558 | static void |
1559 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1559 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1560 | { |
1560 | { |
1561 | struct sg_page_iter sg_iter; |
1561 | struct sg_page_iter sg_iter; |
1562 | int ret; |
1562 | int ret; |
1563 | 1563 | ||
1564 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1564 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1565 | 1565 | ||
1566 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1566 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1567 | if (ret) { |
1567 | if (ret) { |
1568 | /* In the event of a disaster, abandon all caches and |
1568 | /* In the event of a disaster, abandon all caches and |
1569 | * hope for the best. |
1569 | * hope for the best. |
1570 | */ |
1570 | */ |
1571 | WARN_ON(ret != -EIO); |
1571 | WARN_ON(ret != -EIO); |
1572 | i915_gem_clflush_object(obj, true); |
1572 | i915_gem_clflush_object(obj, true); |
1573 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1573 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1574 | } |
1574 | } |
1575 | 1575 | ||
1576 | if (obj->madv == I915_MADV_DONTNEED) |
1576 | if (obj->madv == I915_MADV_DONTNEED) |
1577 | obj->dirty = 0; |
1577 | obj->dirty = 0; |
1578 | 1578 | ||
1579 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
1579 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
1580 | struct page *page = sg_page_iter_page(&sg_iter); |
1580 | struct page *page = sg_page_iter_page(&sg_iter); |
1581 | 1581 | ||
1582 | page_cache_release(page); |
1582 | page_cache_release(page); |
1583 | } |
1583 | } |
1584 | obj->dirty = 0; |
1584 | obj->dirty = 0; |
1585 | 1585 | ||
1586 | sg_free_table(obj->pages); |
1586 | sg_free_table(obj->pages); |
1587 | kfree(obj->pages); |
1587 | kfree(obj->pages); |
1588 | } |
1588 | } |
1589 | 1589 | ||
1590 | int |
1590 | int |
1591 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1591 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1592 | { |
1592 | { |
1593 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1593 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1594 | 1594 | ||
1595 | if (obj->pages == NULL) |
1595 | if (obj->pages == NULL) |
1596 | return 0; |
1596 | return 0; |
1597 | 1597 | ||
1598 | if (obj->pages_pin_count) |
1598 | if (obj->pages_pin_count) |
1599 | return -EBUSY; |
1599 | return -EBUSY; |
1600 | 1600 | ||
1601 | BUG_ON(i915_gem_obj_bound_any(obj)); |
1601 | BUG_ON(i915_gem_obj_bound_any(obj)); |
1602 | 1602 | ||
1603 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1603 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1604 | * array, hence protect them from being reaped by removing them from gtt |
1604 | * array, hence protect them from being reaped by removing them from gtt |
1605 | * lists early. */ |
1605 | * lists early. */ |
1606 | list_del(&obj->global_list); |
1606 | list_del(&obj->global_list); |
1607 | 1607 | ||
1608 | ops->put_pages(obj); |
1608 | ops->put_pages(obj); |
1609 | obj->pages = NULL; |
1609 | obj->pages = NULL; |
1610 | 1610 | ||
1611 | i915_gem_object_invalidate(obj); |
1611 | i915_gem_object_invalidate(obj); |
1612 | 1612 | ||
1613 | return 0; |
1613 | return 0; |
1614 | } |
1614 | } |
1615 | 1615 | ||
1616 | 1616 | ||
1617 | 1617 | ||
1618 | 1618 | ||
1619 | 1619 | ||
1620 | 1620 | ||
1621 | 1621 | ||
1622 | 1622 | ||
1623 | static int |
1623 | static int |
1624 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
1624 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
1625 | { |
1625 | { |
1626 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1626 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1627 | int page_count, i; |
1627 | int page_count, i; |
1628 | struct sg_table *st; |
1628 | struct sg_table *st; |
1629 | struct scatterlist *sg; |
1629 | struct scatterlist *sg; |
1630 | struct sg_page_iter sg_iter; |
1630 | struct sg_page_iter sg_iter; |
1631 | struct page *page; |
1631 | struct page *page; |
1632 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
1632 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
1633 | gfp_t gfp; |
1633 | gfp_t gfp; |
1634 | 1634 | ||
1635 | /* Assert that the object is not currently in any GPU domain. As it |
1635 | /* Assert that the object is not currently in any GPU domain. As it |
1636 | * wasn't in the GTT, there shouldn't be any way it could have been in |
1636 | * wasn't in the GTT, there shouldn't be any way it could have been in |
1637 | * a GPU cache |
1637 | * a GPU cache |
1638 | */ |
1638 | */ |
1639 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
1639 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
1640 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
1640 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
1641 | 1641 | ||
1642 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1642 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1643 | if (st == NULL) |
1643 | if (st == NULL) |
1644 | return -ENOMEM; |
1644 | return -ENOMEM; |
1645 | 1645 | ||
1646 | page_count = obj->base.size / PAGE_SIZE; |
1646 | page_count = obj->base.size / PAGE_SIZE; |
1647 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1647 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1648 | kfree(st); |
1648 | kfree(st); |
1649 | FAIL(); |
- | |
1650 | return -ENOMEM; |
1649 | return -ENOMEM; |
1651 | } |
1650 | } |
1652 | 1651 | ||
1653 | /* Get the list of pages out of our struct file. They'll be pinned |
1652 | /* Get the list of pages out of our struct file. They'll be pinned |
1654 | * at this point until we release them. |
1653 | * at this point until we release them. |
1655 | * |
1654 | * |
1656 | * Fail silently without starting the shrinker |
1655 | * Fail silently without starting the shrinker |
1657 | */ |
1656 | */ |
1658 | sg = st->sgl; |
1657 | sg = st->sgl; |
1659 | st->nents = 0; |
1658 | st->nents = 0; |
1660 | for (i = 0; i < page_count; i++) { |
1659 | for (i = 0; i < page_count; i++) { |
1661 | page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp); |
1660 | page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp); |
1662 | if (IS_ERR(page)) { |
1661 | if (IS_ERR(page)) { |
1663 | dbgprintf("%s invalid page %p\n", __FUNCTION__, page); |
1662 | dbgprintf("%s invalid page %p\n", __FUNCTION__, page); |
1664 | goto err_pages; |
1663 | goto err_pages; |
1665 | - | ||
1666 | } |
1664 | } |
1667 | #ifdef CONFIG_SWIOTLB |
1665 | #ifdef CONFIG_SWIOTLB |
1668 | if (swiotlb_nr_tbl()) { |
1666 | if (swiotlb_nr_tbl()) { |
1669 | st->nents++; |
1667 | st->nents++; |
1670 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1668 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1671 | sg = sg_next(sg); |
1669 | sg = sg_next(sg); |
1672 | continue; |
1670 | continue; |
1673 | } |
1671 | } |
1674 | #endif |
1672 | #endif |
1675 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1673 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1676 | if (i) |
1674 | if (i) |
1677 | sg = sg_next(sg); |
1675 | sg = sg_next(sg); |
1678 | st->nents++; |
1676 | st->nents++; |
1679 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1677 | sg_set_page(sg, page, PAGE_SIZE, 0); |
1680 | } else { |
1678 | } else { |
1681 | sg->length += PAGE_SIZE; |
1679 | sg->length += PAGE_SIZE; |
1682 | } |
1680 | } |
1683 | last_pfn = page_to_pfn(page); |
1681 | last_pfn = page_to_pfn(page); |
1684 | } |
1682 | } |
1685 | #ifdef CONFIG_SWIOTLB |
1683 | #ifdef CONFIG_SWIOTLB |
1686 | if (!swiotlb_nr_tbl()) |
1684 | if (!swiotlb_nr_tbl()) |
1687 | #endif |
1685 | #endif |
1688 | sg_mark_end(sg); |
1686 | sg_mark_end(sg); |
1689 | obj->pages = st; |
1687 | obj->pages = st; |
- | 1688 | ||
- | 1689 | ||
- | 1690 | if (obj->tiling_mode != I915_TILING_NONE && |
|
- | 1691 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
|
- | 1692 | i915_gem_object_pin_pages(obj); |
|
1690 | 1693 | ||
1691 | return 0; |
1694 | return 0; |
1692 | 1695 | ||
1693 | err_pages: |
1696 | err_pages: |
1694 | sg_mark_end(sg); |
1697 | sg_mark_end(sg); |
1695 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
1698 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
1696 | page_cache_release(sg_page_iter_page(&sg_iter)); |
1699 | page_cache_release(sg_page_iter_page(&sg_iter)); |
1697 | sg_free_table(st); |
1700 | sg_free_table(st); |
1698 | kfree(st); |
1701 | kfree(st); |
1699 | FAIL(); |
1702 | |
1700 | return PTR_ERR(page); |
1703 | return PTR_ERR(page); |
1701 | } |
1704 | } |
1702 | 1705 | ||
1703 | /* Ensure that the associated pages are gathered from the backing storage |
1706 | /* Ensure that the associated pages are gathered from the backing storage |
1704 | * and pinned into our object. i915_gem_object_get_pages() may be called |
1707 | * and pinned into our object. i915_gem_object_get_pages() may be called |
1705 | * multiple times before they are released by a single call to |
1708 | * multiple times before they are released by a single call to |
1706 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
1709 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
1707 | * either as a result of memory pressure (reaping pages under the shrinker) |
1710 | * either as a result of memory pressure (reaping pages under the shrinker) |
1708 | * or as the object is itself released. |
1711 | * or as the object is itself released. |
1709 | */ |
1712 | */ |
1710 | int |
1713 | int |
1711 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
1714 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
1712 | { |
1715 | { |
1713 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1716 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1714 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1717 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
1715 | int ret; |
1718 | int ret; |
1716 | 1719 | ||
1717 | if (obj->pages) |
1720 | if (obj->pages) |
1718 | return 0; |
1721 | return 0; |
1719 | 1722 | ||
1720 | if (obj->madv != I915_MADV_WILLNEED) { |
1723 | if (obj->madv != I915_MADV_WILLNEED) { |
1721 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
1724 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
1722 | return -EFAULT; |
1725 | return -EFAULT; |
1723 | } |
1726 | } |
1724 | 1727 | ||
1725 | BUG_ON(obj->pages_pin_count); |
1728 | BUG_ON(obj->pages_pin_count); |
1726 | 1729 | ||
1727 | ret = ops->get_pages(obj); |
1730 | ret = ops->get_pages(obj); |
1728 | if (ret) |
1731 | if (ret) |
1729 | return ret; |
1732 | return ret; |
1730 | 1733 | ||
1731 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
1734 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
1732 | return 0; |
1735 | return 0; |
1733 | } |
1736 | } |
1734 | 1737 | ||
1735 | static void |
1738 | static void |
1736 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1739 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1737 | struct intel_engine_cs *ring) |
1740 | struct intel_engine_cs *ring) |
1738 | { |
1741 | { |
1739 | u32 seqno = intel_ring_get_seqno(ring); |
1742 | u32 seqno = intel_ring_get_seqno(ring); |
1740 | 1743 | ||
1741 | BUG_ON(ring == NULL); |
1744 | BUG_ON(ring == NULL); |
1742 | if (obj->ring != ring && obj->last_write_seqno) { |
1745 | if (obj->ring != ring && obj->last_write_seqno) { |
1743 | /* Keep the seqno relative to the current ring */ |
1746 | /* Keep the seqno relative to the current ring */ |
1744 | obj->last_write_seqno = seqno; |
1747 | obj->last_write_seqno = seqno; |
1745 | } |
1748 | } |
1746 | obj->ring = ring; |
1749 | obj->ring = ring; |
1747 | 1750 | ||
1748 | /* Add a reference if we're newly entering the active list. */ |
1751 | /* Add a reference if we're newly entering the active list. */ |
1749 | if (!obj->active) { |
1752 | if (!obj->active) { |
1750 | drm_gem_object_reference(&obj->base); |
1753 | drm_gem_object_reference(&obj->base); |
1751 | obj->active = 1; |
1754 | obj->active = 1; |
1752 | } |
1755 | } |
1753 | 1756 | ||
1754 | list_move_tail(&obj->ring_list, &ring->active_list); |
1757 | list_move_tail(&obj->ring_list, &ring->active_list); |
1755 | 1758 | ||
1756 | obj->last_read_seqno = seqno; |
1759 | obj->last_read_seqno = seqno; |
1757 | } |
1760 | } |
1758 | 1761 | ||
1759 | void i915_vma_move_to_active(struct i915_vma *vma, |
1762 | void i915_vma_move_to_active(struct i915_vma *vma, |
1760 | struct intel_engine_cs *ring) |
1763 | struct intel_engine_cs *ring) |
1761 | { |
1764 | { |
1762 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
1765 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
1763 | return i915_gem_object_move_to_active(vma->obj, ring); |
1766 | return i915_gem_object_move_to_active(vma->obj, ring); |
1764 | } |
1767 | } |
1765 | 1768 | ||
1766 | static void |
1769 | static void |
1767 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
1770 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
1768 | { |
1771 | { |
1769 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1772 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1770 | struct i915_address_space *vm; |
1773 | struct i915_address_space *vm; |
1771 | struct i915_vma *vma; |
1774 | struct i915_vma *vma; |
1772 | 1775 | ||
1773 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
1776 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
1774 | BUG_ON(!obj->active); |
1777 | BUG_ON(!obj->active); |
1775 | 1778 | ||
1776 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1779 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1777 | vma = i915_gem_obj_to_vma(obj, vm); |
1780 | vma = i915_gem_obj_to_vma(obj, vm); |
1778 | if (vma && !list_empty(&vma->mm_list)) |
1781 | if (vma && !list_empty(&vma->mm_list)) |
1779 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
1782 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
1780 | } |
1783 | } |
1781 | 1784 | ||
1782 | intel_fb_obj_flush(obj, true); |
1785 | intel_fb_obj_flush(obj, true); |
1783 | 1786 | ||
1784 | list_del_init(&obj->ring_list); |
1787 | list_del_init(&obj->ring_list); |
1785 | obj->ring = NULL; |
1788 | obj->ring = NULL; |
1786 | 1789 | ||
1787 | obj->last_read_seqno = 0; |
1790 | obj->last_read_seqno = 0; |
1788 | obj->last_write_seqno = 0; |
1791 | obj->last_write_seqno = 0; |
1789 | obj->base.write_domain = 0; |
1792 | obj->base.write_domain = 0; |
1790 | 1793 | ||
1791 | obj->last_fenced_seqno = 0; |
1794 | obj->last_fenced_seqno = 0; |
1792 | 1795 | ||
1793 | obj->active = 0; |
1796 | obj->active = 0; |
1794 | drm_gem_object_unreference(&obj->base); |
1797 | drm_gem_object_unreference(&obj->base); |
1795 | 1798 | ||
1796 | WARN_ON(i915_verify_lists(dev)); |
1799 | WARN_ON(i915_verify_lists(dev)); |
1797 | } |
1800 | } |
1798 | 1801 | ||
1799 | static void |
1802 | static void |
1800 | i915_gem_object_retire(struct drm_i915_gem_object *obj) |
1803 | i915_gem_object_retire(struct drm_i915_gem_object *obj) |
1801 | { |
1804 | { |
1802 | struct intel_engine_cs *ring = obj->ring; |
1805 | struct intel_engine_cs *ring = obj->ring; |
1803 | 1806 | ||
1804 | if (ring == NULL) |
1807 | if (ring == NULL) |
1805 | return; |
1808 | return; |
1806 | 1809 | ||
1807 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
1810 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
1808 | obj->last_read_seqno)) |
1811 | obj->last_read_seqno)) |
1809 | i915_gem_object_move_to_inactive(obj); |
1812 | i915_gem_object_move_to_inactive(obj); |
1810 | } |
1813 | } |
1811 | 1814 | ||
1812 | static int |
1815 | static int |
1813 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
1816 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
1814 | { |
1817 | { |
1815 | struct drm_i915_private *dev_priv = dev->dev_private; |
1818 | struct drm_i915_private *dev_priv = dev->dev_private; |
1816 | struct intel_engine_cs *ring; |
1819 | struct intel_engine_cs *ring; |
1817 | int ret, i, j; |
1820 | int ret, i, j; |
1818 | 1821 | ||
1819 | /* Carefully retire all requests without writing to the rings */ |
1822 | /* Carefully retire all requests without writing to the rings */ |
1820 | for_each_ring(ring, dev_priv, i) { |
1823 | for_each_ring(ring, dev_priv, i) { |
1821 | ret = intel_ring_idle(ring); |
1824 | ret = intel_ring_idle(ring); |
1822 | if (ret) |
1825 | if (ret) |
1823 | return ret; |
1826 | return ret; |
1824 | } |
1827 | } |
1825 | i915_gem_retire_requests(dev); |
1828 | i915_gem_retire_requests(dev); |
1826 | 1829 | ||
1827 | /* Finally reset hw state */ |
1830 | /* Finally reset hw state */ |
1828 | for_each_ring(ring, dev_priv, i) { |
1831 | for_each_ring(ring, dev_priv, i) { |
1829 | intel_ring_init_seqno(ring, seqno); |
1832 | intel_ring_init_seqno(ring, seqno); |
1830 | 1833 | ||
1831 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
1834 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
1832 | ring->semaphore.sync_seqno[j] = 0; |
1835 | ring->semaphore.sync_seqno[j] = 0; |
1833 | } |
1836 | } |
1834 | 1837 | ||
1835 | return 0; |
1838 | return 0; |
1836 | } |
1839 | } |
1837 | 1840 | ||
1838 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1841 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1839 | { |
1842 | { |
1840 | struct drm_i915_private *dev_priv = dev->dev_private; |
1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
1841 | int ret; |
1844 | int ret; |
1842 | 1845 | ||
1843 | if (seqno == 0) |
1846 | if (seqno == 0) |
1844 | return -EINVAL; |
1847 | return -EINVAL; |
1845 | 1848 | ||
1846 | /* HWS page needs to be set less than what we |
1849 | /* HWS page needs to be set less than what we |
1847 | * will inject to ring |
1850 | * will inject to ring |
1848 | */ |
1851 | */ |
1849 | ret = i915_gem_init_seqno(dev, seqno - 1); |
1852 | ret = i915_gem_init_seqno(dev, seqno - 1); |
1850 | if (ret) |
1853 | if (ret) |
1851 | return ret; |
1854 | return ret; |
1852 | 1855 | ||
1853 | /* Carefully set the last_seqno value so that wrap |
1856 | /* Carefully set the last_seqno value so that wrap |
1854 | * detection still works |
1857 | * detection still works |
1855 | */ |
1858 | */ |
1856 | dev_priv->next_seqno = seqno; |
1859 | dev_priv->next_seqno = seqno; |
1857 | dev_priv->last_seqno = seqno - 1; |
1860 | dev_priv->last_seqno = seqno - 1; |
1858 | if (dev_priv->last_seqno == 0) |
1861 | if (dev_priv->last_seqno == 0) |
1859 | dev_priv->last_seqno--; |
1862 | dev_priv->last_seqno--; |
1860 | 1863 | ||
1861 | return 0; |
1864 | return 0; |
1862 | } |
1865 | } |
1863 | 1866 | ||
1864 | int |
1867 | int |
1865 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
1868 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
1866 | { |
1869 | { |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
1870 | struct drm_i915_private *dev_priv = dev->dev_private; |
1868 | 1871 | ||
1869 | /* reserve 0 for non-seqno */ |
1872 | /* reserve 0 for non-seqno */ |
1870 | if (dev_priv->next_seqno == 0) { |
1873 | if (dev_priv->next_seqno == 0) { |
1871 | int ret = i915_gem_init_seqno(dev, 0); |
1874 | int ret = i915_gem_init_seqno(dev, 0); |
1872 | if (ret) |
1875 | if (ret) |
1873 | return ret; |
1876 | return ret; |
1874 | 1877 | ||
1875 | dev_priv->next_seqno = 1; |
1878 | dev_priv->next_seqno = 1; |
1876 | } |
1879 | } |
1877 | 1880 | ||
1878 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
1881 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
1879 | return 0; |
1882 | return 0; |
1880 | } |
1883 | } |
1881 | 1884 | ||
1882 | int __i915_add_request(struct intel_engine_cs *ring, |
1885 | int __i915_add_request(struct intel_engine_cs *ring, |
1883 | struct drm_file *file, |
1886 | struct drm_file *file, |
1884 | struct drm_i915_gem_object *obj, |
1887 | struct drm_i915_gem_object *obj, |
1885 | u32 *out_seqno) |
1888 | u32 *out_seqno) |
1886 | { |
1889 | { |
1887 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1890 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1888 | struct drm_i915_gem_request *request; |
1891 | struct drm_i915_gem_request *request; |
1889 | struct intel_ringbuffer *ringbuf; |
1892 | struct intel_ringbuffer *ringbuf; |
1890 | u32 request_ring_position, request_start; |
1893 | u32 request_ring_position, request_start; |
1891 | int ret; |
1894 | int ret; |
1892 | 1895 | ||
1893 | request = ring->preallocated_lazy_request; |
1896 | request = ring->preallocated_lazy_request; |
1894 | if (WARN_ON(request == NULL)) |
1897 | if (WARN_ON(request == NULL)) |
1895 | return -ENOMEM; |
1898 | return -ENOMEM; |
1896 | 1899 | ||
1897 | if (i915.enable_execlists) { |
1900 | if (i915.enable_execlists) { |
1898 | struct intel_context *ctx = request->ctx; |
1901 | struct intel_context *ctx = request->ctx; |
1899 | ringbuf = ctx->engine[ring->id].ringbuf; |
1902 | ringbuf = ctx->engine[ring->id].ringbuf; |
1900 | } else |
1903 | } else |
1901 | ringbuf = ring->buffer; |
1904 | ringbuf = ring->buffer; |
1902 | 1905 | ||
1903 | request_start = intel_ring_get_tail(ringbuf); |
1906 | request_start = intel_ring_get_tail(ringbuf); |
1904 | /* |
1907 | /* |
1905 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
1908 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
1906 | * after having emitted the batchbuffer command. Hence we need to fix |
1909 | * after having emitted the batchbuffer command. Hence we need to fix |
1907 | * things up similar to emitting the lazy request. The difference here |
1910 | * things up similar to emitting the lazy request. The difference here |
1908 | * is that the flush _must_ happen before the next request, no matter |
1911 | * is that the flush _must_ happen before the next request, no matter |
1909 | * what. |
1912 | * what. |
1910 | */ |
1913 | */ |
1911 | if (i915.enable_execlists) { |
1914 | if (i915.enable_execlists) { |
1912 | ret = logical_ring_flush_all_caches(ringbuf); |
1915 | ret = logical_ring_flush_all_caches(ringbuf); |
1913 | if (ret) |
1916 | if (ret) |
1914 | return ret; |
1917 | return ret; |
1915 | } else { |
1918 | } else { |
1916 | ret = intel_ring_flush_all_caches(ring); |
1919 | ret = intel_ring_flush_all_caches(ring); |
1917 | if (ret) |
1920 | if (ret) |
1918 | return ret; |
1921 | return ret; |
1919 | } |
1922 | } |
1920 | 1923 | ||
1921 | /* Record the position of the start of the request so that |
1924 | /* Record the position of the start of the request so that |
1922 | * should we detect the updated seqno part-way through the |
1925 | * should we detect the updated seqno part-way through the |
1923 | * GPU processing the request, we never over-estimate the |
1926 | * GPU processing the request, we never over-estimate the |
1924 | * position of the head. |
1927 | * position of the head. |
1925 | */ |
1928 | */ |
1926 | request_ring_position = intel_ring_get_tail(ringbuf); |
1929 | request_ring_position = intel_ring_get_tail(ringbuf); |
1927 | 1930 | ||
1928 | if (i915.enable_execlists) { |
1931 | if (i915.enable_execlists) { |
1929 | ret = ring->emit_request(ringbuf); |
1932 | ret = ring->emit_request(ringbuf); |
1930 | if (ret) |
1933 | if (ret) |
1931 | return ret; |
1934 | return ret; |
1932 | } else { |
1935 | } else { |
1933 | ret = ring->add_request(ring); |
1936 | ret = ring->add_request(ring); |
1934 | if (ret) |
1937 | if (ret) |
1935 | return ret; |
1938 | return ret; |
1936 | } |
1939 | } |
1937 | 1940 | ||
1938 | request->seqno = intel_ring_get_seqno(ring); |
1941 | request->seqno = intel_ring_get_seqno(ring); |
1939 | request->ring = ring; |
1942 | request->ring = ring; |
1940 | request->head = request_start; |
1943 | request->head = request_start; |
1941 | request->tail = request_ring_position; |
1944 | request->tail = request_ring_position; |
1942 | 1945 | ||
1943 | /* Whilst this request exists, batch_obj will be on the |
1946 | /* Whilst this request exists, batch_obj will be on the |
1944 | * active_list, and so will hold the active reference. Only when this |
1947 | * active_list, and so will hold the active reference. Only when this |
1945 | * request is retired will the the batch_obj be moved onto the |
1948 | * request is retired will the the batch_obj be moved onto the |
1946 | * inactive_list and lose its active reference. Hence we do not need |
1949 | * inactive_list and lose its active reference. Hence we do not need |
1947 | * to explicitly hold another reference here. |
1950 | * to explicitly hold another reference here. |
1948 | */ |
1951 | */ |
1949 | request->batch_obj = obj; |
1952 | request->batch_obj = obj; |
1950 | 1953 | ||
1951 | if (!i915.enable_execlists) { |
1954 | if (!i915.enable_execlists) { |
1952 | /* Hold a reference to the current context so that we can inspect |
1955 | /* Hold a reference to the current context so that we can inspect |
1953 | * it later in case a hangcheck error event fires. |
1956 | * it later in case a hangcheck error event fires. |
1954 | */ |
1957 | */ |
1955 | request->ctx = ring->last_context; |
1958 | request->ctx = ring->last_context; |
1956 | if (request->ctx) |
1959 | if (request->ctx) |
1957 | i915_gem_context_reference(request->ctx); |
1960 | i915_gem_context_reference(request->ctx); |
1958 | } |
1961 | } |
1959 | 1962 | ||
1960 | request->emitted_jiffies = jiffies; |
1963 | request->emitted_jiffies = jiffies; |
1961 | list_add_tail(&request->list, &ring->request_list); |
1964 | list_add_tail(&request->list, &ring->request_list); |
1962 | request->file_priv = NULL; |
1965 | request->file_priv = NULL; |
1963 | 1966 | ||
1964 | if (file) { |
1967 | if (file) { |
1965 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1968 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1966 | 1969 | ||
1967 | spin_lock(&file_priv->mm.lock); |
1970 | spin_lock(&file_priv->mm.lock); |
1968 | request->file_priv = file_priv; |
1971 | request->file_priv = file_priv; |
1969 | list_add_tail(&request->client_list, |
1972 | list_add_tail(&request->client_list, |
1970 | &file_priv->mm.request_list); |
1973 | &file_priv->mm.request_list); |
1971 | spin_unlock(&file_priv->mm.lock); |
1974 | spin_unlock(&file_priv->mm.lock); |
1972 | } |
1975 | } |
1973 | 1976 | ||
1974 | trace_i915_gem_request_add(ring, request->seqno); |
1977 | trace_i915_gem_request_add(ring, request->seqno); |
1975 | ring->outstanding_lazy_seqno = 0; |
1978 | ring->outstanding_lazy_seqno = 0; |
1976 | ring->preallocated_lazy_request = NULL; |
1979 | ring->preallocated_lazy_request = NULL; |
1977 | 1980 | ||
1978 | // i915_queue_hangcheck(ring->dev); |
1981 | // i915_queue_hangcheck(ring->dev); |
1979 | 1982 | ||
1980 | queue_delayed_work(dev_priv->wq, |
1983 | queue_delayed_work(dev_priv->wq, |
1981 | &dev_priv->mm.retire_work, |
1984 | &dev_priv->mm.retire_work, |
1982 | round_jiffies_up_relative(HZ)); |
1985 | round_jiffies_up_relative(HZ)); |
1983 | intel_mark_busy(dev_priv->dev); |
1986 | intel_mark_busy(dev_priv->dev); |
1984 | 1987 | ||
1985 | if (out_seqno) |
1988 | if (out_seqno) |
1986 | *out_seqno = request->seqno; |
1989 | *out_seqno = request->seqno; |
1987 | return 0; |
1990 | return 0; |
1988 | } |
1991 | } |
1989 | 1992 | ||
1990 | static inline void |
1993 | static inline void |
1991 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
1994 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
1992 | { |
1995 | { |
1993 | struct drm_i915_file_private *file_priv = request->file_priv; |
1996 | struct drm_i915_file_private *file_priv = request->file_priv; |
1994 | 1997 | ||
1995 | if (!file_priv) |
1998 | if (!file_priv) |
1996 | return; |
1999 | return; |
1997 | 2000 | ||
1998 | spin_lock(&file_priv->mm.lock); |
2001 | spin_lock(&file_priv->mm.lock); |
1999 | list_del(&request->client_list); |
2002 | list_del(&request->client_list); |
2000 | request->file_priv = NULL; |
2003 | request->file_priv = NULL; |
2001 | spin_unlock(&file_priv->mm.lock); |
2004 | spin_unlock(&file_priv->mm.lock); |
2002 | } |
2005 | } |
2003 | 2006 | ||
2004 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
2007 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
2005 | const struct intel_context *ctx) |
2008 | const struct intel_context *ctx) |
2006 | { |
2009 | { |
2007 | unsigned long elapsed; |
2010 | unsigned long elapsed; |
2008 | 2011 | ||
2009 | elapsed = GetTimerTicks()/100 - ctx->hang_stats.guilty_ts; |
2012 | elapsed = GetTimerTicks()/100 - ctx->hang_stats.guilty_ts; |
2010 | 2013 | ||
2011 | if (ctx->hang_stats.banned) |
2014 | if (ctx->hang_stats.banned) |
2012 | return true; |
2015 | return true; |
2013 | 2016 | ||
2014 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
2017 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
2015 | if (!i915_gem_context_is_default(ctx)) { |
2018 | if (!i915_gem_context_is_default(ctx)) { |
2016 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2019 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2017 | return true; |
2020 | return true; |
2018 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2021 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2019 | if (i915_stop_ring_allow_warn(dev_priv)) |
2022 | if (i915_stop_ring_allow_warn(dev_priv)) |
2020 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
2023 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
2021 | return true; |
2024 | return true; |
2022 | } |
2025 | } |
2023 | } |
2026 | } |
2024 | 2027 | ||
2025 | return false; |
2028 | return false; |
2026 | } |
2029 | } |
2027 | 2030 | ||
2028 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2031 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
2029 | struct intel_context *ctx, |
2032 | struct intel_context *ctx, |
2030 | const bool guilty) |
2033 | const bool guilty) |
2031 | { |
2034 | { |
2032 | struct i915_ctx_hang_stats *hs; |
2035 | struct i915_ctx_hang_stats *hs; |
2033 | 2036 | ||
2034 | if (WARN_ON(!ctx)) |
2037 | if (WARN_ON(!ctx)) |
2035 | return; |
2038 | return; |
2036 | 2039 | ||
2037 | hs = &ctx->hang_stats; |
2040 | hs = &ctx->hang_stats; |
2038 | 2041 | ||
2039 | if (guilty) { |
2042 | if (guilty) { |
2040 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
2043 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
2041 | hs->batch_active++; |
2044 | hs->batch_active++; |
2042 | hs->guilty_ts = GetTimerTicks()/100; |
2045 | hs->guilty_ts = GetTimerTicks()/100; |
2043 | } else { |
2046 | } else { |
2044 | hs->batch_pending++; |
2047 | hs->batch_pending++; |
2045 | } |
2048 | } |
2046 | } |
2049 | } |
2047 | 2050 | ||
2048 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2051 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2049 | { |
2052 | { |
2050 | struct intel_context *ctx = request->ctx; |
2053 | struct intel_context *ctx = request->ctx; |
2051 | 2054 | ||
2052 | list_del(&request->list); |
2055 | list_del(&request->list); |
2053 | i915_gem_request_remove_from_client(request); |
2056 | i915_gem_request_remove_from_client(request); |
2054 | 2057 | ||
2055 | if (ctx) { |
2058 | if (ctx) { |
2056 | if (i915.enable_execlists) { |
2059 | if (i915.enable_execlists) { |
2057 | struct intel_engine_cs *ring = request->ring; |
2060 | struct intel_engine_cs *ring = request->ring; |
2058 | 2061 | ||
2059 | if (ctx != ring->default_context) |
2062 | if (ctx != ring->default_context) |
2060 | intel_lr_context_unpin(ring, ctx); |
2063 | intel_lr_context_unpin(ring, ctx); |
2061 | } |
2064 | } |
2062 | i915_gem_context_unreference(ctx); |
2065 | i915_gem_context_unreference(ctx); |
2063 | } |
2066 | } |
2064 | kfree(request); |
2067 | kfree(request); |
2065 | } |
2068 | } |
2066 | 2069 | ||
2067 | struct drm_i915_gem_request * |
2070 | struct drm_i915_gem_request * |
2068 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
2071 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
2069 | { |
2072 | { |
2070 | struct drm_i915_gem_request *request; |
2073 | struct drm_i915_gem_request *request; |
2071 | u32 completed_seqno; |
2074 | u32 completed_seqno; |
2072 | 2075 | ||
2073 | completed_seqno = ring->get_seqno(ring, false); |
2076 | completed_seqno = ring->get_seqno(ring, false); |
2074 | 2077 | ||
2075 | list_for_each_entry(request, &ring->request_list, list) { |
2078 | list_for_each_entry(request, &ring->request_list, list) { |
2076 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
2079 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
2077 | continue; |
2080 | continue; |
2078 | 2081 | ||
2079 | return request; |
2082 | return request; |
2080 | } |
2083 | } |
2081 | 2084 | ||
2082 | return NULL; |
2085 | return NULL; |
2083 | } |
2086 | } |
2084 | 2087 | ||
2085 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
2088 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
2086 | struct intel_engine_cs *ring) |
2089 | struct intel_engine_cs *ring) |
2087 | { |
2090 | { |
2088 | struct drm_i915_gem_request *request; |
2091 | struct drm_i915_gem_request *request; |
2089 | bool ring_hung; |
2092 | bool ring_hung; |
2090 | 2093 | ||
2091 | request = i915_gem_find_active_request(ring); |
2094 | request = i915_gem_find_active_request(ring); |
2092 | 2095 | ||
2093 | if (request == NULL) |
2096 | if (request == NULL) |
2094 | return; |
2097 | return; |
2095 | 2098 | ||
2096 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
2099 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
2097 | 2100 | ||
2098 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
2101 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
2099 | 2102 | ||
2100 | list_for_each_entry_continue(request, &ring->request_list, list) |
2103 | list_for_each_entry_continue(request, &ring->request_list, list) |
2101 | i915_set_reset_status(dev_priv, request->ctx, false); |
2104 | i915_set_reset_status(dev_priv, request->ctx, false); |
2102 | } |
2105 | } |
2103 | 2106 | ||
2104 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2107 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
2105 | struct intel_engine_cs *ring) |
2108 | struct intel_engine_cs *ring) |
2106 | { |
2109 | { |
2107 | while (!list_empty(&ring->active_list)) { |
2110 | while (!list_empty(&ring->active_list)) { |
2108 | struct drm_i915_gem_object *obj; |
2111 | struct drm_i915_gem_object *obj; |
2109 | 2112 | ||
2110 | obj = list_first_entry(&ring->active_list, |
2113 | obj = list_first_entry(&ring->active_list, |
2111 | struct drm_i915_gem_object, |
2114 | struct drm_i915_gem_object, |
2112 | ring_list); |
2115 | ring_list); |
2113 | 2116 | ||
2114 | i915_gem_object_move_to_inactive(obj); |
2117 | i915_gem_object_move_to_inactive(obj); |
2115 | } |
2118 | } |
2116 | 2119 | ||
2117 | /* |
2120 | /* |
2118 | * Clear the execlists queue up before freeing the requests, as those |
2121 | * Clear the execlists queue up before freeing the requests, as those |
2119 | * are the ones that keep the context and ringbuffer backing objects |
2122 | * are the ones that keep the context and ringbuffer backing objects |
2120 | * pinned in place. |
2123 | * pinned in place. |
2121 | */ |
2124 | */ |
2122 | while (!list_empty(&ring->execlist_queue)) { |
2125 | while (!list_empty(&ring->execlist_queue)) { |
2123 | struct intel_ctx_submit_request *submit_req; |
2126 | struct intel_ctx_submit_request *submit_req; |
2124 | 2127 | ||
2125 | submit_req = list_first_entry(&ring->execlist_queue, |
2128 | submit_req = list_first_entry(&ring->execlist_queue, |
2126 | struct intel_ctx_submit_request, |
2129 | struct intel_ctx_submit_request, |
2127 | execlist_link); |
2130 | execlist_link); |
2128 | list_del(&submit_req->execlist_link); |
2131 | list_del(&submit_req->execlist_link); |
2129 | intel_runtime_pm_put(dev_priv); |
2132 | intel_runtime_pm_put(dev_priv); |
2130 | i915_gem_context_unreference(submit_req->ctx); |
2133 | i915_gem_context_unreference(submit_req->ctx); |
2131 | kfree(submit_req); |
2134 | kfree(submit_req); |
2132 | } |
2135 | } |
2133 | 2136 | ||
2134 | /* |
2137 | /* |
2135 | * We must free the requests after all the corresponding objects have |
2138 | * We must free the requests after all the corresponding objects have |
2136 | * been moved off active lists. Which is the same order as the normal |
2139 | * been moved off active lists. Which is the same order as the normal |
2137 | * retire_requests function does. This is important if object hold |
2140 | * retire_requests function does. This is important if object hold |
2138 | * implicit references on things like e.g. ppgtt address spaces through |
2141 | * implicit references on things like e.g. ppgtt address spaces through |
2139 | * the request. |
2142 | * the request. |
2140 | */ |
2143 | */ |
2141 | while (!list_empty(&ring->request_list)) { |
2144 | while (!list_empty(&ring->request_list)) { |
2142 | struct drm_i915_gem_request *request; |
2145 | struct drm_i915_gem_request *request; |
2143 | 2146 | ||
2144 | request = list_first_entry(&ring->request_list, |
2147 | request = list_first_entry(&ring->request_list, |
2145 | struct drm_i915_gem_request, |
2148 | struct drm_i915_gem_request, |
2146 | list); |
2149 | list); |
2147 | 2150 | ||
2148 | i915_gem_free_request(request); |
2151 | i915_gem_free_request(request); |
2149 | } |
2152 | } |
2150 | 2153 | ||
2151 | /* These may not have been flush before the reset, do so now */ |
2154 | /* These may not have been flush before the reset, do so now */ |
2152 | kfree(ring->preallocated_lazy_request); |
2155 | kfree(ring->preallocated_lazy_request); |
2153 | ring->preallocated_lazy_request = NULL; |
2156 | ring->preallocated_lazy_request = NULL; |
2154 | ring->outstanding_lazy_seqno = 0; |
2157 | ring->outstanding_lazy_seqno = 0; |
2155 | } |
2158 | } |
2156 | 2159 | ||
2157 | void i915_gem_restore_fences(struct drm_device *dev) |
2160 | void i915_gem_restore_fences(struct drm_device *dev) |
2158 | { |
2161 | { |
2159 | struct drm_i915_private *dev_priv = dev->dev_private; |
2162 | struct drm_i915_private *dev_priv = dev->dev_private; |
2160 | int i; |
2163 | int i; |
2161 | 2164 | ||
2162 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
2165 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
2163 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
2166 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
2164 | 2167 | ||
2165 | /* |
2168 | /* |
2166 | * Commit delayed tiling changes if we have an object still |
2169 | * Commit delayed tiling changes if we have an object still |
2167 | * attached to the fence, otherwise just clear the fence. |
2170 | * attached to the fence, otherwise just clear the fence. |
2168 | */ |
2171 | */ |
2169 | if (reg->obj) { |
2172 | if (reg->obj) { |
2170 | i915_gem_object_update_fence(reg->obj, reg, |
2173 | i915_gem_object_update_fence(reg->obj, reg, |
2171 | reg->obj->tiling_mode); |
2174 | reg->obj->tiling_mode); |
2172 | } else { |
2175 | } else { |
2173 | i915_gem_write_fence(dev, i, NULL); |
2176 | i915_gem_write_fence(dev, i, NULL); |
2174 | } |
2177 | } |
2175 | } |
2178 | } |
2176 | } |
2179 | } |
2177 | 2180 | ||
2178 | void i915_gem_reset(struct drm_device *dev) |
2181 | void i915_gem_reset(struct drm_device *dev) |
2179 | { |
2182 | { |
2180 | struct drm_i915_private *dev_priv = dev->dev_private; |
2183 | struct drm_i915_private *dev_priv = dev->dev_private; |
2181 | struct intel_engine_cs *ring; |
2184 | struct intel_engine_cs *ring; |
2182 | int i; |
2185 | int i; |
2183 | 2186 | ||
2184 | /* |
2187 | /* |
2185 | * Before we free the objects from the requests, we need to inspect |
2188 | * Before we free the objects from the requests, we need to inspect |
2186 | * them for finding the guilty party. As the requests only borrow |
2189 | * them for finding the guilty party. As the requests only borrow |
2187 | * their reference to the objects, the inspection must be done first. |
2190 | * their reference to the objects, the inspection must be done first. |
2188 | */ |
2191 | */ |
2189 | for_each_ring(ring, dev_priv, i) |
2192 | for_each_ring(ring, dev_priv, i) |
2190 | i915_gem_reset_ring_status(dev_priv, ring); |
2193 | i915_gem_reset_ring_status(dev_priv, ring); |
2191 | 2194 | ||
2192 | for_each_ring(ring, dev_priv, i) |
2195 | for_each_ring(ring, dev_priv, i) |
2193 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
2196 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
2194 | 2197 | ||
2195 | i915_gem_context_reset(dev); |
2198 | i915_gem_context_reset(dev); |
2196 | 2199 | ||
2197 | i915_gem_restore_fences(dev); |
2200 | i915_gem_restore_fences(dev); |
2198 | } |
2201 | } |
2199 | 2202 | ||
2200 | /** |
2203 | /** |
2201 | * This function clears the request list as sequence numbers are passed. |
2204 | * This function clears the request list as sequence numbers are passed. |
2202 | */ |
2205 | */ |
2203 | void |
2206 | void |
2204 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
2207 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
2205 | { |
2208 | { |
2206 | uint32_t seqno; |
2209 | uint32_t seqno; |
2207 | 2210 | ||
2208 | if (list_empty(&ring->request_list)) |
2211 | if (list_empty(&ring->request_list)) |
2209 | return; |
2212 | return; |
2210 | 2213 | ||
2211 | WARN_ON(i915_verify_lists(ring->dev)); |
2214 | WARN_ON(i915_verify_lists(ring->dev)); |
2212 | 2215 | ||
2213 | seqno = ring->get_seqno(ring, true); |
2216 | seqno = ring->get_seqno(ring, true); |
2214 | 2217 | ||
2215 | /* Move any buffers on the active list that are no longer referenced |
2218 | /* Move any buffers on the active list that are no longer referenced |
2216 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
2219 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
2217 | * before we free the context associated with the requests. |
2220 | * before we free the context associated with the requests. |
2218 | */ |
2221 | */ |
2219 | while (!list_empty(&ring->active_list)) { |
2222 | while (!list_empty(&ring->active_list)) { |
2220 | struct drm_i915_gem_object *obj; |
2223 | struct drm_i915_gem_object *obj; |
2221 | 2224 | ||
2222 | obj = list_first_entry(&ring->active_list, |
2225 | obj = list_first_entry(&ring->active_list, |
2223 | struct drm_i915_gem_object, |
2226 | struct drm_i915_gem_object, |
2224 | ring_list); |
2227 | ring_list); |
2225 | 2228 | ||
2226 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
2229 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
2227 | break; |
2230 | break; |
2228 | 2231 | ||
2229 | i915_gem_object_move_to_inactive(obj); |
2232 | i915_gem_object_move_to_inactive(obj); |
2230 | } |
2233 | } |
2231 | 2234 | ||
2232 | 2235 | ||
2233 | while (!list_empty(&ring->request_list)) { |
2236 | while (!list_empty(&ring->request_list)) { |
2234 | struct drm_i915_gem_request *request; |
2237 | struct drm_i915_gem_request *request; |
2235 | struct intel_ringbuffer *ringbuf; |
2238 | struct intel_ringbuffer *ringbuf; |
2236 | 2239 | ||
2237 | request = list_first_entry(&ring->request_list, |
2240 | request = list_first_entry(&ring->request_list, |
2238 | struct drm_i915_gem_request, |
2241 | struct drm_i915_gem_request, |
2239 | list); |
2242 | list); |
2240 | 2243 | ||
2241 | if (!i915_seqno_passed(seqno, request->seqno)) |
2244 | if (!i915_seqno_passed(seqno, request->seqno)) |
2242 | break; |
2245 | break; |
2243 | 2246 | ||
2244 | trace_i915_gem_request_retire(ring, request->seqno); |
2247 | trace_i915_gem_request_retire(ring, request->seqno); |
2245 | 2248 | ||
2246 | /* This is one of the few common intersection points |
2249 | /* This is one of the few common intersection points |
2247 | * between legacy ringbuffer submission and execlists: |
2250 | * between legacy ringbuffer submission and execlists: |
2248 | * we need to tell them apart in order to find the correct |
2251 | * we need to tell them apart in order to find the correct |
2249 | * ringbuffer to which the request belongs to. |
2252 | * ringbuffer to which the request belongs to. |
2250 | */ |
2253 | */ |
2251 | if (i915.enable_execlists) { |
2254 | if (i915.enable_execlists) { |
2252 | struct intel_context *ctx = request->ctx; |
2255 | struct intel_context *ctx = request->ctx; |
2253 | ringbuf = ctx->engine[ring->id].ringbuf; |
2256 | ringbuf = ctx->engine[ring->id].ringbuf; |
2254 | } else |
2257 | } else |
2255 | ringbuf = ring->buffer; |
2258 | ringbuf = ring->buffer; |
2256 | 2259 | ||
2257 | /* We know the GPU must have read the request to have |
2260 | /* We know the GPU must have read the request to have |
2258 | * sent us the seqno + interrupt, so use the position |
2261 | * sent us the seqno + interrupt, so use the position |
2259 | * of tail of the request to update the last known position |
2262 | * of tail of the request to update the last known position |
2260 | * of the GPU head. |
2263 | * of the GPU head. |
2261 | */ |
2264 | */ |
2262 | ringbuf->last_retired_head = request->tail; |
2265 | ringbuf->last_retired_head = request->tail; |
2263 | 2266 | ||
2264 | i915_gem_free_request(request); |
2267 | i915_gem_free_request(request); |
2265 | } |
2268 | } |
2266 | 2269 | ||
2267 | if (unlikely(ring->trace_irq_seqno && |
2270 | if (unlikely(ring->trace_irq_seqno && |
2268 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
2271 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
2269 | ring->irq_put(ring); |
2272 | ring->irq_put(ring); |
2270 | ring->trace_irq_seqno = 0; |
2273 | ring->trace_irq_seqno = 0; |
2271 | } |
2274 | } |
2272 | 2275 | ||
2273 | WARN_ON(i915_verify_lists(ring->dev)); |
2276 | WARN_ON(i915_verify_lists(ring->dev)); |
2274 | } |
2277 | } |
2275 | 2278 | ||
2276 | bool |
2279 | bool |
2277 | i915_gem_retire_requests(struct drm_device *dev) |
2280 | i915_gem_retire_requests(struct drm_device *dev) |
2278 | { |
2281 | { |
2279 | struct drm_i915_private *dev_priv = dev->dev_private; |
2282 | struct drm_i915_private *dev_priv = dev->dev_private; |
2280 | struct intel_engine_cs *ring; |
2283 | struct intel_engine_cs *ring; |
2281 | bool idle = true; |
2284 | bool idle = true; |
2282 | int i; |
2285 | int i; |
2283 | 2286 | ||
2284 | for_each_ring(ring, dev_priv, i) { |
2287 | for_each_ring(ring, dev_priv, i) { |
2285 | i915_gem_retire_requests_ring(ring); |
2288 | i915_gem_retire_requests_ring(ring); |
2286 | idle &= list_empty(&ring->request_list); |
2289 | idle &= list_empty(&ring->request_list); |
2287 | if (i915.enable_execlists) { |
2290 | if (i915.enable_execlists) { |
2288 | unsigned long flags; |
2291 | unsigned long flags; |
2289 | 2292 | ||
2290 | spin_lock_irqsave(&ring->execlist_lock, flags); |
2293 | spin_lock_irqsave(&ring->execlist_lock, flags); |
2291 | idle &= list_empty(&ring->execlist_queue); |
2294 | idle &= list_empty(&ring->execlist_queue); |
2292 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2295 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2293 | 2296 | ||
2294 | intel_execlists_retire_requests(ring); |
2297 | intel_execlists_retire_requests(ring); |
2295 | } |
2298 | } |
2296 | } |
2299 | } |
2297 | 2300 | ||
2298 | if (idle) |
2301 | if (idle) |
2299 | mod_delayed_work(dev_priv->wq, |
2302 | mod_delayed_work(dev_priv->wq, |
2300 | &dev_priv->mm.idle_work, |
2303 | &dev_priv->mm.idle_work, |
2301 | msecs_to_jiffies(100)); |
2304 | msecs_to_jiffies(100)); |
2302 | 2305 | ||
2303 | return idle; |
2306 | return idle; |
2304 | } |
2307 | } |
2305 | 2308 | ||
2306 | static void |
2309 | static void |
2307 | i915_gem_retire_work_handler(struct work_struct *work) |
2310 | i915_gem_retire_work_handler(struct work_struct *work) |
2308 | { |
2311 | { |
2309 | struct drm_i915_private *dev_priv = |
2312 | struct drm_i915_private *dev_priv = |
2310 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
2313 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
2311 | struct drm_device *dev = dev_priv->dev; |
2314 | struct drm_device *dev = dev_priv->dev; |
2312 | bool idle; |
2315 | bool idle; |
2313 | 2316 | ||
2314 | /* Come back later if the device is busy... */ |
2317 | /* Come back later if the device is busy... */ |
2315 | idle = false; |
2318 | idle = false; |
2316 | if (mutex_trylock(&dev->struct_mutex)) { |
2319 | if (mutex_trylock(&dev->struct_mutex)) { |
2317 | idle = i915_gem_retire_requests(dev); |
2320 | idle = i915_gem_retire_requests(dev); |
2318 | mutex_unlock(&dev->struct_mutex); |
2321 | mutex_unlock(&dev->struct_mutex); |
2319 | } |
2322 | } |
2320 | if (!idle) |
2323 | if (!idle) |
2321 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2324 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2322 | round_jiffies_up_relative(HZ)); |
2325 | round_jiffies_up_relative(HZ)); |
2323 | } |
2326 | } |
2324 | 2327 | ||
2325 | static void |
2328 | static void |
2326 | i915_gem_idle_work_handler(struct work_struct *work) |
2329 | i915_gem_idle_work_handler(struct work_struct *work) |
2327 | { |
2330 | { |
2328 | struct drm_i915_private *dev_priv = |
2331 | struct drm_i915_private *dev_priv = |
2329 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
2332 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
2330 | 2333 | ||
2331 | intel_mark_idle(dev_priv->dev); |
2334 | intel_mark_idle(dev_priv->dev); |
2332 | } |
2335 | } |
2333 | 2336 | ||
2334 | /** |
2337 | /** |
2335 | * Ensures that an object will eventually get non-busy by flushing any required |
2338 | * Ensures that an object will eventually get non-busy by flushing any required |
2336 | * write domains, emitting any outstanding lazy request and retiring and |
2339 | * write domains, emitting any outstanding lazy request and retiring and |
2337 | * completed requests. |
2340 | * completed requests. |
2338 | */ |
2341 | */ |
2339 | static int |
2342 | static int |
2340 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
2343 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
2341 | { |
2344 | { |
2342 | int ret; |
2345 | int ret; |
2343 | 2346 | ||
2344 | if (obj->active) { |
2347 | if (obj->active) { |
2345 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
2348 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
2346 | if (ret) |
2349 | if (ret) |
2347 | return ret; |
2350 | return ret; |
2348 | 2351 | ||
2349 | i915_gem_retire_requests_ring(obj->ring); |
2352 | i915_gem_retire_requests_ring(obj->ring); |
2350 | } |
2353 | } |
2351 | 2354 | ||
2352 | return 0; |
2355 | return 0; |
2353 | } |
2356 | } |
2354 | 2357 | ||
2355 | /** |
2358 | /** |
2356 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
2359 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
2357 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
2360 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
2358 | * |
2361 | * |
2359 | * Returns 0 if successful, else an error is returned with the remaining time in |
2362 | * Returns 0 if successful, else an error is returned with the remaining time in |
2360 | * the timeout parameter. |
2363 | * the timeout parameter. |
2361 | * -ETIME: object is still busy after timeout |
2364 | * -ETIME: object is still busy after timeout |
2362 | * -ERESTARTSYS: signal interrupted the wait |
2365 | * -ERESTARTSYS: signal interrupted the wait |
2363 | * -ENONENT: object doesn't exist |
2366 | * -ENONENT: object doesn't exist |
2364 | * Also possible, but rare: |
2367 | * Also possible, but rare: |
2365 | * -EAGAIN: GPU wedged |
2368 | * -EAGAIN: GPU wedged |
2366 | * -ENOMEM: damn |
2369 | * -ENOMEM: damn |
2367 | * -ENODEV: Internal IRQ fail |
2370 | * -ENODEV: Internal IRQ fail |
2368 | * -E?: The add request failed |
2371 | * -E?: The add request failed |
2369 | * |
2372 | * |
2370 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
2373 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
2371 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
2374 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
2372 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
2375 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
2373 | * without holding struct_mutex the object may become re-busied before this |
2376 | * without holding struct_mutex the object may become re-busied before this |
2374 | * function completes. A similar but shorter * race condition exists in the busy |
2377 | * function completes. A similar but shorter * race condition exists in the busy |
2375 | * ioctl |
2378 | * ioctl |
2376 | */ |
2379 | */ |
2377 | int |
2380 | int |
2378 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
2381 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
2379 | { |
2382 | { |
2380 | struct drm_i915_private *dev_priv = dev->dev_private; |
2383 | struct drm_i915_private *dev_priv = dev->dev_private; |
2381 | struct drm_i915_gem_wait *args = data; |
2384 | struct drm_i915_gem_wait *args = data; |
2382 | struct drm_i915_gem_object *obj; |
2385 | struct drm_i915_gem_object *obj; |
2383 | struct intel_engine_cs *ring = NULL; |
2386 | struct intel_engine_cs *ring = NULL; |
2384 | unsigned reset_counter; |
2387 | unsigned reset_counter; |
2385 | u32 seqno = 0; |
2388 | u32 seqno = 0; |
2386 | int ret = 0; |
2389 | int ret = 0; |
2387 | 2390 | ||
2388 | if (args->flags != 0) |
2391 | if (args->flags != 0) |
2389 | return -EINVAL; |
2392 | return -EINVAL; |
2390 | 2393 | ||
2391 | ret = i915_mutex_lock_interruptible(dev); |
2394 | ret = i915_mutex_lock_interruptible(dev); |
2392 | if (ret) |
2395 | if (ret) |
2393 | return ret; |
2396 | return ret; |
2394 | 2397 | ||
2395 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
2398 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
2396 | if (&obj->base == NULL) { |
2399 | if (&obj->base == NULL) { |
2397 | mutex_unlock(&dev->struct_mutex); |
2400 | mutex_unlock(&dev->struct_mutex); |
2398 | return -ENOENT; |
2401 | return -ENOENT; |
2399 | } |
2402 | } |
2400 | 2403 | ||
2401 | /* Need to make sure the object gets inactive eventually. */ |
2404 | /* Need to make sure the object gets inactive eventually. */ |
2402 | ret = i915_gem_object_flush_active(obj); |
2405 | ret = i915_gem_object_flush_active(obj); |
2403 | if (ret) |
2406 | if (ret) |
2404 | goto out; |
2407 | goto out; |
2405 | 2408 | ||
2406 | if (obj->active) { |
2409 | if (obj->active) { |
2407 | seqno = obj->last_read_seqno; |
2410 | seqno = obj->last_read_seqno; |
2408 | ring = obj->ring; |
2411 | ring = obj->ring; |
2409 | } |
2412 | } |
2410 | 2413 | ||
2411 | if (seqno == 0) |
2414 | if (seqno == 0) |
2412 | goto out; |
2415 | goto out; |
2413 | 2416 | ||
2414 | /* Do this after OLR check to make sure we make forward progress polling |
2417 | /* Do this after OLR check to make sure we make forward progress polling |
2415 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
2418 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
2416 | */ |
2419 | */ |
2417 | if (args->timeout_ns <= 0) { |
2420 | if (args->timeout_ns <= 0) { |
2418 | ret = -ETIME; |
2421 | ret = -ETIME; |
2419 | goto out; |
2422 | goto out; |
2420 | } |
2423 | } |
2421 | 2424 | ||
2422 | drm_gem_object_unreference(&obj->base); |
2425 | drm_gem_object_unreference(&obj->base); |
2423 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
2426 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
2424 | mutex_unlock(&dev->struct_mutex); |
2427 | mutex_unlock(&dev->struct_mutex); |
2425 | 2428 | ||
2426 | return __i915_wait_seqno(ring, seqno, reset_counter, true, |
2429 | return __i915_wait_seqno(ring, seqno, reset_counter, true, |
2427 | &args->timeout_ns, file->driver_priv); |
2430 | &args->timeout_ns, file->driver_priv); |
2428 | 2431 | ||
2429 | out: |
2432 | out: |
2430 | drm_gem_object_unreference(&obj->base); |
2433 | drm_gem_object_unreference(&obj->base); |
2431 | mutex_unlock(&dev->struct_mutex); |
2434 | mutex_unlock(&dev->struct_mutex); |
2432 | return ret; |
2435 | return ret; |
2433 | } |
2436 | } |
2434 | 2437 | ||
2435 | /** |
2438 | /** |
2436 | * i915_gem_object_sync - sync an object to a ring. |
2439 | * i915_gem_object_sync - sync an object to a ring. |
2437 | * |
2440 | * |
2438 | * @obj: object which may be in use on another ring. |
2441 | * @obj: object which may be in use on another ring. |
2439 | * @to: ring we wish to use the object on. May be NULL. |
2442 | * @to: ring we wish to use the object on. May be NULL. |
2440 | * |
2443 | * |
2441 | * This code is meant to abstract object synchronization with the GPU. |
2444 | * This code is meant to abstract object synchronization with the GPU. |
2442 | * Calling with NULL implies synchronizing the object with the CPU |
2445 | * Calling with NULL implies synchronizing the object with the CPU |
2443 | * rather than a particular GPU ring. |
2446 | * rather than a particular GPU ring. |
2444 | * |
2447 | * |
2445 | * Returns 0 if successful, else propagates up the lower layer error. |
2448 | * Returns 0 if successful, else propagates up the lower layer error. |
2446 | */ |
2449 | */ |
2447 | int |
2450 | int |
2448 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2451 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2449 | struct intel_engine_cs *to) |
2452 | struct intel_engine_cs *to) |
2450 | { |
2453 | { |
2451 | struct intel_engine_cs *from = obj->ring; |
2454 | struct intel_engine_cs *from = obj->ring; |
2452 | u32 seqno; |
2455 | u32 seqno; |
2453 | int ret, idx; |
2456 | int ret, idx; |
2454 | 2457 | ||
2455 | if (from == NULL || to == from) |
2458 | if (from == NULL || to == from) |
2456 | return 0; |
2459 | return 0; |
2457 | 2460 | ||
2458 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2461 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2459 | return i915_gem_object_wait_rendering(obj, false); |
2462 | return i915_gem_object_wait_rendering(obj, false); |
2460 | 2463 | ||
2461 | idx = intel_ring_sync_index(from, to); |
2464 | idx = intel_ring_sync_index(from, to); |
2462 | 2465 | ||
2463 | seqno = obj->last_read_seqno; |
2466 | seqno = obj->last_read_seqno; |
2464 | /* Optimization: Avoid semaphore sync when we are sure we already |
2467 | /* Optimization: Avoid semaphore sync when we are sure we already |
2465 | * waited for an object with higher seqno */ |
2468 | * waited for an object with higher seqno */ |
2466 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2469 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2467 | return 0; |
2470 | return 0; |
2468 | 2471 | ||
2469 | ret = i915_gem_check_olr(obj->ring, seqno); |
2472 | ret = i915_gem_check_olr(obj->ring, seqno); |
2470 | if (ret) |
2473 | if (ret) |
2471 | return ret; |
2474 | return ret; |
2472 | 2475 | ||
2473 | trace_i915_gem_ring_sync_to(from, to, seqno); |
2476 | trace_i915_gem_ring_sync_to(from, to, seqno); |
2474 | ret = to->semaphore.sync_to(to, from, seqno); |
2477 | ret = to->semaphore.sync_to(to, from, seqno); |
2475 | if (!ret) |
2478 | if (!ret) |
2476 | /* We use last_read_seqno because sync_to() |
2479 | /* We use last_read_seqno because sync_to() |
2477 | * might have just caused seqno wrap under |
2480 | * might have just caused seqno wrap under |
2478 | * the radar. |
2481 | * the radar. |
2479 | */ |
2482 | */ |
2480 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2483 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
2481 | 2484 | ||
2482 | return ret; |
2485 | return ret; |
2483 | } |
2486 | } |
2484 | 2487 | ||
2485 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2488 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2486 | { |
2489 | { |
2487 | u32 old_write_domain, old_read_domains; |
2490 | u32 old_write_domain, old_read_domains; |
2488 | 2491 | ||
2489 | /* Force a pagefault for domain tracking on next user access */ |
2492 | /* Force a pagefault for domain tracking on next user access */ |
2490 | // i915_gem_release_mmap(obj); |
2493 | // i915_gem_release_mmap(obj); |
2491 | 2494 | ||
2492 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2495 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2493 | return; |
2496 | return; |
2494 | 2497 | ||
2495 | /* Wait for any direct GTT access to complete */ |
2498 | /* Wait for any direct GTT access to complete */ |
2496 | mb(); |
2499 | mb(); |
2497 | 2500 | ||
2498 | old_read_domains = obj->base.read_domains; |
2501 | old_read_domains = obj->base.read_domains; |
2499 | old_write_domain = obj->base.write_domain; |
2502 | old_write_domain = obj->base.write_domain; |
2500 | 2503 | ||
2501 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
2504 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
2502 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
2505 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
2503 | 2506 | ||
2504 | trace_i915_gem_object_change_domain(obj, |
2507 | trace_i915_gem_object_change_domain(obj, |
2505 | old_read_domains, |
2508 | old_read_domains, |
2506 | old_write_domain); |
2509 | old_write_domain); |
2507 | } |
2510 | } |
2508 | 2511 | ||
2509 | int i915_vma_unbind(struct i915_vma *vma) |
2512 | int i915_vma_unbind(struct i915_vma *vma) |
2510 | { |
2513 | { |
2511 | struct drm_i915_gem_object *obj = vma->obj; |
2514 | struct drm_i915_gem_object *obj = vma->obj; |
2512 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2515 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2513 | int ret; |
2516 | int ret; |
2514 | - | ||
2515 | if(obj == get_fb_obj()) |
2517 | if(obj == get_fb_obj()) |
- | 2518 | { |
|
- | 2519 | WARN(1,"attempt to unbind fb object\n"); |
|
2516 | return 0; |
2520 | return 0; |
- | 2521 | }; |
|
2517 | 2522 | ||
2518 | if (list_empty(&vma->vma_link)) |
2523 | if (list_empty(&vma->vma_link)) |
2519 | return 0; |
2524 | return 0; |
2520 | 2525 | ||
2521 | if (!drm_mm_node_allocated(&vma->node)) { |
2526 | if (!drm_mm_node_allocated(&vma->node)) { |
2522 | i915_gem_vma_destroy(vma); |
2527 | i915_gem_vma_destroy(vma); |
2523 | return 0; |
2528 | return 0; |
2524 | } |
2529 | } |
2525 | 2530 | ||
2526 | if (vma->pin_count) |
2531 | if (vma->pin_count) |
2527 | return -EBUSY; |
2532 | return -EBUSY; |
2528 | 2533 | ||
2529 | BUG_ON(obj->pages == NULL); |
2534 | BUG_ON(obj->pages == NULL); |
2530 | 2535 | ||
2531 | ret = i915_gem_object_finish_gpu(obj); |
2536 | ret = i915_gem_object_finish_gpu(obj); |
2532 | if (ret) |
2537 | if (ret) |
2533 | return ret; |
2538 | return ret; |
2534 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2539 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2535 | * should be safe and we need to cleanup or else we might |
2540 | * should be safe and we need to cleanup or else we might |
2536 | * cause memory corruption through use-after-free. |
2541 | * cause memory corruption through use-after-free. |
2537 | */ |
2542 | */ |
2538 | 2543 | ||
2539 | /* Throw away the active reference before moving to the unbound list */ |
2544 | /* Throw away the active reference before moving to the unbound list */ |
2540 | i915_gem_object_retire(obj); |
2545 | i915_gem_object_retire(obj); |
2541 | 2546 | ||
2542 | if (i915_is_ggtt(vma->vm)) { |
2547 | if (i915_is_ggtt(vma->vm)) { |
2543 | i915_gem_object_finish_gtt(obj); |
2548 | i915_gem_object_finish_gtt(obj); |
2544 | 2549 | ||
2545 | /* release the fence reg _after_ flushing */ |
2550 | /* release the fence reg _after_ flushing */ |
2546 | ret = i915_gem_object_put_fence(obj); |
2551 | ret = i915_gem_object_put_fence(obj); |
2547 | if (ret) |
2552 | if (ret) |
2548 | return ret; |
2553 | return ret; |
2549 | } |
2554 | } |
2550 | 2555 | ||
2551 | trace_i915_vma_unbind(vma); |
2556 | trace_i915_vma_unbind(vma); |
2552 | 2557 | ||
2553 | vma->unbind_vma(vma); |
2558 | vma->unbind_vma(vma); |
2554 | 2559 | ||
2555 | list_del_init(&vma->mm_list); |
2560 | list_del_init(&vma->mm_list); |
2556 | if (i915_is_ggtt(vma->vm)) |
2561 | if (i915_is_ggtt(vma->vm)) |
2557 | obj->map_and_fenceable = false; |
2562 | obj->map_and_fenceable = false; |
2558 | 2563 | ||
2559 | drm_mm_remove_node(&vma->node); |
2564 | drm_mm_remove_node(&vma->node); |
2560 | i915_gem_vma_destroy(vma); |
2565 | i915_gem_vma_destroy(vma); |
2561 | 2566 | ||
2562 | /* Since the unbound list is global, only move to that list if |
2567 | /* Since the unbound list is global, only move to that list if |
2563 | * no more VMAs exist. */ |
2568 | * no more VMAs exist. */ |
2564 | if (list_empty(&obj->vma_list)) { |
2569 | if (list_empty(&obj->vma_list)) { |
2565 | i915_gem_gtt_finish_object(obj); |
2570 | i915_gem_gtt_finish_object(obj); |
2566 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
2571 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
2567 | } |
2572 | } |
2568 | 2573 | ||
2569 | /* And finally now the object is completely decoupled from this vma, |
2574 | /* And finally now the object is completely decoupled from this vma, |
2570 | * we can drop its hold on the backing storage and allow it to be |
2575 | * we can drop its hold on the backing storage and allow it to be |
2571 | * reaped by the shrinker. |
2576 | * reaped by the shrinker. |
2572 | */ |
2577 | */ |
2573 | i915_gem_object_unpin_pages(obj); |
2578 | i915_gem_object_unpin_pages(obj); |
2574 | 2579 | ||
2575 | return 0; |
2580 | return 0; |
2576 | } |
2581 | } |
2577 | 2582 | ||
2578 | int i915_gpu_idle(struct drm_device *dev) |
2583 | int i915_gpu_idle(struct drm_device *dev) |
2579 | { |
2584 | { |
2580 | struct drm_i915_private *dev_priv = dev->dev_private; |
2585 | struct drm_i915_private *dev_priv = dev->dev_private; |
2581 | struct intel_engine_cs *ring; |
2586 | struct intel_engine_cs *ring; |
2582 | int ret, i; |
2587 | int ret, i; |
2583 | 2588 | ||
2584 | /* Flush everything onto the inactive list. */ |
2589 | /* Flush everything onto the inactive list. */ |
2585 | for_each_ring(ring, dev_priv, i) { |
2590 | for_each_ring(ring, dev_priv, i) { |
2586 | if (!i915.enable_execlists) { |
2591 | if (!i915.enable_execlists) { |
2587 | ret = i915_switch_context(ring, ring->default_context); |
2592 | ret = i915_switch_context(ring, ring->default_context); |
2588 | if (ret) |
2593 | if (ret) |
2589 | return ret; |
2594 | return ret; |
2590 | } |
2595 | } |
2591 | 2596 | ||
2592 | ret = intel_ring_idle(ring); |
2597 | ret = intel_ring_idle(ring); |
2593 | if (ret) |
2598 | if (ret) |
2594 | return ret; |
2599 | return ret; |
2595 | } |
2600 | } |
2596 | 2601 | ||
2597 | return 0; |
2602 | return 0; |
2598 | } |
2603 | } |
2599 | 2604 | ||
2600 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2605 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2601 | struct drm_i915_gem_object *obj) |
2606 | struct drm_i915_gem_object *obj) |
2602 | { |
2607 | { |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; |
2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
2604 | int fence_reg; |
2609 | int fence_reg; |
2605 | int fence_pitch_shift; |
2610 | int fence_pitch_shift; |
2606 | 2611 | ||
2607 | if (INTEL_INFO(dev)->gen >= 6) { |
2612 | if (INTEL_INFO(dev)->gen >= 6) { |
2608 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
2613 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
2609 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2614 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2610 | } else { |
2615 | } else { |
2611 | fence_reg = FENCE_REG_965_0; |
2616 | fence_reg = FENCE_REG_965_0; |
2612 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
2617 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
2613 | } |
2618 | } |
2614 | 2619 | ||
2615 | fence_reg += reg * 8; |
2620 | fence_reg += reg * 8; |
2616 | 2621 | ||
2617 | /* To w/a incoherency with non-atomic 64-bit register updates, |
2622 | /* To w/a incoherency with non-atomic 64-bit register updates, |
2618 | * we split the 64-bit update into two 32-bit writes. In order |
2623 | * we split the 64-bit update into two 32-bit writes. In order |
2619 | * for a partial fence not to be evaluated between writes, we |
2624 | * for a partial fence not to be evaluated between writes, we |
2620 | * precede the update with write to turn off the fence register, |
2625 | * precede the update with write to turn off the fence register, |
2621 | * and only enable the fence as the last step. |
2626 | * and only enable the fence as the last step. |
2622 | * |
2627 | * |
2623 | * For extra levels of paranoia, we make sure each step lands |
2628 | * For extra levels of paranoia, we make sure each step lands |
2624 | * before applying the next step. |
2629 | * before applying the next step. |
2625 | */ |
2630 | */ |
2626 | I915_WRITE(fence_reg, 0); |
2631 | I915_WRITE(fence_reg, 0); |
2627 | POSTING_READ(fence_reg); |
2632 | POSTING_READ(fence_reg); |
2628 | 2633 | ||
2629 | if (obj) { |
2634 | if (obj) { |
2630 | u32 size = i915_gem_obj_ggtt_size(obj); |
2635 | u32 size = i915_gem_obj_ggtt_size(obj); |
2631 | uint64_t val; |
2636 | uint64_t val; |
2632 | 2637 | ||
2633 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
2638 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
2634 | 0xfffff000) << 32; |
2639 | 0xfffff000) << 32; |
2635 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
2640 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
2636 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
2641 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
2637 | if (obj->tiling_mode == I915_TILING_Y) |
2642 | if (obj->tiling_mode == I915_TILING_Y) |
2638 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2643 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2639 | val |= I965_FENCE_REG_VALID; |
2644 | val |= I965_FENCE_REG_VALID; |
2640 | 2645 | ||
2641 | I915_WRITE(fence_reg + 4, val >> 32); |
2646 | I915_WRITE(fence_reg + 4, val >> 32); |
2642 | POSTING_READ(fence_reg + 4); |
2647 | POSTING_READ(fence_reg + 4); |
2643 | 2648 | ||
2644 | I915_WRITE(fence_reg + 0, val); |
2649 | I915_WRITE(fence_reg + 0, val); |
2645 | POSTING_READ(fence_reg); |
2650 | POSTING_READ(fence_reg); |
2646 | } else { |
2651 | } else { |
2647 | I915_WRITE(fence_reg + 4, 0); |
2652 | I915_WRITE(fence_reg + 4, 0); |
2648 | POSTING_READ(fence_reg + 4); |
2653 | POSTING_READ(fence_reg + 4); |
2649 | } |
2654 | } |
2650 | } |
2655 | } |
2651 | 2656 | ||
2652 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2657 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2653 | struct drm_i915_gem_object *obj) |
2658 | struct drm_i915_gem_object *obj) |
2654 | { |
2659 | { |
2655 | struct drm_i915_private *dev_priv = dev->dev_private; |
2660 | struct drm_i915_private *dev_priv = dev->dev_private; |
2656 | u32 val; |
2661 | u32 val; |
2657 | 2662 | ||
2658 | if (obj) { |
2663 | if (obj) { |
2659 | u32 size = i915_gem_obj_ggtt_size(obj); |
2664 | u32 size = i915_gem_obj_ggtt_size(obj); |
2660 | int pitch_val; |
2665 | int pitch_val; |
2661 | int tile_width; |
2666 | int tile_width; |
2662 | 2667 | ||
2663 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
2668 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
2664 | (size & -size) != size || |
2669 | (size & -size) != size || |
2665 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2670 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2666 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
2671 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
2667 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
2672 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
2668 | 2673 | ||
2669 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2674 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2670 | tile_width = 128; |
2675 | tile_width = 128; |
2671 | else |
2676 | else |
2672 | tile_width = 512; |
2677 | tile_width = 512; |
2673 | 2678 | ||
2674 | /* Note: pitch better be a power of two tile widths */ |
2679 | /* Note: pitch better be a power of two tile widths */ |
2675 | pitch_val = obj->stride / tile_width; |
2680 | pitch_val = obj->stride / tile_width; |
2676 | pitch_val = ffs(pitch_val) - 1; |
2681 | pitch_val = ffs(pitch_val) - 1; |
2677 | 2682 | ||
2678 | val = i915_gem_obj_ggtt_offset(obj); |
2683 | val = i915_gem_obj_ggtt_offset(obj); |
2679 | if (obj->tiling_mode == I915_TILING_Y) |
2684 | if (obj->tiling_mode == I915_TILING_Y) |
2680 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2685 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2681 | val |= I915_FENCE_SIZE_BITS(size); |
2686 | val |= I915_FENCE_SIZE_BITS(size); |
2682 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2687 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2683 | val |= I830_FENCE_REG_VALID; |
2688 | val |= I830_FENCE_REG_VALID; |
2684 | } else |
2689 | } else |
2685 | val = 0; |
2690 | val = 0; |
2686 | 2691 | ||
2687 | if (reg < 8) |
2692 | if (reg < 8) |
2688 | reg = FENCE_REG_830_0 + reg * 4; |
2693 | reg = FENCE_REG_830_0 + reg * 4; |
2689 | else |
2694 | else |
2690 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
2695 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
2691 | 2696 | ||
2692 | I915_WRITE(reg, val); |
2697 | I915_WRITE(reg, val); |
2693 | POSTING_READ(reg); |
2698 | POSTING_READ(reg); |
2694 | } |
2699 | } |
2695 | 2700 | ||
2696 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2701 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2697 | struct drm_i915_gem_object *obj) |
2702 | struct drm_i915_gem_object *obj) |
2698 | { |
2703 | { |
2699 | struct drm_i915_private *dev_priv = dev->dev_private; |
2704 | struct drm_i915_private *dev_priv = dev->dev_private; |
2700 | uint32_t val; |
2705 | uint32_t val; |
2701 | 2706 | ||
2702 | if (obj) { |
2707 | if (obj) { |
2703 | u32 size = i915_gem_obj_ggtt_size(obj); |
2708 | u32 size = i915_gem_obj_ggtt_size(obj); |
2704 | uint32_t pitch_val; |
2709 | uint32_t pitch_val; |
2705 | 2710 | ||
2706 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
2711 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
2707 | (size & -size) != size || |
2712 | (size & -size) != size || |
2708 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2713 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2709 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
2714 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
2710 | i915_gem_obj_ggtt_offset(obj), size); |
2715 | i915_gem_obj_ggtt_offset(obj), size); |
2711 | 2716 | ||
2712 | pitch_val = obj->stride / 128; |
2717 | pitch_val = obj->stride / 128; |
2713 | pitch_val = ffs(pitch_val) - 1; |
2718 | pitch_val = ffs(pitch_val) - 1; |
2714 | 2719 | ||
2715 | val = i915_gem_obj_ggtt_offset(obj); |
2720 | val = i915_gem_obj_ggtt_offset(obj); |
2716 | if (obj->tiling_mode == I915_TILING_Y) |
2721 | if (obj->tiling_mode == I915_TILING_Y) |
2717 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2722 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
2718 | val |= I830_FENCE_SIZE_BITS(size); |
2723 | val |= I830_FENCE_SIZE_BITS(size); |
2719 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2724 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2720 | val |= I830_FENCE_REG_VALID; |
2725 | val |= I830_FENCE_REG_VALID; |
2721 | } else |
2726 | } else |
2722 | val = 0; |
2727 | val = 0; |
2723 | 2728 | ||
2724 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2729 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2725 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
2730 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
2726 | } |
2731 | } |
2727 | 2732 | ||
2728 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2733 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2729 | { |
2734 | { |
2730 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
2735 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
2731 | } |
2736 | } |
2732 | 2737 | ||
2733 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2738 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2734 | struct drm_i915_gem_object *obj) |
2739 | struct drm_i915_gem_object *obj) |
2735 | { |
2740 | { |
2736 | struct drm_i915_private *dev_priv = dev->dev_private; |
2741 | struct drm_i915_private *dev_priv = dev->dev_private; |
2737 | 2742 | ||
2738 | /* Ensure that all CPU reads are completed before installing a fence |
2743 | /* Ensure that all CPU reads are completed before installing a fence |
2739 | * and all writes before removing the fence. |
2744 | * and all writes before removing the fence. |
2740 | */ |
2745 | */ |
2741 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
2746 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
2742 | mb(); |
2747 | mb(); |
2743 | 2748 | ||
2744 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2749 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2745 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
2750 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
2746 | obj->stride, obj->tiling_mode); |
2751 | obj->stride, obj->tiling_mode); |
2747 | 2752 | ||
2748 | switch (INTEL_INFO(dev)->gen) { |
2753 | switch (INTEL_INFO(dev)->gen) { |
2749 | case 9: |
2754 | case 9: |
2750 | case 8: |
2755 | case 8: |
2751 | case 7: |
2756 | case 7: |
2752 | case 6: |
2757 | case 6: |
2753 | case 5: |
2758 | case 5: |
2754 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
2759 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
2755 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
2760 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
2756 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
2761 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
2757 | default: BUG(); |
2762 | default: BUG(); |
2758 | } |
2763 | } |
2759 | 2764 | ||
2760 | /* And similarly be paranoid that no direct access to this region |
2765 | /* And similarly be paranoid that no direct access to this region |
2761 | * is reordered to before the fence is installed. |
2766 | * is reordered to before the fence is installed. |
2762 | */ |
2767 | */ |
2763 | if (i915_gem_object_needs_mb(obj)) |
2768 | if (i915_gem_object_needs_mb(obj)) |
2764 | mb(); |
2769 | mb(); |
2765 | } |
2770 | } |
2766 | 2771 | ||
2767 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2772 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2768 | struct drm_i915_fence_reg *fence) |
2773 | struct drm_i915_fence_reg *fence) |
2769 | { |
2774 | { |
2770 | return fence - dev_priv->fence_regs; |
2775 | return fence - dev_priv->fence_regs; |
2771 | } |
2776 | } |
2772 | 2777 | ||
2773 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2778 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2774 | struct drm_i915_fence_reg *fence, |
2779 | struct drm_i915_fence_reg *fence, |
2775 | bool enable) |
2780 | bool enable) |
2776 | { |
2781 | { |
2777 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2782 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2778 | int reg = fence_number(dev_priv, fence); |
2783 | int reg = fence_number(dev_priv, fence); |
2779 | 2784 | ||
2780 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
2785 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
2781 | 2786 | ||
2782 | if (enable) { |
2787 | if (enable) { |
2783 | obj->fence_reg = reg; |
2788 | obj->fence_reg = reg; |
2784 | fence->obj = obj; |
2789 | fence->obj = obj; |
2785 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
2790 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
2786 | } else { |
2791 | } else { |
2787 | obj->fence_reg = I915_FENCE_REG_NONE; |
2792 | obj->fence_reg = I915_FENCE_REG_NONE; |
2788 | fence->obj = NULL; |
2793 | fence->obj = NULL; |
2789 | list_del_init(&fence->lru_list); |
2794 | list_del_init(&fence->lru_list); |
2790 | } |
2795 | } |
2791 | obj->fence_dirty = false; |
2796 | obj->fence_dirty = false; |
2792 | } |
2797 | } |
2793 | 2798 | ||
2794 | static int |
2799 | static int |
2795 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
2800 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
2796 | { |
2801 | { |
2797 | if (obj->last_fenced_seqno) { |
2802 | if (obj->last_fenced_seqno) { |
2798 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
2803 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
2799 | if (ret) |
2804 | if (ret) |
2800 | return ret; |
2805 | return ret; |
2801 | 2806 | ||
2802 | obj->last_fenced_seqno = 0; |
2807 | obj->last_fenced_seqno = 0; |
2803 | } |
2808 | } |
2804 | 2809 | ||
2805 | return 0; |
2810 | return 0; |
2806 | } |
2811 | } |
2807 | 2812 | ||
2808 | int |
2813 | int |
2809 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
2814 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
2810 | { |
2815 | { |
2811 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2816 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2812 | struct drm_i915_fence_reg *fence; |
2817 | struct drm_i915_fence_reg *fence; |
2813 | int ret; |
2818 | int ret; |
2814 | 2819 | ||
2815 | ret = i915_gem_object_wait_fence(obj); |
2820 | ret = i915_gem_object_wait_fence(obj); |
2816 | if (ret) |
2821 | if (ret) |
2817 | return ret; |
2822 | return ret; |
2818 | 2823 | ||
2819 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2824 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2820 | return 0; |
2825 | return 0; |
2821 | 2826 | ||
2822 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2827 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2823 | 2828 | ||
2824 | if (WARN_ON(fence->pin_count)) |
2829 | if (WARN_ON(fence->pin_count)) |
2825 | return -EBUSY; |
2830 | return -EBUSY; |
2826 | 2831 | ||
2827 | i915_gem_object_fence_lost(obj); |
2832 | i915_gem_object_fence_lost(obj); |
2828 | i915_gem_object_update_fence(obj, fence, false); |
2833 | i915_gem_object_update_fence(obj, fence, false); |
2829 | 2834 | ||
2830 | return 0; |
2835 | return 0; |
2831 | } |
2836 | } |
2832 | 2837 | ||
2833 | static struct drm_i915_fence_reg * |
2838 | static struct drm_i915_fence_reg * |
2834 | i915_find_fence_reg(struct drm_device *dev) |
2839 | i915_find_fence_reg(struct drm_device *dev) |
2835 | { |
2840 | { |
2836 | struct drm_i915_private *dev_priv = dev->dev_private; |
2841 | struct drm_i915_private *dev_priv = dev->dev_private; |
2837 | struct drm_i915_fence_reg *reg, *avail; |
2842 | struct drm_i915_fence_reg *reg, *avail; |
2838 | int i; |
2843 | int i; |
2839 | 2844 | ||
2840 | /* First try to find a free reg */ |
2845 | /* First try to find a free reg */ |
2841 | avail = NULL; |
2846 | avail = NULL; |
2842 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2847 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2843 | reg = &dev_priv->fence_regs[i]; |
2848 | reg = &dev_priv->fence_regs[i]; |
2844 | if (!reg->obj) |
2849 | if (!reg->obj) |
2845 | return reg; |
2850 | return reg; |
2846 | 2851 | ||
2847 | if (!reg->pin_count) |
2852 | if (!reg->pin_count) |
2848 | avail = reg; |
2853 | avail = reg; |
2849 | } |
2854 | } |
2850 | 2855 | ||
2851 | if (avail == NULL) |
2856 | if (avail == NULL) |
2852 | goto deadlock; |
2857 | goto deadlock; |
2853 | 2858 | ||
2854 | /* None available, try to steal one or wait for a user to finish */ |
2859 | /* None available, try to steal one or wait for a user to finish */ |
2855 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
2860 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
2856 | if (reg->pin_count) |
2861 | if (reg->pin_count) |
2857 | continue; |
2862 | continue; |
2858 | 2863 | ||
2859 | return reg; |
2864 | return reg; |
2860 | } |
2865 | } |
2861 | 2866 | ||
2862 | deadlock: |
2867 | deadlock: |
2863 | /* Wait for completion of pending flips which consume fences */ |
2868 | /* Wait for completion of pending flips which consume fences */ |
2864 | // if (intel_has_pending_fb_unpin(dev)) |
2869 | // if (intel_has_pending_fb_unpin(dev)) |
2865 | // return ERR_PTR(-EAGAIN); |
2870 | // return ERR_PTR(-EAGAIN); |
2866 | 2871 | ||
2867 | return ERR_PTR(-EDEADLK); |
2872 | return ERR_PTR(-EDEADLK); |
2868 | } |
2873 | } |
2869 | 2874 | ||
2870 | /** |
2875 | /** |
2871 | * i915_gem_object_get_fence - set up fencing for an object |
2876 | * i915_gem_object_get_fence - set up fencing for an object |
2872 | * @obj: object to map through a fence reg |
2877 | * @obj: object to map through a fence reg |
2873 | * |
2878 | * |
2874 | * When mapping objects through the GTT, userspace wants to be able to write |
2879 | * When mapping objects through the GTT, userspace wants to be able to write |
2875 | * to them without having to worry about swizzling if the object is tiled. |
2880 | * to them without having to worry about swizzling if the object is tiled. |
2876 | * This function walks the fence regs looking for a free one for @obj, |
2881 | * This function walks the fence regs looking for a free one for @obj, |
2877 | * stealing one if it can't find any. |
2882 | * stealing one if it can't find any. |
2878 | * |
2883 | * |
2879 | * It then sets up the reg based on the object's properties: address, pitch |
2884 | * It then sets up the reg based on the object's properties: address, pitch |
2880 | * and tiling format. |
2885 | * and tiling format. |
2881 | * |
2886 | * |
2882 | * For an untiled surface, this removes any existing fence. |
2887 | * For an untiled surface, this removes any existing fence. |
2883 | */ |
2888 | */ |
2884 | int |
2889 | int |
2885 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
2890 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
2886 | { |
2891 | { |
2887 | struct drm_device *dev = obj->base.dev; |
2892 | struct drm_device *dev = obj->base.dev; |
2888 | struct drm_i915_private *dev_priv = dev->dev_private; |
2893 | struct drm_i915_private *dev_priv = dev->dev_private; |
2889 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
2894 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
2890 | struct drm_i915_fence_reg *reg; |
2895 | struct drm_i915_fence_reg *reg; |
2891 | int ret; |
2896 | int ret; |
2892 | 2897 | ||
2893 | /* Have we updated the tiling parameters upon the object and so |
2898 | /* Have we updated the tiling parameters upon the object and so |
2894 | * will need to serialise the write to the associated fence register? |
2899 | * will need to serialise the write to the associated fence register? |
2895 | */ |
2900 | */ |
2896 | if (obj->fence_dirty) { |
2901 | if (obj->fence_dirty) { |
2897 | ret = i915_gem_object_wait_fence(obj); |
2902 | ret = i915_gem_object_wait_fence(obj); |
2898 | if (ret) |
2903 | if (ret) |
2899 | return ret; |
2904 | return ret; |
2900 | } |
2905 | } |
2901 | 2906 | ||
2902 | /* Just update our place in the LRU if our fence is getting reused. */ |
2907 | /* Just update our place in the LRU if our fence is getting reused. */ |
2903 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2908 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2904 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
2909 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
2905 | if (!obj->fence_dirty) { |
2910 | if (!obj->fence_dirty) { |
2906 | list_move_tail(®->lru_list, |
2911 | list_move_tail(®->lru_list, |
2907 | &dev_priv->mm.fence_list); |
2912 | &dev_priv->mm.fence_list); |
2908 | return 0; |
2913 | return 0; |
2909 | } |
2914 | } |
2910 | } else if (enable) { |
2915 | } else if (enable) { |
2911 | if (WARN_ON(!obj->map_and_fenceable)) |
2916 | if (WARN_ON(!obj->map_and_fenceable)) |
2912 | return -EINVAL; |
2917 | return -EINVAL; |
2913 | 2918 | ||
2914 | reg = i915_find_fence_reg(dev); |
2919 | reg = i915_find_fence_reg(dev); |
2915 | if (IS_ERR(reg)) |
2920 | if (IS_ERR(reg)) |
2916 | return PTR_ERR(reg); |
2921 | return PTR_ERR(reg); |
2917 | 2922 | ||
2918 | if (reg->obj) { |
2923 | if (reg->obj) { |
2919 | struct drm_i915_gem_object *old = reg->obj; |
2924 | struct drm_i915_gem_object *old = reg->obj; |
2920 | 2925 | ||
2921 | ret = i915_gem_object_wait_fence(old); |
2926 | ret = i915_gem_object_wait_fence(old); |
2922 | if (ret) |
2927 | if (ret) |
2923 | return ret; |
2928 | return ret; |
2924 | 2929 | ||
2925 | i915_gem_object_fence_lost(old); |
2930 | i915_gem_object_fence_lost(old); |
2926 | } |
2931 | } |
2927 | } else |
2932 | } else |
2928 | return 0; |
2933 | return 0; |
2929 | 2934 | ||
2930 | i915_gem_object_update_fence(obj, reg, enable); |
2935 | i915_gem_object_update_fence(obj, reg, enable); |
2931 | 2936 | ||
2932 | return 0; |
2937 | return 0; |
2933 | } |
2938 | } |
2934 | 2939 | ||
2935 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
2940 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
2936 | unsigned long cache_level) |
2941 | unsigned long cache_level) |
2937 | { |
2942 | { |
2938 | struct drm_mm_node *gtt_space = &vma->node; |
2943 | struct drm_mm_node *gtt_space = &vma->node; |
2939 | struct drm_mm_node *other; |
2944 | struct drm_mm_node *other; |
2940 | 2945 | ||
2941 | /* |
2946 | /* |
2942 | * On some machines we have to be careful when putting differing types |
2947 | * On some machines we have to be careful when putting differing types |
2943 | * of snoopable memory together to avoid the prefetcher crossing memory |
2948 | * of snoopable memory together to avoid the prefetcher crossing memory |
2944 | * domains and dying. During vm initialisation, we decide whether or not |
2949 | * domains and dying. During vm initialisation, we decide whether or not |
2945 | * these constraints apply and set the drm_mm.color_adjust |
2950 | * these constraints apply and set the drm_mm.color_adjust |
2946 | * appropriately. |
2951 | * appropriately. |
2947 | */ |
2952 | */ |
2948 | if (vma->vm->mm.color_adjust == NULL) |
2953 | if (vma->vm->mm.color_adjust == NULL) |
2949 | return true; |
2954 | return true; |
2950 | 2955 | ||
2951 | if (!drm_mm_node_allocated(gtt_space)) |
2956 | if (!drm_mm_node_allocated(gtt_space)) |
2952 | return true; |
2957 | return true; |
2953 | 2958 | ||
2954 | if (list_empty(>t_space->node_list)) |
2959 | if (list_empty(>t_space->node_list)) |
2955 | return true; |
2960 | return true; |
2956 | 2961 | ||
2957 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
2962 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
2958 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
2963 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
2959 | return false; |
2964 | return false; |
2960 | 2965 | ||
2961 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
2966 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
2962 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
2967 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
2963 | return false; |
2968 | return false; |
2964 | 2969 | ||
2965 | return true; |
2970 | return true; |
2966 | } |
2971 | } |
2967 | 2972 | ||
2968 | /** |
2973 | /** |
2969 | * Finds free space in the GTT aperture and binds the object there. |
2974 | * Finds free space in the GTT aperture and binds the object there. |
2970 | */ |
2975 | */ |
2971 | static struct i915_vma * |
2976 | static struct i915_vma * |
2972 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
2977 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
2973 | struct i915_address_space *vm, |
2978 | struct i915_address_space *vm, |
2974 | unsigned alignment, |
2979 | unsigned alignment, |
2975 | uint64_t flags) |
2980 | uint64_t flags) |
2976 | { |
2981 | { |
2977 | struct drm_device *dev = obj->base.dev; |
2982 | struct drm_device *dev = obj->base.dev; |
2978 | struct drm_i915_private *dev_priv = dev->dev_private; |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; |
2979 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
2984 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
2980 | unsigned long start = |
2985 | unsigned long start = |
2981 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
2986 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
2982 | unsigned long end = |
2987 | unsigned long end = |
2983 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2988 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2984 | struct i915_vma *vma; |
2989 | struct i915_vma *vma; |
2985 | int ret; |
2990 | int ret; |
2986 | 2991 | ||
2987 | fence_size = i915_gem_get_gtt_size(dev, |
2992 | fence_size = i915_gem_get_gtt_size(dev, |
2988 | obj->base.size, |
2993 | obj->base.size, |
2989 | obj->tiling_mode); |
2994 | obj->tiling_mode); |
2990 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
2995 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
2991 | obj->base.size, |
2996 | obj->base.size, |
2992 | obj->tiling_mode, true); |
2997 | obj->tiling_mode, true); |
2993 | unfenced_alignment = |
2998 | unfenced_alignment = |
2994 | i915_gem_get_gtt_alignment(dev, |
2999 | i915_gem_get_gtt_alignment(dev, |
2995 | obj->base.size, |
3000 | obj->base.size, |
2996 | obj->tiling_mode, false); |
3001 | obj->tiling_mode, false); |
2997 | 3002 | ||
2998 | if (alignment == 0) |
3003 | if (alignment == 0) |
2999 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
3004 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
3000 | unfenced_alignment; |
3005 | unfenced_alignment; |
3001 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
3006 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
3002 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
3007 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
3003 | return ERR_PTR(-EINVAL); |
3008 | return ERR_PTR(-EINVAL); |
3004 | } |
3009 | } |
3005 | 3010 | ||
3006 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
3011 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
3007 | 3012 | ||
3008 | /* If the object is bigger than the entire aperture, reject it early |
3013 | /* If the object is bigger than the entire aperture, reject it early |
3009 | * before evicting everything in a vain attempt to find space. |
3014 | * before evicting everything in a vain attempt to find space. |
3010 | */ |
3015 | */ |
3011 | if (obj->base.size > end) { |
3016 | if (obj->base.size > end) { |
3012 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", |
3017 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", |
3013 | obj->base.size, |
3018 | obj->base.size, |
3014 | flags & PIN_MAPPABLE ? "mappable" : "total", |
3019 | flags & PIN_MAPPABLE ? "mappable" : "total", |
3015 | end); |
3020 | end); |
3016 | return ERR_PTR(-E2BIG); |
3021 | return ERR_PTR(-E2BIG); |
3017 | } |
3022 | } |
3018 | 3023 | ||
3019 | ret = i915_gem_object_get_pages(obj); |
3024 | ret = i915_gem_object_get_pages(obj); |
3020 | if (ret) |
3025 | if (ret) |
3021 | return ERR_PTR(ret); |
3026 | return ERR_PTR(ret); |
3022 | 3027 | ||
3023 | i915_gem_object_pin_pages(obj); |
3028 | i915_gem_object_pin_pages(obj); |
3024 | 3029 | ||
3025 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
3030 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
3026 | if (IS_ERR(vma)) |
3031 | if (IS_ERR(vma)) |
3027 | goto err_unpin; |
3032 | goto err_unpin; |
3028 | 3033 | ||
3029 | search_free: |
3034 | search_free: |
3030 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3035 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3031 | size, alignment, |
3036 | size, alignment, |
3032 | obj->cache_level, |
3037 | obj->cache_level, |
3033 | start, end, |
3038 | start, end, |
3034 | DRM_MM_SEARCH_DEFAULT, |
3039 | DRM_MM_SEARCH_DEFAULT, |
3035 | DRM_MM_CREATE_DEFAULT); |
3040 | DRM_MM_CREATE_DEFAULT); |
3036 | if (ret) { |
3041 | if (ret) { |
3037 | 3042 | ||
3038 | goto err_free_vma; |
3043 | goto err_free_vma; |
3039 | } |
3044 | } |
3040 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
3045 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
3041 | ret = -EINVAL; |
3046 | ret = -EINVAL; |
3042 | goto err_remove_node; |
3047 | goto err_remove_node; |
3043 | } |
3048 | } |
3044 | 3049 | ||
3045 | ret = i915_gem_gtt_prepare_object(obj); |
3050 | ret = i915_gem_gtt_prepare_object(obj); |
3046 | if (ret) |
3051 | if (ret) |
3047 | goto err_remove_node; |
3052 | goto err_remove_node; |
3048 | 3053 | ||
3049 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
3054 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
3050 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
3055 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
3051 | 3056 | ||
3052 | trace_i915_vma_bind(vma, flags); |
3057 | trace_i915_vma_bind(vma, flags); |
3053 | vma->bind_vma(vma, obj->cache_level, |
3058 | vma->bind_vma(vma, obj->cache_level, |
3054 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
3059 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
3055 | 3060 | ||
3056 | return vma; |
3061 | return vma; |
3057 | 3062 | ||
3058 | err_remove_node: |
3063 | err_remove_node: |
3059 | drm_mm_remove_node(&vma->node); |
3064 | drm_mm_remove_node(&vma->node); |
3060 | err_free_vma: |
3065 | err_free_vma: |
3061 | i915_gem_vma_destroy(vma); |
3066 | i915_gem_vma_destroy(vma); |
3062 | vma = ERR_PTR(ret); |
3067 | vma = ERR_PTR(ret); |
3063 | err_unpin: |
3068 | err_unpin: |
3064 | i915_gem_object_unpin_pages(obj); |
3069 | i915_gem_object_unpin_pages(obj); |
3065 | return vma; |
3070 | return vma; |
3066 | } |
3071 | } |
3067 | 3072 | ||
3068 | bool |
3073 | bool |
3069 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3074 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3070 | bool force) |
3075 | bool force) |
3071 | { |
3076 | { |
3072 | /* If we don't have a page list set up, then we're not pinned |
3077 | /* If we don't have a page list set up, then we're not pinned |
3073 | * to GPU, and we can ignore the cache flush because it'll happen |
3078 | * to GPU, and we can ignore the cache flush because it'll happen |
3074 | * again at bind time. |
3079 | * again at bind time. |
3075 | */ |
3080 | */ |
3076 | if (obj->pages == NULL) |
3081 | if (obj->pages == NULL) |
3077 | return false; |
3082 | return false; |
3078 | 3083 | ||
3079 | /* |
3084 | /* |
3080 | * Stolen memory is always coherent with the GPU as it is explicitly |
3085 | * Stolen memory is always coherent with the GPU as it is explicitly |
3081 | * marked as wc by the system, or the system is cache-coherent. |
3086 | * marked as wc by the system, or the system is cache-coherent. |
3082 | */ |
3087 | */ |
3083 | if (obj->stolen || obj->phys_handle) |
3088 | if (obj->stolen || obj->phys_handle) |
3084 | return false; |
3089 | return false; |
3085 | 3090 | ||
3086 | /* If the GPU is snooping the contents of the CPU cache, |
3091 | /* If the GPU is snooping the contents of the CPU cache, |
3087 | * we do not need to manually clear the CPU cache lines. However, |
3092 | * we do not need to manually clear the CPU cache lines. However, |
3088 | * the caches are only snooped when the render cache is |
3093 | * the caches are only snooped when the render cache is |
3089 | * flushed/invalidated. As we always have to emit invalidations |
3094 | * flushed/invalidated. As we always have to emit invalidations |
3090 | * and flushes when moving into and out of the RENDER domain, correct |
3095 | * and flushes when moving into and out of the RENDER domain, correct |
3091 | * snooping behaviour occurs naturally as the result of our domain |
3096 | * snooping behaviour occurs naturally as the result of our domain |
3092 | * tracking. |
3097 | * tracking. |
3093 | */ |
3098 | */ |
3094 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
3099 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
3095 | return false; |
3100 | return false; |
3096 | 3101 | ||
3097 | trace_i915_gem_object_clflush(obj); |
3102 | trace_i915_gem_object_clflush(obj); |
3098 | drm_clflush_sg(obj->pages); |
3103 | drm_clflush_sg(obj->pages); |
3099 | 3104 | ||
3100 | return true; |
3105 | return true; |
3101 | } |
3106 | } |
3102 | 3107 | ||
3103 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3108 | /** Flushes the GTT write domain for the object if it's dirty. */ |
3104 | static void |
3109 | static void |
3105 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
3110 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
3106 | { |
3111 | { |
3107 | uint32_t old_write_domain; |
3112 | uint32_t old_write_domain; |
3108 | 3113 | ||
3109 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
3114 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
3110 | return; |
3115 | return; |
3111 | 3116 | ||
3112 | /* No actual flushing is required for the GTT write domain. Writes |
3117 | /* No actual flushing is required for the GTT write domain. Writes |
3113 | * to it immediately go to main memory as far as we know, so there's |
3118 | * to it immediately go to main memory as far as we know, so there's |
3114 | * no chipset flush. It also doesn't land in render cache. |
3119 | * no chipset flush. It also doesn't land in render cache. |
3115 | * |
3120 | * |
3116 | * However, we do have to enforce the order so that all writes through |
3121 | * However, we do have to enforce the order so that all writes through |
3117 | * the GTT land before any writes to the device, such as updates to |
3122 | * the GTT land before any writes to the device, such as updates to |
3118 | * the GATT itself. |
3123 | * the GATT itself. |
3119 | */ |
3124 | */ |
3120 | wmb(); |
3125 | wmb(); |
3121 | 3126 | ||
3122 | old_write_domain = obj->base.write_domain; |
3127 | old_write_domain = obj->base.write_domain; |
3123 | obj->base.write_domain = 0; |
3128 | obj->base.write_domain = 0; |
3124 | 3129 | ||
3125 | intel_fb_obj_flush(obj, false); |
3130 | intel_fb_obj_flush(obj, false); |
3126 | 3131 | ||
3127 | trace_i915_gem_object_change_domain(obj, |
3132 | trace_i915_gem_object_change_domain(obj, |
3128 | obj->base.read_domains, |
3133 | obj->base.read_domains, |
3129 | old_write_domain); |
3134 | old_write_domain); |
3130 | } |
3135 | } |
3131 | 3136 | ||
3132 | /** Flushes the CPU write domain for the object if it's dirty. */ |
3137 | /** Flushes the CPU write domain for the object if it's dirty. */ |
3133 | static void |
3138 | static void |
3134 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3139 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3135 | bool force) |
3140 | bool force) |
3136 | { |
3141 | { |
3137 | uint32_t old_write_domain; |
3142 | uint32_t old_write_domain; |
3138 | 3143 | ||
3139 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
3144 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
3140 | return; |
3145 | return; |
3141 | 3146 | ||
3142 | if (i915_gem_clflush_object(obj, force)) |
3147 | if (i915_gem_clflush_object(obj, force)) |
3143 | i915_gem_chipset_flush(obj->base.dev); |
3148 | i915_gem_chipset_flush(obj->base.dev); |
3144 | 3149 | ||
3145 | old_write_domain = obj->base.write_domain; |
3150 | old_write_domain = obj->base.write_domain; |
3146 | obj->base.write_domain = 0; |
3151 | obj->base.write_domain = 0; |
3147 | 3152 | ||
3148 | intel_fb_obj_flush(obj, false); |
3153 | intel_fb_obj_flush(obj, false); |
3149 | 3154 | ||
3150 | trace_i915_gem_object_change_domain(obj, |
3155 | trace_i915_gem_object_change_domain(obj, |
3151 | obj->base.read_domains, |
3156 | obj->base.read_domains, |
3152 | old_write_domain); |
3157 | old_write_domain); |
3153 | } |
3158 | } |
3154 | 3159 | ||
3155 | /** |
3160 | /** |
3156 | * Moves a single object to the GTT read, and possibly write domain. |
3161 | * Moves a single object to the GTT read, and possibly write domain. |
3157 | * |
3162 | * |
3158 | * This function returns when the move is complete, including waiting on |
3163 | * This function returns when the move is complete, including waiting on |
3159 | * flushes to occur. |
3164 | * flushes to occur. |
3160 | */ |
3165 | */ |
3161 | int |
3166 | int |
3162 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
3167 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
3163 | { |
3168 | { |
3164 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3169 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3165 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
3170 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
3166 | uint32_t old_write_domain, old_read_domains; |
3171 | uint32_t old_write_domain, old_read_domains; |
3167 | int ret; |
3172 | int ret; |
3168 | 3173 | ||
3169 | /* Not valid to be called on unbound objects. */ |
3174 | /* Not valid to be called on unbound objects. */ |
3170 | if (vma == NULL) |
3175 | if (vma == NULL) |
3171 | return -EINVAL; |
3176 | return -EINVAL; |
3172 | 3177 | ||
3173 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3178 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3174 | return 0; |
3179 | return 0; |
3175 | 3180 | ||
3176 | ret = i915_gem_object_wait_rendering(obj, !write); |
3181 | ret = i915_gem_object_wait_rendering(obj, !write); |
3177 | if (ret) |
3182 | if (ret) |
3178 | return ret; |
3183 | return ret; |
3179 | 3184 | ||
3180 | i915_gem_object_retire(obj); |
3185 | i915_gem_object_retire(obj); |
3181 | i915_gem_object_flush_cpu_write_domain(obj, false); |
3186 | i915_gem_object_flush_cpu_write_domain(obj, false); |
3182 | 3187 | ||
3183 | /* Serialise direct access to this object with the barriers for |
3188 | /* Serialise direct access to this object with the barriers for |
3184 | * coherent writes from the GPU, by effectively invalidating the |
3189 | * coherent writes from the GPU, by effectively invalidating the |
3185 | * GTT domain upon first access. |
3190 | * GTT domain upon first access. |
3186 | */ |
3191 | */ |
3187 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3192 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3188 | mb(); |
3193 | mb(); |
3189 | 3194 | ||
3190 | old_write_domain = obj->base.write_domain; |
3195 | old_write_domain = obj->base.write_domain; |
3191 | old_read_domains = obj->base.read_domains; |
3196 | old_read_domains = obj->base.read_domains; |
3192 | 3197 | ||
3193 | /* It should now be out of any other write domains, and we can update |
3198 | /* It should now be out of any other write domains, and we can update |
3194 | * the domain values for our changes. |
3199 | * the domain values for our changes. |
3195 | */ |
3200 | */ |
3196 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3201 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3197 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3202 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3198 | if (write) { |
3203 | if (write) { |
3199 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3204 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3200 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
3205 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
3201 | obj->dirty = 1; |
3206 | obj->dirty = 1; |
3202 | } |
3207 | } |
3203 | 3208 | ||
3204 | if (write) |
3209 | if (write) |
3205 | intel_fb_obj_invalidate(obj, NULL); |
3210 | intel_fb_obj_invalidate(obj, NULL); |
3206 | 3211 | ||
3207 | trace_i915_gem_object_change_domain(obj, |
3212 | trace_i915_gem_object_change_domain(obj, |
3208 | old_read_domains, |
3213 | old_read_domains, |
3209 | old_write_domain); |
3214 | old_write_domain); |
3210 | 3215 | ||
3211 | /* And bump the LRU for this access */ |
3216 | /* And bump the LRU for this access */ |
3212 | if (i915_gem_object_is_inactive(obj)) |
3217 | if (i915_gem_object_is_inactive(obj)) |
3213 | list_move_tail(&vma->mm_list, |
3218 | list_move_tail(&vma->mm_list, |
3214 | &dev_priv->gtt.base.inactive_list); |
3219 | &dev_priv->gtt.base.inactive_list); |
3215 | 3220 | ||
3216 | return 0; |
3221 | return 0; |
3217 | } |
3222 | } |
3218 | 3223 | ||
3219 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3224 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3220 | enum i915_cache_level cache_level) |
3225 | enum i915_cache_level cache_level) |
3221 | { |
3226 | { |
3222 | struct drm_device *dev = obj->base.dev; |
3227 | struct drm_device *dev = obj->base.dev; |
3223 | struct i915_vma *vma, *next; |
3228 | struct i915_vma *vma, *next; |
3224 | int ret; |
3229 | int ret; |
3225 | 3230 | ||
3226 | if (obj->cache_level == cache_level) |
3231 | if (obj->cache_level == cache_level) |
3227 | return 0; |
3232 | return 0; |
3228 | 3233 | ||
3229 | if (i915_gem_obj_is_pinned(obj)) { |
3234 | if (i915_gem_obj_is_pinned(obj)) { |
3230 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3235 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3231 | return -EBUSY; |
3236 | return -EBUSY; |
3232 | } |
3237 | } |
3233 | 3238 | ||
3234 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3239 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
3235 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
3240 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
3236 | ret = i915_vma_unbind(vma); |
3241 | ret = i915_vma_unbind(vma); |
3237 | if (ret) |
3242 | if (ret) |
3238 | return ret; |
3243 | return ret; |
3239 | } |
3244 | } |
3240 | } |
3245 | } |
3241 | 3246 | ||
3242 | if (i915_gem_obj_bound_any(obj)) { |
3247 | if (i915_gem_obj_bound_any(obj)) { |
3243 | ret = i915_gem_object_finish_gpu(obj); |
3248 | ret = i915_gem_object_finish_gpu(obj); |
3244 | if (ret) |
3249 | if (ret) |
3245 | return ret; |
3250 | return ret; |
3246 | 3251 | ||
3247 | i915_gem_object_finish_gtt(obj); |
3252 | i915_gem_object_finish_gtt(obj); |
3248 | 3253 | ||
3249 | /* Before SandyBridge, you could not use tiling or fence |
3254 | /* Before SandyBridge, you could not use tiling or fence |
3250 | * registers with snooped memory, so relinquish any fences |
3255 | * registers with snooped memory, so relinquish any fences |
3251 | * currently pointing to our region in the aperture. |
3256 | * currently pointing to our region in the aperture. |
3252 | */ |
3257 | */ |
3253 | if (INTEL_INFO(dev)->gen < 6) { |
3258 | if (INTEL_INFO(dev)->gen < 6) { |
3254 | ret = i915_gem_object_put_fence(obj); |
3259 | ret = i915_gem_object_put_fence(obj); |
3255 | if (ret) |
3260 | if (ret) |
3256 | return ret; |
3261 | return ret; |
3257 | } |
3262 | } |
3258 | 3263 | ||
3259 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3264 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3260 | if (drm_mm_node_allocated(&vma->node)) |
3265 | if (drm_mm_node_allocated(&vma->node)) |
3261 | vma->bind_vma(vma, cache_level, |
3266 | vma->bind_vma(vma, cache_level, |
3262 | vma->bound & GLOBAL_BIND); |
3267 | vma->bound & GLOBAL_BIND); |
3263 | } |
3268 | } |
3264 | 3269 | ||
3265 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3270 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3266 | vma->node.color = cache_level; |
3271 | vma->node.color = cache_level; |
3267 | obj->cache_level = cache_level; |
3272 | obj->cache_level = cache_level; |
3268 | 3273 | ||
3269 | if (cpu_write_needs_clflush(obj)) { |
3274 | if (cpu_write_needs_clflush(obj)) { |
3270 | u32 old_read_domains, old_write_domain; |
3275 | u32 old_read_domains, old_write_domain; |
3271 | 3276 | ||
3272 | /* If we're coming from LLC cached, then we haven't |
3277 | /* If we're coming from LLC cached, then we haven't |
3273 | * actually been tracking whether the data is in the |
3278 | * actually been tracking whether the data is in the |
3274 | * CPU cache or not, since we only allow one bit set |
3279 | * CPU cache or not, since we only allow one bit set |
3275 | * in obj->write_domain and have been skipping the clflushes. |
3280 | * in obj->write_domain and have been skipping the clflushes. |
3276 | * Just set it to the CPU cache for now. |
3281 | * Just set it to the CPU cache for now. |
3277 | */ |
3282 | */ |
3278 | i915_gem_object_retire(obj); |
3283 | i915_gem_object_retire(obj); |
3279 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
3284 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
3280 | 3285 | ||
3281 | old_read_domains = obj->base.read_domains; |
3286 | old_read_domains = obj->base.read_domains; |
3282 | old_write_domain = obj->base.write_domain; |
3287 | old_write_domain = obj->base.write_domain; |
3283 | 3288 | ||
3284 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3289 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3285 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3290 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3286 | 3291 | ||
3287 | trace_i915_gem_object_change_domain(obj, |
3292 | trace_i915_gem_object_change_domain(obj, |
3288 | old_read_domains, |
3293 | old_read_domains, |
3289 | old_write_domain); |
3294 | old_write_domain); |
3290 | } |
3295 | } |
3291 | 3296 | ||
3292 | return 0; |
3297 | return 0; |
3293 | } |
3298 | } |
3294 | 3299 | ||
3295 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3300 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3296 | struct drm_file *file) |
3301 | struct drm_file *file) |
3297 | { |
3302 | { |
3298 | struct drm_i915_gem_caching *args = data; |
3303 | struct drm_i915_gem_caching *args = data; |
3299 | struct drm_i915_gem_object *obj; |
3304 | struct drm_i915_gem_object *obj; |
3300 | int ret; |
3305 | int ret; |
3301 | 3306 | ||
3302 | ret = i915_mutex_lock_interruptible(dev); |
3307 | ret = i915_mutex_lock_interruptible(dev); |
3303 | if (ret) |
3308 | if (ret) |
3304 | return ret; |
3309 | return ret; |
3305 | 3310 | ||
3306 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3311 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3307 | if (&obj->base == NULL) { |
3312 | if (&obj->base == NULL) { |
3308 | ret = -ENOENT; |
3313 | ret = -ENOENT; |
3309 | goto unlock; |
3314 | goto unlock; |
3310 | } |
3315 | } |
3311 | 3316 | ||
3312 | switch (obj->cache_level) { |
3317 | switch (obj->cache_level) { |
3313 | case I915_CACHE_LLC: |
3318 | case I915_CACHE_LLC: |
3314 | case I915_CACHE_L3_LLC: |
3319 | case I915_CACHE_L3_LLC: |
3315 | args->caching = I915_CACHING_CACHED; |
3320 | args->caching = I915_CACHING_CACHED; |
3316 | break; |
3321 | break; |
3317 | 3322 | ||
3318 | case I915_CACHE_WT: |
3323 | case I915_CACHE_WT: |
3319 | args->caching = I915_CACHING_DISPLAY; |
3324 | args->caching = I915_CACHING_DISPLAY; |
3320 | break; |
3325 | break; |
3321 | 3326 | ||
3322 | default: |
3327 | default: |
3323 | args->caching = I915_CACHING_NONE; |
3328 | args->caching = I915_CACHING_NONE; |
3324 | break; |
3329 | break; |
3325 | } |
3330 | } |
3326 | 3331 | ||
3327 | drm_gem_object_unreference(&obj->base); |
3332 | drm_gem_object_unreference(&obj->base); |
3328 | unlock: |
3333 | unlock: |
3329 | mutex_unlock(&dev->struct_mutex); |
3334 | mutex_unlock(&dev->struct_mutex); |
3330 | return ret; |
3335 | return ret; |
3331 | } |
3336 | } |
3332 | 3337 | ||
3333 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3338 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3334 | struct drm_file *file) |
3339 | struct drm_file *file) |
3335 | { |
3340 | { |
3336 | struct drm_i915_gem_caching *args = data; |
3341 | struct drm_i915_gem_caching *args = data; |
3337 | struct drm_i915_gem_object *obj; |
3342 | struct drm_i915_gem_object *obj; |
3338 | enum i915_cache_level level; |
3343 | enum i915_cache_level level; |
3339 | int ret; |
3344 | int ret; |
3340 | 3345 | ||
3341 | switch (args->caching) { |
3346 | switch (args->caching) { |
3342 | case I915_CACHING_NONE: |
3347 | case I915_CACHING_NONE: |
3343 | level = I915_CACHE_NONE; |
3348 | level = I915_CACHE_NONE; |
3344 | break; |
3349 | break; |
3345 | case I915_CACHING_CACHED: |
3350 | case I915_CACHING_CACHED: |
3346 | level = I915_CACHE_LLC; |
3351 | level = I915_CACHE_LLC; |
3347 | break; |
3352 | break; |
3348 | case I915_CACHING_DISPLAY: |
3353 | case I915_CACHING_DISPLAY: |
3349 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
3354 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
3350 | break; |
3355 | break; |
3351 | default: |
3356 | default: |
3352 | return -EINVAL; |
3357 | return -EINVAL; |
3353 | } |
3358 | } |
3354 | 3359 | ||
3355 | ret = i915_mutex_lock_interruptible(dev); |
3360 | ret = i915_mutex_lock_interruptible(dev); |
3356 | if (ret) |
3361 | if (ret) |
3357 | return ret; |
3362 | return ret; |
3358 | 3363 | ||
3359 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3364 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3360 | if (&obj->base == NULL) { |
3365 | if (&obj->base == NULL) { |
3361 | ret = -ENOENT; |
3366 | ret = -ENOENT; |
3362 | goto unlock; |
3367 | goto unlock; |
3363 | } |
3368 | } |
3364 | 3369 | ||
3365 | ret = i915_gem_object_set_cache_level(obj, level); |
3370 | ret = i915_gem_object_set_cache_level(obj, level); |
3366 | 3371 | ||
3367 | drm_gem_object_unreference(&obj->base); |
3372 | drm_gem_object_unreference(&obj->base); |
3368 | unlock: |
3373 | unlock: |
3369 | mutex_unlock(&dev->struct_mutex); |
3374 | mutex_unlock(&dev->struct_mutex); |
3370 | return ret; |
3375 | return ret; |
3371 | } |
3376 | } |
3372 | 3377 | ||
3373 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3378 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3374 | { |
3379 | { |
3375 | struct i915_vma *vma; |
3380 | struct i915_vma *vma; |
3376 | 3381 | ||
3377 | vma = i915_gem_obj_to_ggtt(obj); |
3382 | vma = i915_gem_obj_to_ggtt(obj); |
3378 | if (!vma) |
3383 | if (!vma) |
3379 | return false; |
3384 | return false; |
3380 | 3385 | ||
3381 | /* There are 3 sources that pin objects: |
3386 | /* There are 3 sources that pin objects: |
3382 | * 1. The display engine (scanouts, sprites, cursors); |
3387 | * 1. The display engine (scanouts, sprites, cursors); |
3383 | * 2. Reservations for execbuffer; |
3388 | * 2. Reservations for execbuffer; |
3384 | * 3. The user. |
3389 | * 3. The user. |
3385 | * |
3390 | * |
3386 | * We can ignore reservations as we hold the struct_mutex and |
3391 | * We can ignore reservations as we hold the struct_mutex and |
3387 | * are only called outside of the reservation path. The user |
3392 | * are only called outside of the reservation path. The user |
3388 | * can only increment pin_count once, and so if after |
3393 | * can only increment pin_count once, and so if after |
3389 | * subtracting the potential reference by the user, any pin_count |
3394 | * subtracting the potential reference by the user, any pin_count |
3390 | * remains, it must be due to another use by the display engine. |
3395 | * remains, it must be due to another use by the display engine. |
3391 | */ |
3396 | */ |
3392 | return vma->pin_count - !!obj->user_pin_count; |
3397 | return vma->pin_count - !!obj->user_pin_count; |
3393 | } |
3398 | } |
3394 | 3399 | ||
3395 | /* |
3400 | /* |
3396 | * Prepare buffer for display plane (scanout, cursors, etc). |
3401 | * Prepare buffer for display plane (scanout, cursors, etc). |
3397 | * Can be called from an uninterruptible phase (modesetting) and allows |
3402 | * Can be called from an uninterruptible phase (modesetting) and allows |
3398 | * any flushes to be pipelined (for pageflips). |
3403 | * any flushes to be pipelined (for pageflips). |
3399 | */ |
3404 | */ |
3400 | int |
3405 | int |
3401 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3406 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3402 | u32 alignment, |
3407 | u32 alignment, |
3403 | struct intel_engine_cs *pipelined) |
3408 | struct intel_engine_cs *pipelined) |
3404 | { |
3409 | { |
3405 | u32 old_read_domains, old_write_domain; |
3410 | u32 old_read_domains, old_write_domain; |
3406 | bool was_pin_display; |
3411 | bool was_pin_display; |
3407 | int ret; |
3412 | int ret; |
3408 | 3413 | ||
3409 | if (pipelined != obj->ring) { |
3414 | if (pipelined != obj->ring) { |
3410 | ret = i915_gem_object_sync(obj, pipelined); |
3415 | ret = i915_gem_object_sync(obj, pipelined); |
3411 | if (ret) |
3416 | if (ret) |
3412 | return ret; |
3417 | return ret; |
3413 | } |
3418 | } |
3414 | 3419 | ||
3415 | /* Mark the pin_display early so that we account for the |
3420 | /* Mark the pin_display early so that we account for the |
3416 | * display coherency whilst setting up the cache domains. |
3421 | * display coherency whilst setting up the cache domains. |
3417 | */ |
3422 | */ |
3418 | was_pin_display = obj->pin_display; |
3423 | was_pin_display = obj->pin_display; |
3419 | obj->pin_display = true; |
3424 | obj->pin_display = true; |
3420 | 3425 | ||
3421 | /* The display engine is not coherent with the LLC cache on gen6. As |
3426 | /* The display engine is not coherent with the LLC cache on gen6. As |
3422 | * a result, we make sure that the pinning that is about to occur is |
3427 | * a result, we make sure that the pinning that is about to occur is |
3423 | * done with uncached PTEs. This is lowest common denominator for all |
3428 | * done with uncached PTEs. This is lowest common denominator for all |
3424 | * chipsets. |
3429 | * chipsets. |
3425 | * |
3430 | * |
3426 | * However for gen6+, we could do better by using the GFDT bit instead |
3431 | * However for gen6+, we could do better by using the GFDT bit instead |
3427 | * of uncaching, which would allow us to flush all the LLC-cached data |
3432 | * of uncaching, which would allow us to flush all the LLC-cached data |
3428 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
3433 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
3429 | */ |
3434 | */ |
3430 | ret = i915_gem_object_set_cache_level(obj, |
3435 | ret = i915_gem_object_set_cache_level(obj, |
3431 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
3436 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
3432 | if (ret) |
3437 | if (ret) |
3433 | goto err_unpin_display; |
3438 | goto err_unpin_display; |
3434 | 3439 | ||
3435 | /* As the user may map the buffer once pinned in the display plane |
3440 | /* As the user may map the buffer once pinned in the display plane |
3436 | * (e.g. libkms for the bootup splash), we have to ensure that we |
3441 | * (e.g. libkms for the bootup splash), we have to ensure that we |
3437 | * always use map_and_fenceable for all scanout buffers. |
3442 | * always use map_and_fenceable for all scanout buffers. |
3438 | */ |
3443 | */ |
3439 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
3444 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
3440 | if (ret) |
3445 | if (ret) |
3441 | goto err_unpin_display; |
3446 | goto err_unpin_display; |
3442 | 3447 | ||
3443 | i915_gem_object_flush_cpu_write_domain(obj, true); |
3448 | i915_gem_object_flush_cpu_write_domain(obj, true); |
3444 | 3449 | ||
3445 | old_write_domain = obj->base.write_domain; |
3450 | old_write_domain = obj->base.write_domain; |
3446 | old_read_domains = obj->base.read_domains; |
3451 | old_read_domains = obj->base.read_domains; |
3447 | 3452 | ||
3448 | /* It should now be out of any other write domains, and we can update |
3453 | /* It should now be out of any other write domains, and we can update |
3449 | * the domain values for our changes. |
3454 | * the domain values for our changes. |
3450 | */ |
3455 | */ |
3451 | obj->base.write_domain = 0; |
3456 | obj->base.write_domain = 0; |
3452 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3457 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
3453 | 3458 | ||
3454 | trace_i915_gem_object_change_domain(obj, |
3459 | trace_i915_gem_object_change_domain(obj, |
3455 | old_read_domains, |
3460 | old_read_domains, |
3456 | old_write_domain); |
3461 | old_write_domain); |
3457 | 3462 | ||
3458 | return 0; |
3463 | return 0; |
3459 | 3464 | ||
3460 | err_unpin_display: |
3465 | err_unpin_display: |
3461 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3466 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3462 | obj->pin_display = was_pin_display; |
3467 | obj->pin_display = was_pin_display; |
3463 | return ret; |
3468 | return ret; |
3464 | } |
3469 | } |
3465 | 3470 | ||
3466 | void |
3471 | void |
3467 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
3472 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
3468 | { |
3473 | { |
3469 | i915_gem_object_ggtt_unpin(obj); |
3474 | i915_gem_object_ggtt_unpin(obj); |
3470 | obj->pin_display = is_pin_display(obj); |
3475 | obj->pin_display = is_pin_display(obj); |
3471 | } |
3476 | } |
3472 | 3477 | ||
3473 | int |
3478 | int |
3474 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
3479 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
3475 | { |
3480 | { |
3476 | int ret; |
3481 | int ret; |
3477 | 3482 | ||
3478 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
3483 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
3479 | return 0; |
3484 | return 0; |
3480 | 3485 | ||
3481 | ret = i915_gem_object_wait_rendering(obj, false); |
3486 | ret = i915_gem_object_wait_rendering(obj, false); |
3482 | if (ret) |
3487 | if (ret) |
3483 | return ret; |
3488 | return ret; |
3484 | 3489 | ||
3485 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3490 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3486 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
3491 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
3487 | return 0; |
3492 | return 0; |
3488 | } |
3493 | } |
3489 | 3494 | ||
3490 | /** |
3495 | /** |
3491 | * Moves a single object to the CPU read, and possibly write domain. |
3496 | * Moves a single object to the CPU read, and possibly write domain. |
3492 | * |
3497 | * |
3493 | * This function returns when the move is complete, including waiting on |
3498 | * This function returns when the move is complete, including waiting on |
3494 | * flushes to occur. |
3499 | * flushes to occur. |
3495 | */ |
3500 | */ |
3496 | int |
3501 | int |
3497 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
3502 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
3498 | { |
3503 | { |
3499 | uint32_t old_write_domain, old_read_domains; |
3504 | uint32_t old_write_domain, old_read_domains; |
3500 | int ret; |
3505 | int ret; |
3501 | 3506 | ||
3502 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3507 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3503 | return 0; |
3508 | return 0; |
3504 | 3509 | ||
3505 | ret = i915_gem_object_wait_rendering(obj, !write); |
3510 | ret = i915_gem_object_wait_rendering(obj, !write); |
3506 | if (ret) |
3511 | if (ret) |
3507 | return ret; |
3512 | return ret; |
3508 | 3513 | ||
3509 | i915_gem_object_retire(obj); |
3514 | i915_gem_object_retire(obj); |
3510 | i915_gem_object_flush_gtt_write_domain(obj); |
3515 | i915_gem_object_flush_gtt_write_domain(obj); |
3511 | 3516 | ||
3512 | old_write_domain = obj->base.write_domain; |
3517 | old_write_domain = obj->base.write_domain; |
3513 | old_read_domains = obj->base.read_domains; |
3518 | old_read_domains = obj->base.read_domains; |
3514 | 3519 | ||
3515 | /* Flush the CPU cache if it's still invalid. */ |
3520 | /* Flush the CPU cache if it's still invalid. */ |
3516 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
3521 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
3517 | i915_gem_clflush_object(obj, false); |
3522 | i915_gem_clflush_object(obj, false); |
3518 | 3523 | ||
3519 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
3524 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
3520 | } |
3525 | } |
3521 | 3526 | ||
3522 | /* It should now be out of any other write domains, and we can update |
3527 | /* It should now be out of any other write domains, and we can update |
3523 | * the domain values for our changes. |
3528 | * the domain values for our changes. |
3524 | */ |
3529 | */ |
3525 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3530 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3526 | 3531 | ||
3527 | /* If we're writing through the CPU, then the GPU read domains will |
3532 | /* If we're writing through the CPU, then the GPU read domains will |
3528 | * need to be invalidated at next use. |
3533 | * need to be invalidated at next use. |
3529 | */ |
3534 | */ |
3530 | if (write) { |
3535 | if (write) { |
3531 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3536 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3532 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3537 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3533 | } |
3538 | } |
3534 | 3539 | ||
3535 | if (write) |
3540 | if (write) |
3536 | intel_fb_obj_invalidate(obj, NULL); |
3541 | intel_fb_obj_invalidate(obj, NULL); |
3537 | 3542 | ||
3538 | trace_i915_gem_object_change_domain(obj, |
3543 | trace_i915_gem_object_change_domain(obj, |
3539 | old_read_domains, |
3544 | old_read_domains, |
3540 | old_write_domain); |
3545 | old_write_domain); |
3541 | 3546 | ||
3542 | return 0; |
3547 | return 0; |
3543 | } |
3548 | } |
3544 | 3549 | ||
3545 | /* Throttle our rendering by waiting until the ring has completed our requests |
3550 | /* Throttle our rendering by waiting until the ring has completed our requests |
3546 | * emitted over 20 msec ago. |
3551 | * emitted over 20 msec ago. |
3547 | * |
3552 | * |
3548 | * Note that if we were to use the current jiffies each time around the loop, |
3553 | * Note that if we were to use the current jiffies each time around the loop, |
3549 | * we wouldn't escape the function with any frames outstanding if the time to |
3554 | * we wouldn't escape the function with any frames outstanding if the time to |
3550 | * render a frame was over 20ms. |
3555 | * render a frame was over 20ms. |
3551 | * |
3556 | * |
3552 | * This should get us reasonable parallelism between CPU and GPU but also |
3557 | * This should get us reasonable parallelism between CPU and GPU but also |
3553 | * relatively low latency when blocking on a particular request to finish. |
3558 | * relatively low latency when blocking on a particular request to finish. |
3554 | */ |
3559 | */ |
3555 | static int |
3560 | static int |
3556 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
3561 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
3557 | { |
3562 | { |
3558 | struct drm_i915_private *dev_priv = dev->dev_private; |
3563 | struct drm_i915_private *dev_priv = dev->dev_private; |
3559 | struct drm_i915_file_private *file_priv = file->driver_priv; |
3564 | struct drm_i915_file_private *file_priv = file->driver_priv; |
3560 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
3565 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
3561 | struct drm_i915_gem_request *request; |
3566 | struct drm_i915_gem_request *request; |
3562 | struct intel_engine_cs *ring = NULL; |
3567 | struct intel_engine_cs *ring = NULL; |
3563 | unsigned reset_counter; |
3568 | unsigned reset_counter; |
3564 | u32 seqno = 0; |
3569 | u32 seqno = 0; |
3565 | int ret; |
3570 | int ret; |
3566 | 3571 | ||
3567 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3572 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3568 | if (ret) |
3573 | if (ret) |
3569 | return ret; |
3574 | return ret; |
3570 | 3575 | ||
3571 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
3576 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
3572 | if (ret) |
3577 | if (ret) |
3573 | return ret; |
3578 | return ret; |
3574 | 3579 | ||
3575 | spin_lock(&file_priv->mm.lock); |
3580 | spin_lock(&file_priv->mm.lock); |
3576 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
3581 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
3577 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3582 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3578 | break; |
3583 | break; |
3579 | 3584 | ||
3580 | ring = request->ring; |
3585 | ring = request->ring; |
3581 | seqno = request->seqno; |
3586 | seqno = request->seqno; |
3582 | } |
3587 | } |
3583 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3588 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3584 | spin_unlock(&file_priv->mm.lock); |
3589 | spin_unlock(&file_priv->mm.lock); |
3585 | 3590 | ||
3586 | if (seqno == 0) |
3591 | if (seqno == 0) |
3587 | return 0; |
3592 | return 0; |
3588 | 3593 | ||
3589 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
3594 | ret = __i915_wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
3590 | if (ret == 0) |
3595 | if (ret == 0) |
3591 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
3596 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
3592 | 3597 | ||
3593 | return ret; |
3598 | return ret; |
3594 | } |
3599 | } |
3595 | 3600 | ||
3596 | static bool |
3601 | static bool |
3597 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
3602 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
3598 | { |
3603 | { |
3599 | struct drm_i915_gem_object *obj = vma->obj; |
3604 | struct drm_i915_gem_object *obj = vma->obj; |
3600 | 3605 | ||
3601 | if (alignment && |
3606 | if (alignment && |
3602 | vma->node.start & (alignment - 1)) |
3607 | vma->node.start & (alignment - 1)) |
3603 | return true; |
3608 | return true; |
3604 | 3609 | ||
3605 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
3610 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
3606 | return true; |
3611 | return true; |
3607 | 3612 | ||
3608 | if (flags & PIN_OFFSET_BIAS && |
3613 | if (flags & PIN_OFFSET_BIAS && |
3609 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
3614 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
3610 | return true; |
3615 | return true; |
3611 | 3616 | ||
3612 | return false; |
3617 | return false; |
3613 | } |
3618 | } |
3614 | 3619 | ||
3615 | int |
3620 | int |
3616 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3621 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3617 | struct i915_address_space *vm, |
3622 | struct i915_address_space *vm, |
3618 | uint32_t alignment, |
3623 | uint32_t alignment, |
3619 | uint64_t flags) |
3624 | uint64_t flags) |
3620 | { |
3625 | { |
3621 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3626 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3622 | struct i915_vma *vma; |
3627 | struct i915_vma *vma; |
3623 | unsigned bound; |
3628 | unsigned bound; |
3624 | int ret; |
3629 | int ret; |
3625 | 3630 | ||
3626 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
3631 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
3627 | return -ENODEV; |
3632 | return -ENODEV; |
3628 | 3633 | ||
3629 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
3634 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
3630 | return -EINVAL; |
3635 | return -EINVAL; |
3631 | 3636 | ||
3632 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
3637 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
3633 | return -EINVAL; |
3638 | return -EINVAL; |
3634 | 3639 | ||
3635 | vma = i915_gem_obj_to_vma(obj, vm); |
3640 | vma = i915_gem_obj_to_vma(obj, vm); |
3636 | if (vma) { |
3641 | if (vma) { |
3637 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3642 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3638 | return -EBUSY; |
3643 | return -EBUSY; |
3639 | 3644 | ||
3640 | if (i915_vma_misplaced(vma, alignment, flags)) { |
3645 | if (i915_vma_misplaced(vma, alignment, flags)) { |
3641 | WARN(vma->pin_count, |
3646 | WARN(vma->pin_count, |
3642 | "bo is already pinned with incorrect alignment:" |
3647 | "bo is already pinned with incorrect alignment:" |
3643 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
3648 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
3644 | " obj->map_and_fenceable=%d\n", |
3649 | " obj->map_and_fenceable=%d\n", |
3645 | i915_gem_obj_offset(obj, vm), alignment, |
3650 | i915_gem_obj_offset(obj, vm), alignment, |
3646 | !!(flags & PIN_MAPPABLE), |
3651 | !!(flags & PIN_MAPPABLE), |
3647 | obj->map_and_fenceable); |
3652 | obj->map_and_fenceable); |
3648 | ret = i915_vma_unbind(vma); |
3653 | ret = i915_vma_unbind(vma); |
3649 | if (ret) |
3654 | if (ret) |
3650 | return ret; |
3655 | return ret; |
3651 | 3656 | ||
3652 | vma = NULL; |
3657 | vma = NULL; |
3653 | } |
3658 | } |
3654 | } |
3659 | } |
3655 | 3660 | ||
3656 | bound = vma ? vma->bound : 0; |
3661 | bound = vma ? vma->bound : 0; |
3657 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
3662 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
3658 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3663 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
3659 | if (IS_ERR(vma)) |
3664 | if (IS_ERR(vma)) |
3660 | return PTR_ERR(vma); |
3665 | return PTR_ERR(vma); |
3661 | } |
3666 | } |
3662 | 3667 | ||
3663 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
3668 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
3664 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
3669 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
3665 | 3670 | ||
3666 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
3671 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
3667 | bool mappable, fenceable; |
3672 | bool mappable, fenceable; |
3668 | u32 fence_size, fence_alignment; |
3673 | u32 fence_size, fence_alignment; |
3669 | 3674 | ||
3670 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
3675 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
3671 | obj->base.size, |
3676 | obj->base.size, |
3672 | obj->tiling_mode); |
3677 | obj->tiling_mode); |
3673 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
3678 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
3674 | obj->base.size, |
3679 | obj->base.size, |
3675 | obj->tiling_mode, |
3680 | obj->tiling_mode, |
3676 | true); |
3681 | true); |
3677 | 3682 | ||
3678 | fenceable = (vma->node.size == fence_size && |
3683 | fenceable = (vma->node.size == fence_size && |
3679 | (vma->node.start & (fence_alignment - 1)) == 0); |
3684 | (vma->node.start & (fence_alignment - 1)) == 0); |
3680 | 3685 | ||
3681 | mappable = (vma->node.start + obj->base.size <= |
3686 | mappable = (vma->node.start + obj->base.size <= |
3682 | dev_priv->gtt.mappable_end); |
3687 | dev_priv->gtt.mappable_end); |
3683 | 3688 | ||
3684 | obj->map_and_fenceable = mappable && fenceable; |
3689 | obj->map_and_fenceable = mappable && fenceable; |
3685 | } |
3690 | } |
3686 | 3691 | ||
3687 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
3692 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
3688 | 3693 | ||
3689 | vma->pin_count++; |
3694 | vma->pin_count++; |
3690 | if (flags & PIN_MAPPABLE) |
3695 | if (flags & PIN_MAPPABLE) |
3691 | obj->pin_mappable |= true; |
3696 | obj->pin_mappable |= true; |
3692 | 3697 | ||
3693 | return 0; |
3698 | return 0; |
3694 | } |
3699 | } |
3695 | 3700 | ||
3696 | void |
3701 | void |
3697 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
3702 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
3698 | { |
3703 | { |
3699 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
3704 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
3700 | 3705 | ||
3701 | BUG_ON(!vma); |
3706 | BUG_ON(!vma); |
3702 | BUG_ON(vma->pin_count == 0); |
3707 | BUG_ON(vma->pin_count == 0); |
3703 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
3708 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
3704 | 3709 | ||
3705 | if (--vma->pin_count == 0) |
3710 | if (--vma->pin_count == 0) |
3706 | obj->pin_mappable = false; |
3711 | obj->pin_mappable = false; |
3707 | } |
3712 | } |
3708 | 3713 | ||
3709 | bool |
3714 | bool |
3710 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
3715 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
3711 | { |
3716 | { |
3712 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3717 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3713 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3718 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3714 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
3719 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
3715 | 3720 | ||
3716 | WARN_ON(!ggtt_vma || |
3721 | WARN_ON(!ggtt_vma || |
3717 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
3722 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
3718 | ggtt_vma->pin_count); |
3723 | ggtt_vma->pin_count); |
3719 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
3724 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
3720 | return true; |
3725 | return true; |
3721 | } else |
3726 | } else |
3722 | return false; |
3727 | return false; |
3723 | } |
3728 | } |
3724 | 3729 | ||
3725 | void |
3730 | void |
3726 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
3731 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
3727 | { |
3732 | { |
3728 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3733 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3729 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3734 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3730 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
3735 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
3731 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
3736 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
3732 | } |
3737 | } |
3733 | } |
3738 | } |
3734 | 3739 | ||
3735 | int |
3740 | int |
3736 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
3741 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
3737 | struct drm_file *file) |
3742 | struct drm_file *file) |
3738 | { |
3743 | { |
3739 | struct drm_i915_gem_pin *args = data; |
3744 | struct drm_i915_gem_pin *args = data; |
3740 | struct drm_i915_gem_object *obj; |
3745 | struct drm_i915_gem_object *obj; |
3741 | int ret; |
3746 | int ret; |
3742 | 3747 | ||
3743 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3748 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3744 | return -ENODEV; |
3749 | return -ENODEV; |
3745 | 3750 | ||
3746 | ret = i915_mutex_lock_interruptible(dev); |
3751 | ret = i915_mutex_lock_interruptible(dev); |
3747 | if (ret) |
3752 | if (ret) |
3748 | return ret; |
3753 | return ret; |
3749 | 3754 | ||
3750 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3755 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3751 | if (&obj->base == NULL) { |
3756 | if (&obj->base == NULL) { |
3752 | ret = -ENOENT; |
3757 | ret = -ENOENT; |
3753 | goto unlock; |
3758 | goto unlock; |
3754 | } |
3759 | } |
3755 | 3760 | ||
3756 | if (obj->madv != I915_MADV_WILLNEED) { |
3761 | if (obj->madv != I915_MADV_WILLNEED) { |
3757 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
3762 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
3758 | ret = -EFAULT; |
3763 | ret = -EFAULT; |
3759 | goto out; |
3764 | goto out; |
3760 | } |
3765 | } |
3761 | 3766 | ||
3762 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
3767 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
3763 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3768 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3764 | args->handle); |
3769 | args->handle); |
3765 | ret = -EINVAL; |
3770 | ret = -EINVAL; |
3766 | goto out; |
3771 | goto out; |
3767 | } |
3772 | } |
3768 | 3773 | ||
3769 | if (obj->user_pin_count == ULONG_MAX) { |
3774 | if (obj->user_pin_count == ULONG_MAX) { |
3770 | ret = -EBUSY; |
3775 | ret = -EBUSY; |
3771 | goto out; |
3776 | goto out; |
3772 | } |
3777 | } |
3773 | 3778 | ||
3774 | if (obj->user_pin_count == 0) { |
3779 | if (obj->user_pin_count == 0) { |
3775 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
3780 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
3776 | if (ret) |
3781 | if (ret) |
3777 | goto out; |
3782 | goto out; |
3778 | } |
3783 | } |
3779 | 3784 | ||
3780 | obj->user_pin_count++; |
3785 | obj->user_pin_count++; |
3781 | obj->pin_filp = file; |
3786 | obj->pin_filp = file; |
3782 | 3787 | ||
3783 | args->offset = i915_gem_obj_ggtt_offset(obj); |
3788 | args->offset = i915_gem_obj_ggtt_offset(obj); |
3784 | out: |
3789 | out: |
3785 | drm_gem_object_unreference(&obj->base); |
3790 | drm_gem_object_unreference(&obj->base); |
3786 | unlock: |
3791 | unlock: |
3787 | mutex_unlock(&dev->struct_mutex); |
3792 | mutex_unlock(&dev->struct_mutex); |
3788 | return ret; |
3793 | return ret; |
3789 | } |
3794 | } |
3790 | 3795 | ||
3791 | int |
3796 | int |
3792 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
3797 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
3793 | struct drm_file *file) |
3798 | struct drm_file *file) |
3794 | { |
3799 | { |
3795 | struct drm_i915_gem_pin *args = data; |
3800 | struct drm_i915_gem_pin *args = data; |
3796 | struct drm_i915_gem_object *obj; |
3801 | struct drm_i915_gem_object *obj; |
3797 | int ret; |
3802 | int ret; |
3798 | 3803 | ||
3799 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3804 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3800 | return -ENODEV; |
3805 | return -ENODEV; |
3801 | 3806 | ||
3802 | ret = i915_mutex_lock_interruptible(dev); |
3807 | ret = i915_mutex_lock_interruptible(dev); |
3803 | if (ret) |
3808 | if (ret) |
3804 | return ret; |
3809 | return ret; |
3805 | 3810 | ||
3806 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3811 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3807 | if (&obj->base == NULL) { |
3812 | if (&obj->base == NULL) { |
3808 | ret = -ENOENT; |
3813 | ret = -ENOENT; |
3809 | goto unlock; |
3814 | goto unlock; |
3810 | } |
3815 | } |
3811 | 3816 | ||
3812 | if (obj->pin_filp != file) { |
3817 | if (obj->pin_filp != file) { |
3813 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3818 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3814 | args->handle); |
3819 | args->handle); |
3815 | ret = -EINVAL; |
3820 | ret = -EINVAL; |
3816 | goto out; |
3821 | goto out; |
3817 | } |
3822 | } |
3818 | obj->user_pin_count--; |
3823 | obj->user_pin_count--; |
3819 | if (obj->user_pin_count == 0) { |
3824 | if (obj->user_pin_count == 0) { |
3820 | obj->pin_filp = NULL; |
3825 | obj->pin_filp = NULL; |
3821 | i915_gem_object_ggtt_unpin(obj); |
3826 | i915_gem_object_ggtt_unpin(obj); |
3822 | } |
3827 | } |
3823 | 3828 | ||
3824 | out: |
3829 | out: |
3825 | drm_gem_object_unreference(&obj->base); |
3830 | drm_gem_object_unreference(&obj->base); |
3826 | unlock: |
3831 | unlock: |
3827 | mutex_unlock(&dev->struct_mutex); |
3832 | mutex_unlock(&dev->struct_mutex); |
3828 | return ret; |
3833 | return ret; |
3829 | } |
3834 | } |
3830 | 3835 | ||
3831 | int |
3836 | int |
3832 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3837 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3833 | struct drm_file *file) |
3838 | struct drm_file *file) |
3834 | { |
3839 | { |
3835 | struct drm_i915_gem_busy *args = data; |
3840 | struct drm_i915_gem_busy *args = data; |
3836 | struct drm_i915_gem_object *obj; |
3841 | struct drm_i915_gem_object *obj; |
3837 | int ret; |
3842 | int ret; |
3838 | 3843 | ||
3839 | ret = i915_mutex_lock_interruptible(dev); |
3844 | ret = i915_mutex_lock_interruptible(dev); |
3840 | if (ret) |
3845 | if (ret) |
3841 | return ret; |
3846 | return ret; |
3842 | 3847 | ||
3843 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3848 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3844 | if (&obj->base == NULL) { |
3849 | if (&obj->base == NULL) { |
3845 | ret = -ENOENT; |
3850 | ret = -ENOENT; |
3846 | goto unlock; |
3851 | goto unlock; |
3847 | } |
3852 | } |
3848 | 3853 | ||
3849 | /* Count all active objects as busy, even if they are currently not used |
3854 | /* Count all active objects as busy, even if they are currently not used |
3850 | * by the gpu. Users of this interface expect objects to eventually |
3855 | * by the gpu. Users of this interface expect objects to eventually |
3851 | * become non-busy without any further actions, therefore emit any |
3856 | * become non-busy without any further actions, therefore emit any |
3852 | * necessary flushes here. |
3857 | * necessary flushes here. |
3853 | */ |
3858 | */ |
3854 | ret = i915_gem_object_flush_active(obj); |
3859 | ret = i915_gem_object_flush_active(obj); |
3855 | 3860 | ||
3856 | args->busy = obj->active; |
3861 | args->busy = obj->active; |
3857 | if (obj->ring) { |
3862 | if (obj->ring) { |
3858 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
3863 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
3859 | args->busy |= intel_ring_flag(obj->ring) << 16; |
3864 | args->busy |= intel_ring_flag(obj->ring) << 16; |
3860 | } |
3865 | } |
3861 | 3866 | ||
3862 | drm_gem_object_unreference(&obj->base); |
3867 | drm_gem_object_unreference(&obj->base); |
3863 | unlock: |
3868 | unlock: |
3864 | mutex_unlock(&dev->struct_mutex); |
3869 | mutex_unlock(&dev->struct_mutex); |
3865 | return ret; |
3870 | return ret; |
3866 | } |
3871 | } |
3867 | 3872 | ||
3868 | int |
3873 | int |
3869 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3874 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3870 | struct drm_file *file_priv) |
3875 | struct drm_file *file_priv) |
3871 | { |
3876 | { |
3872 | return i915_gem_ring_throttle(dev, file_priv); |
3877 | return i915_gem_ring_throttle(dev, file_priv); |
3873 | } |
3878 | } |
3874 | 3879 | ||
3875 | #if 0 |
3880 | #if 0 |
3876 | 3881 | ||
3877 | int |
3882 | int |
3878 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3883 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3879 | struct drm_file *file_priv) |
3884 | struct drm_file *file_priv) |
3880 | { |
3885 | { |
3881 | struct drm_i915_private *dev_priv = dev->dev_private; |
3886 | struct drm_i915_private *dev_priv = dev->dev_private; |
3882 | struct drm_i915_gem_madvise *args = data; |
3887 | struct drm_i915_gem_madvise *args = data; |
3883 | struct drm_i915_gem_object *obj; |
3888 | struct drm_i915_gem_object *obj; |
3884 | int ret; |
3889 | int ret; |
3885 | 3890 | ||
3886 | switch (args->madv) { |
3891 | switch (args->madv) { |
3887 | case I915_MADV_DONTNEED: |
3892 | case I915_MADV_DONTNEED: |
3888 | case I915_MADV_WILLNEED: |
3893 | case I915_MADV_WILLNEED: |
3889 | break; |
3894 | break; |
3890 | default: |
3895 | default: |
3891 | return -EINVAL; |
3896 | return -EINVAL; |
3892 | } |
3897 | } |
3893 | 3898 | ||
3894 | ret = i915_mutex_lock_interruptible(dev); |
3899 | ret = i915_mutex_lock_interruptible(dev); |
3895 | if (ret) |
3900 | if (ret) |
3896 | return ret; |
3901 | return ret; |
3897 | 3902 | ||
3898 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3903 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3899 | if (&obj->base == NULL) { |
3904 | if (&obj->base == NULL) { |
3900 | ret = -ENOENT; |
3905 | ret = -ENOENT; |
3901 | goto unlock; |
3906 | goto unlock; |
3902 | } |
3907 | } |
3903 | 3908 | ||
3904 | if (i915_gem_obj_is_pinned(obj)) { |
3909 | if (i915_gem_obj_is_pinned(obj)) { |
3905 | ret = -EINVAL; |
3910 | ret = -EINVAL; |
3906 | goto out; |
3911 | goto out; |
3907 | } |
3912 | } |
3908 | 3913 | ||
3909 | if (obj->pages && |
3914 | if (obj->pages && |
3910 | obj->tiling_mode != I915_TILING_NONE && |
3915 | obj->tiling_mode != I915_TILING_NONE && |
3911 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
3916 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
3912 | if (obj->madv == I915_MADV_WILLNEED) |
3917 | if (obj->madv == I915_MADV_WILLNEED) |
3913 | i915_gem_object_unpin_pages(obj); |
3918 | i915_gem_object_unpin_pages(obj); |
3914 | if (args->madv == I915_MADV_WILLNEED) |
3919 | if (args->madv == I915_MADV_WILLNEED) |
3915 | i915_gem_object_pin_pages(obj); |
3920 | i915_gem_object_pin_pages(obj); |
3916 | } |
3921 | } |
3917 | 3922 | ||
3918 | if (obj->madv != __I915_MADV_PURGED) |
3923 | if (obj->madv != __I915_MADV_PURGED) |
3919 | obj->madv = args->madv; |
3924 | obj->madv = args->madv; |
3920 | 3925 | ||
3921 | /* if the object is no longer attached, discard its backing storage */ |
3926 | /* if the object is no longer attached, discard its backing storage */ |
3922 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
3927 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
3923 | i915_gem_object_truncate(obj); |
3928 | i915_gem_object_truncate(obj); |
3924 | 3929 | ||
3925 | args->retained = obj->madv != __I915_MADV_PURGED; |
3930 | args->retained = obj->madv != __I915_MADV_PURGED; |
3926 | 3931 | ||
3927 | out: |
3932 | out: |
3928 | drm_gem_object_unreference(&obj->base); |
3933 | drm_gem_object_unreference(&obj->base); |
3929 | unlock: |
3934 | unlock: |
3930 | mutex_unlock(&dev->struct_mutex); |
3935 | mutex_unlock(&dev->struct_mutex); |
3931 | return ret; |
3936 | return ret; |
3932 | } |
3937 | } |
3933 | #endif |
3938 | #endif |
3934 | 3939 | ||
3935 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3940 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3936 | const struct drm_i915_gem_object_ops *ops) |
3941 | const struct drm_i915_gem_object_ops *ops) |
3937 | { |
3942 | { |
3938 | INIT_LIST_HEAD(&obj->global_list); |
3943 | INIT_LIST_HEAD(&obj->global_list); |
3939 | INIT_LIST_HEAD(&obj->ring_list); |
3944 | INIT_LIST_HEAD(&obj->ring_list); |
3940 | INIT_LIST_HEAD(&obj->obj_exec_link); |
3945 | INIT_LIST_HEAD(&obj->obj_exec_link); |
3941 | INIT_LIST_HEAD(&obj->vma_list); |
3946 | INIT_LIST_HEAD(&obj->vma_list); |
3942 | 3947 | ||
3943 | obj->ops = ops; |
3948 | obj->ops = ops; |
3944 | 3949 | ||
3945 | obj->fence_reg = I915_FENCE_REG_NONE; |
3950 | obj->fence_reg = I915_FENCE_REG_NONE; |
3946 | obj->madv = I915_MADV_WILLNEED; |
3951 | obj->madv = I915_MADV_WILLNEED; |
3947 | 3952 | ||
3948 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
3953 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
3949 | } |
3954 | } |
3950 | 3955 | ||
3951 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3956 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3952 | .get_pages = i915_gem_object_get_pages_gtt, |
3957 | .get_pages = i915_gem_object_get_pages_gtt, |
3953 | .put_pages = i915_gem_object_put_pages_gtt, |
3958 | .put_pages = i915_gem_object_put_pages_gtt, |
3954 | }; |
3959 | }; |
3955 | 3960 | ||
3956 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3961 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3957 | size_t size) |
3962 | size_t size) |
3958 | { |
3963 | { |
3959 | struct drm_i915_gem_object *obj; |
3964 | struct drm_i915_gem_object *obj; |
3960 | struct address_space *mapping; |
3965 | struct address_space *mapping; |
3961 | gfp_t mask; |
3966 | gfp_t mask; |
3962 | 3967 | ||
3963 | obj = i915_gem_object_alloc(dev); |
3968 | obj = i915_gem_object_alloc(dev); |
3964 | if (obj == NULL) |
3969 | if (obj == NULL) |
3965 | return NULL; |
3970 | return NULL; |
3966 | 3971 | ||
3967 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3972 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3968 | i915_gem_object_free(obj); |
3973 | i915_gem_object_free(obj); |
3969 | return NULL; |
3974 | return NULL; |
3970 | } |
3975 | } |
3971 | 3976 | ||
3972 | 3977 | ||
3973 | i915_gem_object_init(obj, &i915_gem_object_ops); |
3978 | i915_gem_object_init(obj, &i915_gem_object_ops); |
3974 | 3979 | ||
3975 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3980 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3976 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3981 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3977 | 3982 | ||
3978 | if (HAS_LLC(dev)) { |
3983 | if (HAS_LLC(dev)) { |
3979 | /* On some devices, we can have the GPU use the LLC (the CPU |
3984 | /* On some devices, we can have the GPU use the LLC (the CPU |
3980 | * cache) for about a 10% performance improvement |
3985 | * cache) for about a 10% performance improvement |
3981 | * compared to uncached. Graphics requests other than |
3986 | * compared to uncached. Graphics requests other than |
3982 | * display scanout are coherent with the CPU in |
3987 | * display scanout are coherent with the CPU in |
3983 | * accessing this cache. This means in this mode we |
3988 | * accessing this cache. This means in this mode we |
3984 | * don't need to clflush on the CPU side, and on the |
3989 | * don't need to clflush on the CPU side, and on the |
3985 | * GPU side we only need to flush internal caches to |
3990 | * GPU side we only need to flush internal caches to |
3986 | * get data visible to the CPU. |
3991 | * get data visible to the CPU. |
3987 | * |
3992 | * |
3988 | * However, we maintain the display planes as UC, and so |
3993 | * However, we maintain the display planes as UC, and so |
3989 | * need to rebind when first used as such. |
3994 | * need to rebind when first used as such. |
3990 | */ |
3995 | */ |
3991 | obj->cache_level = I915_CACHE_LLC; |
3996 | obj->cache_level = I915_CACHE_LLC; |
3992 | } else |
3997 | } else |
3993 | obj->cache_level = I915_CACHE_NONE; |
3998 | obj->cache_level = I915_CACHE_NONE; |
3994 | 3999 | ||
3995 | trace_i915_gem_object_create(obj); |
4000 | trace_i915_gem_object_create(obj); |
3996 | 4001 | ||
3997 | return obj; |
4002 | return obj; |
3998 | } |
4003 | } |
3999 | 4004 | ||
4000 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4005 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4001 | { |
4006 | { |
4002 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
4007 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
4003 | struct drm_device *dev = obj->base.dev; |
4008 | struct drm_device *dev = obj->base.dev; |
4004 | struct drm_i915_private *dev_priv = dev->dev_private; |
4009 | struct drm_i915_private *dev_priv = dev->dev_private; |
4005 | struct i915_vma *vma, *next; |
4010 | struct i915_vma *vma, *next; |
4006 | 4011 | ||
4007 | intel_runtime_pm_get(dev_priv); |
4012 | intel_runtime_pm_get(dev_priv); |
4008 | 4013 | ||
4009 | trace_i915_gem_object_destroy(obj); |
4014 | trace_i915_gem_object_destroy(obj); |
4010 | 4015 | ||
4011 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4016 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4012 | int ret; |
4017 | int ret; |
4013 | 4018 | ||
4014 | vma->pin_count = 0; |
4019 | vma->pin_count = 0; |
4015 | ret = i915_vma_unbind(vma); |
4020 | ret = i915_vma_unbind(vma); |
4016 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4021 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4017 | bool was_interruptible; |
4022 | bool was_interruptible; |
4018 | 4023 | ||
4019 | was_interruptible = dev_priv->mm.interruptible; |
4024 | was_interruptible = dev_priv->mm.interruptible; |
4020 | dev_priv->mm.interruptible = false; |
4025 | dev_priv->mm.interruptible = false; |
4021 | 4026 | ||
4022 | WARN_ON(i915_vma_unbind(vma)); |
4027 | WARN_ON(i915_vma_unbind(vma)); |
4023 | 4028 | ||
4024 | dev_priv->mm.interruptible = was_interruptible; |
4029 | dev_priv->mm.interruptible = was_interruptible; |
4025 | } |
4030 | } |
4026 | } |
4031 | } |
4027 | 4032 | ||
4028 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4033 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4029 | * before progressing. */ |
4034 | * before progressing. */ |
4030 | if (obj->stolen) |
4035 | if (obj->stolen) |
4031 | i915_gem_object_unpin_pages(obj); |
4036 | i915_gem_object_unpin_pages(obj); |
4032 | 4037 | ||
4033 | WARN_ON(obj->frontbuffer_bits); |
4038 | WARN_ON(obj->frontbuffer_bits); |
4034 | 4039 | ||
4035 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4040 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4036 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
4041 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
4037 | obj->tiling_mode != I915_TILING_NONE) |
4042 | obj->tiling_mode != I915_TILING_NONE) |
4038 | i915_gem_object_unpin_pages(obj); |
4043 | i915_gem_object_unpin_pages(obj); |
4039 | 4044 | ||
4040 | if (WARN_ON(obj->pages_pin_count)) |
4045 | if (WARN_ON(obj->pages_pin_count)) |
4041 | obj->pages_pin_count = 0; |
4046 | obj->pages_pin_count = 0; |
4042 | i915_gem_object_put_pages(obj); |
4047 | i915_gem_object_put_pages(obj); |
4043 | // i915_gem_object_free_mmap_offset(obj); |
4048 | // i915_gem_object_free_mmap_offset(obj); |
4044 | 4049 | ||
4045 | BUG_ON(obj->pages); |
4050 | BUG_ON(obj->pages); |
4046 | 4051 | ||
4047 | 4052 | ||
4048 | if(obj->base.filp != NULL) |
4053 | if(obj->base.filp != NULL) |
4049 | { |
4054 | { |
4050 | // printf("filp %p\n", obj->base.filp); |
4055 | // printf("filp %p\n", obj->base.filp); |
4051 | shmem_file_delete(obj->base.filp); |
4056 | shmem_file_delete(obj->base.filp); |
4052 | } |
4057 | } |
4053 | 4058 | ||
4054 | drm_gem_object_release(&obj->base); |
4059 | drm_gem_object_release(&obj->base); |
4055 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
4060 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
4056 | 4061 | ||
4057 | kfree(obj->bit_17); |
4062 | kfree(obj->bit_17); |
4058 | i915_gem_object_free(obj); |
4063 | i915_gem_object_free(obj); |
4059 | 4064 | ||
4060 | intel_runtime_pm_put(dev_priv); |
4065 | intel_runtime_pm_put(dev_priv); |
4061 | } |
4066 | } |
4062 | 4067 | ||
4063 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4068 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4064 | struct i915_address_space *vm) |
4069 | struct i915_address_space *vm) |
4065 | { |
4070 | { |
4066 | struct i915_vma *vma; |
4071 | struct i915_vma *vma; |
4067 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
4072 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
4068 | if (vma->vm == vm) |
4073 | if (vma->vm == vm) |
4069 | return vma; |
4074 | return vma; |
4070 | 4075 | ||
4071 | return NULL; |
4076 | return NULL; |
4072 | } |
4077 | } |
4073 | 4078 | ||
4074 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4079 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4075 | { |
4080 | { |
4076 | struct i915_address_space *vm = NULL; |
4081 | struct i915_address_space *vm = NULL; |
4077 | WARN_ON(vma->node.allocated); |
4082 | WARN_ON(vma->node.allocated); |
4078 | 4083 | ||
4079 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
4084 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
4080 | if (!list_empty(&vma->exec_list)) |
4085 | if (!list_empty(&vma->exec_list)) |
4081 | return; |
4086 | return; |
4082 | 4087 | ||
4083 | vm = vma->vm; |
4088 | vm = vma->vm; |
4084 | 4089 | ||
4085 | if (!i915_is_ggtt(vm)) |
4090 | if (!i915_is_ggtt(vm)) |
4086 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
4091 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
4087 | 4092 | ||
4088 | list_del(&vma->vma_link); |
4093 | list_del(&vma->vma_link); |
4089 | 4094 | ||
4090 | kfree(vma); |
4095 | kfree(vma); |
4091 | } |
4096 | } |
4092 | 4097 | ||
4093 | #if 0 |
4098 | #if 0 |
4094 | int |
4099 | int |
4095 | i915_gem_suspend(struct drm_device *dev) |
4100 | i915_gem_suspend(struct drm_device *dev) |
4096 | { |
4101 | { |
4097 | struct drm_i915_private *dev_priv = dev->dev_private; |
4102 | struct drm_i915_private *dev_priv = dev->dev_private; |
4098 | int ret = 0; |
4103 | int ret = 0; |
4099 | 4104 | ||
4100 | mutex_lock(&dev->struct_mutex); |
4105 | mutex_lock(&dev->struct_mutex); |
4101 | ret = i915_gpu_idle(dev); |
4106 | ret = i915_gpu_idle(dev); |
4102 | if (ret) |
4107 | if (ret) |
4103 | goto err; |
4108 | goto err; |
4104 | 4109 | ||
4105 | i915_gem_retire_requests(dev); |
4110 | i915_gem_retire_requests(dev); |
4106 | 4111 | ||
4107 | /* Under UMS, be paranoid and evict. */ |
4112 | /* Under UMS, be paranoid and evict. */ |
4108 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4113 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4109 | i915_gem_evict_everything(dev); |
4114 | i915_gem_evict_everything(dev); |
4110 | 4115 | ||
4111 | i915_gem_stop_ringbuffers(dev); |
4116 | i915_gem_stop_ringbuffers(dev); |
4112 | mutex_unlock(&dev->struct_mutex); |
4117 | mutex_unlock(&dev->struct_mutex); |
4113 | 4118 | ||
4114 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
4119 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
4115 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
4120 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
4116 | flush_delayed_work(&dev_priv->mm.idle_work); |
4121 | flush_delayed_work(&dev_priv->mm.idle_work); |
4117 | 4122 | ||
4118 | return 0; |
4123 | return 0; |
4119 | 4124 | ||
4120 | err: |
4125 | err: |
4121 | mutex_unlock(&dev->struct_mutex); |
4126 | mutex_unlock(&dev->struct_mutex); |
4122 | return ret; |
4127 | return ret; |
4123 | } |
4128 | } |
4124 | #endif |
4129 | #endif |
4125 | 4130 | ||
4126 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
4131 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
4127 | { |
4132 | { |
4128 | struct drm_device *dev = ring->dev; |
4133 | struct drm_device *dev = ring->dev; |
4129 | struct drm_i915_private *dev_priv = dev->dev_private; |
4134 | struct drm_i915_private *dev_priv = dev->dev_private; |
4130 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4135 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4131 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
4136 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
4132 | int i, ret; |
4137 | int i, ret; |
4133 | 4138 | ||
4134 | if (!HAS_L3_DPF(dev) || !remap_info) |
4139 | if (!HAS_L3_DPF(dev) || !remap_info) |
4135 | return 0; |
4140 | return 0; |
4136 | 4141 | ||
4137 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4142 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4138 | if (ret) |
4143 | if (ret) |
4139 | return ret; |
4144 | return ret; |
4140 | 4145 | ||
4141 | /* |
4146 | /* |
4142 | * Note: We do not worry about the concurrent register cacheline hang |
4147 | * Note: We do not worry about the concurrent register cacheline hang |
4143 | * here because no other code should access these registers other than |
4148 | * here because no other code should access these registers other than |
4144 | * at initialization time. |
4149 | * at initialization time. |
4145 | */ |
4150 | */ |
4146 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
4151 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
4147 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4152 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4148 | intel_ring_emit(ring, reg_base + i); |
4153 | intel_ring_emit(ring, reg_base + i); |
4149 | intel_ring_emit(ring, remap_info[i/4]); |
4154 | intel_ring_emit(ring, remap_info[i/4]); |
4150 | } |
4155 | } |
4151 | 4156 | ||
4152 | intel_ring_advance(ring); |
4157 | intel_ring_advance(ring); |
4153 | 4158 | ||
4154 | return ret; |
4159 | return ret; |
4155 | } |
4160 | } |
4156 | 4161 | ||
4157 | void i915_gem_init_swizzling(struct drm_device *dev) |
4162 | void i915_gem_init_swizzling(struct drm_device *dev) |
4158 | { |
4163 | { |
4159 | struct drm_i915_private *dev_priv = dev->dev_private; |
4164 | struct drm_i915_private *dev_priv = dev->dev_private; |
4160 | 4165 | ||
4161 | if (INTEL_INFO(dev)->gen < 5 || |
4166 | if (INTEL_INFO(dev)->gen < 5 || |
4162 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4167 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4163 | return; |
4168 | return; |
4164 | 4169 | ||
4165 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
4170 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
4166 | DISP_TILE_SURFACE_SWIZZLING); |
4171 | DISP_TILE_SURFACE_SWIZZLING); |
4167 | 4172 | ||
4168 | if (IS_GEN5(dev)) |
4173 | if (IS_GEN5(dev)) |
4169 | return; |
4174 | return; |
4170 | 4175 | ||
4171 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4176 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4172 | if (IS_GEN6(dev)) |
4177 | if (IS_GEN6(dev)) |
4173 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
4178 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
4174 | else if (IS_GEN7(dev)) |
4179 | else if (IS_GEN7(dev)) |
4175 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
4180 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
4176 | else if (IS_GEN8(dev)) |
4181 | else if (IS_GEN8(dev)) |
4177 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
4182 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
4178 | else |
4183 | else |
4179 | BUG(); |
4184 | BUG(); |
4180 | } |
4185 | } |
4181 | 4186 | ||
4182 | static bool |
4187 | static bool |
4183 | intel_enable_blt(struct drm_device *dev) |
4188 | intel_enable_blt(struct drm_device *dev) |
4184 | { |
4189 | { |
4185 | if (!HAS_BLT(dev)) |
4190 | if (!HAS_BLT(dev)) |
4186 | return false; |
4191 | return false; |
4187 | 4192 | ||
4188 | /* The blitter was dysfunctional on early prototypes */ |
4193 | /* The blitter was dysfunctional on early prototypes */ |
4189 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
4194 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
4190 | DRM_INFO("BLT not supported on this pre-production hardware;" |
4195 | DRM_INFO("BLT not supported on this pre-production hardware;" |
4191 | " graphics performance will be degraded.\n"); |
4196 | " graphics performance will be degraded.\n"); |
4192 | return false; |
4197 | return false; |
4193 | } |
4198 | } |
4194 | 4199 | ||
4195 | return true; |
4200 | return true; |
4196 | } |
4201 | } |
4197 | 4202 | ||
4198 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4203 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4199 | { |
4204 | { |
4200 | struct drm_i915_private *dev_priv = dev->dev_private; |
4205 | struct drm_i915_private *dev_priv = dev->dev_private; |
4201 | 4206 | ||
4202 | I915_WRITE(RING_CTL(base), 0); |
4207 | I915_WRITE(RING_CTL(base), 0); |
4203 | I915_WRITE(RING_HEAD(base), 0); |
4208 | I915_WRITE(RING_HEAD(base), 0); |
4204 | I915_WRITE(RING_TAIL(base), 0); |
4209 | I915_WRITE(RING_TAIL(base), 0); |
4205 | I915_WRITE(RING_START(base), 0); |
4210 | I915_WRITE(RING_START(base), 0); |
4206 | } |
4211 | } |
4207 | 4212 | ||
4208 | static void init_unused_rings(struct drm_device *dev) |
4213 | static void init_unused_rings(struct drm_device *dev) |
4209 | { |
4214 | { |
4210 | if (IS_I830(dev)) { |
4215 | if (IS_I830(dev)) { |
4211 | init_unused_ring(dev, PRB1_BASE); |
4216 | init_unused_ring(dev, PRB1_BASE); |
4212 | init_unused_ring(dev, SRB0_BASE); |
4217 | init_unused_ring(dev, SRB0_BASE); |
4213 | init_unused_ring(dev, SRB1_BASE); |
4218 | init_unused_ring(dev, SRB1_BASE); |
4214 | init_unused_ring(dev, SRB2_BASE); |
4219 | init_unused_ring(dev, SRB2_BASE); |
4215 | init_unused_ring(dev, SRB3_BASE); |
4220 | init_unused_ring(dev, SRB3_BASE); |
4216 | } else if (IS_GEN2(dev)) { |
4221 | } else if (IS_GEN2(dev)) { |
4217 | init_unused_ring(dev, SRB0_BASE); |
4222 | init_unused_ring(dev, SRB0_BASE); |
4218 | init_unused_ring(dev, SRB1_BASE); |
4223 | init_unused_ring(dev, SRB1_BASE); |
4219 | } else if (IS_GEN3(dev)) { |
4224 | } else if (IS_GEN3(dev)) { |
4220 | init_unused_ring(dev, PRB1_BASE); |
4225 | init_unused_ring(dev, PRB1_BASE); |
4221 | init_unused_ring(dev, PRB2_BASE); |
4226 | init_unused_ring(dev, PRB2_BASE); |
4222 | } |
4227 | } |
4223 | } |
4228 | } |
4224 | 4229 | ||
4225 | int i915_gem_init_rings(struct drm_device *dev) |
4230 | int i915_gem_init_rings(struct drm_device *dev) |
4226 | { |
4231 | { |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; |
4232 | struct drm_i915_private *dev_priv = dev->dev_private; |
4228 | int ret; |
4233 | int ret; |
4229 | 4234 | ||
4230 | /* |
4235 | /* |
4231 | * At least 830 can leave some of the unused rings |
4236 | * At least 830 can leave some of the unused rings |
4232 | * "active" (ie. head != tail) after resume which |
4237 | * "active" (ie. head != tail) after resume which |
4233 | * will prevent c3 entry. Makes sure all unused rings |
4238 | * will prevent c3 entry. Makes sure all unused rings |
4234 | * are totally idle. |
4239 | * are totally idle. |
4235 | */ |
4240 | */ |
4236 | init_unused_rings(dev); |
4241 | init_unused_rings(dev); |
4237 | 4242 | ||
4238 | ret = intel_init_render_ring_buffer(dev); |
4243 | ret = intel_init_render_ring_buffer(dev); |
4239 | if (ret) |
4244 | if (ret) |
4240 | return ret; |
4245 | return ret; |
4241 | 4246 | ||
4242 | if (HAS_BSD(dev)) { |
4247 | if (HAS_BSD(dev)) { |
4243 | ret = intel_init_bsd_ring_buffer(dev); |
4248 | ret = intel_init_bsd_ring_buffer(dev); |
4244 | if (ret) |
4249 | if (ret) |
4245 | goto cleanup_render_ring; |
4250 | goto cleanup_render_ring; |
4246 | } |
4251 | } |
4247 | 4252 | ||
4248 | if (intel_enable_blt(dev)) { |
4253 | if (intel_enable_blt(dev)) { |
4249 | ret = intel_init_blt_ring_buffer(dev); |
4254 | ret = intel_init_blt_ring_buffer(dev); |
4250 | if (ret) |
4255 | if (ret) |
4251 | goto cleanup_bsd_ring; |
4256 | goto cleanup_bsd_ring; |
4252 | } |
4257 | } |
4253 | 4258 | ||
4254 | if (HAS_VEBOX(dev)) { |
4259 | if (HAS_VEBOX(dev)) { |
4255 | ret = intel_init_vebox_ring_buffer(dev); |
4260 | ret = intel_init_vebox_ring_buffer(dev); |
4256 | if (ret) |
4261 | if (ret) |
4257 | goto cleanup_blt_ring; |
4262 | goto cleanup_blt_ring; |
4258 | } |
4263 | } |
4259 | 4264 | ||
4260 | if (HAS_BSD2(dev)) { |
4265 | if (HAS_BSD2(dev)) { |
4261 | ret = intel_init_bsd2_ring_buffer(dev); |
4266 | ret = intel_init_bsd2_ring_buffer(dev); |
4262 | if (ret) |
4267 | if (ret) |
4263 | goto cleanup_vebox_ring; |
4268 | goto cleanup_vebox_ring; |
4264 | } |
4269 | } |
4265 | 4270 | ||
4266 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4271 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4267 | if (ret) |
4272 | if (ret) |
4268 | goto cleanup_bsd2_ring; |
4273 | goto cleanup_bsd2_ring; |
4269 | 4274 | ||
4270 | return 0; |
4275 | return 0; |
4271 | 4276 | ||
4272 | cleanup_bsd2_ring: |
4277 | cleanup_bsd2_ring: |
4273 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
4278 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
4274 | cleanup_vebox_ring: |
4279 | cleanup_vebox_ring: |
4275 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
4280 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
4276 | cleanup_blt_ring: |
4281 | cleanup_blt_ring: |
4277 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
4282 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
4278 | cleanup_bsd_ring: |
4283 | cleanup_bsd_ring: |
4279 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
4284 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
4280 | cleanup_render_ring: |
4285 | cleanup_render_ring: |
4281 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
4286 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
4282 | 4287 | ||
4283 | return ret; |
4288 | return ret; |
4284 | } |
4289 | } |
4285 | 4290 | ||
4286 | int |
4291 | int |
4287 | i915_gem_init_hw(struct drm_device *dev) |
4292 | i915_gem_init_hw(struct drm_device *dev) |
4288 | { |
4293 | { |
4289 | struct drm_i915_private *dev_priv = dev->dev_private; |
4294 | struct drm_i915_private *dev_priv = dev->dev_private; |
4290 | int ret, i; |
4295 | int ret, i; |
4291 | 4296 | ||
4292 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
4297 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
4293 | return -EIO; |
4298 | return -EIO; |
4294 | 4299 | ||
4295 | if (dev_priv->ellc_size) |
4300 | if (dev_priv->ellc_size) |
4296 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4301 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4297 | 4302 | ||
4298 | if (IS_HASWELL(dev)) |
4303 | if (IS_HASWELL(dev)) |
4299 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
4304 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
4300 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
4305 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
4301 | 4306 | ||
4302 | if (HAS_PCH_NOP(dev)) { |
4307 | if (HAS_PCH_NOP(dev)) { |
4303 | if (IS_IVYBRIDGE(dev)) { |
4308 | if (IS_IVYBRIDGE(dev)) { |
4304 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4309 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4305 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
4310 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
4306 | I915_WRITE(GEN7_MSG_CTL, temp); |
4311 | I915_WRITE(GEN7_MSG_CTL, temp); |
4307 | } else if (INTEL_INFO(dev)->gen >= 7) { |
4312 | } else if (INTEL_INFO(dev)->gen >= 7) { |
4308 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4313 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4309 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
4314 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
4310 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
4315 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
4311 | } |
4316 | } |
4312 | } |
4317 | } |
4313 | 4318 | ||
4314 | i915_gem_init_swizzling(dev); |
4319 | i915_gem_init_swizzling(dev); |
4315 | 4320 | ||
4316 | ret = dev_priv->gt.init_rings(dev); |
4321 | ret = dev_priv->gt.init_rings(dev); |
4317 | if (ret) |
4322 | if (ret) |
4318 | return ret; |
4323 | return ret; |
4319 | 4324 | ||
4320 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4325 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4321 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
4326 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
4322 | 4327 | ||
4323 | /* |
4328 | /* |
4324 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4329 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4325 | * default context switch however is something we'd like to do after |
4330 | * default context switch however is something we'd like to do after |
4326 | * reset or thaw (the latter may not actually be necessary for HW, but |
4331 | * reset or thaw (the latter may not actually be necessary for HW, but |
4327 | * goes with our code better). Context switching requires rings (for |
4332 | * goes with our code better). Context switching requires rings (for |
4328 | * the do_switch), but before enabling PPGTT. So don't move this. |
4333 | * the do_switch), but before enabling PPGTT. So don't move this. |
4329 | */ |
4334 | */ |
4330 | ret = i915_gem_context_enable(dev_priv); |
4335 | ret = i915_gem_context_enable(dev_priv); |
4331 | if (ret && ret != -EIO) { |
4336 | if (ret && ret != -EIO) { |
4332 | DRM_ERROR("Context enable failed %d\n", ret); |
4337 | DRM_ERROR("Context enable failed %d\n", ret); |
4333 | i915_gem_cleanup_ringbuffer(dev); |
4338 | i915_gem_cleanup_ringbuffer(dev); |
4334 | 4339 | ||
4335 | return ret; |
4340 | return ret; |
4336 | } |
4341 | } |
4337 | 4342 | ||
4338 | ret = i915_ppgtt_init_hw(dev); |
4343 | ret = i915_ppgtt_init_hw(dev); |
4339 | if (ret && ret != -EIO) { |
4344 | if (ret && ret != -EIO) { |
4340 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
4345 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
4341 | i915_gem_cleanup_ringbuffer(dev); |
4346 | i915_gem_cleanup_ringbuffer(dev); |
4342 | } |
4347 | } |
4343 | 4348 | ||
4344 | return ret; |
4349 | return ret; |
4345 | } |
4350 | } |
4346 | 4351 | ||
4347 | int i915_gem_init(struct drm_device *dev) |
4352 | int i915_gem_init(struct drm_device *dev) |
4348 | { |
4353 | { |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; |
4354 | struct drm_i915_private *dev_priv = dev->dev_private; |
4350 | int ret; |
4355 | int ret; |
4351 | 4356 | ||
4352 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4357 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4353 | i915.enable_execlists); |
4358 | i915.enable_execlists); |
4354 | 4359 | ||
4355 | mutex_lock(&dev->struct_mutex); |
4360 | mutex_lock(&dev->struct_mutex); |
4356 | 4361 | ||
4357 | if (IS_VALLEYVIEW(dev)) { |
4362 | if (IS_VALLEYVIEW(dev)) { |
4358 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
4363 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
4359 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4364 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4360 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
4365 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
4361 | VLV_GTLC_ALLOWWAKEACK), 10)) |
4366 | VLV_GTLC_ALLOWWAKEACK), 10)) |
4362 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4367 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4363 | } |
4368 | } |
4364 | 4369 | ||
4365 | if (!i915.enable_execlists) { |
4370 | if (!i915.enable_execlists) { |
4366 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; |
4371 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; |
4367 | dev_priv->gt.init_rings = i915_gem_init_rings; |
4372 | dev_priv->gt.init_rings = i915_gem_init_rings; |
4368 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
4373 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
4369 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
4374 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
4370 | } else { |
4375 | } else { |
4371 | dev_priv->gt.do_execbuf = intel_execlists_submission; |
4376 | dev_priv->gt.do_execbuf = intel_execlists_submission; |
4372 | dev_priv->gt.init_rings = intel_logical_rings_init; |
4377 | dev_priv->gt.init_rings = intel_logical_rings_init; |
4373 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
4378 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
4374 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
4379 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
4375 | } |
4380 | } |
4376 | 4381 | ||
4377 | // ret = i915_gem_init_userptr(dev); |
4382 | // ret = i915_gem_init_userptr(dev); |
4378 | // if (ret) { |
4383 | // if (ret) { |
4379 | // mutex_unlock(&dev->struct_mutex); |
4384 | // mutex_unlock(&dev->struct_mutex); |
4380 | // return ret; |
4385 | // return ret; |
4381 | // } |
4386 | // } |
4382 | 4387 | ||
4383 | i915_gem_init_global_gtt(dev); |
4388 | i915_gem_init_global_gtt(dev); |
4384 | 4389 | ||
4385 | ret = i915_gem_context_init(dev); |
4390 | ret = i915_gem_context_init(dev); |
4386 | if (ret) { |
4391 | if (ret) { |
4387 | mutex_unlock(&dev->struct_mutex); |
4392 | mutex_unlock(&dev->struct_mutex); |
4388 | return ret; |
4393 | return ret; |
4389 | } |
4394 | } |
4390 | 4395 | ||
4391 | ret = i915_gem_init_hw(dev); |
4396 | ret = i915_gem_init_hw(dev); |
4392 | if (ret == -EIO) { |
4397 | if (ret == -EIO) { |
4393 | /* Allow ring initialisation to fail by marking the GPU as |
4398 | /* Allow ring initialisation to fail by marking the GPU as |
4394 | * wedged. But we only want to do this where the GPU is angry, |
4399 | * wedged. But we only want to do this where the GPU is angry, |
4395 | * for all other failure, such as an allocation failure, bail. |
4400 | * for all other failure, such as an allocation failure, bail. |
4396 | */ |
4401 | */ |
4397 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
4402 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
4398 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
4403 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
4399 | ret = 0; |
4404 | ret = 0; |
4400 | } |
4405 | } |
4401 | mutex_unlock(&dev->struct_mutex); |
4406 | mutex_unlock(&dev->struct_mutex); |
4402 | 4407 | ||
4403 | return ret; |
4408 | return ret; |
4404 | } |
4409 | } |
4405 | 4410 | ||
4406 | void |
4411 | void |
4407 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4412 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4408 | { |
4413 | { |
4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
4414 | struct drm_i915_private *dev_priv = dev->dev_private; |
4410 | struct intel_engine_cs *ring; |
4415 | struct intel_engine_cs *ring; |
4411 | int i; |
4416 | int i; |
4412 | 4417 | ||
4413 | for_each_ring(ring, dev_priv, i) |
4418 | for_each_ring(ring, dev_priv, i) |
4414 | dev_priv->gt.cleanup_ring(ring); |
4419 | dev_priv->gt.cleanup_ring(ring); |
4415 | } |
4420 | } |
4416 | 4421 | ||
4417 | static void |
4422 | static void |
4418 | init_ring_lists(struct intel_engine_cs *ring) |
4423 | init_ring_lists(struct intel_engine_cs *ring) |
4419 | { |
4424 | { |
4420 | INIT_LIST_HEAD(&ring->active_list); |
4425 | INIT_LIST_HEAD(&ring->active_list); |
4421 | INIT_LIST_HEAD(&ring->request_list); |
4426 | INIT_LIST_HEAD(&ring->request_list); |
4422 | } |
4427 | } |
4423 | 4428 | ||
4424 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4429 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4425 | struct i915_address_space *vm) |
4430 | struct i915_address_space *vm) |
4426 | { |
4431 | { |
4427 | if (!i915_is_ggtt(vm)) |
4432 | if (!i915_is_ggtt(vm)) |
4428 | drm_mm_init(&vm->mm, vm->start, vm->total); |
4433 | drm_mm_init(&vm->mm, vm->start, vm->total); |
4429 | vm->dev = dev_priv->dev; |
4434 | vm->dev = dev_priv->dev; |
4430 | INIT_LIST_HEAD(&vm->active_list); |
4435 | INIT_LIST_HEAD(&vm->active_list); |
4431 | INIT_LIST_HEAD(&vm->inactive_list); |
4436 | INIT_LIST_HEAD(&vm->inactive_list); |
4432 | INIT_LIST_HEAD(&vm->global_link); |
4437 | INIT_LIST_HEAD(&vm->global_link); |
4433 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
4438 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
4434 | } |
4439 | } |
4435 | 4440 | ||
4436 | void |
4441 | void |
4437 | i915_gem_load(struct drm_device *dev) |
4442 | i915_gem_load(struct drm_device *dev) |
4438 | { |
4443 | { |
4439 | struct drm_i915_private *dev_priv = dev->dev_private; |
4444 | struct drm_i915_private *dev_priv = dev->dev_private; |
4440 | int i; |
4445 | int i; |
4441 | 4446 | ||
4442 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4447 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4443 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
4448 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
4444 | 4449 | ||
4445 | INIT_LIST_HEAD(&dev_priv->context_list); |
4450 | INIT_LIST_HEAD(&dev_priv->context_list); |
4446 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4451 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4447 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
4452 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
4448 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4453 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4449 | for (i = 0; i < I915_NUM_RINGS; i++) |
4454 | for (i = 0; i < I915_NUM_RINGS; i++) |
4450 | init_ring_lists(&dev_priv->ring[i]); |
4455 | init_ring_lists(&dev_priv->ring[i]); |
4451 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
4456 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
4452 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
4457 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
4453 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4458 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4454 | i915_gem_retire_work_handler); |
4459 | i915_gem_retire_work_handler); |
4455 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4460 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4456 | i915_gem_idle_work_handler); |
4461 | i915_gem_idle_work_handler); |
4457 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
4462 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
4458 | 4463 | ||
4459 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4464 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4460 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
4465 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
4461 | I915_WRITE(MI_ARB_STATE, |
4466 | I915_WRITE(MI_ARB_STATE, |
4462 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
4467 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
4463 | } |
4468 | } |
4464 | 4469 | ||
4465 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4470 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4466 | 4471 | ||
4467 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
4472 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
4468 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4473 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4469 | dev_priv->fence_reg_start = 3; |
4474 | dev_priv->fence_reg_start = 3; |
4470 | 4475 | ||
4471 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4476 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4472 | dev_priv->num_fence_regs = 32; |
4477 | dev_priv->num_fence_regs = 32; |
4473 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4478 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4474 | dev_priv->num_fence_regs = 16; |
4479 | dev_priv->num_fence_regs = 16; |
4475 | else |
4480 | else |
4476 | dev_priv->num_fence_regs = 8; |
4481 | dev_priv->num_fence_regs = 8; |
4477 | 4482 | ||
4478 | /* Initialize fence registers to zero */ |
4483 | /* Initialize fence registers to zero */ |
4479 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4484 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4480 | i915_gem_restore_fences(dev); |
4485 | i915_gem_restore_fences(dev); |
4481 | 4486 | ||
4482 | i915_gem_detect_bit_6_swizzle(dev); |
4487 | i915_gem_detect_bit_6_swizzle(dev); |
4483 | 4488 | ||
4484 | dev_priv->mm.interruptible = true; |
4489 | dev_priv->mm.interruptible = true; |
4485 | 4490 | ||
4486 | mutex_init(&dev_priv->fb_tracking.lock); |
4491 | mutex_init(&dev_priv->fb_tracking.lock); |
4487 | } |
4492 | } |
4488 | 4493 | ||
4489 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
4494 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
4490 | { |
4495 | { |
4491 | struct drm_i915_file_private *file_priv; |
4496 | struct drm_i915_file_private *file_priv; |
4492 | int ret; |
4497 | int ret; |
4493 | 4498 | ||
4494 | DRM_DEBUG_DRIVER("\n"); |
4499 | DRM_DEBUG_DRIVER("\n"); |
4495 | 4500 | ||
4496 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
4501 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
4497 | if (!file_priv) |
4502 | if (!file_priv) |
4498 | return -ENOMEM; |
4503 | return -ENOMEM; |
4499 | 4504 | ||
4500 | file->driver_priv = file_priv; |
4505 | file->driver_priv = file_priv; |
4501 | file_priv->dev_priv = dev->dev_private; |
4506 | file_priv->dev_priv = dev->dev_private; |
4502 | file_priv->file = file; |
4507 | file_priv->file = file; |
4503 | 4508 | ||
4504 | spin_lock_init(&file_priv->mm.lock); |
4509 | spin_lock_init(&file_priv->mm.lock); |
4505 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
4510 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
4506 | // INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
4511 | // INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
4507 | // i915_gem_file_idle_work_handler); |
4512 | // i915_gem_file_idle_work_handler); |
4508 | 4513 | ||
4509 | ret = i915_gem_context_open(dev, file); |
4514 | ret = i915_gem_context_open(dev, file); |
4510 | if (ret) |
4515 | if (ret) |
4511 | kfree(file_priv); |
4516 | kfree(file_priv); |
4512 | 4517 | ||
4513 | return ret; |
4518 | return ret; |
4514 | } |
4519 | } |
4515 | 4520 | ||
4516 | /** |
4521 | /** |
4517 | * i915_gem_track_fb - update frontbuffer tracking |
4522 | * i915_gem_track_fb - update frontbuffer tracking |
4518 | * old: current GEM buffer for the frontbuffer slots |
4523 | * old: current GEM buffer for the frontbuffer slots |
4519 | * new: new GEM buffer for the frontbuffer slots |
4524 | * new: new GEM buffer for the frontbuffer slots |
4520 | * frontbuffer_bits: bitmask of frontbuffer slots |
4525 | * frontbuffer_bits: bitmask of frontbuffer slots |
4521 | * |
4526 | * |
4522 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
4527 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
4523 | * from @old and setting them in @new. Both @old and @new can be NULL. |
4528 | * from @old and setting them in @new. Both @old and @new can be NULL. |
4524 | */ |
4529 | */ |
4525 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4530 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4526 | struct drm_i915_gem_object *new, |
4531 | struct drm_i915_gem_object *new, |
4527 | unsigned frontbuffer_bits) |
4532 | unsigned frontbuffer_bits) |
4528 | { |
4533 | { |
4529 | if (old) { |
4534 | if (old) { |
4530 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
4535 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
4531 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
4536 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
4532 | old->frontbuffer_bits &= ~frontbuffer_bits; |
4537 | old->frontbuffer_bits &= ~frontbuffer_bits; |
4533 | } |
4538 | } |
4534 | 4539 | ||
4535 | if (new) { |
4540 | if (new) { |
4536 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
4541 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
4537 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
4542 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
4538 | new->frontbuffer_bits |= frontbuffer_bits; |
4543 | new->frontbuffer_bits |= frontbuffer_bits; |
4539 | } |
4544 | } |
4540 | } |
4545 | } |
4541 | 4546 | ||
4542 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4547 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4543 | { |
4548 | { |
4544 | if (!mutex_is_locked(mutex)) |
4549 | if (!mutex_is_locked(mutex)) |
4545 | return false; |
4550 | return false; |
4546 | 4551 | ||
4547 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
4552 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
4548 | return mutex->owner == task; |
4553 | return mutex->owner == task; |
4549 | #else |
4554 | #else |
4550 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
4555 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
4551 | return false; |
4556 | return false; |
4552 | #endif |
4557 | #endif |
4553 | } |
4558 | } |
4554 | 4559 | ||
4555 | /* All the new VM stuff */ |
4560 | /* All the new VM stuff */ |
4556 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4561 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4557 | struct i915_address_space *vm) |
4562 | struct i915_address_space *vm) |
4558 | { |
4563 | { |
4559 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4564 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4560 | struct i915_vma *vma; |
4565 | struct i915_vma *vma; |
4561 | 4566 | ||
4562 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
4567 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
4563 | 4568 | ||
4564 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
4569 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
4565 | if (vma->vm == vm) |
4570 | if (vma->vm == vm) |
4566 | return vma->node.start; |
4571 | return vma->node.start; |
4567 | 4572 | ||
4568 | } |
4573 | } |
4569 | WARN(1, "%s vma for this object not found.\n", |
4574 | WARN(1, "%s vma for this object not found.\n", |
4570 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
4575 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
4571 | return -1; |
4576 | return -1; |
4572 | } |
4577 | } |
4573 | 4578 | ||
4574 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
4579 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
4575 | struct i915_address_space *vm) |
4580 | struct i915_address_space *vm) |
4576 | { |
4581 | { |
4577 | struct i915_vma *vma; |
4582 | struct i915_vma *vma; |
4578 | 4583 | ||
4579 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4584 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4580 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
4585 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
4581 | return true; |
4586 | return true; |
4582 | 4587 | ||
4583 | return false; |
4588 | return false; |
4584 | } |
4589 | } |
4585 | 4590 | ||
4586 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
4591 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
4587 | { |
4592 | { |
4588 | struct i915_vma *vma; |
4593 | struct i915_vma *vma; |
4589 | 4594 | ||
4590 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4595 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4591 | if (drm_mm_node_allocated(&vma->node)) |
4596 | if (drm_mm_node_allocated(&vma->node)) |
4592 | return true; |
4597 | return true; |
4593 | 4598 | ||
4594 | return false; |
4599 | return false; |
4595 | } |
4600 | } |
4596 | 4601 | ||
4597 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
4602 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
4598 | struct i915_address_space *vm) |
4603 | struct i915_address_space *vm) |
4599 | { |
4604 | { |
4600 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4605 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
4601 | struct i915_vma *vma; |
4606 | struct i915_vma *vma; |
4602 | 4607 | ||
4603 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
4608 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
4604 | 4609 | ||
4605 | BUG_ON(list_empty(&o->vma_list)); |
4610 | BUG_ON(list_empty(&o->vma_list)); |
4606 | 4611 | ||
4607 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4612 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4608 | if (vma->vm == vm) |
4613 | if (vma->vm == vm) |
4609 | return vma->node.size; |
4614 | return vma->node.size; |
4610 | 4615 | ||
4611 | return 0; |
4616 | return 0; |
4612 | } |
4617 | } |
4613 | 4618 | ||
4614 | 4619 | ||
4615 | 4620 | ||
4616 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
4621 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
4617 | { |
4622 | { |
4618 | struct i915_vma *vma; |
4623 | struct i915_vma *vma; |
4619 | 4624 | ||
4620 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
4625 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
4621 | if (vma->vm != i915_obj_to_ggtt(obj)) |
4626 | if (vma->vm != i915_obj_to_ggtt(obj)) |
4622 | return NULL; |
4627 | return NULL; |
4623 | 4628 | ||
4624 | return vma; |
4629 | return vma; |
4625 | }>>>>>>>><>=>= |
4630 | }>>>>>>>><>=>= |
4626 | >>>>><>><>>><>><>><>><>><>=>=>=0>>=>>>>=><=>>><>=>><>=>> |
4631 | >>>>><>><>>><>><>><>><>><>=>=>=0>>=>>>>=><=>>><>=>><>=>> |