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1 | /************************************************************************** |
1 | /************************************************************************** |
2 | 2 | ||
3 | Copyright © 2006 Dave Airlie |
3 | Copyright © 2006 Dave Airlie |
4 | 4 | ||
5 | All Rights Reserved. |
5 | All Rights Reserved. |
6 | 6 | ||
7 | Permission is hereby granted, free of charge, to any person obtaining a |
7 | Permission is hereby granted, free of charge, to any person obtaining a |
8 | copy of this software and associated documentation files (the |
8 | copy of this software and associated documentation files (the |
9 | "Software"), to deal in the Software without restriction, including |
9 | "Software"), to deal in the Software without restriction, including |
10 | without limitation the rights to use, copy, modify, merge, publish, |
10 | without limitation the rights to use, copy, modify, merge, publish, |
11 | distribute, sub license, and/or sell copies of the Software, and to |
11 | distribute, sub license, and/or sell copies of the Software, and to |
12 | permit persons to whom the Software is furnished to do so, subject to |
12 | permit persons to whom the Software is furnished to do so, subject to |
13 | the following conditions: |
13 | the following conditions: |
14 | 14 | ||
15 | The above copyright notice and this permission notice (including the |
15 | The above copyright notice and this permission notice (including the |
16 | next paragraph) shall be included in all copies or substantial portions |
16 | next paragraph) shall be included in all copies or substantial portions |
17 | of the Software. |
17 | of the Software. |
18 | 18 | ||
19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
19 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
20 | OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
20 | OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
21 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
21 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
22 | IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
22 | IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
23 | ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
23 | ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
24 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
24 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
25 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
25 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
26 | 26 | ||
27 | **************************************************************************/ |
27 | **************************************************************************/ |
28 | 28 | ||
29 | #include "dvo.h" |
29 | #include "dvo.h" |
30 | 30 | ||
31 | #define CH7xxx_REG_VID 0x4a |
31 | #define CH7xxx_REG_VID 0x4a |
32 | #define CH7xxx_REG_DID 0x4b |
32 | #define CH7xxx_REG_DID 0x4b |
33 | 33 | ||
34 | #define CH7011_VID 0x83 /* 7010 as well */ |
34 | #define CH7011_VID 0x83 /* 7010 as well */ |
35 | #define CH7010B_VID 0x05 |
35 | #define CH7010B_VID 0x05 |
36 | #define CH7009A_VID 0x84 |
36 | #define CH7009A_VID 0x84 |
37 | #define CH7009B_VID 0x85 |
37 | #define CH7009B_VID 0x85 |
38 | #define CH7301_VID 0x95 |
38 | #define CH7301_VID 0x95 |
39 | 39 | ||
40 | #define CH7xxx_VID 0x84 |
40 | #define CH7xxx_VID 0x84 |
41 | #define CH7xxx_DID 0x17 |
41 | #define CH7xxx_DID 0x17 |
42 | #define CH7010_DID 0x16 |
42 | #define CH7010_DID 0x16 |
43 | 43 | ||
44 | #define CH7xxx_NUM_REGS 0x4c |
44 | #define CH7xxx_NUM_REGS 0x4c |
45 | 45 | ||
46 | #define CH7xxx_CM 0x1c |
46 | #define CH7xxx_CM 0x1c |
47 | #define CH7xxx_CM_XCM (1<<0) |
47 | #define CH7xxx_CM_XCM (1<<0) |
48 | #define CH7xxx_CM_MCP (1<<2) |
48 | #define CH7xxx_CM_MCP (1<<2) |
49 | #define CH7xxx_INPUT_CLOCK 0x1d |
49 | #define CH7xxx_INPUT_CLOCK 0x1d |
50 | #define CH7xxx_GPIO 0x1e |
50 | #define CH7xxx_GPIO 0x1e |
51 | #define CH7xxx_GPIO_HPIR (1<<3) |
51 | #define CH7xxx_GPIO_HPIR (1<<3) |
52 | #define CH7xxx_IDF 0x1f |
52 | #define CH7xxx_IDF 0x1f |
53 | 53 | ||
54 | #define CH7xxx_IDF_HSP (1<<3) |
54 | #define CH7xxx_IDF_HSP (1<<3) |
55 | #define CH7xxx_IDF_VSP (1<<4) |
55 | #define CH7xxx_IDF_VSP (1<<4) |
56 | 56 | ||
57 | #define CH7xxx_CONNECTION_DETECT 0x20 |
57 | #define CH7xxx_CONNECTION_DETECT 0x20 |
58 | #define CH7xxx_CDET_DVI (1<<5) |
58 | #define CH7xxx_CDET_DVI (1<<5) |
59 | 59 | ||
60 | #define CH7301_DAC_CNTL 0x21 |
60 | #define CH7301_DAC_CNTL 0x21 |
61 | #define CH7301_HOTPLUG 0x23 |
61 | #define CH7301_HOTPLUG 0x23 |
62 | #define CH7xxx_TCTL 0x31 |
62 | #define CH7xxx_TCTL 0x31 |
63 | #define CH7xxx_TVCO 0x32 |
63 | #define CH7xxx_TVCO 0x32 |
64 | #define CH7xxx_TPCP 0x33 |
64 | #define CH7xxx_TPCP 0x33 |
65 | #define CH7xxx_TPD 0x34 |
65 | #define CH7xxx_TPD 0x34 |
66 | #define CH7xxx_TPVT 0x35 |
66 | #define CH7xxx_TPVT 0x35 |
67 | #define CH7xxx_TLPF 0x36 |
67 | #define CH7xxx_TLPF 0x36 |
68 | #define CH7xxx_TCT 0x37 |
68 | #define CH7xxx_TCT 0x37 |
69 | #define CH7301_TEST_PATTERN 0x48 |
69 | #define CH7301_TEST_PATTERN 0x48 |
70 | 70 | ||
71 | #define CH7xxx_PM 0x49 |
71 | #define CH7xxx_PM 0x49 |
72 | #define CH7xxx_PM_FPD (1<<0) |
72 | #define CH7xxx_PM_FPD (1<<0) |
73 | #define CH7301_PM_DACPD0 (1<<1) |
73 | #define CH7301_PM_DACPD0 (1<<1) |
74 | #define CH7301_PM_DACPD1 (1<<2) |
74 | #define CH7301_PM_DACPD1 (1<<2) |
75 | #define CH7301_PM_DACPD2 (1<<3) |
75 | #define CH7301_PM_DACPD2 (1<<3) |
76 | #define CH7xxx_PM_DVIL (1<<6) |
76 | #define CH7xxx_PM_DVIL (1<<6) |
77 | #define CH7xxx_PM_DVIP (1<<7) |
77 | #define CH7xxx_PM_DVIP (1<<7) |
78 | 78 | ||
79 | #define CH7301_SYNC_POLARITY 0x56 |
79 | #define CH7301_SYNC_POLARITY 0x56 |
80 | #define CH7301_SYNC_RGB_YUV (1<<0) |
80 | #define CH7301_SYNC_RGB_YUV (1<<0) |
81 | #define CH7301_SYNC_POL_DVI (1<<5) |
81 | #define CH7301_SYNC_POL_DVI (1<<5) |
82 | 82 | ||
83 | /** @file |
83 | /** @file |
84 | * driver for the Chrontel 7xxx DVI chip over DVO. |
84 | * driver for the Chrontel 7xxx DVI chip over DVO. |
85 | */ |
85 | */ |
86 | 86 | ||
87 | static struct ch7xxx_id_struct { |
87 | static struct ch7xxx_id_struct { |
88 | uint8_t vid; |
88 | uint8_t vid; |
89 | char *name; |
89 | char *name; |
90 | } ch7xxx_ids[] = { |
90 | } ch7xxx_ids[] = { |
91 | { CH7011_VID, "CH7011" }, |
91 | { CH7011_VID, "CH7011" }, |
92 | { CH7010B_VID, "CH7010B" }, |
92 | { CH7010B_VID, "CH7010B" }, |
93 | { CH7009A_VID, "CH7009A" }, |
93 | { CH7009A_VID, "CH7009A" }, |
94 | { CH7009B_VID, "CH7009B" }, |
94 | { CH7009B_VID, "CH7009B" }, |
95 | { CH7301_VID, "CH7301" }, |
95 | { CH7301_VID, "CH7301" }, |
96 | }; |
96 | }; |
97 | 97 | ||
98 | static struct ch7xxx_did_struct { |
98 | static struct ch7xxx_did_struct { |
99 | uint8_t did; |
99 | uint8_t did; |
100 | char *name; |
100 | char *name; |
101 | } ch7xxx_dids[] = { |
101 | } ch7xxx_dids[] = { |
102 | { CH7xxx_DID, "CH7XXX" }, |
102 | { CH7xxx_DID, "CH7XXX" }, |
103 | { CH7010_DID, "CH7010B" }, |
103 | { CH7010_DID, "CH7010B" }, |
104 | }; |
104 | }; |
105 | 105 | ||
106 | struct ch7xxx_priv { |
106 | struct ch7xxx_priv { |
107 | bool quiet; |
107 | bool quiet; |
108 | }; |
108 | }; |
109 | 109 | ||
110 | static char *ch7xxx_get_id(uint8_t vid) |
110 | static char *ch7xxx_get_id(uint8_t vid) |
111 | { |
111 | { |
112 | int i; |
112 | int i; |
113 | 113 | ||
114 | for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { |
114 | for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { |
115 | if (ch7xxx_ids[i].vid == vid) |
115 | if (ch7xxx_ids[i].vid == vid) |
116 | return ch7xxx_ids[i].name; |
116 | return ch7xxx_ids[i].name; |
117 | } |
117 | } |
118 | 118 | ||
119 | return NULL; |
119 | return NULL; |
120 | } |
120 | } |
121 | 121 | ||
122 | static char *ch7xxx_get_did(uint8_t did) |
122 | static char *ch7xxx_get_did(uint8_t did) |
123 | { |
123 | { |
124 | int i; |
124 | int i; |
125 | 125 | ||
126 | for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) { |
126 | for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) { |
127 | if (ch7xxx_dids[i].did == did) |
127 | if (ch7xxx_dids[i].did == did) |
128 | return ch7xxx_dids[i].name; |
128 | return ch7xxx_dids[i].name; |
129 | } |
129 | } |
130 | 130 | ||
131 | return NULL; |
131 | return NULL; |
132 | } |
132 | } |
133 | 133 | ||
134 | /** Reads an 8 bit register */ |
134 | /** Reads an 8 bit register */ |
135 | static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) |
135 | static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) |
136 | { |
136 | { |
137 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
137 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
138 | struct i2c_adapter *adapter = dvo->i2c_bus; |
138 | struct i2c_adapter *adapter = dvo->i2c_bus; |
139 | u8 out_buf[2]; |
139 | u8 out_buf[2]; |
140 | u8 in_buf[2]; |
140 | u8 in_buf[2]; |
141 | 141 | ||
142 | struct i2c_msg msgs[] = { |
142 | struct i2c_msg msgs[] = { |
143 | { |
143 | { |
144 | .addr = dvo->slave_addr, |
144 | .addr = dvo->slave_addr, |
145 | .flags = 0, |
145 | .flags = 0, |
146 | .len = 1, |
146 | .len = 1, |
147 | .buf = out_buf, |
147 | .buf = out_buf, |
148 | }, |
148 | }, |
149 | { |
149 | { |
150 | .addr = dvo->slave_addr, |
150 | .addr = dvo->slave_addr, |
151 | .flags = I2C_M_RD, |
151 | .flags = I2C_M_RD, |
152 | .len = 1, |
152 | .len = 1, |
153 | .buf = in_buf, |
153 | .buf = in_buf, |
154 | } |
154 | } |
155 | }; |
155 | }; |
156 | 156 | ||
157 | out_buf[0] = addr; |
157 | out_buf[0] = addr; |
158 | out_buf[1] = 0; |
158 | out_buf[1] = 0; |
159 | 159 | ||
160 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
160 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
161 | *ch = in_buf[0]; |
161 | *ch = in_buf[0]; |
162 | return true; |
162 | return true; |
163 | } |
163 | } |
164 | 164 | ||
165 | if (!ch7xxx->quiet) { |
165 | if (!ch7xxx->quiet) { |
166 | DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", |
166 | DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", |
167 | addr, adapter->name, dvo->slave_addr); |
167 | addr, adapter->name, dvo->slave_addr); |
168 | } |
168 | } |
169 | return false; |
169 | return false; |
170 | } |
170 | } |
171 | 171 | ||
172 | /** Writes an 8 bit register */ |
172 | /** Writes an 8 bit register */ |
173 | static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) |
173 | static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) |
174 | { |
174 | { |
175 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
175 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
176 | struct i2c_adapter *adapter = dvo->i2c_bus; |
176 | struct i2c_adapter *adapter = dvo->i2c_bus; |
177 | uint8_t out_buf[2]; |
177 | uint8_t out_buf[2]; |
178 | struct i2c_msg msg = { |
178 | struct i2c_msg msg = { |
179 | .addr = dvo->slave_addr, |
179 | .addr = dvo->slave_addr, |
180 | .flags = 0, |
180 | .flags = 0, |
181 | .len = 2, |
181 | .len = 2, |
182 | .buf = out_buf, |
182 | .buf = out_buf, |
183 | }; |
183 | }; |
184 | 184 | ||
185 | out_buf[0] = addr; |
185 | out_buf[0] = addr; |
186 | out_buf[1] = ch; |
186 | out_buf[1] = ch; |
187 | 187 | ||
188 | if (i2c_transfer(adapter, &msg, 1) == 1) |
188 | if (i2c_transfer(adapter, &msg, 1) == 1) |
189 | return true; |
189 | return true; |
190 | 190 | ||
191 | if (!ch7xxx->quiet) { |
191 | if (!ch7xxx->quiet) { |
192 | DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", |
192 | DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", |
193 | addr, adapter->name, dvo->slave_addr); |
193 | addr, adapter->name, dvo->slave_addr); |
194 | } |
194 | } |
195 | 195 | ||
196 | return false; |
196 | return false; |
197 | } |
197 | } |
198 | 198 | ||
199 | static bool ch7xxx_init(struct intel_dvo_device *dvo, |
199 | static bool ch7xxx_init(struct intel_dvo_device *dvo, |
200 | struct i2c_adapter *adapter) |
200 | struct i2c_adapter *adapter) |
201 | { |
201 | { |
202 | /* this will detect the CH7xxx chip on the specified i2c bus */ |
202 | /* this will detect the CH7xxx chip on the specified i2c bus */ |
203 | struct ch7xxx_priv *ch7xxx; |
203 | struct ch7xxx_priv *ch7xxx; |
204 | uint8_t vendor, device; |
204 | uint8_t vendor, device; |
205 | char *name, *devid; |
205 | char *name, *devid; |
206 | 206 | ||
207 | ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); |
207 | ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); |
208 | if (ch7xxx == NULL) |
208 | if (ch7xxx == NULL) |
209 | return false; |
209 | return false; |
210 | 210 | ||
211 | dvo->i2c_bus = adapter; |
211 | dvo->i2c_bus = adapter; |
212 | dvo->dev_priv = ch7xxx; |
212 | dvo->dev_priv = ch7xxx; |
213 | ch7xxx->quiet = true; |
213 | ch7xxx->quiet = true; |
214 | 214 | ||
215 | if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) |
215 | if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) |
216 | goto out; |
216 | goto out; |
217 | 217 | ||
218 | name = ch7xxx_get_id(vendor); |
218 | name = ch7xxx_get_id(vendor); |
219 | if (!name) { |
219 | if (!name) { |
220 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
220 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
221 | "slave %d.\n", |
221 | "slave %d.\n", |
222 | vendor, adapter->name, dvo->slave_addr); |
222 | vendor, adapter->name, dvo->slave_addr); |
223 | goto out; |
223 | goto out; |
224 | } |
224 | } |
225 | 225 | ||
226 | 226 | ||
227 | if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) |
227 | if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) |
228 | goto out; |
228 | goto out; |
229 | 229 | ||
230 | devid = ch7xxx_get_did(device); |
230 | devid = ch7xxx_get_did(device); |
231 | if (!devid) { |
231 | if (!devid) { |
232 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
232 | DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " |
233 | "slave %d.\n", |
233 | "slave %d.\n", |
234 | vendor, adapter->name, dvo->slave_addr); |
234 | vendor, adapter->name, dvo->slave_addr); |
235 | goto out; |
235 | goto out; |
236 | } |
236 | } |
237 | 237 | ||
238 | ch7xxx->quiet = false; |
238 | ch7xxx->quiet = false; |
239 | DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", |
239 | DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", |
240 | name, vendor, device); |
240 | name, vendor, device); |
241 | return true; |
241 | return true; |
242 | out: |
242 | out: |
243 | kfree(ch7xxx); |
243 | kfree(ch7xxx); |
244 | return false; |
244 | return false; |
245 | } |
245 | } |
246 | 246 | ||
247 | static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) |
247 | static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) |
248 | { |
248 | { |
249 | uint8_t cdet, orig_pm, pm; |
249 | uint8_t cdet, orig_pm, pm; |
250 | 250 | ||
251 | ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); |
251 | ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); |
252 | 252 | ||
253 | pm = orig_pm; |
253 | pm = orig_pm; |
254 | pm &= ~CH7xxx_PM_FPD; |
254 | pm &= ~CH7xxx_PM_FPD; |
255 | pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; |
255 | pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; |
256 | 256 | ||
257 | ch7xxx_writeb(dvo, CH7xxx_PM, pm); |
257 | ch7xxx_writeb(dvo, CH7xxx_PM, pm); |
258 | 258 | ||
259 | ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); |
259 | ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); |
260 | 260 | ||
261 | ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); |
261 | ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); |
262 | 262 | ||
263 | if (cdet & CH7xxx_CDET_DVI) |
263 | if (cdet & CH7xxx_CDET_DVI) |
264 | return connector_status_connected; |
264 | return connector_status_connected; |
265 | return connector_status_disconnected; |
265 | return connector_status_disconnected; |
266 | } |
266 | } |
267 | 267 | ||
268 | static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, |
268 | static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, |
269 | struct drm_display_mode *mode) |
269 | struct drm_display_mode *mode) |
270 | { |
270 | { |
271 | if (mode->clock > 165000) |
271 | if (mode->clock > 165000) |
272 | return MODE_CLOCK_HIGH; |
272 | return MODE_CLOCK_HIGH; |
273 | 273 | ||
274 | return MODE_OK; |
274 | return MODE_OK; |
275 | } |
275 | } |
276 | 276 | ||
277 | static void ch7xxx_mode_set(struct intel_dvo_device *dvo, |
277 | static void ch7xxx_mode_set(struct intel_dvo_device *dvo, |
278 | const struct drm_display_mode *mode, |
278 | const struct drm_display_mode *mode, |
279 | const struct drm_display_mode *adjusted_mode) |
279 | const struct drm_display_mode *adjusted_mode) |
280 | { |
280 | { |
281 | uint8_t tvco, tpcp, tpd, tlpf, idf; |
281 | uint8_t tvco, tpcp, tpd, tlpf, idf; |
282 | 282 | ||
283 | if (mode->clock <= 65000) { |
283 | if (mode->clock <= 65000) { |
284 | tvco = 0x23; |
284 | tvco = 0x23; |
285 | tpcp = 0x08; |
285 | tpcp = 0x08; |
286 | tpd = 0x16; |
286 | tpd = 0x16; |
287 | tlpf = 0x60; |
287 | tlpf = 0x60; |
288 | } else { |
288 | } else { |
289 | tvco = 0x2d; |
289 | tvco = 0x2d; |
290 | tpcp = 0x06; |
290 | tpcp = 0x06; |
291 | tpd = 0x26; |
291 | tpd = 0x26; |
292 | tlpf = 0xa0; |
292 | tlpf = 0xa0; |
293 | } |
293 | } |
294 | 294 | ||
295 | ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); |
295 | ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); |
296 | ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); |
296 | ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); |
297 | ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); |
297 | ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); |
298 | ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); |
298 | ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); |
299 | ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); |
299 | ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); |
300 | ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); |
300 | ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); |
301 | ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); |
301 | ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); |
302 | 302 | ||
303 | ch7xxx_readb(dvo, CH7xxx_IDF, &idf); |
303 | ch7xxx_readb(dvo, CH7xxx_IDF, &idf); |
304 | 304 | ||
305 | idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); |
305 | idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); |
306 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
306 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
307 | idf |= CH7xxx_IDF_HSP; |
307 | idf |= CH7xxx_IDF_HSP; |
308 | 308 | ||
309 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
309 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
310 | idf |= CH7xxx_IDF_VSP; |
310 | idf |= CH7xxx_IDF_VSP; |
311 | 311 | ||
312 | ch7xxx_writeb(dvo, CH7xxx_IDF, idf); |
312 | ch7xxx_writeb(dvo, CH7xxx_IDF, idf); |
313 | } |
313 | } |
314 | 314 | ||
315 | /* set the CH7xxx power state */ |
315 | /* set the CH7xxx power state */ |
316 | static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) |
316 | static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) |
317 | { |
317 | { |
318 | if (enable) |
318 | if (enable) |
319 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); |
319 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); |
320 | else |
320 | else |
321 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); |
321 | ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); |
322 | } |
322 | } |
323 | 323 | ||
324 | static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo) |
324 | static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo) |
325 | { |
325 | { |
326 | u8 val; |
326 | u8 val; |
327 | 327 | ||
328 | ch7xxx_readb(dvo, CH7xxx_PM, &val); |
328 | ch7xxx_readb(dvo, CH7xxx_PM, &val); |
329 | 329 | ||
330 | if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) |
330 | if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) |
331 | return true; |
331 | return true; |
332 | else |
332 | else |
333 | return false; |
333 | return false; |
334 | } |
334 | } |
335 | 335 | ||
336 | static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) |
336 | static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) |
337 | { |
337 | { |
338 | int i; |
338 | int i; |
339 | 339 | ||
340 | for (i = 0; i < CH7xxx_NUM_REGS; i++) { |
340 | for (i = 0; i < CH7xxx_NUM_REGS; i++) { |
341 | uint8_t val; |
341 | uint8_t val; |
342 | if ((i % 8) == 0) |
342 | if ((i % 8) == 0) |
343 | DRM_DEBUG_KMS("\n %02X: ", i); |
343 | DRM_DEBUG_KMS("\n %02X: ", i); |
344 | ch7xxx_readb(dvo, i, &val); |
344 | ch7xxx_readb(dvo, i, &val); |
345 | DRM_DEBUG_KMS("%02X ", val); |
345 | DRM_DEBUG_KMS("%02X ", val); |
346 | } |
346 | } |
347 | } |
347 | } |
348 | 348 | ||
349 | static void ch7xxx_destroy(struct intel_dvo_device *dvo) |
349 | static void ch7xxx_destroy(struct intel_dvo_device *dvo) |
350 | { |
350 | { |
351 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
351 | struct ch7xxx_priv *ch7xxx = dvo->dev_priv; |
352 | 352 | ||
353 | if (ch7xxx) { |
353 | if (ch7xxx) { |
354 | kfree(ch7xxx); |
354 | kfree(ch7xxx); |
355 | dvo->dev_priv = NULL; |
355 | dvo->dev_priv = NULL; |
356 | } |
356 | } |
357 | } |
357 | } |
358 | 358 | ||
359 | struct intel_dvo_dev_ops ch7xxx_ops = { |
359 | const struct intel_dvo_dev_ops ch7xxx_ops = { |
360 | .init = ch7xxx_init, |
360 | .init = ch7xxx_init, |
361 | .detect = ch7xxx_detect, |
361 | .detect = ch7xxx_detect, |
362 | .mode_valid = ch7xxx_mode_valid, |
362 | .mode_valid = ch7xxx_mode_valid, |
363 | .mode_set = ch7xxx_mode_set, |
363 | .mode_set = ch7xxx_mode_set, |
364 | .dpms = ch7xxx_dpms, |
364 | .dpms = ch7xxx_dpms, |
365 | .get_hw_state = ch7xxx_get_hw_state, |
365 | .get_hw_state = ch7xxx_get_hw_state, |
366 | .dump_regs = ch7xxx_dump_regs, |
366 | .dump_regs = ch7xxx_dump_regs, |
367 | .destroy = ch7xxx_destroy, |
367 | .destroy = ch7xxx_destroy, |
368 | };>=>>>5) |
368 | };>=>>>5) |
369 | 369 | ||
370 | /**><5) |
370 | /**><5) |
371 | 371 | ||
372 | /**>0) |
372 | /**>0) |
373 | #define><0) |
373 | #define><0) |
374 | #define>7) |
374 | #define>7) |
375 | 375 | ||
376 | #define><7) |
376 | #define><7) |
377 | 377 | ||
378 | #define>6) |
378 | #define>6) |
379 | #define><6) |
379 | #define><6) |
380 | #define>3) |
380 | #define>3) |
381 | #define><3) |
381 | #define><3) |
382 | #define>2) |
382 | #define>2) |
383 | #define><2) |
383 | #define><2) |
384 | #define>1) |
384 | #define>1) |
385 | #define><1) |
385 | #define><1) |
386 | #define>0) |
386 | #define>0) |
387 | #define><0) |
387 | #define><0) |
388 | #define>5) |
388 | #define>5) |
389 | 389 | ||
390 | #define><5) |
390 | #define><5) |
391 | 391 | ||
392 | #define>4) |
392 | #define>4) |
393 | 393 | ||
394 | #define><4) |
394 | #define><4) |
395 | 395 | ||
396 | #define>3) |
396 | #define>3) |
397 | #define><3) |
397 | #define><3) |
398 | #define>3) |
398 | #define>3) |
399 | #define><3) |
399 | #define><3) |
400 | #define>2) |
400 | #define>2) |
401 | #define><2) |
401 | #define><2) |
402 | #define>0) |
402 | #define>0) |
403 | #define><0) |
403 | #define><0) |
404 | #define> |
404 | #define> |