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1 | /* |
1 | /* |
2 | * pci.h |
2 | * pci.h |
3 | * |
3 | * |
4 | * PCI defines and function prototypes |
4 | * PCI defines and function prototypes |
5 | * Copyright 1994, Drew Eckhardt |
5 | * Copyright 1994, Drew Eckhardt |
6 | * Copyright 1997--1999 Martin Mares |
6 | * Copyright 1997--1999 Martin Mares |
7 | * |
7 | * |
8 | * For more information, please consult the following manuals (look at |
8 | * For more information, please consult the following manuals (look at |
9 | * http://www.pcisig.com/ for how to get them): |
9 | * http://www.pcisig.com/ for how to get them): |
10 | * |
10 | * |
11 | * PCI BIOS Specification |
11 | * PCI BIOS Specification |
12 | * PCI Local Bus Specification |
12 | * PCI Local Bus Specification |
13 | * PCI to PCI Bridge Specification |
13 | * PCI to PCI Bridge Specification |
14 | * PCI System Design Guide |
14 | * PCI System Design Guide |
15 | */ |
15 | */ |
16 | #ifndef LINUX_PCI_H |
16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H |
17 | #define LINUX_PCI_H |
18 | 18 | ||
19 | #include |
19 | #include |
20 | #include |
20 | #include |
21 | #include |
21 | #include |
22 | #include |
22 | #include |
23 | 23 | ||
24 | 24 | ||
25 | #define PCI_CFG_SPACE_SIZE 256 |
25 | #define PCI_CFG_SPACE_SIZE 256 |
26 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
26 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
27 | 27 | ||
28 | 28 | ||
29 | #define PCI_ANY_ID (~0) |
29 | #define PCI_ANY_ID (~0) |
30 | 30 | ||
31 | 31 | ||
32 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
32 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
33 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
33 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
34 | 34 | ||
35 | #define PCI_BASE_CLASS_STORAGE 0x01 |
35 | #define PCI_BASE_CLASS_STORAGE 0x01 |
36 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
36 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
37 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
37 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
38 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
38 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
39 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
39 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
40 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
40 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
41 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
41 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
42 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
42 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
43 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
43 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
44 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
44 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
45 | 45 | ||
46 | #define PCI_BASE_CLASS_NETWORK 0x02 |
46 | #define PCI_BASE_CLASS_NETWORK 0x02 |
47 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
47 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
48 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
48 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
49 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
49 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
50 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
50 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
51 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
51 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
52 | 52 | ||
53 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
53 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
54 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
54 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
55 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
55 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
56 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
56 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
57 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
57 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
58 | 58 | ||
59 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
59 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
60 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
60 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
61 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
61 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
62 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
62 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
63 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
63 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
64 | 64 | ||
65 | #define PCI_BASE_CLASS_MEMORY 0x05 |
65 | #define PCI_BASE_CLASS_MEMORY 0x05 |
66 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
66 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
67 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
67 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
68 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
68 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
69 | 69 | ||
70 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
70 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
71 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
71 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
72 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
72 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
73 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
73 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
74 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
74 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
75 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
75 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
76 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
76 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
77 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
77 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
78 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
78 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
79 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
79 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
80 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
80 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
81 | 81 | ||
82 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
82 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
83 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
83 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
84 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
84 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
85 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
85 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
86 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
86 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
87 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
87 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
88 | 88 | ||
89 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
89 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
90 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
90 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
91 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
91 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
92 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
92 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
93 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
93 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
94 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
94 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
95 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
95 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
96 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
96 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
97 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
97 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
98 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
98 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
99 | 99 | ||
100 | #define PCI_BASE_CLASS_INPUT 0x09 |
100 | #define PCI_BASE_CLASS_INPUT 0x09 |
101 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
101 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
102 | #define PCI_CLASS_INPUT_PEN 0x0901 |
102 | #define PCI_CLASS_INPUT_PEN 0x0901 |
103 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
103 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
104 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
104 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
105 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
105 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
106 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
106 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
107 | 107 | ||
108 | #define PCI_BASE_CLASS_DOCKING 0x0a |
108 | #define PCI_BASE_CLASS_DOCKING 0x0a |
109 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
109 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
110 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
110 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
111 | 111 | ||
112 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
112 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
113 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
113 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
114 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
114 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
115 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
115 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
116 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
116 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
117 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
117 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
118 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
118 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
119 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
119 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
120 | 120 | ||
121 | #define PCI_BASE_CLASS_SERIAL 0x0c |
121 | #define PCI_BASE_CLASS_SERIAL 0x0c |
122 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
122 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
123 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
123 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
124 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
124 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
125 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
125 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
126 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
126 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
127 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
127 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
128 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
128 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
129 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
129 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
130 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
130 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
131 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
131 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
132 | 132 | ||
133 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
133 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
134 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
134 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
135 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
135 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
136 | 136 | ||
137 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
137 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
138 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
138 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
139 | 139 | ||
140 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
140 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
141 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
141 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
142 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
142 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
143 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
143 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
144 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
144 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
145 | 145 | ||
146 | #define PCI_BASE_CLASS_CRYPT 0x10 |
146 | #define PCI_BASE_CLASS_CRYPT 0x10 |
147 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
147 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
148 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
148 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
149 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
149 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
150 | 150 | ||
151 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
151 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
152 | #define PCI_CLASS_SP_DPIO 0x1100 |
152 | #define PCI_CLASS_SP_DPIO 0x1100 |
153 | #define PCI_CLASS_SP_OTHER 0x1180 |
153 | #define PCI_CLASS_SP_OTHER 0x1180 |
154 | 154 | ||
155 | #define PCI_CLASS_OTHERS 0xff |
155 | #define PCI_CLASS_OTHERS 0xff |
156 | 156 | ||
157 | 157 | ||
158 | 158 | ||
159 | 159 | ||
160 | 160 | ||
161 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
161 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
162 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
162 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
163 | 163 | ||
164 | #define PCI_MAP_IS64BITMEM(b) \ |
164 | #define PCI_MAP_IS64BITMEM(b) \ |
165 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
165 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
166 | 166 | ||
167 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
167 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
168 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
168 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
169 | #define PCIGETMEMORY64(b) \ |
169 | #define PCIGETMEMORY64(b) \ |
170 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
170 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
171 | 171 | ||
172 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
172 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
173 | 173 | ||
174 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
174 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
175 | 175 | ||
176 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
176 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
177 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
177 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
178 | 178 | ||
179 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
179 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
180 | 180 | ||
181 | 181 | ||
182 | #ifndef PCI_DOM_MASK |
182 | #ifndef PCI_DOM_MASK |
183 | # define PCI_DOM_MASK 0x0ffu |
183 | # define PCI_DOM_MASK 0x0ffu |
184 | #endif |
184 | #endif |
185 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
185 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
186 | 186 | ||
187 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
187 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
188 | (((d) & 0x00001fu) << 11) | \ |
188 | (((d) & 0x00001fu) << 11) | \ |
189 | (((f) & 0x000007u) << 8)) |
189 | (((f) & 0x000007u) << 8)) |
190 | 190 | ||
191 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
191 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
192 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
192 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
193 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
193 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
194 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
194 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
195 | 195 | ||
196 | /* |
196 | /* |
197 | * The PCI interface treats multi-function devices as independent |
197 | * The PCI interface treats multi-function devices as independent |
198 | * devices. The slot/function address of each device is encoded |
198 | * devices. The slot/function address of each device is encoded |
199 | * in a single byte as follows: |
199 | * in a single byte as follows: |
200 | * |
200 | * |
201 | * 7:3 = slot |
201 | * 7:3 = slot |
202 | * 2:0 = function |
202 | * 2:0 = function |
203 | */ |
203 | */ |
204 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
204 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
205 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
205 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
206 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
206 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
207 | 207 | ||
208 | 208 | ||
209 | 209 | ||
210 | typedef unsigned int PCITAG; |
210 | typedef unsigned int PCITAG; |
211 | 211 | ||
212 | extern inline PCITAG |
212 | extern inline PCITAG |
213 | pciTag(int busnum, int devnum, int funcnum) |
213 | pciTag(int busnum, int devnum, int funcnum) |
214 | { |
214 | { |
215 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
215 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
216 | } |
216 | } |
217 | 217 | ||
218 | /* pci_slot represents a physical slot */ |
218 | /* pci_slot represents a physical slot */ |
219 | struct pci_slot { |
219 | struct pci_slot { |
220 | struct pci_bus *bus; /* The bus this slot is on */ |
220 | struct pci_bus *bus; /* The bus this slot is on */ |
221 | struct list_head list; /* node in list of slots on this bus */ |
221 | struct list_head list; /* node in list of slots on this bus */ |
222 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
222 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
223 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
223 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
224 | }; |
224 | }; |
225 | 225 | ||
226 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
226 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
227 | enum pci_mmap_state { |
227 | enum pci_mmap_state { |
228 | pci_mmap_io, |
228 | pci_mmap_io, |
229 | pci_mmap_mem |
229 | pci_mmap_mem |
230 | }; |
230 | }; |
231 | 231 | ||
232 | /* This defines the direction arg to the DMA mapping routines. */ |
232 | /* This defines the direction arg to the DMA mapping routines. */ |
233 | #define PCI_DMA_BIDIRECTIONAL 0 |
233 | #define PCI_DMA_BIDIRECTIONAL 0 |
234 | #define PCI_DMA_TODEVICE 1 |
234 | #define PCI_DMA_TODEVICE 1 |
235 | #define PCI_DMA_FROMDEVICE 2 |
235 | #define PCI_DMA_FROMDEVICE 2 |
236 | #define PCI_DMA_NONE 3 |
236 | #define PCI_DMA_NONE 3 |
237 | 237 | ||
238 | /* |
238 | /* |
239 | * For PCI devices, the region numbers are assigned this way: |
239 | * For PCI devices, the region numbers are assigned this way: |
240 | */ |
240 | */ |
241 | enum { |
241 | enum { |
242 | /* #0-5: standard PCI resources */ |
242 | /* #0-5: standard PCI resources */ |
243 | PCI_STD_RESOURCES, |
243 | PCI_STD_RESOURCES, |
244 | PCI_STD_RESOURCE_END = 5, |
244 | PCI_STD_RESOURCE_END = 5, |
245 | 245 | ||
246 | /* #6: expansion ROM resource */ |
246 | /* #6: expansion ROM resource */ |
247 | PCI_ROM_RESOURCE, |
247 | PCI_ROM_RESOURCE, |
248 | 248 | ||
249 | /* device specific resources */ |
249 | /* device specific resources */ |
250 | #ifdef CONFIG_PCI_IOV |
250 | #ifdef CONFIG_PCI_IOV |
251 | PCI_IOV_RESOURCES, |
251 | PCI_IOV_RESOURCES, |
252 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
252 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
253 | #endif |
253 | #endif |
254 | 254 | ||
255 | /* resources assigned to buses behind the bridge */ |
255 | /* resources assigned to buses behind the bridge */ |
256 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
256 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
257 | 257 | ||
258 | PCI_BRIDGE_RESOURCES, |
258 | PCI_BRIDGE_RESOURCES, |
259 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
259 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
260 | PCI_BRIDGE_RESOURCE_NUM - 1, |
260 | PCI_BRIDGE_RESOURCE_NUM - 1, |
261 | 261 | ||
262 | /* total resources associated with a PCI device */ |
262 | /* total resources associated with a PCI device */ |
263 | PCI_NUM_RESOURCES, |
263 | PCI_NUM_RESOURCES, |
264 | 264 | ||
265 | /* preserve this for compatibility */ |
265 | /* preserve this for compatibility */ |
266 | DEVICE_COUNT_RESOURCE |
266 | DEVICE_COUNT_RESOURCE |
267 | }; |
267 | }; |
268 | 268 | ||
269 | typedef int __bitwise pci_power_t; |
269 | typedef int __bitwise pci_power_t; |
270 | 270 | ||
271 | #define PCI_D0 ((pci_power_t __force) 0) |
271 | #define PCI_D0 ((pci_power_t __force) 0) |
272 | #define PCI_D1 ((pci_power_t __force) 1) |
272 | #define PCI_D1 ((pci_power_t __force) 1) |
273 | #define PCI_D2 ((pci_power_t __force) 2) |
273 | #define PCI_D2 ((pci_power_t __force) 2) |
274 | #define PCI_D3hot ((pci_power_t __force) 3) |
274 | #define PCI_D3hot ((pci_power_t __force) 3) |
275 | #define PCI_D3cold ((pci_power_t __force) 4) |
275 | #define PCI_D3cold ((pci_power_t __force) 4) |
276 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
276 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
277 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
277 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
278 | 278 | ||
279 | /* Remember to update this when the list above changes! */ |
279 | /* Remember to update this when the list above changes! */ |
280 | extern const char *pci_power_names[]; |
280 | extern const char *pci_power_names[]; |
281 | 281 | ||
282 | static inline const char *pci_power_name(pci_power_t state) |
282 | static inline const char *pci_power_name(pci_power_t state) |
283 | { |
283 | { |
284 | return pci_power_names[1 + (int) state]; |
284 | return pci_power_names[1 + (int) state]; |
285 | } |
285 | } |
286 | 286 | ||
287 | #define PCI_PM_D2_DELAY 200 |
287 | #define PCI_PM_D2_DELAY 200 |
288 | #define PCI_PM_D3_WAIT 10 |
288 | #define PCI_PM_D3_WAIT 10 |
289 | #define PCI_PM_D3COLD_WAIT 100 |
289 | #define PCI_PM_D3COLD_WAIT 100 |
290 | #define PCI_PM_BUS_WAIT 50 |
290 | #define PCI_PM_BUS_WAIT 50 |
291 | 291 | ||
292 | /** The pci_channel state describes connectivity between the CPU and |
292 | /** The pci_channel state describes connectivity between the CPU and |
293 | * the pci device. If some PCI bus between here and the pci device |
293 | * the pci device. If some PCI bus between here and the pci device |
294 | * has crashed or locked up, this info is reflected here. |
294 | * has crashed or locked up, this info is reflected here. |
295 | */ |
295 | */ |
296 | typedef unsigned int __bitwise pci_channel_state_t; |
296 | typedef unsigned int __bitwise pci_channel_state_t; |
297 | 297 | ||
298 | enum pci_channel_state { |
298 | enum pci_channel_state { |
299 | /* I/O channel is in normal state */ |
299 | /* I/O channel is in normal state */ |
300 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
300 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
301 | 301 | ||
302 | /* I/O to channel is blocked */ |
302 | /* I/O to channel is blocked */ |
303 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
303 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
304 | 304 | ||
305 | /* PCI card is dead */ |
305 | /* PCI card is dead */ |
306 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
306 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
307 | }; |
307 | }; |
308 | typedef unsigned short __bitwise pci_bus_flags_t; |
308 | typedef unsigned short __bitwise pci_bus_flags_t; |
309 | enum pci_bus_flags { |
309 | enum pci_bus_flags { |
310 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
310 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
311 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
311 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
312 | }; |
312 | }; |
313 | 313 | ||
314 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
314 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
315 | enum pci_bus_speed { |
315 | enum pci_bus_speed { |
316 | PCI_SPEED_33MHz = 0x00, |
316 | PCI_SPEED_33MHz = 0x00, |
317 | PCI_SPEED_66MHz = 0x01, |
317 | PCI_SPEED_66MHz = 0x01, |
318 | PCI_SPEED_66MHz_PCIX = 0x02, |
318 | PCI_SPEED_66MHz_PCIX = 0x02, |
319 | PCI_SPEED_100MHz_PCIX = 0x03, |
319 | PCI_SPEED_100MHz_PCIX = 0x03, |
320 | PCI_SPEED_133MHz_PCIX = 0x04, |
320 | PCI_SPEED_133MHz_PCIX = 0x04, |
321 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
321 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
322 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
322 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
323 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
323 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
324 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
324 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
325 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
325 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
326 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
326 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
327 | AGP_UNKNOWN = 0x0c, |
327 | AGP_UNKNOWN = 0x0c, |
328 | AGP_1X = 0x0d, |
328 | AGP_1X = 0x0d, |
329 | AGP_2X = 0x0e, |
329 | AGP_2X = 0x0e, |
330 | AGP_4X = 0x0f, |
330 | AGP_4X = 0x0f, |
331 | AGP_8X = 0x10, |
331 | AGP_8X = 0x10, |
332 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
332 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
333 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
333 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
334 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
334 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
335 | PCIE_SPEED_2_5GT = 0x14, |
335 | PCIE_SPEED_2_5GT = 0x14, |
336 | PCIE_SPEED_5_0GT = 0x15, |
336 | PCIE_SPEED_5_0GT = 0x15, |
337 | PCIE_SPEED_8_0GT = 0x16, |
337 | PCIE_SPEED_8_0GT = 0x16, |
338 | PCI_SPEED_UNKNOWN = 0xff, |
338 | PCI_SPEED_UNKNOWN = 0xff, |
339 | }; |
339 | }; |
340 | 340 | ||
341 | /* |
341 | /* |
342 | * The pci_dev structure is used to describe PCI devices. |
342 | * The pci_dev structure is used to describe PCI devices. |
343 | */ |
343 | */ |
344 | struct pci_dev { |
344 | struct pci_dev { |
345 | struct list_head bus_list; /* node in per-bus list */ |
345 | struct list_head bus_list; /* node in per-bus list */ |
346 | struct pci_bus *bus; /* bus this device is on */ |
346 | struct pci_bus *bus; /* bus this device is on */ |
347 | struct pci_bus *subordinate; /* bus this device bridges to */ |
347 | struct pci_bus *subordinate; /* bus this device bridges to */ |
348 | 348 | ||
349 | void *sysdata; /* hook for sys-specific extension */ |
349 | void *sysdata; /* hook for sys-specific extension */ |
350 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
350 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
351 | struct pci_slot *slot; /* Physical slot this device is in */ |
351 | struct pci_slot *slot; /* Physical slot this device is in */ |
352 | u32_t busnr; |
352 | u32_t busnr; |
353 | unsigned int devfn; /* encoded device & function index */ |
353 | unsigned int devfn; /* encoded device & function index */ |
354 | unsigned short vendor; |
354 | unsigned short vendor; |
355 | unsigned short device; |
355 | unsigned short device; |
356 | unsigned short subsystem_vendor; |
356 | unsigned short subsystem_vendor; |
357 | unsigned short subsystem_device; |
357 | unsigned short subsystem_device; |
358 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
358 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
359 | u8 revision; /* PCI revision, low byte of class word */ |
359 | u8 revision; /* PCI revision, low byte of class word */ |
360 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
360 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
361 | u8 pcie_cap; /* PCI-E capability offset */ |
361 | u8 pcie_cap; /* PCI-E capability offset */ |
362 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
362 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
363 | u8 rom_base_reg; /* which config register controls the ROM */ |
363 | u8 rom_base_reg; /* which config register controls the ROM */ |
364 | u8 pin; /* which interrupt pin this device uses */ |
364 | u8 pin; /* which interrupt pin this device uses */ |
365 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
365 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
366 | 366 | ||
367 | // struct pci_driver *driver; /* which driver has allocated this device */ |
367 | // struct pci_driver *driver; /* which driver has allocated this device */ |
368 | uint64_t dma_mask; /* Mask of the bits of bus address this |
368 | uint64_t dma_mask; /* Mask of the bits of bus address this |
369 | device implements. Normally this is |
369 | device implements. Normally this is |
370 | 0xffffffff. You only need to change |
370 | 0xffffffff. You only need to change |
371 | this if your device has broken DMA |
371 | this if your device has broken DMA |
372 | or supports 64-bit transfers. */ |
372 | or supports 64-bit transfers. */ |
373 | 373 | ||
374 | // struct device_dma_parameters dma_parms; |
374 | // struct device_dma_parameters dma_parms; |
375 | 375 | ||
376 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
376 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
377 | this is D0-D3, D0 being fully functional, |
377 | this is D0-D3, D0 being fully functional, |
378 | and D3 being off. */ |
378 | and D3 being off. */ |
379 | int pm_cap; /* PM capability offset in the |
379 | int pm_cap; /* PM capability offset in the |
380 | configuration space */ |
380 | configuration space */ |
381 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
381 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
382 | can be generated */ |
382 | can be generated */ |
383 | unsigned int pme_interrupt:1; |
383 | unsigned int pme_interrupt:1; |
384 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
384 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
385 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
385 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
386 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
386 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
387 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
387 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
388 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
388 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
389 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
389 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
390 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
390 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
391 | decoding during bar sizing */ |
391 | decoding during bar sizing */ |
392 | unsigned int wakeup_prepared:1; |
392 | unsigned int wakeup_prepared:1; |
393 | unsigned int runtime_d3cold:1; /* whether go through runtime |
393 | unsigned int runtime_d3cold:1; /* whether go through runtime |
394 | D3cold, not set for devices |
394 | D3cold, not set for devices |
395 | powered on/off by the |
395 | powered on/off by the |
396 | corresponding bridge */ |
396 | corresponding bridge */ |
397 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
397 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
398 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
398 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
399 | 399 | ||
400 | #ifdef CONFIG_PCIEASPM |
400 | #ifdef CONFIG_PCIEASPM |
401 | struct pcie_link_state *link_state; /* ASPM link state. */ |
401 | struct pcie_link_state *link_state; /* ASPM link state. */ |
402 | #endif |
402 | #endif |
403 | 403 | ||
404 | pci_channel_state_t error_state; /* current connectivity state */ |
404 | pci_channel_state_t error_state; /* current connectivity state */ |
405 | struct device dev; /* Generic device interface */ |
405 | struct device dev; /* Generic device interface */ |
406 | struct acpi_device *acpi_dev; |
406 | struct acpi_device *acpi_dev; |
407 | int cfg_size; /* Size of configuration space */ |
407 | int cfg_size; /* Size of configuration space */ |
408 | 408 | ||
409 | /* |
409 | /* |
410 | * Instead of touching interrupt line and base address registers |
410 | * Instead of touching interrupt line and base address registers |
411 | * directly, use the values stored here. They might be different! |
411 | * directly, use the values stored here. They might be different! |
412 | */ |
412 | */ |
413 | unsigned int irq; |
413 | unsigned int irq; |
414 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
414 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
415 | 415 | ||
416 | /* These fields are used by common fixups */ |
416 | /* These fields are used by common fixups */ |
417 | unsigned int transparent:1; /* Transparent PCI bridge */ |
417 | unsigned int transparent:1; /* Transparent PCI bridge */ |
418 | unsigned int multifunction:1;/* Part of multi-function device */ |
418 | unsigned int multifunction:1;/* Part of multi-function device */ |
419 | /* keep track of device state */ |
419 | /* keep track of device state */ |
420 | unsigned int is_added:1; |
420 | unsigned int is_added:1; |
421 | unsigned int is_busmaster:1; /* device is busmaster */ |
421 | unsigned int is_busmaster:1; /* device is busmaster */ |
422 | unsigned int no_msi:1; /* device may not use msi */ |
422 | unsigned int no_msi:1; /* device may not use msi */ |
423 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
423 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
424 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
424 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
425 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
425 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
426 | unsigned int msi_enabled:1; |
426 | unsigned int msi_enabled:1; |
427 | unsigned int msix_enabled:1; |
427 | unsigned int msix_enabled:1; |
428 | unsigned int ari_enabled:1; /* ARI forwarding */ |
428 | unsigned int ari_enabled:1; /* ARI forwarding */ |
429 | unsigned int is_managed:1; |
429 | unsigned int is_managed:1; |
430 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
430 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
431 | Use pci_is_pcie() instead */ |
431 | Use pci_is_pcie() instead */ |
432 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
432 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
433 | unsigned int state_saved:1; |
433 | unsigned int state_saved:1; |
434 | unsigned int is_physfn:1; |
434 | unsigned int is_physfn:1; |
435 | unsigned int is_virtfn:1; |
435 | unsigned int is_virtfn:1; |
436 | unsigned int reset_fn:1; |
436 | unsigned int reset_fn:1; |
437 | unsigned int is_hotplug_bridge:1; |
437 | unsigned int is_hotplug_bridge:1; |
438 | unsigned int __aer_firmware_first_valid:1; |
438 | unsigned int __aer_firmware_first_valid:1; |
439 | unsigned int __aer_firmware_first:1; |
439 | unsigned int __aer_firmware_first:1; |
440 | unsigned int broken_intx_masking:1; |
440 | unsigned int broken_intx_masking:1; |
441 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
441 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
442 | // pci_dev_flags_t dev_flags; |
442 | // pci_dev_flags_t dev_flags; |
443 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
443 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
444 | 444 | ||
445 | 445 | ||
446 | 446 | ||
447 | }; |
447 | }; |
448 | 448 | ||
449 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
449 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
450 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
450 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
451 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
451 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
452 | #define pci_resource_len(dev,bar) \ |
452 | #define pci_resource_len(dev,bar) \ |
453 | ((pci_resource_start((dev), (bar)) == 0 && \ |
453 | ((pci_resource_start((dev), (bar)) == 0 && \ |
454 | pci_resource_end((dev), (bar)) == \ |
454 | pci_resource_end((dev), (bar)) == \ |
455 | pci_resource_start((dev), (bar))) ? 0 : \ |
455 | pci_resource_start((dev), (bar))) ? 0 : \ |
456 | \ |
456 | \ |
457 | (pci_resource_end((dev), (bar)) - \ |
457 | (pci_resource_end((dev), (bar)) - \ |
458 | pci_resource_start((dev), (bar)) + 1)) |
458 | pci_resource_start((dev), (bar)) + 1)) |
459 | 459 | ||
460 | 460 | ||
461 | struct pci_bus { |
461 | struct pci_bus { |
462 | struct list_head node; /* node in list of buses */ |
462 | struct list_head node; /* node in list of buses */ |
463 | struct pci_bus *parent; /* parent bus this bridge is on */ |
463 | struct pci_bus *parent; /* parent bus this bridge is on */ |
464 | struct list_head children; /* list of child buses */ |
464 | struct list_head children; /* list of child buses */ |
465 | struct list_head devices; /* list of devices on this bus */ |
465 | struct list_head devices; /* list of devices on this bus */ |
466 | struct pci_dev *self; /* bridge device as seen by parent */ |
466 | struct pci_dev *self; /* bridge device as seen by parent */ |
467 | struct list_head slots; /* list of slots on this bus */ |
467 | struct list_head slots; /* list of slots on this bus */ |
468 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
468 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
469 | struct list_head resources; /* address space routed to this bus */ |
469 | struct list_head resources; /* address space routed to this bus */ |
470 | struct resource busn_res; /* bus numbers routed to this bus */ |
470 | struct resource busn_res; /* bus numbers routed to this bus */ |
471 | 471 | ||
472 | struct pci_ops *ops; /* configuration access functions */ |
472 | struct pci_ops *ops; /* configuration access functions */ |
473 | void *sysdata; /* hook for sys-specific extension */ |
473 | void *sysdata; /* hook for sys-specific extension */ |
474 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
474 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
475 | 475 | ||
476 | unsigned char number; /* bus number */ |
476 | unsigned char number; /* bus number */ |
477 | unsigned char primary; /* number of primary bridge */ |
477 | unsigned char primary; /* number of primary bridge */ |
478 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
478 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
479 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
479 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
480 | 480 | ||
481 | char name[48]; |
481 | char name[48]; |
482 | 482 | ||
483 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
483 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
484 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
484 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
485 | struct device *bridge; |
485 | struct device *bridge; |
486 | struct device dev; |
486 | struct device dev; |
487 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
487 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
488 | struct bin_attribute *legacy_mem; /* legacy mem */ |
488 | struct bin_attribute *legacy_mem; /* legacy mem */ |
489 | unsigned int is_added:1; |
489 | unsigned int is_added:1; |
490 | }; |
490 | }; |
491 | 491 | ||
492 | 492 | ||
493 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
493 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
494 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
494 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
495 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
495 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
496 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
496 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
497 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
497 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
498 | 498 | ||
499 | 499 | ||
500 | /* Low-level architecture-dependent routines */ |
500 | /* Low-level architecture-dependent routines */ |
501 | 501 | ||
502 | struct pci_sysdata { |
502 | struct pci_sysdata { |
503 | int domain; /* PCI domain */ |
503 | int domain; /* PCI domain */ |
504 | int node; /* NUMA node */ |
504 | int node; /* NUMA node */ |
505 | }; |
505 | }; |
506 | 506 | ||
507 | 507 | ||
508 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
508 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
509 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
509 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
510 | 510 | ||
511 | /* |
511 | /* |
512 | * Returns true if the pci bus is root (behind host-pci bridge), |
512 | * Returns true if the pci bus is root (behind host-pci bridge), |
513 | * false otherwise |
513 | * false otherwise |
514 | */ |
514 | */ |
515 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
515 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
516 | { |
516 | { |
517 | return !(pbus->parent); |
517 | return !(pbus->parent); |
518 | } |
518 | } |
519 | 519 | ||
520 | struct pci_bus * |
520 | struct pci_bus * |
521 | pci_find_next_bus(const struct pci_bus *from); |
521 | pci_find_next_bus(const struct pci_bus *from); |
522 | 522 | ||
523 | 523 | ||
524 | /* |
524 | /* |
525 | * Error values that may be returned by PCI functions. |
525 | * Error values that may be returned by PCI functions. |
526 | */ |
526 | */ |
527 | #define PCIBIOS_SUCCESSFUL 0x00 |
527 | #define PCIBIOS_SUCCESSFUL 0x00 |
528 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
528 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
529 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
529 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
530 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
530 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
531 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
531 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
532 | #define PCIBIOS_SET_FAILED 0x88 |
532 | #define PCIBIOS_SET_FAILED 0x88 |
533 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
533 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
534 | 534 | ||
535 | /* Low-level architecture-dependent routines */ |
535 | /* Low-level architecture-dependent routines */ |
536 | 536 | ||
537 | struct pci_ops { |
537 | struct pci_ops { |
538 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
538 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
539 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
539 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
540 | }; |
540 | }; |
541 | 541 | ||
542 | 542 | ||
543 | enum pci_bar_type { |
543 | enum pci_bar_type { |
544 | pci_bar_unknown, /* Standard PCI BAR probe */ |
544 | pci_bar_unknown, /* Standard PCI BAR probe */ |
545 | pci_bar_io, /* An io port BAR */ |
545 | pci_bar_io, /* An io port BAR */ |
546 | pci_bar_mem32, /* A 32-bit memory BAR */ |
546 | pci_bar_mem32, /* A 32-bit memory BAR */ |
547 | pci_bar_mem64, /* A 64-bit memory BAR */ |
547 | pci_bar_mem64, /* A 64-bit memory BAR */ |
548 | }; |
548 | }; |
549 | 549 | ||
550 | /* |
550 | /* |
551 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
551 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
552 | * a PCI domain is defined to be a set of PCI busses which share |
552 | * a PCI domain is defined to be a set of PCI busses which share |
553 | * configuration space. |
553 | * configuration space. |
554 | */ |
554 | */ |
555 | #ifdef CONFIG_PCI_DOMAINS |
555 | #ifdef CONFIG_PCI_DOMAINS |
556 | extern int pci_domains_supported; |
556 | extern int pci_domains_supported; |
557 | #else |
557 | #else |
558 | enum { pci_domains_supported = 0 }; |
558 | enum { pci_domains_supported = 0 }; |
559 | static inline int pci_domain_nr(struct pci_bus *bus) |
559 | static inline int pci_domain_nr(struct pci_bus *bus) |
560 | { |
560 | { |
561 | return 0; |
561 | return 0; |
562 | } |
562 | } |
563 | 563 | ||
564 | static inline int pci_proc_domain(struct pci_bus *bus) |
564 | static inline int pci_proc_domain(struct pci_bus *bus) |
565 | { |
565 | { |
566 | return 0; |
566 | return 0; |
567 | } |
567 | } |
568 | #endif /* CONFIG_PCI_DOMAINS */ |
568 | #endif /* CONFIG_PCI_DOMAINS */ |
569 | 569 | ||
570 | /** |
570 | /** |
571 | * pci_pcie_cap - get the saved PCIe capability offset |
571 | * pci_pcie_cap - get the saved PCIe capability offset |
572 | * @dev: PCI device |
572 | * @dev: PCI device |
573 | * |
573 | * |
574 | * PCIe capability offset is calculated at PCI device initialization |
574 | * PCIe capability offset is calculated at PCI device initialization |
575 | * time and saved in the data structure. This function returns saved |
575 | * time and saved in the data structure. This function returns saved |
576 | * PCIe capability offset. Using this instead of pci_find_capability() |
576 | * PCIe capability offset. Using this instead of pci_find_capability() |
577 | * reduces unnecessary search in the PCI configuration space. If you |
577 | * reduces unnecessary search in the PCI configuration space. If you |
578 | * need to calculate PCIe capability offset from raw device for some |
578 | * need to calculate PCIe capability offset from raw device for some |
579 | * reasons, please use pci_find_capability() instead. |
579 | * reasons, please use pci_find_capability() instead. |
580 | */ |
580 | */ |
581 | static inline int pci_pcie_cap(struct pci_dev *dev) |
581 | static inline int pci_pcie_cap(struct pci_dev *dev) |
582 | { |
582 | { |
583 | return dev->pcie_cap; |
583 | return dev->pcie_cap; |
584 | } |
584 | } |
585 | 585 | ||
586 | /** |
586 | /** |
587 | * pci_is_pcie - check if the PCI device is PCI Express capable |
587 | * pci_is_pcie - check if the PCI device is PCI Express capable |
588 | * @dev: PCI device |
588 | * @dev: PCI device |
589 | * |
589 | * |
590 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
590 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
591 | */ |
591 | */ |
592 | static inline bool pci_is_pcie(struct pci_dev *dev) |
592 | static inline bool pci_is_pcie(struct pci_dev *dev) |
593 | { |
593 | { |
594 | return !!pci_pcie_cap(dev); |
594 | return !!pci_pcie_cap(dev); |
595 | } |
595 | } |
596 | 596 | ||
597 | /** |
597 | /** |
598 | * pci_pcie_type - get the PCIe device/port type |
598 | * pci_pcie_type - get the PCIe device/port type |
599 | * @dev: PCI device |
599 | * @dev: PCI device |
600 | */ |
600 | */ |
601 | static inline int pci_pcie_type(const struct pci_dev *dev) |
601 | static inline int pci_pcie_type(const struct pci_dev *dev) |
602 | { |
602 | { |
603 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
603 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
604 | } |
604 | } |
605 | 605 | ||
606 | 606 | ||
607 | static inline int pci_iov_init(struct pci_dev *dev) |
607 | static inline int pci_iov_init(struct pci_dev *dev) |
608 | { |
608 | { |
609 | return -ENODEV; |
609 | return -ENODEV; |
610 | } |
610 | } |
611 | static inline void pci_iov_release(struct pci_dev *dev) |
611 | static inline void pci_iov_release(struct pci_dev *dev) |
612 | 612 | ||
613 | {} |
613 | {} |
614 | 614 | ||
615 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
615 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
616 | enum pci_bar_type *type) |
616 | enum pci_bar_type *type) |
617 | { |
617 | { |
618 | return 0; |
618 | return 0; |
619 | } |
619 | } |
620 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
620 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
621 | { |
621 | { |
622 | } |
622 | } |
623 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
623 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
624 | { |
624 | { |
625 | return 0; |
625 | return 0; |
626 | } |
626 | } |
627 | 627 | ||
628 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
628 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
629 | { |
629 | { |
630 | return -ENODEV; |
630 | return -ENODEV; |
631 | } |
631 | } |
632 | static inline void pci_disable_ats(struct pci_dev *dev) |
632 | static inline void pci_disable_ats(struct pci_dev *dev) |
633 | { |
633 | { |
634 | } |
634 | } |
635 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
635 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
636 | { |
636 | { |
637 | return -ENODEV; |
637 | return -ENODEV; |
638 | } |
638 | } |
639 | static inline int pci_ats_enabled(struct pci_dev *dev) |
639 | static inline int pci_ats_enabled(struct pci_dev *dev) |
640 | { |
640 | { |
641 | return 0; |
641 | return 0; |
642 | } |
642 | } |
643 | 643 | ||
644 | int pci_setup_device(struct pci_dev *dev); |
644 | int pci_setup_device(struct pci_dev *dev); |
645 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
645 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
646 | struct resource *res, unsigned int reg); |
646 | struct resource *res, unsigned int reg); |
647 | int pci_resource_bar(struct pci_dev *dev, int resno, |
647 | int pci_resource_bar(struct pci_dev *dev, int resno, |
648 | enum pci_bar_type *type); |
648 | enum pci_bar_type *type); |
649 | int pci_bus_add_child(struct pci_bus *bus); |
649 | int pci_bus_add_child(struct pci_bus *bus); |
650 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
650 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
651 | 651 | ||
652 | 652 | ||
653 | typedef struct |
653 | typedef struct |
654 | { |
654 | { |
655 | struct list_head link; |
655 | struct list_head link; |
656 | struct pci_dev pci_dev; |
656 | struct pci_dev pci_dev; |
657 | }pci_dev_t; |
657 | }pci_dev_t; |
658 | 658 | ||
659 | int enum_pci_devices(void); |
659 | int enum_pci_devices(void); |
660 | 660 | ||
661 | const struct pci_device_id* |
661 | const struct pci_device_id* |
662 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
662 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
663 | 663 | ||
664 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
664 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
665 | 665 | ||
- | 666 | #define pci_set_dma_mask(a, b) 0 |
|
666 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
667 | #define pci_set_consistent_dma_mask(a, b) |
667 | 668 | ||
668 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
669 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
669 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
670 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
670 | 671 | ||
671 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
672 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
672 | 673 | ||
673 | #define pci_name(x) "radeon" |
674 | #define pci_name(x) "radeon" |
674 | 675 | ||
675 | #endif //__PCI__H__(n))-1)) |
676 | #endif //__PCI__H__(n))-1)) |
676 | 677 | ||
677 | int><(n))-1)) |
678 | #define><(n))-1)) |
678 | 679 | ||
679 | int>><>><>><>><>><>><> |
680 | #define>><>><>><>><>><>><> |